Semiconductor memory device

Abstract

The semiconductor memory device may include a first electrode and a second electrode spaced apart from each other in a first direction and a first semiconductor pattern in contact with both the first electrode and the second electrode. The first semiconductor pattern may include first to fourth sub-semiconductor patterns sequentially arranged in the first direction. The first sub-semiconductor pattern and the fourth sub-semiconductor pattern may be in contact with the first electrode and the second electrode, respectively. The first sub-semiconductor pattern and the third sub-semiconductor pattern may have a first conductivity type, and the second sub-semiconductor pattern and the fourth sub-semiconductor pattern may have a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogenide element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2020-0007347, titled “Semiconductor Memory Device”, filed on January 20, 2020 in the Korean Intellectual Property Office, is claimed to be incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor memory device. Background Art

[0004] Higher integration of semiconductor devices is very important to provide excellent performance and low price. Improved integration is an important factor in determining product prices. In the case of two-dimensional or planar semiconductor devices, since its integration is mainly determined by the area occupied by the unit memory cell, the integration is greatly affected by the level of fine pattern formation technology. Summary of the invention

[0005] An embodiment relates to a semiconductor memory device, including: a first electrode and a second electrode spaced apart from each other in a first direction; and a first semiconductor pattern in contact with both the first electrode and the second electrode. The first semiconductor pattern may include first to fourth sub-semiconductor patterns sequentially arranged in the first direction. The first sub-semiconductor pattern may be in contact with the first electrode, and the fourth sub-semiconductor pattern may be in contact with the second electrode. The first sub-semiconductor pattern and the third sub-semiconductor pattern may have a first conductivity type, and the second sub-semiconductor pattern and the fourth sub-semiconductor pattern may have a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogenide element.

[0006] Embodiments also relate to a semiconductor memory device, including: a first electrode and a second electrode spaced apart from each other in a first direction; a semiconductor pattern in contact with both the first electrode and the second electrode; and a penetrating insulating pattern penetrating the semiconductor pattern. The semiconductor pattern may include first to fourth sub-semiconductor patterns sequentially arranged in the first direction, and the penetrating insulating pattern may penetrate the first to fourth sub-semiconductor patterns. The first sub-semiconductor pattern may be in contact with the first electrode, and the fourth sub-semiconductor pattern may be in contact with the second electrode. The first sub-semiconductor pattern and the third sub-semiconductor pattern may have a first conductivity type, and the second sub-semiconductor pattern and the fourth sub-semiconductor pattern may have a second conductivity type different from the first conductivity type.

[0007] Embodiments also relate to a semiconductor memory device, including a first electrode and a second electrode spaced apart from each other in a first direction; and a semiconductor pattern that contacts both the first electrode and the second electrode. The first semiconductor pattern may include first to fourth sub-semiconductor patterns sequentially arranged in the first direction. The first sub-semiconductor pattern and the third sub-semiconductor pattern may have a first width and a third width in the first direction, respectively, and the third width may be n times the first width, where n may be a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing example embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a circuit diagram schematically illustrating a cell array of a semiconductor memory device according to example embodiments.

[0010] Figure 2A is according to an example embodiment having Figure 1 A three-dimensional view of a semiconductor memory device with a circuit diagram.

[0011] Figure 2B is along Figure 2A A cross-sectional view taken along line AA'.

[0012] Figure 3 is a diagram showing a method according to an example embodiment Figure 2A An enlarged perspective view of a memory cell.

[0013] Figure 4 is an energy band diagram illustrating a sub-semiconductor pattern and an energy band gap of silicon according to example embodiments.

[0014] Figure 5 is a diagram showing a method according to an example embodiment Figure 2A An enlarged perspective view of a memory cell.

[0015] Figure 6 is along Figure 5 A cross-sectional view taken along line BB'.

[0016] Figure 7 is a diagram showing a method according to an example embodiment Figure 2A An enlarged perspective view of a memory cell.

[0017] Figure 8 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to example embodiments.

[0018] Fig. 9 is a perspective view illustrating a three-dimensional semiconductor memory device according to example embodiments.

[0019] Fig.10 It shows Fig. 9 An enlarged perspective view of a memory cell of a memory device.

[0020] Fig.11 It shows Fig.10 A plan view of a memory cell.

[0021] Fig.12 is along Fig.11 A cross-sectional view taken along line CC'.

[0022] Fig.13 is an enlarged perspective view illustrating a memory cell of a three-dimensional semiconductor memory device according to example embodiments.

[0023] Fig.14 It shows Fig.13 A plan view of a memory cell.

[0024] Fig.15 is along Fig.14 A cross-sectional view taken along line CC'.

[0025] Fig.16 is an enlarged perspective view illustrating a memory cell of a three-dimensional semiconductor memory device according to example embodiments.

[0026] Fig.17 is an enlarged perspective view illustrating a first memory cell and a second memory cell of a three-dimensional semiconductor memory device according to example embodiments.

[0027] Fig.18 It shows Fig.17 A plan view of a first memory cell and a second memory cell.

[0028] Fig.19 is an enlarged perspective view illustrating a first memory cell and a second memory cell of a three-dimensional semiconductor memory device according to example embodiments.

[0029] Fig. 20A is along Fig.14 A cross-sectional view taken along line CC'.

[0030] Fig. 20B is along Fig.11 A cross-sectional view taken along line CC'.

[0031] Fig.21 is a diagram showing a method according to an example embodiment Fig.13 A plan view of a memory cell. DETAILED DESCRIPTION

[0032] Figure 1is a circuit diagram schematically illustrating a cell array of a semiconductor memory device according to example embodiments.

[0033] Reference Figure 1 , the semiconductor memory device may include a cell array CA. The cell array CA may include first conductive lines CL1 and second conductive lines CL2 arranged to cross each other and a plurality of memory cells MC placed at respective intersections of the first conductive lines CL1 and the second conductive lines CL2. The first conductive lines CL1 may be spaced apart from each other in a first direction D1 and may extend in a second direction D2 crossing the first direction D1. The second conductive lines CL2 may be spaced apart from each other in the second direction D2 and may extend in the first direction D1. The conductive lines may be, for example, electrodes.

[0034] Each of the memory cells MC may be, for example, a thyristor, the first conductive line CL1 may be, for example, a cathode line, and the second conductive line CL2 may be, for example, an anode line. The semiconductor memory device may be, for example, a thyristor device. The thyristor may include a first diode and a second diode connected in series.

[0035] When the same forward bias voltage is applied to the thyristor, the amount of current flowing through the thyristor can be large when the thyristor is in a high conductance state, or can be small or substantially zero when it is in a low conductance state. The high conductance state and the low conductance state of the thyristor can be used to implement the "1" and "0" states of the semiconductor memory device according to the present example embodiment.

[0036] The operation of the semiconductor memory device may include a latching step of turning on a selected one of the memory cells MC from an off state to an on state (e.g., from a "0" state to a "1" state) and a holding step of keeping the memory cell MC in an on state (e.g., a "1" state). The minimum value of the anode current required for the latching step may be referred to as a latching current, and the minimum value of the anode current required for the holding step may be referred to as a holding current.

[0037] Figure 2A is according to an example embodiment having Figure 1 A three-dimensional view of a semiconductor memory device with a circuit diagram. Figure 2B is along Figure 2A A cross-sectional view taken along line AA'. Figure 2A A structure from which the first to third interlayer insulating layers are omitted is shown.

[0038] Reference Figure 2A and Figure 2B, the first interlayer insulating layer IL1 may be disposed on the substrate 100. The substrate 100 may be, for example, a single crystal silicon substrate, an epitaxial silicon layer, or a silicon on insulator (SOI) substrate. The transistor may be disposed on the substrate 100, and the first interlayer insulating layer IL1 may cover the transistor. In addition, an interconnect layer may be disposed in the first interlayer insulating layer IL1. The first conductive line CL1 may be disposed on the first interlayer insulating layer. The first conductive lines CL1 may be spaced apart from each other in the first direction D1, and may extend in the second direction D2. The space between the first conductive lines CL1 may be filled with the second interlayer insulating layer IL2. A plurality of semiconductor patterns CP may be disposed on the first conductive line CL1. The semiconductor pattern CP may be a channel pattern. The space between the semiconductor patterns CP may be filled with the third interlayer insulating layer IL3. The second conductive line CL2 may be disposed on each semiconductor pattern CP, respectively. Each of the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the third interlayer insulating layer IL3 may have a single-layer structure or a multilayer structure including, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous insulating layer. The first conductive line CL1 and the second conductive line CL2 may be formed of or include, for example, one or more of doped polysilicon, metal nitrides (e.g., titanium nitride, tungsten nitride, and tantalum nitride), metal silicides (e.g., cobalt silicide), and metal-containing materials (e.g., tungsten, copper, and aluminum), and may have a single-layer structure or a multi-layer structure.

[0039] The first conductive line CL1 and the second conductive line CL2 may be arranged to cross each other. The memory cells MC may be arranged at the intersections of the first conductive line CL1 and the second conductive line CL2, respectively. The first conductive line CL1, the second conductive line CL2, and the memory cells MC may constitute a single-layer cell array CA. A plurality of cell arrays CA may be stacked on the substrate 100 in a third direction D3 perpendicular to the top surface of the substrate 100.

[0040] Figure 3 is a diagram showing a method according to an example embodiment Figure 2A An enlarged perspective view of a memory cell.

[0041] Reference Figure 3 , the memory cell MC may include a portion of the first conductive line CL1, a portion of the second conductive line CL2, and a semiconductor pattern CP interposed therebetween. The semiconductor pattern CP may include first to fourth sub-semiconductor patterns SP1 to SP4 sequentially stacked in the third direction D3. The first sub-semiconductor pattern SP1 and the second sub-semiconductor pattern SP2 may be connected to form a semiconductor pattern CP. Figure 1The third sub-semiconductor pattern SP3 and the fourth sub-semiconductor pattern SP4 may correspond to the first diode of the memory cell MC. Figure 1 The first sub-semiconductor pattern SP1 to the fourth sub-semiconductor pattern SP4 may each have, for example, a rectangular, quadrangular, circular, or elliptical shape when viewed in a plan view. The first sub-semiconductor pattern SP1 and the third sub-semiconductor pattern SP3 may have a first conductivity type, and the second sub-semiconductor pattern SP2 and the fourth sub-semiconductor pattern SP4 may have a second conductivity type different from the first conductivity type. For example, the first conductivity type may be an n-type, and the second conductivity type may be a p-type.

[0042] In example embodiments, each of the first to fourth sub-semiconductor patterns SP1 to SP4 may be a two-dimensional semiconductor material. The first to fourth sub-semiconductor patterns SP1 to SP4 may have a two-dimensional grid structure, and the height of one layer in the grid structure may be, for example, in the range of 0.1 nm to 1 nm. The first to fourth sub-semiconductor patterns SP1 to SP4 may have a grid structure with a very small thickness. Therefore, the total vertical size of the semiconductor pattern CP may be reduced. Therefore, a highly integrated semiconductor memory device may be implemented.

[0043] In example embodiments, each of the first to fourth sub-semiconductor patterns SP1 to SP4 may include a two-dimensional semiconductor material having a single-layer mesh structure. Each of the first to fourth sub-semiconductor patterns SP1 to SP4 may have a first thickness T1 in the third direction D3. In example embodiments, the first thickness T1 may be, for example, about 0.7 nm. The memory cell MC may have a second thickness T2 in the third direction D3. In example embodiments, the first thickness T1 may be, for example, in a range of about 2.8 nm to about 3.0 nm.

[0044] In example embodiments, each of the first to fourth sub-semiconductor patterns SP1 to SP4 may include a transition metal and a chalcogenide element. Each of the first to fourth sub-semiconductor patterns SP1 to SP4 may include a chalcogenide element whose content does not satisfy its stoichiometric ratio (e.g., a non-stoichiometric chalcogenide). The material included in the first to fourth sub-semiconductor patterns SP1 to SP4 may be a transition metal dichalcogenide (TMDC). The transition metal may be, for example, tungsten (W) or molybdenum (Mo). The chalcogenide element may be, for example, sulfur (S), selenium (Se), or tellurium (Te).

[0045] In example embodiments, the first and third sub-semiconductor patterns SP1 and SP3 may be made of MoS a or WSb Forming or including MoS a or WS b The second sub-semiconductor pattern SP2 and the fourth sub-semiconductor pattern SP4 may be made of MoSe c or WSe d Forming or including MoSe c or WSe d , wherein subscripts a to d are each independently a positive real number equal to or less than 2. Subscripts a and c may be the same as each other or may be different from each other.

[0046] Since the subscripts a and c become less than 2, the amount of electrons in the first sub-semiconductor pattern SP1 and the third sub-semiconductor pattern SP3 may increase, in which case the first sub-semiconductor pattern SP1 and the third sub-semiconductor pattern SP3 may behave more like an n-type semiconductor material. The subscripts b and d may be the same as or may be different from each other. Since the subscripts b and d become less than 2, the amount of holes in the second sub-semiconductor pattern SP2 and the fourth sub-semiconductor pattern SP4 may increase, in which case the second sub-semiconductor pattern SP2 and the fourth sub-semiconductor pattern SP4 may behave more like a p-type semiconductor material.

[0047] In example embodiments, subscript c may be greater than subscript a. Subscript b may be greater than subscript d. Therefore, the amount of electrons in the third sub-semiconductor pattern SP3 may be less than the amount of electrons in the first sub-semiconductor pattern SP1. In addition, the amount of holes in the second sub-semiconductor pattern SP2 may be less than the amount of holes in the fourth sub-semiconductor pattern SP4. The difference between the amount of electrons and holes may cause a change in the energy band gap therebetween, and the amount of electron-hole recombination occurring in the boundary between the second sub-semiconductor pattern SP2 and the third sub-semiconductor pattern SP3 may be reduced. Therefore, the holding current may be reduced.

[0048] In example embodiments, in order to express an n-type semiconductor behavior and a p-type semiconductor behavior or to increase the amount of electrons or holes, at least one of the subscripts a to d may be greater than 2.

[0049] Figure 4 is an energy band diagram illustrating a sub-semiconductor pattern and an energy band gap of silicon according to example embodiments.

[0050] Reference Figure 4 Each of the first to fourth sub-semiconductor patterns SP1 to SP4 may include a material having an energy band gap (Eg) greater than that of silicon. For example, the energy band gap of silicon may be about 1.1 eV, and the energy band gap of each of the first to fourth sub-semiconductor patterns SP1 to SP4 may be about 2.0 eV.

[0051] In the holding step of the semiconductor memory device, it is necessary to supply additional electrons in an amount greater than the amount of electrons to be lost by electron-hole recombination. Such additional electrons may constitute a holding current. In an example embodiment, each of the first to fourth sub-semiconductor patterns SP1 to SP4 is formed of a material having an energy band gap greater than that of silicon. Therefore, compared with electron-hole recombination in silicon, electron-hole recombination may be suppressed. Due to such suppression of electron-hole recombination, the number of additional electrons supplied may be reduced, thereby reducing the holding current. Therefore, the semiconductor memory device may be operated with low power consumption.

[0052] It can be produced by the following method Figure 2B A semiconductor memory device.

[0053] Reference Figure 2B , a first interlayer insulating layer IL1 may be formed on the substrate 100. A first conductive line CL1 may be formed by forming a conductive layer on the first interlayer insulating layer IL1 and patterning the conductive layer. A second interlayer insulating layer IL2 may be formed on the first conductive line CL1, and the second interlayer insulating layer IL2 may be etched back in an etch-back manner to expose the first conductive line CL1. First to fourth sub-semiconductor layers may be sequentially formed on the second interlayer insulating layer IL2 and the first conductive line CL1. The first to fourth sub-semiconductor layers may be formed of or include a two-dimensional semiconductor material. The material for the first to fourth sub-semiconductor layers may be the same as the material for the first to fourth sub-semiconductor patterns SP1 to SP4. The first to fourth sub-semiconductor layers may be formed by, for example, a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. An etching process may be performed to pattern the first to fourth sub-semiconductor layers, thereby forming the first to fourth sub-semiconductor patterns SP1 to SP4 constituting the semiconductor pattern CP. A third interlayer insulating layer IL3 may be formed to fill the space between the semiconductor patterns CP. A second conductive line CL2 may be formed on the semiconductor patterns CP.

[0054] Figure 5 is a diagram showing a method according to an example embodiment Figure 2A An enlarged perspective view of a memory cell. Figure 6 is along Figure 5 A cross-sectional view taken along line BB'.

[0055] Reference Figure 5 and Figure 6, the penetration insulating pattern IP may be arranged to penetrate the first to fourth sub-semiconductor patterns SP1 to SP4, and contact the first conductive line CL1 and the second conductive line CL2. When viewed in a plan view, the penetration insulating pattern IP may have, for example, a rectangular, quadrangular, circular or elliptical shape. Each of the first to fourth sub-semiconductor patterns SP1 to SP4 may be arranged to surround the penetration insulating pattern IP, and may have a ring shape or a donut shape. The penetration insulating pattern IP may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a porous insulating layer, a metal oxide layer and a metal nitride layer, and may have a single-layer or multi-layer structure. Therefore, each of the first to fourth sub-semiconductor patterns SP1 to SP4 may have a relatively small width. Therefore, it may be possible to reduce the number of current paths formed between the second conductive line CL2 and the first conductive line CL1. This may enable the probability of electron-hole recombination to be reduced, thereby reducing the holding current.

[0056] Figure 7 is a diagram showing a method according to an example embodiment Figure 2A An enlarged perspective view of a memory cell.

[0057] Reference Figure 7 , the first sub-semiconductor pattern SP1 may have a third thickness T3 in the third direction D3. The second sub-semiconductor pattern SP2 may have a fourth thickness T4 in the third direction D3. The third sub-semiconductor pattern SP3 may have a fifth thickness T5 in the third direction D3. The fourth sub-semiconductor pattern SP4 may have a sixth thickness T6 in the third direction D3.

[0058] The fourth thickness T4 may be greater than the sixth thickness T6. The fifth thickness T5 may be greater than the third thickness T3. The first to fourth sub-semiconductor patterns SP1 to SP4 may have a two-dimensional layered grid structure, the fourth thickness T4 may be n times the sixth thickness T6, and the fifth thickness T5 may be m times the third thickness T3, where each of the numbers n and m is a positive integer.

[0059] In this structure, due to such a thickness difference, the energy band gap can be changed, and in this case, the energy level difference between the start point and the end point through which the current in the memory cell MC travels can be increased. Therefore, the holding current can be reduced.

[0060] Figure 8 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to example embodiments.

[0061] Reference Figure 8, the cell array of the three-dimensional semiconductor memory device according to the embodiment may include a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged in the second direction D2.

[0062] Each of the sub-cell arrays SCA1 and SCA2 may include a plurality of cathode lines CTL, a plurality of gate lines GL, and a plurality of memory cells MC. Each of the memory cells MC may be disposed between a corresponding pair of the gate lines GL and the cathode line CTL.

[0063] Each of the memory cells MC may be a data storage element composed of a thyristor. In an example embodiment, each of the memory cells MC may have a capacitor-free structure. The memory device according to this example embodiment may be a thyristor DRAM that does not include a capacitor. The thyristor may include a first diode, a second diode, and a gate connected to the first diode.

[0064] The cathode line CTL may be a conductive pattern (e.g., a metal line) disposed above the substrate or vertically spaced apart from the substrate. The cathode line CTL may extend in the first direction D1. The cathode lines CTL in each of the subcell arrays SCA1 and SCA2 may be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0065] The gate lines GL may be conductive patterns (eg, metal lines) extending in a vertical direction or a third direction D3 perpendicular to a top surface of a substrate. In each of the subcell arrays SCA1 and SCA2, the gate lines GL may be spaced apart from each other in the first direction D1.

[0066] The common anode line CAL may be disposed between a pair of subcell arrays SCA1 and SCA2 adjacent to each other in the second direction D2. The common anode line CAL may be a conductive pattern (eg, a metal line) extending in a vertical direction (ie, the third direction D3). The common anode lines CAL may be spaced apart from each other in the first direction D1.

[0067] Each of the common anode lines CAL may be commonly connected to a pair of memory cells MC adjacent to each other in the second direction D2. For example, each of the common anode lines CAL may be commonly connected to a pair of memory cells MC adjacent to each other at the same level.

[0068] Fig. 9 is a perspective view illustrating a three-dimensional semiconductor memory device according to example embodiments. Fig.10 It shows Fig. 9 An enlarged perspective view of a memory cell of a memory device. Fig.11 It shows Fig.10 A plan view of a memory cell. Fig.12 is along Fig.11 A cross-sectional view taken along line CC'.

[0069] Reference Figures 8 to 12 , adjacent to each other and refer to Figure 8 The described pair of first sub-cell array SCA1 and second sub-cell array SCA2 may be disposed on a substrate 100. The pair of first sub-cell array SCA1 and second sub-cell array SCA2 may be composed of stacks SS1 and SS2. The stacks SS1 and SS2 may include a first layer L1, a second layer L2, and a third layer L3 vertically stacked on the substrate 100. Each of the first layer L1, the second layer L2, and the third layer L3 may include a pair of first conductive lines CL1 spaced apart from each other in a second direction D2 and a plurality of semiconductor patterns CP connected to each of the first conductive lines CL1.

[0070] Each of the semiconductor patterns CP may include a first sub-semiconductor pattern SP1, a second sub-semiconductor pattern SP2, a third sub-semiconductor pattern SP3, and a fourth sub-semiconductor pattern SP4. The second sub-semiconductor pattern SP2 may be disposed between the first sub-semiconductor pattern SP1 and the third sub-semiconductor pattern SP3. The third sub-semiconductor pattern SP3 may be disposed between the second sub-semiconductor pattern SP2 and the fourth sub-semiconductor pattern SP4.

[0071] The first sub-semiconductor pattern SP1 and the second sub-semiconductor pattern SP2 may be formed Figure 8 The third sub-semiconductor pattern SP3 and the fourth sub-semiconductor pattern SP4 may correspond to the first diode of the memory cell MC. Figure 8 The second diode of the memory cell MC corresponds to the first diode of the memory cell MC. As described above, the memory cell MC may be composed of a thyristor. The thyristor may include a first bipolar transistor composed of a first sub-semiconductor pattern SP1, a second sub-semiconductor pattern SP2, and a third sub-semiconductor pattern SP3, and a second bipolar transistor composed of a second sub-semiconductor pattern SP2, a third sub-semiconductor pattern SP3, and a fourth sub-semiconductor pattern SP4. The thyristor of the memory cell MC may have a floating body. The first conductive line CL1 may be stacked in the third direction D3 and may be spaced apart from each other. The first conductive line CL1 may be used as a reference Figure 8 Described cathode line CTL.

[0072] The third conductive line CL3 penetrating the stacks SS1 and SS2 may be arranged in the first direction D1. The third conductive line CL3 may be used as a reference. Figure 8 The third conductive line CL3 may be electrically disconnected or isolated from the substrate 100 .

[0073] The second conductive lines CL2 may be disposed on the substrate 100 to penetrate a region between the first subcell array SCA1 and the second subcell array SCA2. Each of the second conductive lines CL2 may be disposed between a pair of semiconductor patterns CP adjacent to each other in the second direction D2 when viewed in a plan view.

[0074] Each of the second conductive lines CL2 may extend vertically between the fourth sub-semiconductor pattern SP4 of the semiconductor pattern CP of the first sub-cell array SCA1 and the fourth sub-semiconductor pattern SP4 of the semiconductor pattern CP of the second sub-cell array SCA2. Each of the second conductive lines CL2 may be commonly connected to the fourth sub-semiconductor pattern SP4 of the semiconductor pattern CP of the first sub-cell array SCA1 and the fourth sub-semiconductor pattern SP4 of the semiconductor pattern CP of the second sub-cell array SCA2. The second conductive lines CL2 may be used as reference lines. Figure 8 Describe the common anode line CAL.

[0075] Although not shown, an empty space in the stack SS may be filled with an insulating material. For example, the insulating material may be formed of or include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0076] Will refer to Figures 10 to 12 Describe in more detail Fig. 9 The first sub-semiconductor pattern SP1, the second sub-semiconductor pattern SP2, the third sub-semiconductor pattern SP3, and the fourth sub-semiconductor pattern SP4 may be configured to correspond to the reference Figure 3 and Figures 5 to 7 The described first, second, third, and fourth sub-semiconductor patterns SP1, SP2, SP3, and SP4 have substantially the same features.

[0077] The semiconductor pattern CP may have a first end portion SPe1 and a second end portion SPe2 opposite to each other. The first sub-semiconductor pattern SP1 may be adjacent to the first end portion SPe1 of the semiconductor pattern CP. The fourth sub-semiconductor pattern SP4 may be adjacent to the second end portion SPe2 of the semiconductor pattern CP.

[0078] The first sub-semiconductor pattern SP1, the second sub-semiconductor pattern SP2, the third sub-semiconductor pattern SP3, and the fourth sub-semiconductor pattern SP4 may extend in parallel with the second direction D2, and all of the first sub-semiconductor pattern SP1, the second sub-semiconductor pattern SP2, the third sub-semiconductor pattern SP3, and the fourth sub-semiconductor pattern SP4 may have a first width W1. The first width W1 may be, for example, about 0.7 nm. The first conductive line CL1 may be disposed on the top surface SPt of the semiconductor pattern CP. The first conductive line CL1 may be connected to the first sub-semiconductor pattern SP1.

[0079] The third conductive line CL3 may be adjacent to the second sub-semiconductor pattern SP2. The third conductive line CL3 may be disposed on a sidewall of the second sub-semiconductor pattern SP2 and may extend in the third direction D3. The gate insulating layer GI may be disposed between the third conductive line CL3 and the second sub-semiconductor pattern SP2.

[0080] The second conductive line CL2 may be disposed adjacent to the second end portion SPe2 of the semiconductor pattern CP. The second conductive line CL2 may extend in the third direction D3. As an example, the second conductive line CL2 may be connected to the fourth sub-semiconductor pattern SP4.

[0081] In reference Figures 9 to 11 In the described semiconductor memory device, the third conductive line CL3 and the gate insulating layer GI may be omitted.

[0082] In the following, various exemplary embodiments will be described. In the following description, the previous reference Figures 8 to 12 The described elements may be identified by the same reference numerals without repeating their overlapping descriptions, and the elements not referred to will be described in detail. Figures 8 to 12 Describe the element.

[0083] Fig.13 is an enlarged perspective view illustrating a memory cell of a three-dimensional semiconductor memory device according to example embodiments. Fig.14 It shows Fig.13 A plan view of a memory cell. Fig.15 is along Fig.14 A cross-sectional view taken along line CC'.

[0084] Reference Figures 13 to 15 , the first conductive line CL1 may directly contact the first end portion SPe1 of the semiconductor pattern CP.

[0085] Fig.16 is an enlarged perspective view illustrating a memory cell of a three-dimensional semiconductor memory device according to example embodiments.

[0086] Reference Fig.16, the third conductive line CL3 may be disposed to surround the second sub-semiconductor pattern SP2. A gate insulating layer GI may be interposed between the third conductive line CL3 and the second sub-semiconductor pattern SP2. The transistor including the third conductive line CL3 may be a gate-all-around transistor.

[0087] Fig.17 is an enlarged perspective view illustrating a first memory cell and a second memory cell of a three-dimensional semiconductor memory device according to example embodiments. Fig.18 It shows Fig.17 A plan view of a first memory cell and a second memory cell.

[0088] Reference Fig.17 and Fig.18 , the first memory cell MC1 and the second memory cell MC2 may be arranged in the first direction D1. The third conductive line CL3 may be arranged adjacent to the semiconductor pattern CP. Each of the third conductive lines CL3 may include a first sub-conductive line CL3a and a second sub-conductive line CL3b. Each of the semiconductor patterns CP may be interposed between a corresponding pair of first sub-conductive lines CL3a and second sub-conductive lines CL3b. The first sub-conductive line CL3a may be adjacent to the first side wall SW1 of the second sub-semiconductor pattern SP2, and the second sub-conductive line CL3b may be adjacent to the second side wall SW2 of the second sub-semiconductor pattern SP2. The first sub-conductive line CL2a and the second sub-conductive line CL2b may be connected to the same node, and the first sub-conductive line CL2a and the second sub-conductive line CL2b may be applied with the same electrical signal. The first sub-conductive line CL3a or the second sub-conductive line CL3b may be used as a back gate electrode, and different electrical signals may be applied to the first sub-conductive line CL3a or the second sub-conductive line CL3b.

[0089] Fig.19 is an enlarged perspective view illustrating a first memory cell and a second memory cell of a three-dimensional semiconductor memory device according to example embodiments.

[0090] Reference Fig.19 , the shielded wire SM can be set at Fig.17 The shielding line SM may be disposed between the second sub conductive line CL2b of the first memory cell MC1 and the first sub conductive line CL2a of the second memory cell MC2. The shielding line SM may prevent adjacent third conductive lines CL3 from being electrically coupled to each other.

[0091] Fig. 20A is along Fig.14 A cross-sectional view taken along line CC'. Fig. 20B is along Fig.11 A cross-sectional view taken along line CC'.

[0092] Reference Fig. 20A The penetrating insulating pattern IP may be disposed to penetrate the first sub-semiconductor pattern SP1, the second sub-semiconductor pattern SP2, the third sub-semiconductor pattern SP3, and the fourth sub-semiconductor pattern SP4, and may contact the first conductive line CL1 and the second conductive line CL2. In addition to the above differences, the semiconductor memory device according to the present example embodiment may be similar to the reference Figures 1 to 19 The described semiconductor memory devices have substantially the same features.

[0093] Reference Fig. 20B , the penetration insulation pattern IP may be spaced apart from the first conductive line CL1 and may not contact the first conductive line CL1.

[0094] Fig.21 is a diagram showing a method according to an example embodiment Fig.13 A plan view of a memory cell.

[0095] Reference Fig.21 , the first sub-semiconductor pattern SP1 may have a second width W2 in the second direction D2. The second sub-semiconductor pattern SP2 may have a third width W3 in the second direction D2. The third sub-semiconductor pattern SP3 may have a fourth width W4 in the second direction D2. The fourth sub-semiconductor pattern SP4 may have a fifth width W5 in the second direction D2.

[0096] The third width W3 may be n times the fifth width W5, and the fourth width W4 may be m times the second width W2, where each of the numbers n and m is a positive integer. In example embodiments, the third conductive line CL3 may also have a third width W3 in the second direction D2.

[0097] By way of summary and review, expensive processing equipment is used to increase pattern fineness in semiconductor devices, and this expense may limit the cost-effective integration of two-dimensional or planar semiconductor devices. To overcome this limitation, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed.

[0098] As described above, the embodiments may provide a semiconductor memory device having improved integration density and which may operate with low power consumption.

[0099] According to example embodiments, a three-dimensional semiconductor memory device may include first to fourth sub-semiconductor patterns interposed between a first electrode and a second electrode and including a two-dimensional semiconductor material. This may enable a total vertical size of a memory cell to be reduced, and a retention current to be reduced. Therefore, it may be possible to provide a highly integrated semiconductor memory device that can operate with low power consumption.

[0100] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and explanatory sense only and not for the purpose of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, unless otherwise specifically stated, the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: a first electrode and a second electrode spaced apart from each other in a first direction; as well as a first semiconductor pattern in contact with both the first electrode and the second electrode, wherein: The first semiconductor pattern includes first to fourth sub-semiconductor patterns sequentially arranged in the first direction, The first sub-semiconductor pattern is in contact with the first electrode, The fourth sub-semiconductor pattern is in contact with the second electrode, The first sub-semiconductor pattern and the third sub-semiconductor pattern have a first conductivity type, The second sub-semiconductor pattern and the fourth sub-semiconductor pattern have a second conductivity type different from the first conductivity type, Each of the first to fourth sub-semiconductor patterns includes a transition metal and a chalcogenide element, The first sub-semiconductor pattern and the third sub-semiconductor pattern are made of MoS a or WS b form, The second sub-semiconductor pattern and the fourth sub-semiconductor pattern are made of MoSe c or WSe d form, Subscripts a to d are each independently a positive real number equal to or less than 2, and Subscript c is greater than subscript a and subscript b is greater than subscript d.

2. The semiconductor memory device according to claim 1, wherein Each of the first to fourth sub-semiconductor patterns includes the chalcogenide element in an amount that does not satisfy a stoichiometric ratio.

3. The semiconductor memory device according to claim 1 , further comprising a penetrating insulating pattern disposed to sequentially penetrate the first to fourth sub-semiconductor patterns and to contact the first electrode and the second electrode, in, The first to fourth sub-semiconductor patterns surround the through insulating pattern.

4. The semiconductor memory device according to claim 1, wherein: The first sub-semiconductor pattern and the third sub-semiconductor pattern have a first thickness and a third thickness in the first direction, respectively, and The third thickness is n times the first thickness, where n is a positive integer.

5. The semiconductor memory device according to claim 1, wherein: The second sub-semiconductor pattern and the fourth sub-semiconductor pattern have a second thickness and a fourth thickness in the first direction, respectively, and The second thickness is m times the fourth thickness, where m is a positive integer.

6. The semiconductor memory device according to claim 1, wherein: Each of the first sub-semiconductor pattern and the third sub-semiconductor pattern includes a first transition metal and a first chalcogenide element, and A content of the first chalcogenide element included in the first sub-semiconductor pattern is different from a content of the first chalcogenide element in the third sub-semiconductor pattern.

7. The semiconductor memory device according to claim 1, wherein: Each of the second sub-semiconductor pattern and the fourth sub-semiconductor pattern includes a second transition metal and a second chalcogenide element, and A content of the second chalcogenide element included in the second sub-semiconductor pattern is different from a content of the second chalcogenide element included in the fourth sub-semiconductor pattern.

8. The semiconductor memory device according to claim 1, further comprising: a third electrode adjacent to the second sub-semiconductor pattern; as well as A gate insulating layer is interposed between the second sub-semiconductor pattern and the third electrode.

9. The semiconductor memory device according to claim 8, wherein: The third electrode surrounds the second sub-semiconductor pattern.

10. The semiconductor memory device according to claim 1, wherein: The first electrode includes a plurality of first electrodes, the plurality of first electrodes are linear patterns extending in a second direction intersecting the first direction and spaced apart from each other in a third direction intersecting the first direction and the second direction, The second electrode includes a plurality of second electrodes, the plurality of second electrodes are linear patterns extending in the third direction and are spaced apart from each other in the second direction, and The first semiconductor pattern includes a plurality of first semiconductor patterns disposed at respective intersections of the plurality of first electrodes and the plurality of second electrodes.

11. The semiconductor memory device according to claim 10, further comprising a substrate disposed below the first electrode, wherein: The first direction and the second direction are parallel to the top surface of the substrate, and The third direction is perpendicular to the top surface of the substrate.

12. The semiconductor memory device according to claim 1, further comprising: a third electrode spaced apart from the second electrode in the first direction; as well as a second semiconductor pattern directly contacting the second electrode and the third electrode and spaced apart from the first electrode, wherein: The second semiconductor pattern includes fifth to eighth sub-semiconductor patterns sequentially disposed in a direction opposite to the first direction, The fifth sub-semiconductor pattern is in contact with the third electrode, The eighth sub-semiconductor pattern is in contact with the second electrode, the fifth sub-semiconductor pattern and the seventh sub-semiconductor pattern have the first conductivity type, The sixth sub-semiconductor pattern and the eighth sub-semiconductor pattern have the second conductivity type, and Each of the fifth to eighth sub-semiconductor patterns includes a transition metal and a chalcogenide element.

13. A semiconductor memory device comprising: a first electrode and a second electrode spaced apart from each other in a first direction; a semiconductor pattern in contact with both the first electrode and the second electrode; as well as a penetrating insulating pattern penetrating the semiconductor pattern, wherein: The semiconductor pattern includes first to fourth sub-semiconductor patterns sequentially arranged in the first direction, The penetration insulating pattern penetrates the first sub-semiconductor pattern to the fourth sub-semiconductor pattern, The first sub-semiconductor pattern is in contact with the first electrode, The fourth sub-semiconductor pattern is in contact with the second electrode, The first sub-semiconductor pattern and the third sub-semiconductor pattern have a first conductivity type, The second sub-semiconductor pattern and the fourth sub-semiconductor pattern have a second conductivity type different from the first conductivity type, The first sub-semiconductor pattern and the third sub-semiconductor pattern are made of MoS a or WS b form, The second sub-semiconductor pattern and the fourth sub-semiconductor pattern are made of MoSe c or WSe d form, Subscripts a to d are each independently a positive real number equal to or less than 2, and Subscript c is greater than subscript a and subscript b is greater than subscript d.

14. The semiconductor memory device according to claim 13, wherein: The penetration insulation pattern is spaced apart from the first conductive line and is in contact with the second conductive line.

15. The semiconductor memory device according to claim 13, wherein: Each of the first to fourth sub-semiconductor patterns includes a two-dimensional semiconductor material.

16. The semiconductor memory device according to claim 13, wherein: Each of the first to fourth sub-semiconductor patterns includes a transition metal and a chalcogenide element, and Each of the first to fourth sub-semiconductor patterns includes a chalcogenide element in an amount that does not satisfy a stoichiometric ratio.

17. A semiconductor memory device comprising: a first electrode and a second electrode spaced apart from each other in a first direction; as well as a semiconductor pattern in contact with both the first electrode and the second electrode, wherein: The first semiconductor pattern includes first to fourth sub-semiconductor patterns sequentially arranged in the first direction, The first sub-semiconductor pattern and the third sub-semiconductor pattern have a first width and a third width in the first direction, respectively. The third width is n times the first width, where n is a positive integer. The first sub-semiconductor pattern and the third sub-semiconductor pattern are made of MoS a or WS b form, The second sub-semiconductor pattern and the fourth sub-semiconductor pattern are made of MoSe c or WSe d form, Subscripts a to d are each independently a positive real number equal to or less than 2, and Subscript c is greater than subscript a and subscript b is greater than subscript d.

18. The semiconductor memory device according to claim 17, wherein: The second sub-semiconductor pattern and the fourth sub-semiconductor pattern have a second width and a fourth width in the first direction, respectively, and The second width is m times the fourth width, where m is a positive integer.

19. The semiconductor memory device according to claim 17, wherein: Each of the first to fourth sub-semiconductor patterns includes a two-dimensional semiconductor material.

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