Memory device and method of manufacturing the same

Abstract

A memory device and a method for manufacturing the same, wherein the memory device includes a stack of patterned conductor layers having at least a plurality of layers including conductive strips, the conductive strips including strips continuous with pads and other strips isolated from the pads. An array of vertical columns extending through the stack of patterned conductor layers, wherein memory cells are arranged at intersections between the vertical columns and the patterned conductor layers, the array having an array boundary adjacent to the pads. A first set of isolation blocks extending through the patterned conductor layers and separating the strips continuous with the pads from the other strips isolated from the pads. A second set of isolation blocks located within the array boundary and extending through the patterned conductor layers and isolating the other strips from the pads.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor and integrated circuit technology, and relates to a high-density memory device and a manufacturing method thereof, and more particularly to a memory device in which multiple planes of memory cells are configured to provide a three-dimensional array, including a virtual vertical structure for etching in three-dimensional NAND memory and other circuits. Background Art

[0002] As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have been looking for techniques to stack multiple memory cell planes in three-dimensional circuits to achieve greater storage capacity and lower cost per bit.

[0003] The three-dimensional memory may include blocks of memory cells arranged in a plurality of planes in an array region and word line pads in each plane of the pad region for connecting from the pads to word lines in the array region. Forming the plurality of planes may include etching patterns through multiple layers of material.

[0004] However, due to the differences in the structures formed during etching, the etching rate during etching of these patterns in the array region may be different from the etching rate during etching of these patterns in the pad region. Therefore, a cut may cut through a different number of layers in the array region than in the pad region. In order to cut the same number of conductive material layers in the array region and the pad region, two cuts with different etching rates may need to be used, which increases the cost of the manufacturing process.

[0005] It would be desirable to provide a structure for three-dimensional integrated circuit memory that is easier to manufacture. Summary of the invention

[0006] The present technology provides an easier to manufacture structure for three-dimensional integrated circuits, including memory circuits and other three-dimensional circuits, where the memory circuits have array regions and pad regions, and where the other three-dimensional circuits have regions of denser structures coupled to pad regions for vertical interconnection.

[0007] In the embodiments described herein, the integrated circuit structure includes a three-dimensional memory having an array region, wherein an array of vertical columns extends through multiple layers, wherein the horizontal conductive strips in each layer extend to pads in the pad region. The array region has a boundary adjacent to the pad region. An isolation block is disposed within the boundary of the array region, which separates the horizontal conductors from the pads. In some embodiments, other horizontal conductors are not separated from the pads by the isolation block, so that a cross-finger pattern can be formed in each layer. The vertical columns not used for the memory cells are arranged along the array boundary and between the isolation block and the pad region. The vertical columns used for the memory cells are arranged in an operational relationship with the horizontal conductors. The vertical columns can be vertical channel structures for vertical NAND series, and the horizontal conductors can be word lines.

[0008] This configuration of isolation blocks located within the array region can be formed using patterned etching, where slits are cut within the array boundary through the stack of patterned conductor layers to simultaneously pattern the patterned conductor layers of the series through the array and pattern the ends of the conductive strips isolated from the pads. Since the etch rate for simultaneously etching the ends and sides of the conductive lines within the array region is more uniform, the isolation blocks for the ends of the conductive strips are placed within the array region, thereby making it possible to use a single cut using a single mask for the slits. This can form an array region including a region including vertical pillars for memory cells, and including vertical pillars not used for memory cells in this region adjacent to the pads that can extend through the pads. Since the etch rates for passing through the vertical pillars for memory cells and the vertical pillars not used for memory cells are the same or similar, a single cut can cut through the same number of patterned conductor layers for the vertical pillars for memory cells and the vertical pillars not used for memory cells within the array boundary.

[0009] In addition, in embodiments described herein, the integrated circuit structure includes a three-dimensional memory having an array region, wherein an array of vertical pillars extends through multiple layers, wherein the horizontal conductive strips in each layer extend to pads in the pad region. The memory may include blocks of multiple memory cells, wherein each block may include an array region and a pad region as described above. In embodiments including multiple memory blocks, the array region may be extended to the region between the memory blocks by forming a pattern of vertical pillars in the region between the multiple memory blocks. The array region has a boundary adjacent to the pad region. The isolation block is arranged to extend through the extended region of the array region to separate the patterned conductor layer between adjacent memory blocks. The vertical pillars not used for the memory cells are arranged between the multiple memory blocks. This enables the use of the same single cut using the same single mask to be used to etch the stack of memory block boundary slits across the vertical pillars not used for the memory cells through the patterned conductor layer.

[0010] A memory device is described, comprising a stack of patterned conductor layers, having at least a plurality of layers, the at least a plurality of layers comprising interdigitated conductive strips, the interdigitated conductive strips comprising strips continuous with pads and other strips isolated from the pads. An array of vertical pillars may extend through the stack of patterned conductor layers, wherein memory cells are arranged at intersections between the vertical pillars and the patterned conductor layers. The array has an array boundary adjacent to the pads. A first group of isolation blocks may extend through the patterned conductor layers and separate strips continuous with the pads from other strips isolated from the pads. A second group of isolation blocks located within the array boundary may extend through the patterned conductor layers and isolate other strips from the pads. The array boundary may extend into the pads through one or more vertical pillars and beyond the ends of isolation blocks in the first group of isolation blocks. The second group of isolation blocks may include isolation blocks connecting a pair of adjacent isolation blocks in the first group of isolation blocks. Some vertical pillars between the pads and other strips isolated from the pads may be penetrated by isolation blocks in the second group of isolation blocks within the array boundary. The device may include a second pad, wherein a stripe continuous with the first pad may be separated from the second pad at an end adjacent to the second pad, and a stripe continuous with the second pad may be separated from the first pad at an end adjacent to the first-mentioned pad.

[0011] The device may include a block of vertical pillars and a third pad, the block of vertical pillars being located within the array boundary, the third pad being disposed opposite the first-mentioned pad in a second direction orthogonal to the first direction. The device may include first and second boundary rows of vertical pillars, the first and second boundary rows of vertical pillars extending through the stack of patterned conductor layers in the first direction. The first boundary row and the second boundary row may be disposed adjacent to and across the first pad and the block of vertical pillars, wherein the vertical pillars in the first boundary row and the second boundary row may not be used for memory cells. A block isolation structure extending through the stack of patterned conductor layers may separate the first-mentioned pad from the third pad, wherein the vertical pillars in the first boundary row and the second boundary row may contact a side of the block isolation structure. The device may include a second block of vertical pillars, the second block of vertical pillars being disposed opposite the first block of vertical pillars in the second direction, wherein the block isolation structure may separate the first-mentioned block of vertical pillars from the second block of vertical pillars.

[0012] A method for manufacturing a memory device as described herein is also provided.

[0013] Other aspects and advantages of the invention will be apparent from a review of the drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A simplified layout diagram of an exemplary three-dimensional memory device taken at a patterned conductor layer is shown.

[0015] Figure 2 is a simplified layout diagram of an exemplary 3D memory device showing isolation structures separating a pad from another pad and separating a block of vertical pillars from another block of vertical pillars.

[0016] Figure 3 A more detailed layout diagram of an exemplary three-dimensional memory device is shown taken at a patterned conductor layer including an array extending into a bonding pad.

[0017] Figures 4 to 13 Stages of an exemplary fabrication method for a memory device according to an embodiment are shown.

[0018] Figure 4 , Figure 5 , Figure 5A , Figure 6 , Fig. 6A Stages of a process flow for forming an array of holes through a stack of patterned conductor layers are shown.

[0019] Figure 7 and Fig. 7A The stage of the process flow is shown after the vertical pillars are formed on the sidewalls of the holes.

[0020] Figure 8 and Fig. 8A The stage of the process flow is shown after the holes are filled with insulating material.

[0021] Fig. 9 A photoresist hard mask is shown, which is suitable for use in Figure 4 A first set of slits and a second set of slits are etched over the structure shown.

[0022] Fig.10 Show use of e.g. Fig. 9 The stage of the process flow shown after a single photoresist hard mask has been used to etch a first set of slits and a second set of slits through the stack of conductor layers.

[0023] Fig.11 The stage of the process flow is shown after forming the first set of isolation blocks and the second set of isolation blocks.

[0024] Fig.12 and Fig. 12A The stage of the process flow is shown after forming a common source line and a set of bit lines coupled to vertical pillars for storing memory cells.

[0025] Fig.13 Vertical columns not used for storage cells are shown.

[0026] Fig.14 is a flow chart illustrating a method for manufacturing a memory device.

[0027] Fig.15A , Fig. 15B and Fig. 15C An alternative embodiment of vertical pillars not used for memory cells is shown, wherein the vertical pillars not used for memory cells are located within the array boundary between the bonding pads and the plurality of vertical pillars used for memory cells.

[0028] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D An alternative embodiment of a vertical pillar contacting the block isolation structure is shown.

[0029]

Explanation of symbols

[0030] 10-16, 20-26, 31-37, 41-47: vertical columns

[0031] 100: Simplified layout diagram

[0032] 111~115: Strip

[0033] 116: Bottom row

[0034] 121, 122, 123, 124: Solder pads

[0035] 131-136, 140-146, 141a, 142a: Isolation blocks

[0036] 151-155, 161-165: Boundary section

[0037] 170: Block Isolation Structure

[0038] 171: First border row of vertical column

[0039] 172: Second border line of vertical column

[0040] 200: Simplified layout diagram

[0041] 210, 220: Block

[0042] 322: Solder pad

[0043] 340, 341: Horizontal conductor

[0044] 342: Extension

[0045] 345: The End

[0046] 350: Boundary section

[0047] 315-319, 324-328, 361-364: Vertical columns

[0048] 400: Simplified layout diagram

[0049] 405, 430: Array area

[0050] 410: OK

[0051] 414-416: Hole

[0052] 420: OK

[0053] 423-425: Hole

[0054] 431, 432, 433, 434: Solder pad area

[0055] 470: Sub-area

[0056] 480: Boundary row of holes

[0057] 511~515:Insulation layer

[0058] 520: Top floor

[0059] 525: Top insulation layer

[0060] 675: Hole Etching Level

[0061] 710: Data storage structure

[0062] 713: Horizontal layers of data storage structure

[0063] 720: Semiconductor Film

[0064] 723: Horizontal semiconductor film

[0065] 830: Insulation materials

[0066] 901~904,910~916:Mask area

[0067] 931~936,940~946,941a,942a,960:Opening etching area

[0068] 1031~1036,1040~1046,1041a,1042a:Slit

[0069] 1001-1003: Vertical columns

[0070] 1070: Block boundary gap

[0071] 1251, 1252: Plug

[0072] 1260: Common source line (CSL)

[0073] 1271~1273: Bit line contact window

[0074] 1275: Slit Etching Level

[0075] 1282: Connecting column

[0076] 1291-1293: bit line (BL)

[0077] 1410, 1420, 1430, 1440, 1450, 1460 Steps 1501, 1504, 1511-1518, 1521, 1522, 1528, 1531-1538, 1541, 1551-1560: Vertical column

[0078] 1590: Array Boundary

[0079] 1591, 1592: Blocks

[0080] 1595: Solder pad

[0081] 1601, 1611, 1621, 1631: vertical columns

[0082] GSL ground selection line

[0083] IG inversion gate layer

[0084] P: Spacing

[0085] SSL: Serial Select Line

[0086] W, W1, W2, W3, W4, W5, W6: Width

[0087] WL: Word Line

[0088] X: First direction

[0089] Y: Second direction DETAILED DESCRIPTION

[0090] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0091] The following description will typically refer to specific structural embodiments and methods. It is to be understood that the present technology is not intended to be limited to the specific disclosed embodiments and methods, and the present technology can be implemented using other features, elements, methods and embodiments. The preferred embodiments are described to illustrate the present technology and are not intended to limit the scope thereof, which is defined by the claims. Those skilled in the art will appreciate the diversity of equivalent variations of the following description.

[0092] Figure 1 A simplified layout diagram 100 of an exemplary three-dimensional memory device is shown taken at a patterned conductor layer in a stack of patterned conductor layers. Figure 1 As shown in the example of , the three-dimensional memory device includes interdigitated conductive strips, which include strips (111, 113, 115) continuous with the pad 121 and other strips (112, 114) isolated from the pad (121). The interdigitated conductive strips (111, 113, 115; 112, 114) extend along a first direction (X).

[0093] The device may include a second pad 122, wherein a strip (111, 113, 115) continuous with the first-mentioned pad 121 is separated from the second pad at an end adjacent to the second pad, and a strip (112, 114) continuous with the second pad 122 is separated from the first-mentioned pad at an end adjacent to the first pad.

[0094] As used herein, a pad refers to an area in a patterned conductor layer in a stack of patterned conductor layers, wherein the area is connected to a conductive strip formed in the patterned conductor layer and provides a connection to, for example, a metal line level through an interlayer connector to connect to a decoding circuit. In an embodiment, the conductive strip may serve as a word line or a bit line. A stack of pads may be formed to connect conductive strips formed in a corresponding patterned conductor layer, and provide a connection to a corresponding global wire through a corresponding interlayer connector. The stack of pads may be formed in a stepped structure, wherein a corresponding interlayer connector is formed on a corresponding pad in a corresponding patterned conductor layer.

[0095] An array of vertical pillars (10-16, 20-26, 31-37, 41-47) may extend through the stack of patterned conductor layers, wherein memory cells may be disposed at intersections between the vertical pillars and the patterned conductor layers. The vertical pillars may include data storage structures and semiconductor films.

[0096] The array of vertical pillars has an array boundary near the pad. The array boundary may include a plurality of boundary segments 151-155. The array of vertical pillars may include a block 210 of vertical pillars located within the array boundary, wherein the array boundary is located, for example, at Figure 1 Between the first boundary section 151 on the left side and the second boundary section 152 on the right side relative to the first boundary section 151 in the first direction X.

[0097] For purposes of illustration, the array boundary is defined by lines extending along the outer edges of the vertical columns on the perimeter of the pattern of vertical columns. The vertical columns on the perimeter include vertical columns disposed at the ends of rows of vertical columns in the block 210 of vertical columns. For example, a first boundary segment 151 may be aligned with the outer edge of vertical column 10 at the end of a row of vertical columns (10-16) adjacent to a first pad. For example, a second boundary segment 152 may be aligned with the outer edge of vertical column 37 at the end of another row of vertical columns (31-37) adjacent to a second pad 122. For example, a third boundary segment 153 may be aligned with the bottom edge of the bottom row 116 of vertical columns in the block 210 of vertical columns.

[0098] The first group of isolation blocks (131-136) extending through the plurality of patterned conductor layers can separate the conductive strips (111, 113, 115) continuous with the pad 121 from the other strips 112, 114 isolated from the pad 121. Similarly, the first group of isolation blocks (131-136) extending through the plurality of patterned conductor layers can separate the conductive strips (112, 114) continuous with the second pad 122 from the other strips 111, 113, 115 isolated from the pad 122.

[0099] A second set of isolation blocks (140-146) located within the array boundary and extending through multiple patterned conductor layers can isolate other strips from the pads. For example, isolation blocks 142 and 144 in the second set of isolation blocks can isolate other strips 112, 114 from the pad 121. Similarly, isolation blocks 141, 143, and 145 in the second set of isolation blocks can isolate other strips 111, 113, 115 from the second pad 122. The second set of isolation blocks can include isolation blocks (141, 142), and isolation blocks (141, 142) connect adjacent isolation blocks (131 and 132; 132 and 133) in the first set of isolation blocks.

[0100] In addition, a pair of isolation blocks (141 and 141a, 142 and 142a) located within the array boundary can isolate other strips from the pad. For example, a pair of isolation blocks 142 and 142a located within the array boundary can isolate other strips 112 from the pad 121, and a pair of isolation blocks 141 and 141a in the second group of isolation blocks can isolate other strips 111 from the pad 122.

[0101] The etch rate through the stack of patterned conductor layers in pads (121, 122) without holes outside the array boundary may be much slower than the etch rate through the stack of patterned conductor layers in the block 210 of vertical pillars within the array boundary.

[0102] The etching rate for etching the second set of isolation blocks (140-146) located within the array boundary through the vertical pillars not used for memory cells can be the same as the etching rate for etching the first set of isolation blocks through the vertical pillars used for memory cells. Therefore, a single cut using a single mask can be used to etch slits at the same etch rate for the first set of isolation blocks and the second set of isolation blocks.

[0103] The device may include a first boundary row 171 of the vertical column and a second boundary row 172 of the vertical column, wherein the second boundary row 172 of the vertical column is arranged to be adjacent to and span a block 210 of the vertical column, a first pad 121 and a second pad 122, wherein the first pad 121 and the second pad are relatively arranged across the block of the vertical column in a first direction (X).

[0104] The fourth boundary segment 154 of the array boundary may be aligned with the bottom edge of the vertical column in the second boundary row 172 of vertical columns adjacent to the first pad 121. The fifth boundary segment 155 of the array boundary may be aligned with the bottom edge of the vertical column in the second boundary row 172 of vertical columns adjacent to the first pad 122. The fourth boundary segment 154 and the fifth boundary segment 155 are disposed opposite to each other across the block 210 of vertical columns in the first direction (X).

[0105] The device may include a block isolation structure 170 extending through the stack of patterned conductor layers to isolate a first boundary row 171 of vertical pillars from a second boundary row 172 of vertical pillars. An adjacent memory block, not shown, may be disposed above the block isolation structure 170. The vertical pillars in the first boundary row and the second boundary row contact the side of the block isolation structure. The vertical pillars in the first boundary row and the second boundary row are not used for memory cells and may be referred to as dummy vertical structures. Figure 2 The block isolation structure 170 is further described.

[0106] In an embodiment, the vertical pillars in the block of vertical pillars and the vertical pillars in the first boundary row and the second boundary row may have a common pitch and a common width in the first direction.

[0107] Figure 2 A simplified layout diagram 200 of an exemplary three-dimensional memory device is shown, showing a block isolation structure that separates a pad from another pad and separates a block of vertical columns from another block of vertical columns. Figure 2 As shown in the example of , the device may include a first vertical column block 210 located within a first array boundary and a second vertical column block 220 located within a second array boundary, and the first vertical column block 210 and the second vertical column block 220 are arranged opposite to each other in the second direction (Y). Figure 1 As described, the first array boundary may include a plurality of boundary segments 151-155. Similarly, the second array boundary may include a plurality of boundary segments 161-165.

[0108] The device may include a third pad 123 disposed opposite to the first pad 121 in a second direction (Y), the second direction (Y) being orthogonal to the first direction (X), wherein the conductive strip extends along the first direction (X). Similarly, the device may include a fourth pad 124 disposed opposite to the second pad 122 in the second direction (Y).

[0109] The first boundary row 171 of vertical columns and the second boundary row 172 of vertical columns may extend through the stack of patterned conductor layers in the first direction. The first boundary row and the second boundary row may be disposed adjacent to and across the first pad 121, the block 210 of the vertical columns, and the second pad 122. Similarly, the first boundary row and the second boundary row may be disposed adjacent to and across the third pad 123, the second block of the vertical columns 220, and the fourth pad 124. The vertical columns in the first boundary row and the second boundary row may not be used for memory cells.

[0110] The block isolation structure 170 extending through the stack of patterned conductor layers may separate the first pad 121 from the third pad 123, the second pad 122 from the fourth pad 124, and the first block 210 of vertical pillars from the second block 220 of vertical pillars. The vertical pillars in the first and second boundary rows may contact the side of the block isolation structure.

[0111] Figure 3 A more detailed layout diagram of an exemplary three-dimensional memory device is shown taken at a patterned conductor layer including an array extending into a pad. Figure 3 As shown in the example of , the array may extend into the pad 322 through one or more vertical pillars (361-364) beyond the ends 345 of the isolation blocks 131 and 132 in the first group of isolation blocks. The array may have an array boundary having a boundary segment 350, wherein the boundary segment 350 is aligned with the outer edge of the vertical pillar 362 at the end of the row of vertical pillars (315-319, 361-362) adjacent to the pad 322. In this example, the horizontal conductors 340 and 341 are continuous with the pad 322 partially through the extension 342 of the array area to provide electrical connection to the pad and to provide electrical connection to the layer conductors that contact the pad.

[0112] like Figure 3 As shown in the example of , the second group of isolation blocks may include isolation blocks (141, 141a) connecting a pair of adjacent isolation blocks (131, 132) in the first group of isolation blocks.

[0113] The isolation blocks (e.g., 141, 141a) in the second group of isolation blocks located in the array boundary section 350 may penetrate some vertical pillars (317, 319, 326) between the pad (e.g., 322) and the end of the strip 111, and the vertical pillars (317, 319, 326) may be referred to as virtual vertical pillars. The vertical pillars (315, 316, 324, 325) used for the memory cells and the vertical pillars (318, 327, 328) not used for the memory cells may have a common pitch P and a common width W in the first direction X. The vertical pillars (318, 327, 328) not used for the memory cells may be referred to as virtual vertical pillars.

[0114] Figures 4 to 13 Stages of an exemplary manufacturing process for a memory device are shown in accordance with an embodiment.

[0115] Figure 4 A simplified layout diagram 400 of an exemplary three-dimensional memory device is shown showing an array of holes within an array boundary at a patterned conductor layer in a stack of patterned conductor layers. Figure 4 As shown in the example of FIG. 4 , the array of holes may include a block of holes in a first array region 405 including rows (410, 420) of holes. The array boundary adjacent to the pad region (431, 432) may include a plurality of boundary segments 151-155, wherein the pad region is a region where a pad (e.g., Figure 1 The hole block can be set in the area of ​​121, 122. Figure 4 Between a first boundary segment 151 on the left side in the first direction X and a second boundary segment 152 on the right side relative to the first boundary segment in the first direction X.

[0116] like Figure 4 As shown in the example of , the simplified layout diagram may include a boundary row 480 of holes, which is arranged adjacent to and across the block of holes, the first pad area 431 and the second pad area 432. The third pad area 433 and the fourth pad area 434 are arranged across the boundary row 480 of holes in the second direction Y relative to the first pad area 431 and the second pad area 432, respectively. The second block of holes in the second array area 430 is arranged across the boundary row 480 of holes in the second direction Y relative to the first block of holes.

[0117] The fourth border segment 154 of the array border may be from the bottom edge of the holes in the border row 480 of holes adjacent to the first pad area 431. The fifth border segment 155 of the array border may be from the bottom edge of the holes in the border row 480 of holes adjacent to the second pad area 432.

[0118] Figure 5 and Figure 5A The stage of the process flow after forming a stack of patterned conductor layers separated by insulating layers is shown. Figure 5 A top insulating layer 525 is shown over the stack of patterned conductor layers. Figure 5A is along Figure 5 The line A-A' shown is taken Figure 5A vertical cross-section of a structure in which line AA' is along a second direction orthogonal to the first direction (X-direction). In one embodiment, the stack of patterned conductor layers may include a bottom conductor layer, a top conductor layer, and a plurality of intermediate conductor layers between the top conductor layer and the bottom conductor layer, wherein the bottom conductor layer may be used as an inversion gate layer (IG) or a layer for assisting the gate, the top conductor layer may be etched to form a serial selection line (SSL) or a ground selection line (GSL), and these intermediate conductor layers may be etched to form word lines (WL). In an alternative embodiment, the stack of patterned conductor layers may include a bottom conductor layer, a top conductor layer, and a plurality of intermediate conductor layers between the top conductor layer and the bottom conductor layer, wherein the bottom conductor layer may be used as a ground selection line (GSL), the top conductor layer may be etched to form a serial selection line (SSL), and these intermediate conductor layers may be etched to form word lines (WL). These intermediate conductor layers may include N layers, wherein N is greater than 2. These intermediate conductor layers may be etched to form dummy word source lines that are not coupled to memory cells or used to control the operation of memory cells. The conductor layer may have various materials including doped semiconductors, metals, and conductive compounds, including materials of Si, Ge, SiGe, SiC, TiN, TaN, W, and Pt.

[0119] like Figure 5A As shown in the example of , insulating layers 511-515 separate the conductor layers. The insulating layers may include silicon oxide or other dielectrics on the semiconductor substrate. In this example, a top layer 520 of silicon nitride may be disposed on the stack of conductor layers, and a top insulating layer 525 may be disposed on the top layer 520 of silicon nitride.

[0120] Figure 6 and Fig. 6A The stage of the process flow is shown after forming an array of holes through the stack of conductor layers. Figure 6 yes Figure 4 A magnified view of a sub-region 470 in FIG. 4, which includes holes from two rows of holes. Figure 6 In the example of , a first row 410 of holes (414-416) and a second row 420 of holes (423-425) are arranged along a first direction (X direction). In one embodiment, each hole in a row may have an elliptical cross-section with a major axis in a second direction (Y direction). In an alternative embodiment, each hole in a row may have an elliptical cross-section with a major axis inclined relative to the first direction (X direction). In other embodiments, the holes may have other horizontal cross-sectional shapes, including circular, diamond, square, and rectangular.

[0121] Fig. 6A It is taken along line A-A' Figure 6. The holes in the rows of holes are etched through the top insulating layer 525, the top layer 520 of silicon nitride, the top conductive layer (SSL / GSL), the intermediate conductor layers (WL), and partially through the bottom conductive layer (IG). The etching process may stop at the hole etch level 675 in the bottom conductive layer (IG).

[0122] Figure 7 and Fig. 7A A stage of a process flow is shown after forming vertical pillars on the sidewalls and bottom surfaces of holes in an array of holes, where the vertical pillars may include data storage structures and semiconductor films. Fig. 7A is along Figure 7 The line A-A' shown is taken Figure 7 A vertical cross section showing a U-shaped channel.

[0123] The data storage structure 710 is deposited on the sidewalls of the hole and is located above the bottom of the hole and above the top insulating layer 525. The semiconductor film 720 is deposited above and in contact with the data storage structure 710, thereby forming a U-shaped channel. The data storage structure 710 includes a horizontal layer 713 of the data storage structure in the hole, and the semiconductor film 720 includes a horizontal semiconductor film 723 disposed above the horizontal layer 713 of the data storage structure. At this stage of the process flow, the data storage structure 710 can be deposited on the boundary rows (480, Figure 4 ) on the sidewalls of the holes in the hole, and the semiconductor film 720 can be deposited over and in contact with the data storage structure 710 in the boundary row of the holes.

[0124] The semiconductor film (eg, 720) may include a semiconductor material suitable for use as a channel of a memory cell, such as materials such as Si, Ge, SiGe, GaAs, SiC, and graphene. The data storage structure (e.g., 710) may include a multi-layer data storage structure known in flash memory technology, including, for example, the following flash memory technologies: Oxide-Nitride-Oxide (ONO), Oxide-Nitride-Oxide-Nitride-Oxide (ONONO), silicon-oxide-nitride-oxide-silicon (SONOS), bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS), tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS, and metal-high-k bandgap-engineered silicon-nitride-oxide-silicon (BE-SONOS). silicon-oxide-nitride-oxide-silicon, MA BE-SONOS).

[0125] Figure 8 and Fig. 8A The stage of the process flow after the holes in the row of the plurality of holes are filled with insulating material 830 is shown. Fig. 8A Shown along Figure 8 The line A-A' shown is taken Figure 8 830 is also deposited on the top surface of the semiconductor film 720. At this stage of the process flow, the insulating material 830 can be used to fill the boundary rows of holes (480, Figure 4 ) in the hole.

[0126] Fig. 9 The photoresist hard mask in this example is shown, which is suitable for use in Figure 4 The first set of slits and the second set of slits are etched above the structure shown. The hard mask is patterned to define mask regions (e.g., 901-904, 910-916) and open etching regions (e.g., 940-945, 931-936, 960). The mask regions correspond to the pads (121, 122, Figure 1 ) continuous interdigitated conductive strips (111-115, Figure 1) and other strips isolated from the pads. A first group of open etched regions (931-936) extending in a first direction (X) corresponds to a first group of isolation blocks (131-136, Figure 1 The second group of open etched regions (940-946, 941a, 942a) extending in the second direction (Y) corresponds to the second group of isolation blocks (140-146, 141a, 142a, Figure 1 The third group of opening etching regions (960) corresponds to the block isolation structure (170, Figure 1 ). The open etch area is not protected by the mask area and will be removed.

[0127] Fig.10 Show use of e.g. Fig. 9 The stage of the process flow after a single photoresist hard mask is used to etch a first set of slits and a second set of slits through the stack of conductor layers. The second set of slits is located at Figure 4 The array boundaries are shown. Fig.10 As shown in the example of, the first group of slits includes slits (1031-1036), and the slits (1031-1036) are arranged to span the holes in the row of respective holes. The second group of slits includes slits (1040-1046, 1041a, 1042a), and the slits (1040-1046, 1041a, 1042a) connect adjacent slits in the first group of slits at the ends. The first group of slits extends in a first direction (X), and the second group of slits extends in a second direction (Y) orthogonal to the first direction.

[0128] The first group of slits and the second group of slits are etched through the stack of conductor layers to form interdigitated conductive strips, wherein the interdigitated conductive strips include strips that are continuous with the pads and other strips that are isolated from the pads. For example, the conductive strips (111, 113, 115) are continuous with the first pad (121), and the other strips (112, 114) are isolated from the pad (121). For example, the conductive strips (112, 114) are continuous with the second pad (122), and the other strips (111, 113, 115) are isolated from the second pad (122).

[0129] At this stage of the process flow, the block boundary slits 1070 can be etched through the conductor layer using the same single photoresist hard mask. The block boundary slits are arranged to span the boundary rows of holes (480, Figure 4 ) in which a boundary row 480 of the holes is arranged to be adjacent to and span the first pad area 431, the second pad area 432 and the first array area 405.

[0130] Fig.11The process flow of forming a first set of isolation blocks and a second set of isolation blocks through a patterned conductor layer is shown. For example, the first set of isolation blocks and the second set of isolation blocks can be formed by filling the first set of slits and the second set of slits with an insulating material in a single filling operation. The first set of isolation blocks (131-136) can separate strips (111, 113, 115) that are continuous with the pad (121) from other strips that are isolated from the pad. The second set of isolation blocks (140-146, 141a, 142a) located within the array boundary can isolate other strips (112, 114) from the pad (121).

[0131] The second group of isolation blocks may include an isolation block (e.g., 141) that connects a pair of adjacent isolation blocks (e.g., 131, 132) in the first group of isolation blocks. Some vertical columns (1001-1003) between the pad 122 and the end of the strip 111 may be penetrated by isolation blocks (e.g., 141, 141a) in the second group of isolation blocks within the array boundary.

[0132] At this stage of the process flow, the block isolation structure 170 may be formed in the block boundary slots (1070, Fig.10 ). The vertical pillars in the first boundary row (171) of vertical pillars and the second boundary row (172) of vertical pillars may contact the side of the block isolation structure and are not used for the memory cell. The block isolation structure 170 may separate the first pad region (431, Figure 4 ) and the third pad area (433, Figure 4 ) are separated, the second pad area (432, Figure 4 ) and the fourth pad area (434, Figure 4 ) are separated, and the first array region (405, Figure 4 ) and the second array region (430, Figure 4 )separate.

[0133] Fig.12 and Fig. 12A The process flow is shown at a stage after forming a common source line 1260 and a set of bit lines 1291-1293, wherein the set of bit lines 1291-1293 are coupled to a plurality of vertical pillars for memory cells through bit line contacts 1271-1273, respectively. The common source line CSL 1260 may extend in a first direction (X direction) and the set of bit lines may extend in a second direction (Y direction). Fig. 12A The figure shows a section taken along line A-A'. Fig.12 A vertical section of Fig.11 Line A-A' is shown.

[0134] Deposited in the hole ( Figure 8) can be etched back to form a groove in the hole, and the conductive material can be deposited in the groove. Stages of the process flow for forming the first set of isolation blocks and the second set of isolation blocks ( Fig.11 ) may include etching the conductive material in the groove to form a first plug (1251) and a second plug (1252) above the top surface of the insulating material 830 in the holes in the row of the plurality of holes, wherein the first plug and the second plug are connected to the semiconductor film 720. The etching process for etching the gap ( Fig.10 ) may stop at a slit etch level 1275 in the bottom conductive layer (IG). The slit etch level 1275 is disposed below the plurality of conductor layers (WL) and above the horizontal semiconductor film 723, wherein the horizontal semiconductor film 723 is disposed above the bottom surface of the holes in the row of the plurality of holes. In a memory architecture including a U-shaped channel, the bottom of the U-shaped channel (e.g., the horizontal semiconductor film 723) must be well connected. In other words, a cut through the hole must not pass through the bottom of the U-shaped channel in the hole.

[0135] The common source line CSL 1260 is connected to the first plug 1251 and the top surface of the semiconductor film 720. The bit line contact window 1272 is connected to the second plug 1252 and the top surface of the semiconductor film 720. The via 1282 is connected to the bit line contact window 1272. The bit line BL 1292 is connected to the vertical semiconductor film 720 through the bit line contact window 1272 and the via 1282.

[0136] Fig.13 The vertical columns not used for storage cells are shown. First, refer to Fig.11 , the array of vertical pillars may include vertical pillars (10, 11, 20) not used for storage cells, wherein the vertical pillars (10, 11, 20) not used for storage cells are arranged between the pad 121 and a plurality of vertical pillars (12-16, 21-25) used for storage cells, wherein the vertical pillars (12-16, 21-25) used for storage cells are located in a conductive strip 111 continuous with the pad 121. The array of vertical pillars may include vertical pillars 41 not used for storage cells, wherein the vertical pillars 41 not used for storage cells are arranged between the pad 121 and a plurality of vertical pillars (31-35, 42-46) used for storage cells, wherein the vertical pillars (31-35, 42-46) used for storage cells are located in other conductive strips 112 isolated from the pad 121.

[0137] Fig.13 Shown along Fig.11 A vertical cross section of a vertical column 11 not used for a storage unit taken along the line BB' in Fig.11 A vertical cross section of a vertical column 41 not used for a storage unit taken along line CC' in FIG. Fig.13 The structure shown in Fig.12 and Fig. 12A The difference between the structures shown is that in the finished product, the common source line 1260 and Fig.12 and Fig. 12A The set of bit lines 1291-1293 shown coupled to vertical pillars for memory cells may not be coupled to the same Fig.13 The vertical columns shown are not used for storage units. Fig.13 The vertical columns not used for storage cells shown may also not be coupled to the Fig.12 and Fig. 12A The bit line contact window 1272 and the via 1282 are shown.

[0138] Fig.14 is a flow chart illustrating a method for manufacturing a memory device. At step 1410, an array of holes may be formed by a stack of patterned conductor layers separated by insulating layers. This step is further described in Figure 4 , Figure 5 , Figure 5A , Figure 6 and Fig. 6A middle.

[0139] In step 1420, an array of vertical pillars may be formed in the holes in the array of holes to extend through the stack of patterned conductor layers. For example, the vertical pillars may include data storage structures and semiconductor films, wherein the semiconductor films are formed on the sidewalls of the holes in the array of holes. This step is further described in Figure 7 , Fig. 7A , Figure 8 and Fig. 8A middle.

[0140] In step 1430, a first set of slits and a second set of slits may be etched through the stack of patterned conductor layers using a single mask. The first set of slits may be arranged to span holes in a row of corresponding holes, and the second set of slits may include slits that connect adjacent slits in the first set of slits at their ends. Some vertical columns between pads and other strips isolated from the pads may be penetrated by isolation blocks in the second set of isolation blocks within the array boundary. This step is further described in Fig. 9 and Fig.10 middle.

[0141] In step 1440, interdigitated conductive strips may be formed including strips continuous with the pads and other strips isolated from the pads. Memory cells may be disposed at intersections between vertical pillars and the patterned conductor layer. The array of vertical pillars may have an array boundary adjacent to the pads. In this step, a second pad (122) may be etched, wherein a strip continuous with the first pad (121) is separated from the second pad at an end adjacent to the second pad, and a strip continuous with the second pad is separated from the second pad at an end adjacent to the first mentioned pad. This step is further described in Fig.10 middle.

[0142] In an embodiment, the array boundary may extend to the bonding pad and across the ends of the isolation blocks in the first group of isolation blocks via one or more vertical pillars.

[0143] In step 1450, a first set of isolation regions (131-136) may be formed in a first set of slits through the plurality of patterned conductor layers to separate strips that are continuous with the pads from other strips that are isolated from the pads. This step is further described in Fig.11 middle.

[0144] In step 1460, a second set of isolation blocks may be formed in a second set of slits within the array boundary and extending through the plurality of patterned conductor layers to isolate other strips from the pads. The second set of isolation blocks may include isolation blocks that connect adjacent isolation blocks in the first set of isolation blocks at ends adjacent to the pads. This step is further described in Fig.11 middle.

[0145] The array of vertical pillars may include a plurality of vertical pillars for memory cells in a strip continuous with the pad and a plurality of vertical pillars not used for memory cells, wherein the plurality of vertical pillars not used for memory cells are disposed between the pad and the plurality of vertical pillars for memory cells. The method may include forming a set of bit lines, the set of bit lines being coupled to the plurality of vertical pillars for memory cells in a strip continuous with the pad, and the set of bit lines being not coupled to the vertical pillars not used for memory cells.

[0146] The array of vertical pillars may include a block of vertical pillars and a third pad, the block of vertical pillars being located within the array boundary, the third pad being arranged opposite the first mentioned pad in a second direction orthogonal to the first direction, wherein the conductive strip extends along the first direction.

[0147] In step 1410, the boundary row of the hole (480, Figure 4 ) can be formed to pass through the stack of patterned conductor layers, with the boundary row of the hole being arranged adjacent to and spanning the first pad area, the second pad area, and the block of the hole.

[0148] In step 1420, the first boundary row of vertical columns (171, Fig.10 ) and the second border row of vertical columns (172, Fig.10 ) can be formed to extend through the stack of patterned conductor layers in a first direction, with the first row and the second row being arranged adjacent to and across a block of first pads, second pads, and vertical pillars. The vertical pillars in the first boundary row and the second boundary row are not used for memory cells.

[0149] In step 1430, a single mask ( Fig. 9 ) Etching block boundary slits (1070, Fig.10 ) through a stack of patterned conductor layers, the block boundary gap being configured to span holes in a boundary row of holes.

[0150] In step 1450, the block isolation structure (170, Figure 2 ) may be formed to pass through the stack of patterned conductor layers, wherein the vertical pillars in a first boundary row of vertical pillars and a second boundary row of vertical pillars may contact a side of the isolation structure.

[0151] Fig.15A , Fig. 15B and Fig. 15C An alternative embodiment of a vertical pillar not used for a memory cell is shown, wherein the vertical pillar not used for a memory cell is located within the array boundary between a pad and a plurality of vertical pillars used for a memory cell. Such a vertical pillar not used for a memory cell may have a different width in a first direction (X) than the width of the vertical pillar used for a memory cell.

[0152] like Fig.15A As shown in the example of FIG. 1 , the vertical pillars (1501, 1504) not used for the memory cells are disposed within the array boundary 1590 between the pad 1595 and the plurality of vertical pillars (1511-1518) used for the memory cells. The vertical pillars not used for the memory cells may have a different width W1 in the first direction (X) compared to the width W of the vertical pillars used for the memory cells. The blocks (1591, 1592) in the second group of isolation blocks within the array boundary 1590 may penetrate some of the vertical pillars (1501, 1504) between the pad 1595 and the plurality of vertical pillars used for the memory cells.

[0153] like Fig. 15B As shown in the example of , the vertical pillars (1521, 1522, 1528) not used for the memory cells are arranged within the array boundary 1590 between the pad 1595 and the plurality of vertical pillars (1531-1538) for the memory cells. Compared with the width W of the vertical pillars for the memory cells, the vertical pillars not used for the memory cells may have different widths W2 or W3 in the first direction (X). The blocks (1591, 1592) in the second group of isolation blocks within the array boundary 1590 may penetrate some of the vertical pillars (1521, 1522, 1528) between the pad 1595 and the plurality of vertical pillars for the memory cells. In this example, the vertical pillar 1521 may surround one of the blocks 1591 in the second group of isolation blocks between the pad 1595 and the plurality of vertical pillars for the memory cells.

[0154] like Fig. 15CAs shown in the example of , the vertical pillars (1541) not used for the memory cells are arranged within the array boundary 1590 between the pad 1595 and the plurality of vertical pillars (1551-1560) for the memory cells. Compared with the width W of the vertical pillars for the memory cells, the vertical pillars not used for the memory cells may have a different width W4 in the first direction (X). The blocks (1591, 1592) in the second group of isolation blocks within the array boundary 1590 may penetrate some of the vertical pillars (1541) between the pad 1595 and the plurality of vertical pillars for the memory cells. In this example, the vertical pillars 1541 may surround two blocks (1591, 1592) in the second group of isolation blocks between the pad 1595 and the plurality of vertical pillars for the memory cells.

[0155] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D An alternative embodiment of a vertical column contacting a block isolation structure is shown, wherein the block isolation structure separates a first pad region from a second pad region, wherein the first pad region and the second pad region are disposed opposite each other in a second direction, wherein the second direction (Y) is orthogonal to the first direction (X). The block isolation structure 170 is described in Figure 1 and Fig.11 The width W of the vertical pillar of the contact block isolation structure in the first direction (X) may be equal to or different from the width (W, Figure 3 ).

[0156] like Fig.16A As shown in the example of FIG. 1 , the width W of the vertical pillar (eg, 1601) of the contact block isolation structure in the first direction (X) may be equal to the width W of the vertical pillar (eg, 1511-1518, Fig.15A )’s width W.

[0157] like Fig. 16B As shown in the example of FIG. 1 , the width W5 of the vertical pillar (eg, 1611 ) of the contact block isolation structure in the first direction (X) may be greater than the width W of the vertical pillar for the memory cell.

[0158] like Fig. 16C As shown in the example of FIG. 1 , the width W6 of the vertical pillar (eg, 1621 ) of the contact block isolation structure in the first direction (X) may be greater than twice the width W of the vertical pillar for the memory cell.

[0159] like Fig.16D As shown in the example of FIG. 1 , the width W6 of the vertical pillar (eg, 1631 ) of the contact block isolation structure in the first direction (X) may be greater than three times the width W of the vertical pillar for the memory cell.

[0160] Although the present invention has been described by reference to the preferred embodiments and examples described in detail above, it should be understood that these examples are exemplary only and not restrictive. It is conceivable that modifications and combinations will be easily conceived by those skilled in the art, and these modifications and combinations will be within the spirit of the present invention and the scope of the appended claims.

[0161] In summary, although the present invention has been disclosed above by embodiments and examples, these examples are only exemplary and not restrictive. Modifications and combinations that can be easily thought of by technicians with common common sense in the technical field to which the present invention belongs should be within the scope of protection defined by the claims of the present invention.

Claims

1. A memory device, characterized in that: include: a stack of a plurality of patterned conductor layers having at least a plurality of layers, the at least a plurality of layers comprising a plurality of conductive strips, the conductive strips comprising a plurality of strips continuous with a pad and a plurality of other strips isolated from the pad; an array of a plurality of vertical pillars extending through the stack of the plurality of patterned conductor layers, wherein a plurality of memory cells are disposed at a plurality of intersections between the vertical pillars and the patterned conductor layers, the array having an array boundary adjacent to the pad; a first set of a plurality of isolation blocks extending through the patterned conductor layers and separating the plurality of strips continuous with the pad from the plurality of other strips isolated from the pad; as well as A second plurality of isolation regions are located within the array boundary and extend through the patterned conductor layers and isolate the other strips from the pad.

2. The memory device of claim 1, wherein the second plurality of isolation blocks comprises a plurality of isolation blocks connected to a pair of adjacent isolation blocks in the first plurality of isolation blocks.

3. The memory device of claim 1, wherein some of the vertical pillars between the pad and the other strips isolated from the pad are penetrated by the isolation blocks of the second set of isolation blocks within the array boundary.

4. The memory device of claim 1, wherein the array extends through one or more of the vertical pillars into the pad and beyond ends of the isolation blocks in the first set of isolation blocks.

5. The memory device of claim 1, further comprising: A second pad, wherein a plurality of strips continuous with the pad are separated from the second pad at a plurality of ends adjacent to the second pad, and a plurality of strips continuous with the second pad are separated from the pad at a plurality of ends adjacent to the pad.

6. The memory device of claim 1, further comprising: a block of a plurality of vertical columns, located within the array boundary; a third pad disposed opposite to the pad in a second direction orthogonal to the first direction, wherein the conductive strips extend along the first direction; a plurality of first and second boundary rows of a plurality of vertical pillars extending in the first direction through the stack of the plurality of patterned conductor layers, the plurality of first and second boundary rows being disposed adjacent to and across the pad and the block of the plurality of vertical pillars, the vertical pillars in the plurality of first and second boundary rows being unused for the plurality of memory cells; as well as A plurality of block-isolated structures extend through the stack of the plurality of patterned conductor layers and separate the pad from the third pad, and the vertical pillars in the plurality of first and second boundary rows contact a plurality of side surfaces of the plurality of block-isolated structures.

7. A method for manufacturing a memory device, characterized in that: include: A stack of a plurality of patterned conductor layers separated by an insulating layer forms an array of a plurality of holes; forming an array of a plurality of vertical posts extending through the stack of the plurality of patterned conductor layers in the holes in the array of the plurality of holes; etching a first set of slits and a second set of slits through the stack of the plurality of patterned conductor layers using a single mask, the first set of slits being arranged to span the holes in the respective rows of the plurality of holes, the second set of slits comprising slits connected to adjacent slits at ends of the first set of slits to form the conductive strips, the conductive strips comprising strips continuous with a pad and other strips isolated from the pad, wherein the plurality of memory cells are arranged at intersections between the vertical pillars and the patterned conductor layers, the array of the plurality of vertical pillars having an array boundary adjacent to the pad; forming a first set of a plurality of isolation blocks in the first set of a plurality of slits through the patterned conductor layers, the patterned conductor layers separating the plurality of strips continuous with the pad from the plurality of other strips isolated from the pad; as well as A second set of isolation regions is formed in the second set of slits, within the array boundary and extending through the patterned conductor layers, isolating the other strips from the pad. 8 . The manufacturing method of claim 7 , wherein the second group of isolation blocks comprises a plurality of isolation blocks connected to a pair of adjacent isolation blocks in the first group of isolation blocks.

9. The manufacturing method of claim 7, wherein some of the vertical pillars between the bonding pad and the other strips isolated from the bonding pad are penetrated by the isolation blocks of the second set of isolation blocks within the array boundary. 10 . The method of claim 7 , wherein the array extends into the pad through one or more of the vertical pillars and beyond ends of the isolation blocks in the first set of isolation blocks.

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