Shallow trench isolation (STI) structure for CMOS image sensors

Abstract

Shallow trench isolation (STI) structures and methods of fabrication include a two-step epitaxial growth process. A trench larger than a target STI structure is etched into a semiconductor substrate, a first layer of undoped semiconductor material is epitaxially grown in the trench to provide the STI structure with a target depth and critical dimension, and a second layer of doped semiconductor material is epitaxially grown on the first layer, the second layer filling the trench and forming a protrusion above a front side of the semiconductor substrate.

Description

Technical Field

[0001] This disclosure provides a shallow trench isolation (STI) structure for image sensors. Background Technology

[0002] Wafer-scale manufacturing using complementary metal-oxide-semiconductor (CMOS) technology has enabled the integration of camera modules into many applications, including automotive, security, and mobile devices. For example, Figure 1 A camera 190 for imaging a scene is depicted. The camera 190 includes an image sensor 100, which includes a pixel array 154. In some embodiments, the pixel array 154 is an array of individual pixels formed in a semiconductor wafer substrate such as silicon. Similar cameras used in automotive applications include, for example, rear-facing cameras, as well as front-facing and side-facing cameras.

[0003] There is a persistent demand for higher resolution image sensors, preferably achieved by increasing the number of pixels on the wafer while keeping the entire image sensor the same size or smaller. The more pixels in an image sensor, the higher the resolution of the image captured by the sensor. This can be achieved either by reducing the pixel size, allowing more pixels to be placed on the wafer, or by reducing the space between pixels.

[0004] Each pixel in an image sensor comprises several devices, including, for example, photodiodes and multiple transistors. For efficient operation, these devices in an image sensor must be electrically isolated from each other. However, as pixel sizes become smaller, device isolation becomes more challenging, particularly regarding current leakage between devices. Shallow trench isolation (STI) is a semiconductor processing technique that involves etching trenches in a wafer substrate to isolate pixels and individual devices within the pixel; however, this technique often results in trap-assisted tunneling and increased dark current, especially when used in high-temperature environments, such as those frequently found in automotive applications.

[0005] Figure 2A and Figure 2B An image sensor formed in a semiconductor substrate is shown in plan view. A photodiode 202, a transfer transistor 204, and a floating diffusion node 206 are formed in a photodiode region 200 of a substrate having a first conductivity type (e.g., N-type). A reset transistor 208, a source follower transistor 210, and a row select transistor 212 are formed in a pixel transistor region 214 of a substrate having a second conductivity type (e.g., P-type) opposite to the first conductivity type. The photodiode 202 in the photodiode region 200 and the transistors in the pixel transistor region 214 must be electrically isolated from each other.

[0006] Figure 2AA pixel with a shallow trench isolation structure 216 between a photodiode region 200 and a pixel transistor region 214 is depicted. Shallow trench isolation (STI) is a semiconductor processing technique that involves etching trenches in a wafer substrate and filling them with a dielectric to isolate the pixel from individual devices within the pixel. Silicon dangling bonds on the walls and bottom of the STI structure 216 created by etching can contribute to increased dark current. Dangling or broken bonds formed along the trench sidewalls or between the silicon dioxide and silicon interfaces create trap sites. These trap sites can trap electrons or holes during operation, thereby generating current in or near the photodiode region of the individual pixel and contributing to the generation of dark current or current in the photodiode region even in the absence of incident light. One approach to address this problem is a surface treatment process involving thermal annealing and pad oxidation, which grows a thin oxide layer on the sidewalls of the STI structure; however, this method still leaves enough Si dangling bonds to cause dark current. Another approach is boron implantation to passivate the STI-Si interface; however, boron diffuses into the silicon around the trench and thus affects the full-well capacity of the photodiode by reducing the photodiode area. Therefore, these processes cannot completely resolve silicon dangling bonds.

[0007] By using boron-implanted regions to isolate the device, the problem of dangling bonds can be avoided. Figure 2B Depicting Figure 2A The pixel has a boron-implanted region 218 that separates the photodiode region 200 from the pixel transistor region 214, instead of an STI structure. However, using boron ion implantation to isolate devices in the pixel also presents problems. These include high lateral diffusion of boron atoms into the substrate region adjacent to the boron ion implantation. This reduces the full-well capacity (FWC), or dynamic range, in the photodiode region. It also reduces isolation resolution and causes high junction leakage due to the abrupt change from boron to the N+ junction. Summary of the Invention

[0008] In a first aspect, a CMOS image sensor includes a semiconductor substrate having photodiode regions and pixel transistor regions separated by a shallow trench isolation (STI) structure. The substrate has a front surface forming a trench extending into the semiconductor substrate, and has a trench depth D relative to a flat region of the front surface and a trench width W at the front surface of the substrate. The STI structure of the CMOS image sensor includes a first layer of undoped semiconductor material epitaxially grown in the trench and a second layer of doped semiconductor material epitaxially grown on the first layer, the second layer filling the trench and forming a protrusion above the front side of the semiconductor substrate, and a gate oxide layer and a gate electrode of the pixel transistor formed on the front surface of the second layer.

[0009] In a second aspect, a method for forming a targeted shallow trench isolation (STI) structure in a semiconductor substrate of an image sensor includes patterning and etching trenches having bottom and sidewalls in the semiconductor substrate, the trenches having a depth (D) greater than a target depth (TD) of the target STI structure relative to a flat region of the front surface of the semiconductor surface, and having a width (W) greater than a critical dimension (CD) of the target STI structure at the front surface; growing a first epitaxial layer of undoped semiconductor material in the trenches until the depth is equal to the target depth TD and the width is equal to the critical dimension CD; and growing a second epitaxial layer of doped semiconductor material until the trenches are filled, and the second layer forms a protrusion above the front surface of the substrate. Attached Figure Description

[0010] Figure 1 A camera including an image sensor is described in an embodiment.

[0011] Figure 2A This is a schematic plan view of the pixel layout of an image sensor using shallow trench isolation.

[0012] Figure 2B This is a schematic plan view of the pixel layout of an image sensor using injection isolation.

[0013] Figure 3A This is a cross-sectional view of trenches etched in a semiconductor substrate according to an embodiment.

[0014] Figure 3B According to the implementation method, in subsequent manufacturing steps Figure 3A A cross-sectional view of the STI.

[0015] Figure 3C This is a cross-sectional view of the STI structure according to the implementation method.

[0016] Figure 4A This is a planar view of the pixels in the image sensor in the implementation method.

[0017] Figure 4B It is along Figure 4A The sectional view taken from line 4B-4B.

[0018] Figure 5 This is a flowchart illustrating a method for fabricating an STI structure in a wafer substrate of an image sensor according to an embodiment.

[0019] Figure 6 This is a flowchart illustrating a method for fabricating pixels on a wafer substrate of an image sensor.

[0020] Figure 7 It is a planar view of adjacent pixels in the image sensor in the implementation method.

[0021] Figure 8 It is along a certain distance below the pixel surface Figure 7 The curves comparing the boron distribution measured by line 8-8. Detailed Implementation

[0022] In this implementation, a shallow trench isolation (STI) structure with a width (typically referred to as the critical dimension (CD) and target depth (TD)) can be formed in a wafer substrate. STI formation in the wafer substrate is performed before photodiodes, transistors, and other devices are fabricated in the substrate. The CD of the STI structure significantly affects pixel density and thus impacts the performance of the image sensor. Figures 3A to 3C Several stages in the formation of the STI structure according to the implementation method are described. Figures 3A to 3C It is best to observe them together in the following descriptions.

[0023] Figure 3A This is a cross-sectional view of substrate 302, pad oxide layer 304, and pad nitride layer 306. In this embodiment, substrate 302 is formed of silicon, although other semiconductor materials may be used, such as bulk silicon substrates doped with n-type or p-type dopants, silicon-on-insulator (SOI) substrates, silicon-germanium, etc. Pad oxide layer 304 is formed by forming a thin oxide layer on a flat surface 305 (e.g., the front surface) of substrate 302 through a thermal oxidation process. In one example, pad nitride layer 306 may be formed on pad oxide layer 304 by depositing silicon nitride material on pad oxide layer 304, for example, using a deposition process such as chemical vapor deposition or physical vapor deposition. Pad nitride layer 306 is used for a photolithography process to pattern the surface of substrate 302 in preparation for etching trench 308.

[0024] The trench 308 is patterned and etched through layers 304 and 306 into the substrate 302 via an isotropic dry etching process (e.g., plasma etching). In this embodiment, the isotropic dry etching parameters depend on the material of the substrate 302 and include pressure, gas composition (e.g., oxygen O2, fluorine, SF6, CF4, CHF3, C4F8), gas generation or injection method, and generator power. When the material is removed from the trench 308, the etching process leaves silicon (Si) dangling bonds 310 on the sidewalls and bottom of the trench. For clarity, in Figure 3A Not all Si dangling keys are marked with reference numbers.

[0025] In one embodiment, trench 308 is etched into the substrate 302 to a depth D deeper than the target depth (TD) of the target STI structure, and to a width W wider than the critical dimension (CD) of the target STI structure, as shown in the reference. Figure 3BFurther discussion is needed. In the implementation, the target depth D refers to the depth or distance from the flat surface 305 of the substrate 302, the front surface of the substrate 302, to the substrate 302. The flat surface 305 can be the front surface of the substrate 302 or the top surface of the substrate 302. After etching, the trench 308 may undergo a surface treatment process to remove some Si defects and reduce humidity at the trench surface, for example, Siconi. TM And hydrogen baking. For example, Siconi TM This is a soft dry chemical etching process (e.g., plasma etching), which selectively removes oxidized silicon surface defects by exposing the area to be etched to etch with etchants such as H2, HF3, and NH3. Hydrogen baking is a subsequent surface cleaning process used to remove oxides present at the silicon interface. However, these processes cannot remove all Si dangling bonds created by etching.

[0026] Figure 3B This is a cross-sectional view of the substrate 302 after the epitaxial growth process in this embodiment. The depth D and width W of the trench 308 have been reduced by the epitaxial growth region 312. The same semiconductor material as the substrate 302 is grown on the sidewalls and bottom of the trench 308 within region 312, as indicated by arrow 311. Typically, epitaxy is the process of forming a new layer on a substrate, which, unlike other techniques that result in random crystal orientation, has a crystal structure aligned with the crystal structure of the substrate. In this embodiment, a vapor-phase epitaxial growth process using, for example, BH3 (borane) and SiH4 (silane) is performed at a temperature of approximately 700°C to 750°C. Although a representative example is given, any suitable epitaxial growth process can be used.

[0027] The parameters of the epitaxial growth process, such as time length, growth rate, and temperature, are selected to grow substrate material on the bottom and sides within trench 308, such that the trench is reduced to the target STI structure's CD (target trench width) and target depth TD. In this embodiment, the depth D of trench 308 is reduced by an amount x = D - TD. In this embodiment, the depth of trench 308 is reduced by an amount x of approximately 50 to 500 angstroms through the epitaxial growth process. Due to the geometry of trench 308, the sidewall growth rate is approximately 25-35% of the trench bottom growth rate. In this embodiment, each sidewall undergoes epitaxial growth, such that... The coefficient α is between approximately 0.25 and 0.35. In this embodiment, the sidewalls grow to approximately 15 to 150 angstroms.

[0028] Because the substrate material is epitaxially grown on the sidewalls and bottom surface of trench 308, therefore... Figure 3AThe Si dangling bonds on the sidewalls and bottom of trench 308 are solidified, as shown. Incorporating an epitaxial growth step into STI structure fabrication means that the material grown in trench 308 has a crystal structure aligned with the crystal structure of substrate 302. However, processing steps typically used to complete STI structures (e.g., filling trench 308 with oxide) can cause thermal stress on the semiconductor substrate and compressive stress buildup in the trench.

[0029] Figure 3C This is a cross-sectional view of the STI structure after the second epitaxial growth process. Layer 314 is a doped semiconductor material that has been epitaxially grown in situ within trench 308 for the time necessary to fill trench 308, such that it extends vertically a distance above the flat surface 305 of substrate 302 to form a protrusion 316. The extension distance of the protrusion 316 protruding above the flat surface 305 of substrate 302 is non-zero, but less than the combined thickness of pad oxide layer 304 and pad nitride layer 306. The protrusion 316 has a lateral width extending along the flat surface 305 within the openings in the pad oxide layer 304 and pad nitride layer 306 formed during the formation of trench 308, and this lateral width is related to the width W of trench 308 and is greater than the CD of the STI structure. The protrusion 316 prevents the corners of the corresponding STI structure from being exposed when any corner of the STI trench is exposed, which affects transistor reliability due to TDDB (time-dependent dielectric breakdown) failures caused by gate leakage when the gate electrode is formed on substrate 302. In the example shown, when the epitaxial growth within the openings of the pad oxide layer 304 and the pad nitride layer 306 is consistent, the width of the protrusion 316 is substantially equal to the width W of the trench 308.

[0030] Layer 314 is configured to have the same conductivity type as substrate 302. For example, for a p-type doped substrate 302, layer 314 is made of a p-type doped semiconductor material. The dopant concentration of layer 314 is greater than that of substrate 302. For example, the dopant concentration of substrate 302 may be between approximately 1 × 10¹⁰ / cm² and 1 × 10¹² / cm², and the dopant concentration of layer 314 may be between approximately 1 × 10¹³ / cm² and 1 × 10¹⁵ / cm². Subsequent processing steps include removing pad nitride layer 306 and pad oxide layer 304.

[0031] Figure 4A This is a planar view of the image sensor with 400 pixels. Figure 4B It is along Figure 4A Sectional view of line 4B-4B. Figure 4A and Figure 4B It is best to observe them together in the following description. Pixel 400 includes transistors 412, 414, and 416 in the P-type region 418, transistors 412, 414, and 416 having been combined as described above. Figures 3A to 3CThe formed STI structure 404 is isolated from the N-type photodiode 410. The STI structure 404 is formed in the substrate 402 and includes a protrusion 406 extending above the front surface 408 of the substrate 402. The protrusion 406 has a thickness t1. The gate oxide layer 420 formed below the gate electrode 424 has a thickness t. OX In this embodiment, a gate oxide layer 420 is deposited on the front surface 408 between the STI structures 404. As shown, the gate oxide layer 420 overlaps with the protrusions 406 of the STI structure 404. A gate electrode 424 is formed on the gate oxide layer 420. An N-channel source / drain implantation region 422 is formed in the substrate 402 below the gate electrode 424. In this embodiment, t1 > tOX, and t1 is between approximately 150 and 300 angstroms to provide more hierarchical junctions and minimize junction leakage.

[0032] Figure 5 This is a flowchart illustrating a method 500 for fabricating an STI structure in a wafer substrate of an image sensor. Method 500 includes steps 510, 512, and 514. In an embodiment, method 500 further includes at least one of steps 502, 504, 506, and 508.

[0033] Step 502 includes defining a trench depth W based on the target trench critical size (CD) and a trench depth D based on the target STI structure target depth (TD). In an example of step 502, the CD and target depth TD of the target STI structure are selected based on the preferred pixel density and preferred performance of the image sensor formed in the substrate. Step 504 includes selecting parameters for the epitaxial growth process. In an example of step 504, such as... Figure 3B As shown, the selected parameters will provide a bottom thickness equal to x, which is approximately 50 to 500 angstroms, and approximately within the trench 308. The growth of the sidewall thickness, where the coefficient α is approximately between 0.25 and 0.35.

[0034] Step 506 includes determining Figures 3A to 3C The etching width of trench 308. In the example of step 506, the width W is determined to be equal to CD plus twice the sidewall thickness αx, where α is positive and less than or equal to 1. In the embodiment, the coefficient α is between 0.25 and 0.35. Step 508 includes determining the depth D to be equal to TD plus the bottom thickness x. In the embodiment, steps 504 to 508 can be performed in any order and / or iteratively.

[0035] Step 510 includes, for example, patterning and etching trenches 308 on the front-side flat surface 305 of the substrate via photolithography and etching processes. In an example of step 510, the parameters of the etching process are selected to provide trenches 308 having a width W (width of the trench opening) and a depth D. Step 512 includes epitaxial growth of an undoped epitaxial layer. In an example of step 512, an undoped first layer 312 is formed by an epitaxial growth process according to the parameters selected in step 504, such as... Figure 3C As shown. Step 514 includes epitaxial growth of a doped layer. In the example of step 514, the second epitaxial growth process forms a layer having the same conductivity type as the substrate (e.g., P-type). Figure 3C The in-situ doped second layer 314 fills the trench 308 and forms a protrusion 316 above the front surface 305, such as Figure 3C As shown. To reiterate, the in-situ doped second layer is arranged to fill trench 308 and extends a distance above the front surface plane 305 of substrate 302. The dopant used to form the in-situ doped second layer 314 may include boron, gallium, and indium. Boron as mentioned herein should be understood to include embodiments using gallium or indium.

[0036] Figure 6 This is a flowchart illustrating a method 600 for fabricating pixels on a wafer substrate of an image sensor. Steps 602 to 614 are equivalent to... Figure 5 Steps 502 to 514. After one or more STI structures have been formed on the wafer substrate (e.g., on the front side of the wafer substrate), subsequent steps include manufacturing steps 616 to 620.

[0037] Step 616 includes forming a photodiode region and source / drain for a pixel transistor. In an example of step 616, the photodiode region 410 and source / drain region 422 of FIG4 are formed, for example, adjacent to the STI structure in the wafer substrate by ion implantation.

[0038] Step 618 includes forming a gate oxide layer for a pixel transistor. In an example of step 618, a gate oxide layer 420 is formed on the front surface 408 of the substrate 402, for example by thermal oxidation or oxide deposition and a portion of an adjacent protrusion 406 of an adjacent STI structure.

[0039] Step 620 includes forming a gate electrode for a pixel transistor. In an example of step 620, at least one gate electrode for a pixel transistor is formed on the gate oxide layer 420. In embodiments, fabrication steps 616 to 620 are representative, and portions of the photodiode region, source / drain region, and gate oxide layer may be formed simultaneously or iteratively.

[0040] Figure 7A planar view of adjacent pixels in an image sensor is shown. A photodiode 702, a transfer transistor 704, and a floating diffusion node 706 are formed in a photodiode region 700 (also referred to as an active region or photosensing region) of a wafer substrate. The photodiode 702 and the floating diffusion node 706 are doped regions having a first conductivity type (e.g., N-type), and the wafer substrate is configured to have a second conductivity type opposite to the first conductivity type (e.g., P-type). In an embodiment, each of the transfer transistors 704 connects each corresponding photodiode 702 to a corresponding floating diffusion node 706 and selectively transfers photogenerated charge from the corresponding photodiode 702 to the corresponding floating diffusion node 706 in response to receiving a transfer signal from its corresponding transfer gate. Each of the photodiodes 702 acts as a source region to the corresponding transfer transistor 704, and each of the floating diffusion nodes acts as a drain region to the transfer transistor 704. A reset transistor 708, a source follower transistor 710, and a row select transistor 712 are N-channel transistors formed in a pixel transistor region 714 of the wafer substrate. In such an example, the source and drain regions of each reset transistor 708, source follower transistor 710, and row select transistor 712 are N-type doped regions, i.e., doped regions of a second conductivity type opposite to the first conductivity type of the wafer substrate. The photodiode 702 is isolated from the pixel transistor region 714 by a boron isolation region 716 formed by a boron-doped shallow trench isolation structure, as shown below. Figure 3C and Figure 4B As shown.

[0041] In some embodiments, the junction depth of the source and drain regions associated with each corresponding pixel transistor in pixel transistor region 714 is less than or shallower than the target depth (TD) of the respective STI structures formed in boron isolation region 716, relative to the front surface of the wafer substrate.

[0042] For simplicity, Figure 5 The diagram shows two photodiodes per pixel. In other embodiments, a pixel may include more or fewer photodiodes. Similarly, the pixel layout shown illustrates a "four-transistor configuration," where the pixel transistor for each corresponding pixel includes a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor. In some embodiments, a pixel may be configured as a "three-transistor configuration," including only a transfer transistor, a reset transistor, and a source follower transistor. In some embodiments, a pixel may be configured as a "five-transistor configuration," including a transfer transistor, a row select transistor, a source follower transistor, a reset transistor (and an overflow transistor or a double floating diffuse (DFD) transistor). Therefore, the number of photodiodes in a pixel and the number of pixel transistors used to control pixel operation may depend on the configuration of the relevant pixels.

[0043] Figure 8 It is shown at a distance below the front surface 408 of the pixel, along... Figure 7 The line 8-8 was measured Figures 3A to 3C and Figure 4B A graph comparing boron distribution between ion implantation and in-situ doped epitaxial layer methods. Dopant distribution 820 shows the boron doping concentration at the horizontal (lateral) distance immediately following ion implantation for passivating the sidewalls and bottom of STI trenches (such as trench 308). Dopant distribution 822 shows the boron doping concentration after a heat treatment (e.g., annealing) following the ion implantation process. Dopant distribution 824 shows the boron doping concentration after applying the epitaxial growth process to the above-mentioned... Figure 3C and Figure 4B The boron doping concentration at the horizontal (lateral) distance following the shallow trench isolation structure. Dopant distribution 826 shows the boron doping concentration of dopant distribution 824 after thermal treatment (e.g., annealing) of the active boron dopant in the doped semiconductor material filling the shallow trench isolation. A comparison of dopant distributions 820, 822, 824, and 826 shows that the boron-doped epitaxial growth process of dopant distributions 824 and 826 provides a more uniform distribution compared to the ion implantation method of dopant distributions 820 and 822. Furthermore, the epitaxial growth process has a nearly flat (very uniform) doping distribution across the entire thickness, while ion implantation is less sharp, even after implantation, as shown in dopant distribution 820. Even after diffusion through the thermal budget shown in dopant distributions 822 and 826, the boron distribution of dopant distribution 826 is much sharper than that of dopant distribution 822, as shown in 828. This is due to Figure 3C The undoped epitaxial growth buffer layer 312 results in a smaller diffusion effect of dopant distribution 826 on the full-well capacity of adjacent photodiodes compared to dopant distribution 822. As shown in 830, lateral diffusion in the ion implantation method leads to a loss of full-well capacity.

[0044] In implementations, methods 500 and 600 described above, along with the STI structure 318, offer additional benefits in forming trenches on the substrate using pad nitride as a mask. The photolithography process has lower effective limitations on the size of the area that can be effectively masked. This also limits the critical size achievable for the target STI structure (e.g., the target trench width). In implementations, target STI structures even smaller than the lower photolithographic patterning limitations can be formed by etching trenches at patterning limitations and then epitaxially growing additional substrate material within the trenches. This further reduces the space of the STI (spacer between the photodiode region and the pixel transistor region) and increases the area on the substrate for the photodiode, thus enabling the formation of larger pixel arrays and achieving higher imaging resolution.

[0045] Methods 500 and 600 provide shallow trench isolation structures without Si dangling bonds on the bottom and sidewalls of the trenches created by plasma etching, because silicon is epitaxially grown on these surfaces, thereby solidifying the Si dangling bonds. In the embodiments, any type of substrate can be used, including doped silicon, as doped silicon can also be epitaxially grown to match the substrate. This provides a doped substrate without silicon surface damage caused by boron implantation doping.

[0046] like Figure 8 As shown, the two-step epitaxial growth process described in this paper achieves higher boron isolation resolution with a steeper boron distribution. Furthermore, the STI structure provides a more perfectly matched junction for N+ and prevents damage to the substrate that may be caused by ion implantation.

[0047] Combination of features

[0048] Without departing from the scope of this disclosure, the features described above and those claimed below can be combined in various ways. The following examples illustrate some possible non-limiting combinations:

[0049] (A1) A CMOS image sensor comprising: a semiconductor substrate having a photodiode region and a pixel transistor region separated by a shallow trench isolation (STI) structure, the substrate having a front surface forming a trench extending into the semiconductor substrate and having a trench depth D relative to a flat region of the front surface and a trench width W at the front surface; a first layer of undoped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth TD less than D and a critical dimension CD less than W; a second layer of doped semiconductor material epitaxially grown on the first layer, the second layer filling the trench and forming a protrusion above the front surface of the semiconductor substrate; and a gate oxide layer and a gate electrode of the pixel transistor formed on the front surface of the second layer.

[0050] (A2) In the sensor (A1), the photodiode region may include a first conductivity type.

[0051] (A3) In the sensor (A1) or (A2), the semiconductor substrate and the first and second layers may include a second conductivity type opposite to the first conductivity type.

[0052] (A4) In any of the sensors (A1) to (A3), the second layer may include a boron-doped semiconductor material with a dopant concentration greater than that of the semiconductor substrate.

[0053] (A5) In any of the sensors (A1) to (A4), a gate oxide layer may be deposited between the gate electrode and the protrusion, and the thickness of the protrusion may be greater than the thickness of the gate oxide layer.

[0054] (A6) In the sensor (A5), the thickness can be between approximately 150 angstroms and 300 angstroms.

[0055] (A7) Any of the sensors (A1) to (A5) may also include multiple STI structures, multiple photodiode regions, and multiple transistors.

[0056] (B1) A shallow trench isolation (STI) structure having a target depth TD and a critical dimension CD, comprising: a semiconductor substrate having a front surface of the substrate forming a trench extending into the semiconductor substrate and having a trench depth D relative to a flat region surrounding the front surface of the substrate, such that D is greater than TD, and having a trench width W at the front surface of the substrate, such that W is greater than CD; a first layer of undoped semiconductor material epitaxially grown in the trench to provide an STI structure having the target depth TD and the critical dimension CD; and a second layer of doped semiconductor material epitaxially grown on the first layer, the second layer filling the trench and forming a protrusion above the front surface of the semiconductor substrate.

[0057] (B2) In structure (B1), the D-TD can be between approximately 50 angstroms and 500 angstroms.

[0058] (B3) In any of the structures (B1) to (B2), (W-CD) / 2 can be between approximately 15 angstroms and 150 angstroms.

[0059] (B4) In any of the structures (B1) to (B3), the semiconductor substrate and the first and second layers may include silicon.

[0060] (B5) In any of the structures (B1) to (B4), the semiconductor substrate and the first and second layers may include the same conductivity type.

[0061] (B6) In any of the structures (B1) to (B5), the second layer may contain a boron-doped semiconductor material with a dopant concentration greater than that of the semiconductor substrate.

[0062] (C1) A method for forming a target shallow trench isolation (STI) structure in a semiconductor substrate, comprising: patterning and etching a trench having a bottom and sidewalls in the semiconductor substrate, the trench having a depth (D) greater than a target depth (TD) of the target STI structure relative to a flat region of a front surface of the semiconductor surface, and having a width (W) greater than a critical dimension (CD) of the target STI structure at the front surface; growing a first epitaxial layer of undoped semiconductor material in the trench until the depth is equal to the target depth TD and the width is equal to the critical dimension CD; and growing a second epitaxial layer of doped semiconductor material until the trench is filled to extend above the front surface of the semiconductor substrate.

[0063] (C2) In the method of (C1), the second epitaxial layer of growing doped semiconductor material may further include growing a second epitaxial layer of doped semiconductor material until the second layer forms a protrusion above the front surface of the semiconductor substrate.

[0064] (C3) In method (C2), the protrusion may have a thickness between approximately 150 angstroms and 300 angstroms.

[0065] (C4) In any of the methods (C1) to (C3), a transistor may be formed in the front surface of a semiconductor substrate adjacent to the target STI structure.

[0066] The methods (C5) and (C4) may include forming a gate oxide layer and a gate electrode of a transistor on a portion of the protrusion of the second layer.

[0067] (C6) In any of the methods (C1) to (C5), the first and second layers can be epitaxially grown at a temperature between about 700°C and 750°C.

[0068] (C7) In any of the methods (C1) to (C6), the D-TD may be between approximately 50 angstroms and 500 angstroms.

[0069] (C8) In any of the methods (C1) to (C7), (W-CD) / 2 can be between about 15 angstroms and 150 angstroms.

[0070] (C9) In any of the methods (C1) to (C8), the semiconductor substrate and the first and second layers may include a second conductivity type.

[0071] (C10) In any of the methods (C1) to (C9), the semiconductor substrate and the first and second layers may include silicon.

[0072] Modifications may be made to the methods and systems described above without departing from the scope of this disclosure. Therefore, it should be noted that the content included in the above description or shown in the accompanying drawings should be interpreted illustratively, not restrictively. In this document, unless otherwise stated: (a) the adjective “exemplary” means used as an example, instance, or illustration, and (b) the phrase “in an embodiment” is equivalent to the phrase “in some embodiments” and does not refer to all embodiments. The appended claims are intended to cover all the general and specific features described herein, as well as all statements within the scope of the methods and systems, which, linguistically, may be said to fall within the scope of the claims.

Claims

1. A CMOS image sensor, comprising: A semiconductor substrate having a photodiode region and a pixel transistor region separated by a shallow trench isolation structure, the semiconductor substrate having a front surface forming a trench that extends into the semiconductor substrate and having a trench depth D relative to a flat region of the front surface and a trench width W at the front surface of the semiconductor substrate. A first layer of undoped semiconductor material is epitaxially grown in the trench to provide a shallow trench isolation structure having a target depth TD less than D and a critical dimension CD less than W. A second layer of doped semiconductor material is epitaxially grown on the first layer, the second layer filling the trench and forming a protrusion above the front surface of the semiconductor substrate; as well as A gate oxide layer and a gate electrode of a pixel transistor are formed on the front surface of the pixel transistor region; The first layer and the semiconductor substrate are formed of the same semiconductor material.

2. The CMOS image sensor according to claim 1, wherein, The photodiode region includes a first conductivity type, and the semiconductor substrate and the second layer include a second conductivity type opposite to the first conductivity type.

3. The CMOS image sensor according to claim 1, wherein, The second layer comprises a boron-doped semiconductor material with a dopant concentration greater than that of the semiconductor substrate.

4. The CMOS image sensor according to claim 1, wherein, The gate oxide layer is deposited between the gate electrode and the protrusion, and the thickness of the protrusion is greater than the thickness of the gate oxide layer.

5. The CMOS image sensor according to claim 4, wherein, The thickness of the gate oxide layer is between 150 angstroms and 300 angstroms.

6. A shallow trench isolation structure having a target depth TD and a critical dimension CD, comprising: A semiconductor substrate has a front surface of the substrate forming a trench that extends into the semiconductor substrate and has a trench depth D relative to a flat region of the front surface of the substrate surrounding the trench, such that D is greater than TD, and has a trench width W at the front surface of the substrate, such that W is greater than CD. A first layer of undoped semiconductor material is epitaxially grown in the trench to provide a shallow trench isolation structure having the target depth TD and the critical dimension CD; A second layer of doped semiconductor material is epitaxially grown on the first layer, the second layer fills the trench and forms a protrusion above the front surface of the semiconductor substrate; The first layer and the semiconductor substrate are formed of the same semiconductor material.

7. The shallow trench isolation structure according to claim 6, wherein, Between 50 angstroms and 500 angstroms.

8. The shallow trench isolation structure according to claim 6, wherein, Between 15 angstroms and 150 angstroms.

9. The shallow trench isolation structure according to claim 6, wherein, The semiconductor substrate, the first layer, and the second layer comprise silicon.

10. The shallow trench isolation structure according to claim 6, wherein, The semiconductor substrate and the second layer have the same conductivity type.

11. The shallow trench isolation structure according to claim 6, wherein, The second layer comprises a boron-doped semiconductor material with a dopant concentration greater than that of the semiconductor substrate.

12. A method for forming a target shallow trench isolation structure in a semiconductor substrate, comprising: A trench having a bottom and sidewalls is etched in the semiconductor substrate, the trench having a depth greater than the target depth of the target shallow trench isolation structure relative to a flat region of the front surface of the semiconductor substrate, and having a width at the front surface greater than the critical dimension of the target shallow trench isolation structure; A first epitaxial layer of undoped semiconductor material is grown in the trench until the depth is equal to the target depth and the width is equal to the critical dimension; and A second epitaxial layer of doped semiconductor material is grown until the trench is filled and extends above the front surface of the semiconductor substrate. The first epitaxial layer and the semiconductor substrate are formed of the same semiconductor material.

13. The method according to claim 12, wherein, The second epitaxial layer of the doped semiconductor material further includes: growing the second epitaxial layer of the doped semiconductor material until the second epitaxial layer forms a protrusion above the front surface of the semiconductor substrate.

14. The method according to claim 13, wherein, The thickness of the protrusion is between 150 angstroms and 300 angstroms.

15. The method of claim 13, further comprising: A transistor is formed in the front surface of the semiconductor substrate adjacent to the target shallow trench isolation structure.

16. The method of claim 15, further comprising: The gate oxide layer and gate electrode of the transistor are formed on the protruding portion of the second epitaxial layer.

17. The method according to claim 12, wherein, The first epitaxial layer and the second epitaxial layer are epitaxially grown at a temperature between 700 °C and 750 °C.

18. The method according to claim 12, wherein, The semiconductor substrate, the first epitaxial layer, and the second epitaxial layer comprise silicon.

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