Image sensing device and manufacturing method thereof

Abstract

An image sensing device and a manufacturing method thereof are provided. The method comprises forming a plurality of photosensitive pixels on a substrate; depositing a dielectric layer on the substrate; etching the dielectric layer to form a first groove in the dielectric layer, the first groove laterally surrounding the photosensitive pixels; forming a light-blocking structure in the first groove, so that the light-blocking structure laterally surrounds the photosensitive pixels.

Description

Technical Field

[0001] The present disclosure relates to an image sensing device and a manufacturing method thereof. Background Art

[0002] Image sensors generate electrical signals in response to stimulation by photons. The magnitude of the electrical signals (e.g., photocurrent) depends on the intensity of the incident light received by each image sensor. Image sensors may be affected by non-optically generated signals, including leakage signals, heat-generated signals, dark current, etc. Therefore, the electrical signals generated by the image sensors are then calibrated to eliminate undesirable signals from the output signals of the image sensors. In order to eliminate these non-optically generated signals, a black reference image sensor is formed and used to generate the non-optically generated signals. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for manufacturing an image sensing device. The method includes forming a plurality of photosensitive pixels on a substrate; depositing a dielectric layer on the substrate; etching the dielectric layer to form a first groove in the dielectric layer, the first groove laterally surrounding the photosensitive pixels; forming a light-blocking structure in the first groove, so that the light-blocking structure laterally surrounds the photosensitive pixels.

[0004] Some embodiments of the present disclosure provide a method for manufacturing an image sensing device. The method includes forming a plurality of photosensitive pixels in a substrate through a front surface of the substrate; forming a doped region in the substrate, wherein the doped region laterally surrounds the photosensitive pixels of the substrate; depositing a dielectric layer on a rear surface of the substrate, wherein the rear surface of the substrate is opposite to the front surface of the substrate; etching the dielectric layer to form a first groove, wherein the first groove overlaps the doped region; and forming a light blocking structure in the first groove.

[0005] Some embodiments of the present disclosure provide an image sensing device, comprising a substrate, a plurality of photosensitive pixels, an internal connection structure, a dielectric layer, and a light-blocking element. The photosensitive pixels are located in the substrate. The internal connection structure is located on a first side of the substrate. The dielectric layer is located on a second side of the substrate, wherein the second side of the substrate is relative to the first side of the substrate. The light-blocking element has a first portion extending on an upper surface of the dielectric layer and a second portion extending in the dielectric layer, wherein the second portion of the light-blocking element laterally surrounds the photosensitive pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure can be understood from the following detailed description and the accompanying drawings. It should be noted that various features are not drawn to the standard scale in industry practice. In fact, the size of various features can be arbitrarily increased or decreased for the sake of clarity of discussion.

[0007] Figure 1A is a top view schematic diagram of an image sensing device according to some embodiments of the present disclosure;

[0008] Figure 1B for Figure 1A an enlarged view of a portion of;

[0009] Figure 1C For along Figure 1B A schematic cross-sectional view of the CC line;

[0010] Figure 2 is a top view schematic diagram of an image sensing device according to some embodiments of the present disclosure;

[0011] Figure 3 is a top view schematic diagram of an image sensing device according to some embodiments of the present disclosure;

[0012] Figure 4 is a top view schematic diagram of an image sensing device according to some embodiments of the present disclosure;

[0013] Figures 5 to 16 A method of manufacturing an image sensing device at various intermediate stages of manufacturing according to some embodiments of the present disclosure is shown;

[0014] Figures 17 to 28 A method of manufacturing an image sensing device at various intermediate stages of manufacturing according to some embodiments of the present disclosure is shown;

[0015] Fig.29 FIG. 4 is a cross-sectional schematic diagram of an image sensing device according to some embodiments of the present disclosure.

[0016]

Explanation of symbols

[0017] 100: Image sensing device

[0018] 102: Pixel array area

[0019] 104: Black level correction area

[0020] 106: Cutting area

[0021] 108: Alignment mark area

[0022] 110:Substrate

[0023] 110A: Surface

[0024] 110B: Surface

[0025] 110T: Groove

[0026] 110D: Doped area

[0027] 110DW1: Width

[0028] 110DW2: Width

[0029] 120: Photosensitive pixels

[0030] 120A: Photosensitive pixels

[0031] 120B: Photosensitive pixels

[0032] 122: Photosensitive area

[0033] 132: Isolation Structure

[0034] 134: Isolation layer

[0035] 150: Internal connection structure

[0036] 152: Interlayer dielectric layer

[0037] 154: Intermetallic dielectric layer

[0038] 154M: Wire

[0039] 160: Dielectric layer

[0040] 160I: Isolation Structure

[0041] 160T1: Groove

[0042] 160T2: Groove

[0043] 162: Charge accumulation layer

[0044] 164: Buffer layer

[0045] 170: light blocking layer

[0046] 170O1: Opening

[0047] 170O2: Opening

[0048] 172: Light blocking grid

[0049] 174: Light blocking element

[0050] 174G: Channel

[0051] 174U:Partial

[0052] 174E: Light blocking structure

[0053] 174EV: Short side

[0054] 174EH: Long side section

[0055] 174EW1: Inner wall

[0056] 174EW2:Outer wall

[0057] 178: Light blocking element

[0058] 178G: Channel

[0059] 180: Dielectric layer

[0060] 190: Buffer oxide layer

[0061] 200: Bonding pad

[0062] 210: Color filter layer

[0063] 212: Color filter element

[0064] 220: Microlens

[0065] 400: Carrier substrate

[0066] B: Area

[0067] CC:Line

[0068] D1: Direction

[0069] D2: Direction

[0070] L1: Length

[0071] L2: Length

[0072] W1: Width

[0073] W2: Width

[0074] PH: Pixel width

[0075] PV: Pixel height

[0076] GA: Gap

[0077] GB: Gap

[0078] O1: Opening DETAILED DESCRIPTION

[0079] The present disclosure below will provide many different implementations or examples to implement the different features of the provided patent subject matter. Many components and settings will be described below with specific examples to simplify the present disclosure. Of course, these examples are only used for illustration and should not be used to limit the present disclosure. For example, the description "a first feature is formed on a second feature" includes multiple implementations, including the first feature being in direct contact with the second feature, and additional features being formed between the first feature and the second feature so that the two are not in direct contact. In addition, in various embodiments, the present disclosure may repeat numbers and / or letters. This repetition is for simplicity and clarity of description, and is not intended to indicate the relationship between the various implementations and / or configurations discussed.

[0080] Furthermore, spatially relative words, such as "lower," "below," "beneath," "beneath," "upper," "above," and other related words, are used herein to simply describe the relationship of an element or feature to another element or feature, as shown in the figures. When in use or operation, these spatially relative words cover different rotations of the device in addition to the rotations shown in the figures. Alternatively, the devices can be rotated (rotated 90 degrees or at other angles), and the spatially relative descriptors used herein can be interpreted accordingly. In some embodiments, the word "approximately" herein means greater than or less than the described value or the described range by a ratio of the described value, such as 5%, 10%, 15%, etc.

[0081] Some embodiments of the present disclosure provide an image sensing device and a method for forming the same, wherein the image sensing device includes an active image sensor and a black reference image sensor. The black reference image sensor may be covered by a light blocking element (e.g., a metal shielding layer) to prevent it from receiving light signals. In an embodiment of the present disclosure, the light blocking element may have an annular light blocking structure that laterally surrounds an area in which the active image sensor is disposed. The annular light blocking structure may block lateral light, thereby preventing light from being transmitted laterally into the black reference image sensor. This document describes multiple intermediate stages in the manufacture of an image sensing device. Variants of the embodiments are also discussed. In the various views and illustrative embodiments, similar reference numerals are used to indicate similar elements.

[0082] Figure 1A1 is a top view of an image sensing device 100 according to some embodiments of the present disclosure. The image sensing device 100 may include a pixel array region 102 and a black level correction (BLC) region 104 laterally surrounding the pixel array region 102. In some embodiments of the present disclosure, a light blocking element 174 is formed in the black level correction region 104 to shield the black level correction region 104 from incident light. The light blocking element 174 may include an annular light blocking structure 174E, which is located adjacent to the pixel array region 102 to prevent light from being transmitted laterally from the pixel array region 102 to the black level correction region 104. The image sensing device 100 may further include other regions, such as a contact pad (E-pad) region and an alignment region (such as a scribe-line primary mark (SPM) region), but these other regions are not explicitly depicted because they are not necessary for understanding the embodiments described herein.

[0083] Figure 1B for Figure 1A An enlarged view of a portion of area B. Figure 1C For along Figure 1B Schematic diagram of the cross section taken along the CC line. Figures 1A to 1C. In some embodiments, the image sensing device 100 includes a substrate 110. Surface 110A may refer to the front surface of the substrate 110, and surface 110B may refer to the rear surface of the substrate 110. A plurality of photosensitive pixels 120 (including photosensitive pixels 120A and 120B) are formed near the front surface 110A of the substrate 110. In some embodiments, the pixel array region 102 of the image sensing device 100 includes active photosensitive pixels 120A, which are used to generate electrical signals based on sensed light. The black level correction region 104 of the image sensing device 100 includes reference photosensitive pixels 120B, which are used to generate reference black level signals. In some embodiments, the photosensitive pixels 120A and 120B may be formed simultaneously, and the materials of the photosensitive pixels 120A and 120B may be the same as each other. The image sensing device 100 may further include an isolation structure 132 between adjacent photosensitive pixels 120 to prevent electrical cross-talk between the photosensitive pixels 120. In some embodiments, the image sensing device 100 further includes an internal connection structure 150 (e.g., including an inter-layer dielectric (ILD) layer 152 and / or an inter-metal dielectric (IMD) layer 154 and multi-layer interconnectors within the ILD layer 152 and the IMD layer 154) on the front surface of the substrate 110 to form a circuit with the photosensitive pixel 120.

[0084] In some embodiments, the image sensing device 100 may include a dielectric layer 160 on the rear surface 110B of the substrate 110. The dielectric layer 160 may extend into a groove formed in the rear surface 110B of the substrate 110, thereby forming an isolation structure 160I between adjacent photosensitive pixels 120A, and the isolation structure 160I can prevent electrical crosstalk between the photosensitive pixels 120A. The isolation structure 160I can be referred to as a backside deep trench isolation (BDTI) structure. In some embodiments, the dielectric layer 160 may include at least one groove 160T1 that laterally surrounds the pixel array region 102. For example, in this embodiment, the groove 160T1 can surround the pixel array region 102.

[0085] In some embodiments, the image sensing device 100 may include a light blocking layer 170. The light blocking layer 170 is made of a reflective metal material or a light absorbing material. For example, the light blocking layer 170 may include a suitable metal material, such as Cu, Au, Ag, Al, Ni, W, an alloy thereof, or the like. The light blocking layer 170 has a light blocking grid 172 in the pixel array area 102 and a light blocking element 174 in the black level correction area 104. The light blocking grid 172 can prevent optical crosstalk between adjacent photosensitive pixels 120A. The light blocking element 174 can cover the photosensitive pixel 120B. For example, the light blocking element 174 can have a portion 174U, wherein the portion 174U is located on the entire top surface of the dielectric layer 160 in the black level correction area 104.

[0086] In some embodiments of the present disclosure, the light blocking element 174 has a long light blocking structure 174E in the groove 160T1 of the dielectric layer 160. Figure 1A As shown, the long light blocking structure 174E extends continuously around the pixel array area 102 and thus has a ring or closed loop shape. With this configuration, the light-sensitive pixels 120B in the black level correction area 104 can generate non-light-generated signals (i.e., signals that are unrelated to the light received in the pixel array area). For example, Figure 1A As shown, the long strip of light blocking structure 174E has two short side portions 174EV and two long side portions 174EH connected between the short side portions 174EV to form a ring structure or a closed loop structure in the top view. In some embodiments, the long side portion 174EH can extend in a direction D1, wherein the direction D1 is different from the extension direction D2 of the short side portion 174EV. For example, the direction D1 is perpendicular to the direction D2. The two short side portions 174EV and the two long side portions 174EH can be respectively located on the four sides of the pixel array area 102, so as to surround the pixel array area 102 when viewed from the top. In other words, when viewed from the top, the inner wall 174EW1 of the long strip of light blocking structure 174E can surround the pixel array area 102, and the outer wall 174EW2 of the long strip of light blocking structure 174E can surround the inner wall 174EW1 of the long strip of light blocking structure 174E.

[0087] In some embodiments of the present disclosure, the light blocking structure 174E extends over at least one reference photosensitive pixel 120B adjacent to the photosensitive pixel 120A. Figure 1B As shown, the light blocking structure 174E is on more than five reference photosensitive pixels 120B adjacent to the photosensitive pixel 120A.

[0088] In some embodiments of the present disclosure, the long side portion 174EH of the light blocking structure 174E has a length L1 (eg, Figure 1A), and the length L1 may be greater than the photosensitive pixel 120 measured in the direction D1 (as shown in FIG. Figure 1B Similarly, in some embodiments, the short side portion 174EV of the light blocking structure 174E has a length L2 in its extension direction D2 (as shown in FIG. Figure 1A ), and the length L2 may be greater than the photosensitive pixel 120 measured in the direction D2 (as shown in FIG. Figure 1B For example, the long side portion 174EH and the short side portion 174EV may span one or more photosensitive pixels 120B. Figure 1A and Figure 1B As shown, the long side portion 174EH of the long light blocking structure 174E spans five photosensitive pixels 120B. In some embodiments, the lengths L1 and L2 of the long side portion 174EH and the short side portion 174EV are respectively greater than the length and width of the pixel array region 102, thereby surrounding the pixel array region 102.

[0089] In some embodiments of the present disclosure, the long side portion 174EH may have a width W1 measured in a direction perpendicular to its extension direction D1, and the width W1 may be equal to or greater than the pixel height PV of the photosensitive pixel. Similarly, in some embodiments, the short side portion 174EV may have a width W2 measured in the direction D1, and the width W2 may be equal to or greater than the pixel width PH of the photosensitive pixel 120.

[0090] In some embodiments, widths W1 and W2 may be in the range of about 0.1 microns to about 500 microns, but other ranges are within the scope of various embodiments of the present disclosure. If widths W1 and W2 are greater than about 500 microns, the wafer may suffer from excessive bowing due to increased metal area. If widths W1 and W2 are less than about 0.1 microns, light blocking structure 174E may not block light from black level correction region 104.

[0091] In some embodiments, the image sensing device 100 may further include a doped region 110D in the substrate 110. The doped region 110D may be located adjacent to the long light-blocking structure 174E. For example, from a top view, the doped region 110D may have a ring or closed loop shape, so that the doped region 110D may laterally surround the four sides of the pixel array region 102. In some embodiments, the widths 110DW1 and 110DW2 of the doped region 110D may be respectively greater than the widths W1 and W2 of the long light-blocking structure 174E, and the lengths of the doped region 110D in directions D1 and D2 may be respectively greater than the lengths L1 and L2 of the long light-blocking structure 174E.

[0092] Figure 2 is a top view of an image sensing device 100 according to some embodiments of the present disclosure. Figures 1A to 1C In the embodiment, the long strip of light blocking structure 174E does not continuously surround the pixel array region 102. For example, the short side portion 174EV and the two long side portions 174EH of the long strip of light blocking structure 174E are disconnected from each other, and when viewed from the top, the short side portion 174EV and the long side portion 174EH are located at positions adjacent to the four sides of the pixel array region 102. In other words, the short side portion 174EV and the long side portion 174EH are separated by a gap GA, and when viewed from the top, the gap GA is set adjacent to the corner of the pixel array region 102. In this embodiment, according to the desired configuration of the light blocking structure 174E, the dielectric layer 160 (refer to Figure 1C ) has a plurality of grooves 160T1. For example, the dielectric layer 160 (refer to Figure 1C ) can be formed at positions adjacent to the four sides of the pixel array region 102, but may not continuously surround the pixel array region 102. Other details of this embodiment are similar to those previously described with respect to Figures 1A to 1C The discussion is identical and therefore will not be repeated for the sake of brevity.

[0093] Figure 3 is a top view of an image sensing device 100 according to some embodiments of the present disclosure. Figure 2 In the embodiment, except when viewed from the top, the long strip of light blocking structure 174E surrounds the corner of the pixel array area 102, but does not continuously surround the pixel array area 102. For example, one of the short side portions 174EV is connected to at least one of the long side portions 174EH, thereby surrounding the corner of the pixel array area 102. In the present embodiment, each long side portion 174EH is divided into discontinuous segments by the gap GB. In some other embodiments, the short side portion 174EV can also be divided into discontinuous segments by the gap GB. In the present embodiment, the dielectric layer 160 (refer to Figure 1C ) has a groove 160T1 according to the desired configuration of the light blocking structure 174E. For example, when viewed from the top, the groove 160T1 can surround the corner of the pixel array area 102, but not continuously surround the pixel array area 102. Other details of this embodiment are similar to those previously described with respect to Figures 1A to 3 The details discussed are therefore not repeated for the sake of brevity.

[0094] Figure 4 is a top view of an image sensing device 100 according to some embodiments of the present disclosure. This embodiment is similar to FIG. 1 except that the elongated light blocking structure 174E does not surround the corner of the pixel array area 102 when viewed from the top. Figure 3Implementation. The short side portion 174EV and the long side portion 174EH can be separated by a gap GA, and both the short side portion 174EV and the long side portion 174EH are divided into discontinuous segments by gaps GB. When viewed from the top, gaps GA are disposed adjacent to the corners of the pixel array region 102, and when viewed from the top, gaps GB are disposed adjacent to the long sides and short sides of the pixel array region 102. In this implementation, according to the desired configuration of the light blocking structure 174E, the dielectric layer 160 (refer to Figure 1C ) has a corresponding groove 160T1. For example, when viewed from the top, the groove 160T1 may not surround the corner of the pixel array area 102. Other details of this embodiment are similar to those previously described with reference to Figures 1A to 1C The details discussed are therefore not repeated for the sake of brevity.

[0095] Figures 5 to 16 1 shows a method of manufacturing an image sensing device 100 at various intermediate stages of manufacturing according to some embodiments of the present disclosure. For simplicity, some components of the image sensing device 100 are omitted. The illustration is merely exemplary and is not intended to limit the specific contents recited in the appended claims. It should be understood that in Figures 5 to 16 There may be additional steps before, during, and after the steps shown, and some of the steps described below may be replaced or eliminated in additional implementations of the method. The order of the steps / processes may be interchanged.

[0096] The image sensing device 100 may include a pixel array region 102 , a black level correction (BLC) region 104 , a scribe line region 106 , and an alignment mark region 108 . Figures 5 to 16 The dashed lines in indicate the approximate boundaries between regions 102 to 108. Photosensitive pixel 120A is formed in pixel array region 102. Photosensitive pixel 120B is formed in black level correction region 104 and is used as a reference pixel for generating a reference black level signal, thereby establishing a baseline for the light intensity of image sensing device 100. Slice road region 106 includes an area that separates one semiconductor die (for example, a semiconductor die including black level correction region 104 and pixel array region 102) from an adjacent semiconductor die (not shown). Slice road region 106 will undergo a die sawing process in a subsequent manufacturing process to separate adjacent dies. Slice road region 106 is cut so that the semiconductor device in each die is not damaged. Slice road region 106 may include an area where one or more test bonding pads (not shown) will be formed in a subsequent process stage so that an electrical connection between image sensing device 100 and an external device can be established.

[0097] refer to Figure 5. Photosensitive pixels 120 are formed in substrate 110. Substrate 110 may include, for example, doped or undoped bulk silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, a semiconductor-on-insulator substrate includes a layer of semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate, such as a silicon or glass substrate. Alternatively, substrate 110 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0098] At the front surface 110A of the substrate 110, a plurality of photosensitive pixels 120 (including photosensitive pixels 120A and 120B) are formed. The photosensitive pixels 120 may include corresponding photosensitive regions 122, which may be formed, for example, by implanting suitable impurity ions into the substrate 110 from the front surface 110A of the substrate 110. In some embodiments, the impurity ions may be implanted into an epitaxial layer (not shown) within the substrate 110. The photosensitive region 122 is configured to convert an optical signal (for example, a photon) into an electrical signal, and may be a PN junction photodiode, a PNP phototransistor, an NPN phototransistor, or the like. For example, the photosensitive region 122 may include an n-type implant region formed within a p-type semiconductor layer (for example, at least a portion of the substrate 110). In such an embodiment, the p-type semiconductor layer may isolate and reduce electrical crosstalk between adjacent photosensitive regions of the photosensitive pixel 120. In some embodiments, the photosensitive region 122 may include a p-type implant region formed within an n-type semiconductor layer (for example, at least a portion of the substrate 110).

[0099] In some embodiments, the plurality of photosensitive pixels 120 form a photosensitive pixel array, such as a two-dimensional rectangular array when viewed from the top (see Figure 1B In some embodiments, each photosensitive pixel 120 may further include a transfer gate transistor (not shown) and a floating diffusion capacitor (not shown). In each photosensitive pixel 120, a first source / drain region of a corresponding transfer gate transistor is electrically coupled to a corresponding photosensitive region 122, and a second source / drain region of a corresponding transfer gate transistor is electrically coupled to a corresponding floating diffusion capacitor.

[0100] Before forming the photosensitive region 122, an isolation structure 132 may be formed at the front surface 110A of the substrate 110. In some embodiments, the isolation structure 132 may include a shallow trench isolation (STI) structure. In some embodiments, the formation of the shallow trench structure may include: forming a groove in the substrate 110 by patterning the front surface 110A of the substrate 110, and filling the groove with a suitable dielectric material to form a shallow trench structure. The dielectric material may include silicon oxide. In some embodiments, the substrate 110 is patterned using a suitable photolithography and etching process. In other embodiments, the isolation structure 132 may include various doped regions formed using a suitable implantation process. In some embodiments, an isolation layer 134 may be formed in the cutting road area 106 and the alignment mark area 108. The isolation layer 134 may be formed simultaneously with the isolation structure 132. In some other embodiments, the isolation structure 132 may be omitted.

[0101] The internal connection structure 150 can be formed on the front surface 110A of the substrate 110 to form a circuit with the photosensitive pixel 120. The internal connection structure 150 can include an interlayer dielectric layer 152 and / or an intermetallic dielectric layer 154 containing conductive features (e.g., wires and vias containing copper, aluminum, tungsten, combinations thereof, and the like), which can be formed using any suitable method, such as inlay, dual inlay, or other similar methods. For example, the internal connection structure 150 includes a wire 154M as shown. The interlayer dielectric layer 152 and the intermetallic dielectric layer 154 can include a low-k dielectric material disposed between such conductive features, the low-k dielectric material having, for example, a k value of less than about 4.0 or even 2.0. In some embodiments, the interlayer dielectric layer 152 and the intermetallic dielectric layer 154 may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, glass spin coating, polymer spin coating, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like, and may be formed by any suitable method, such as spinning, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like.

[0102] In some embodiments, before forming the internal connection structure 150, one or more active and / or passive devices may be formed on the front surface 110A of the substrate 110 in addition to the photosensitive pixel 120 including the photosensitive region 122, the transfer gate transistor, and the floating diffusion capacitor (not shown). The one or more active and / or passive devices may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like. It will be understood by those skilled in the art that the above examples are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. Other circuits may be used as appropriate for a given application.

[0103] refer to Figure 6 . Figure 5 The structure is flipped and selectively bonded to the carrier substrate 400, so that the front surface 110A of the substrate 110 faces the carrier substrate 400 and the rear surface 110B of the substrate 110 is exposed for subsequent processes. Various bonding techniques can be used to achieve Figure 5 and the carrier substrate 400. In some embodiments, the bonding technique may include, for example, a direct bonding process, such as metal-to-metal bonding (e.g., copper-to-copper bonding), dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-dielectric bonding (e.g., oxide-to-copper bonding), hybrid bonding, adhesive bonding, anodic bonding, any combination thereof, and / or the like. In some embodiments, the carrier substrate 400 may provide mechanical support for process steps performed on the rear surface 110B of the substrate 110. In some embodiments, the carrier substrate 400 may be formed of silicon or glass and may not have circuits formed thereon. In such an embodiment, the carrier substrate 400 provides temporary support and is removed from the image sensing device 100 (refer to Fig.16 ) peel off the carrier substrate 400. The carrier substrate 400 may include a semiconductor substrate (not shown), one or more active devices (not shown) on the semiconductor substrate, and an internal connection structure (not shown) above the one or more active devices. In such an embodiment, in addition to providing mechanical support, the carrier substrate 400 may provide additional electrical functions to the image sensing device according to design requirements.

[0104] In the Figure 5After the structure is flipped and bonded to the carrier substrate 400, a thinning process may be performed on the rear surface 110B of the substrate 110 to thin the substrate 110. In some embodiments, the thinning process is used to allow more light to pass from the rear surface 110B of the substrate 110 to the photosensitive region 122 of the photosensitive pixel 120 without being absorbed by the substrate 110. In some embodiments where the photosensitive region 122 is fabricated in the epitaxial layer, the rear surface 110B of the substrate 110 may be thinned until the epitaxial layer is exposed. This may be achieved by using, for example, grinding, polishing, means, The thinning process can be accomplished by suitable techniques such as chemical etching and / or chemical etching.

[0105] refer to Figure 7 . An ion implantation process is performed on the rear surface 110B of the substrate 110 in the black level correction region 104, thereby forming a doped region 110D in the substrate 110 in the black level correction region 104. The doped region 110D may be located adjacent to the pixel array region 102. In some embodiments, a patterned mask (e.g., a photoresist mask) is formed above the rear surface 110B of the substrate 110 to define a desired location of the doped region 110D, and then the ion implantation process is performed using the patterned mask as an implantation mask, and after the ion implantation is completed, the implantation mask is removed (e.g., by using ashing). In some embodiments, the doped region 110D is further present in the substrate 110 in the pixel array region 102. In some embodiments, the photosensitive region 122 is an n-type region formed in a p-type semiconductor layer (e.g., the substrate 110), and the doped region 110D is implanted with an n-type dopant (e.g., phosphorus). In some embodiments, the photosensitive region 122 is a p-type region formed in an n-type semiconductor layer (e.g., substrate 110), and the doped region 110D is implanted with a p-type dopant (e.g., boron). In other words, the doped region 110D and the photosensitive region 122 have the same conductivity type. Figure 1A As shown, from a top view, the doped region 110D may have a ring or closed loop shape. In some embodiments, the dose of the ion implantation process may be about 100E2 to about 100E5 atoms / cm 2 In some embodiments, the dopant concentration of the doped region 110D is lower than the dopant concentration of the photosensitive region 122. In some embodiments, the dopant concentration of the doped region 110D is higher than the dopant concentration of the photosensitive region 122.

[0106] refer to Figure 8. The rear surface 110B of the substrate 110 is patterned to form a plurality of grooves 110T in the substrate 110. In some embodiments, the rear surface 110B of the substrate 110 is patterned using a suitable anisotropic wet etching process, wherein a patterned mask (e.g., a photoresist or a non-photosensitive material, such as silicon nitride) is used as an etching mask. In some embodiments where the substrate 110 is formed of silicon, potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or the like may be used to perform anisotropic wet etching. After the etching process, the patterned mask may be removed. In some embodiments where the patterned mask is formed of a photoresist, an ashing process followed by a wet cleaning process may be used to remove the patterned mask. In other embodiments where the patterned mask is formed of a non-photosensitive material, an appropriate etching process may be used to remove the patterned mask.

[0107] refer to Fig. 9 After forming the groove 110T, a dielectric layer 160 is formed on the rear surface 110B of the substrate 110 to fill the groove 110T. The dielectric layer 160 may include a charge accumulation layer 162 conformally formed on the rear surface 110B of the substrate 110 and a buffer layer 164 over the charge accumulation layer 162 .

[0108] In some embodiments, the charge accumulation layer 162 may include one or more high-k dielectric materials. For example, the charge accumulation layer 162 may include a HfO2 layer and a Ta2O5 layer on the HfO2 layer. The charge accumulation layer 162 helps accumulate negative or positive charges in the substrate 110 to reach the interface between the charge accumulation layer 162 and the substrate 110 to form electric dipoles, which are used as carrier barriers to capture defects such as dangling bonds. The configuration of the charge accumulation layer 162 can reduce leakage current of the image sensing device.

[0109] In some embodiments, the buffer layer 164 may be formed of silicon oxide, but other suitable dielectric materials may be used. In some embodiments, the buffer layer 164 may be formed using atomic layer deposition (ALD), chemical vapor deposition, PECVD, a similar method, or a combination thereof. With this configuration, between adjacent photosensitive pixels 120, a portion of the dielectric layer 160 (including the charge accumulation layer 162 and the buffer layer 164) in the groove of the substrate 110 forms an isolation structure 160I. The isolation structure 160I may prevent electrical crosstalk between the photosensitive pixels 120. The isolation structure 160I may be referred to as a back deep groove isolation (BDTI) structure. In some other embodiments, the charge accumulation layer 162 may be omitted.

[0110] refer to Fig.10 The dielectric layer 160 is patterned to form one or more grooves 160T1 and 160T2, wherein the grooves 160T1 and 160T2 expose the rear surface 110B of the substrate 110 in the black level correction region 104. In some embodiments, the dielectric layer 160 may be patterned using appropriate photolithography and etching processes. For example, a photoresist is coated on the dielectric layer 160 (see Fig. 9 ), and then patterning the photoresist using photolithography techniques to expose portions of the dielectric layer 160 in the black level correction region 104 and the alignment mark region 108. Subsequently, an etching process is performed to remove the exposed portions of the dielectric layer 160, thereby exposing the underlying substrate 110. In some embodiments, from Figure 1A From the top view, the groove 160T1 has a ring or closed loop shape.

[0111] In some embodiments of the present disclosure, the groove 160T1 is located on the doped region 110D of the substrate 110 and exposes the doped region 110D of the substrate 110. The etching process for forming the groove 160T1 may damage the substrate 110, thereby causing leakage in the substrate 110 near the groove 160T1. However, since the doped region 110D crosses the groove 160T1 and the doped region 110D has a conductivity type opposite to that of the substrate 110, a depletion region is formed near the PN junction formed between the doped region 110D and the substrate 110, which can reduce the leakage caused by the damage of the groove etching process. In some embodiments of the present disclosure, the groove 160T2 can have a thickness substantially the same as that of the groove 160T1. The groove 160T2 can be used for alignment correction during the photolithography process.

[0112] refer to Fig.11. A light blocking layer 170 is formed on the dielectric layer 160. The light blocking layer 170 may be a metal layer. In some embodiments, the light blocking layer 170 is made of a reflective metal material or a light absorbing material. For example, the light blocking layer 170 may include Cu, Au, Ag, Al, Ni, W, alloys thereof, or the like, and may be formed using physical vapor deposition (PVD), plating, and the like. In some embodiments, before forming the light blocking layer 170, a barrier / adhesion layer (not shown) may be conformally formed over the dielectric layer 160. The barrier / adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, or a multilayer thereof, and may be formed using physical vapor deposition, chemical vapor deposition, metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), electroplating, and / or the like.

[0113] In some embodiments, the light blocking layer 170 may fill one or more grooves 160T1, thereby forming one or more light blocking structures 174E in the grooves 160T1. Figure 1A From the top view shown, the groove 160T1 has a ring or closed loop shape. Figure 1A From the top view shown, the light blocking structure 174E also has a ring or closed loop shape. The light blocking structure 174E can block lateral light, thereby preventing the reference black level signal detected by the reference photosensitive pixel 120B from being affected by light.

[0114] In some further embodiments, the light blocking layer 170 is formed so that the light blocking layer 170 is electrically coupled to the substrate 110, for example, through the light blocking structure 174E. For example, the light blocking structure 174E contacts the rear surface 110B of the substrate 110. This electrical coupling provides the light blocking layer 170 with a ground potential.

[0115] refer to Fig.12 The patterned light blocking layer 170 (see Fig.11 ) are the light blocking grid 172 in the pixel array region 102, the light blocking element 174 in the black level correction region 104, and the light blocking element 178 in the alignment mark region 108. The patterning process may include appropriate photolithography and etching processes. For example, in the light blocking layer 170 (refer to Fig.11) is formed above the dielectric layer 160, and the patterned mask exposes a portion of the light blocking layer 170 in the pixel array region 102 and a portion of the light blocking layer 170 in the cutting road region 106. Subsequently, an etching process is performed to remove the exposed portion of the light blocking layer 170, thereby forming openings 170O1 and 170O2 in the light blocking layer 170 in the pixel array region 102 and the cutting road region. The etching process may include wet etching, dry etching, or a combination thereof. For example, the etching process may include dry etching using a gas etchant such as CL2, HBr, CF4, etc. The etching process may be performed until the dielectric layer 160 is exposed. In some embodiments, the exposed portion of the dielectric layer 160 may be consumed by the etching process and thus be recessed and dropped below the lateral interface between the light blocking layer 170 and the dielectric layer 160. Through the patterning process, the openings 170O1 and 170O2 of the light blocking layer 170 expose the dielectric layer 160. In some embodiments, the opening 170O1 is aligned with the corresponding photosensitive pixel 120A. In some embodiments, the opening 170O2 is aligned with the conductive line 154M. In some embodiments, during the etching process, the black level correction area 104 and the alignment mark area 108 are protected from etching, and the layers therein are not etched.

[0116] The remaining portion of the light blocking layer 170 in the black level correction area 104 is referred to as a light blocking element 174. The light blocking element 174 blocks light that would otherwise be received by the reference photosensitive pixel 120B. The light blocking element 174 has a light blocking structure 174E at a position adjacent to the pixel array area 102. The lower surface of the light blocking structure 174E is lower than the lower surface of the light blocking grid 172. With this configuration, the light blocking structure 174E can block lateral light, thereby preventing light from propagating toward the black level correction area 104. For example, the light blocking structure 174E can reflect lateral light back to the pixel array area 102. Alternatively, in some embodiments, the light blocking structure 174E may absorb lateral light. The light blocking element 174 can be electrically coupled to the substrate 110, for example, via the light blocking structure 174E. For example, the light blocking structure 174E contacts the rear surface 110B of the substrate 110. This electrical coupling provides a ground potential for the light blocking layer 170. The grounding can discharge unwanted charges in the black level correction region 104. The light blocking element 174 can include a channel 174G corresponding to the groove 160T1. For example, in a top view, the channel 174G can be an annular groove that laterally surrounds or encircles the pixel array region 102.

[0117] The remaining portion of the light blocking layer 170 in the pixel array area 102 is called a light blocking grid 172. The light blocking grid 172 has openings 170O1, which are respectively aligned with each photosensitive pixel 120A. For example, in some embodiments, when viewed from the top, the walls of the light blocking grid 172 can surround each active photosensitive pixel 120A. With this configuration, the light blocking grid 172 prevents optical crosstalk between adjacent active photosensitive pixels 120A. In this embodiment, the light blocking grid 172 and the light blocking element 174 are connected to each other and electrically coupled. In some other embodiments, the light blocking grid 172 can be separated from the light blocking element 174 after the patterning process. In an alternative embodiment, the entire light blocking layer 170 in the pixel array area 102 is removed by a patterning process. That is, after the patterning process, the light blocking layer 170 may not include the light blocking grid 172.

[0118] The remaining portion of the light blocking layer 170 in the alignment mark area 108 may be referred to as a light blocking element 178. The light blocking element 178 may be referred to as an alignment mark, such as a scribe lane primary mark (SPM) or an overlay (OVL) mark. In some embodiments, the light blocking element 178 may include a channel 178G corresponding to the groove 160T2. For example, the channel 178G formed in the light blocking element 178 is used for alignment correction to detect misalignment during the photolithography process. In an alternative embodiment, the entire light blocking layer 170 in the alignment mark area 108 is removed by a patterning process.

[0119] refer to Fig.13 The dielectric layer 180 is formed over the light blocking grid 172 and the light blocking element 174 and fills the openings 170O1 and 170O2. In some embodiments, the same dielectric layer as in the above reference may be used. Fig. 9 The dielectric layer 180 is formed by using materials and methods similar to those described above for the buffer layer 164, which will not be described again. In some embodiments, the dielectric layer 180 and the buffer layer 164 may be formed of the same material. In other embodiments, the dielectric layer 180 and the buffer layer 164 may be formed of different materials. Subsequently, the dielectric layer 180 is planarized using a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or the like.

[0120] refer to Fig.14An etching process is performed to remove a portion of the dielectric layer 180, a portion of the dielectric layer 160, and a portion of the substrate 110 in the scribe line region 106, thereby forming an opening O1 in the scribe line region 106. The opening O1 extends from the rear surface 110B of the substrate 110 toward the isolation layer 134. Subsequently, a buffer oxide layer 190 is formed on the remaining portion of the dielectric layer 180 in the regions 102, 104, and 108, and the buffer oxide layer 190 extends into the opening O1 in the scribe line region 106.

[0121] refer to Fig.15 . The buffer oxide layer 190 and the underlying dielectric material (e.g., the isolation layer 134 and the interlayer dielectric layer 152) in the scribe line region 106 are patterned to expose the conductive wire 154M of the internal connection structure 150. Subsequently, a bonding pad 200 is formed on the internal connection structure 150, so that the bonding pad 200 is electrically coupled to the exposed conductive wire 154M and is separated from the side wall of the substrate 110 by the buffer oxide layer 190. The bonding pad 200 is used to form an electrical connection, such as a wire bond (not shown), and is electrically coupled to the circuit and the photosensitive pixel 120. The bonding pad 200 can be coupled to the photosensitive pixel 120 through the internal connection structure 150.

[0122] refer to Fig.16 . The color filter layer 210 is formed above the dielectric layer 180 in the pixel array area 102. In some embodiments, the color filter layer 210 includes a plurality of color filter elements 212, each aligned with a respective active photosensitive pixel 120A. The color filter elements 212 can be used to allow light of a specific wavelength to pass through while reflecting other wavelengths, thereby allowing the image sensing device 100 to determine the color of the light received by the active photosensitive pixel 120A. For example, the color filter elements 212 can be red, green, and blue color filter elements used in a Bayer pattern. Other combinations, such as cyan, yellow, and magenta, can also be used. The number of different colors of the color filter elements 212 can also be varied. The color filter elements 212 can include a polymer material or resin, such as polymethyl-methacrylate (PMMA), polyglycidyl-methacrylate (PGMA), or the like containing a color pigment.

[0123] An array of microlenses 220 is formed above the color filter layer 210. In some embodiments, the microlenses 220 are aligned to the corresponding color filter elements 212 and the corresponding active light-sensing pixels 120A. The microlenses 220 can be formed of any material that can be patterned and formed into a lens, such as a high-transmittance acrylic polymer. In some embodiments, the microlens layer can be formed using a liquid material, such as a spin coating technique. Other methods, such as chemical vapor deposition, physical vapor deposition, or the like, can also be used. The planar material for the microlens layer can be patterned using suitable photolithography and etching methods to pattern the planar material in an array corresponding to the array of active light-sensing pixels 120A. The planar material can then be reflowed to form a suitable curved surface for the microlenses 220. Subsequently, the microlenses 220 can be cured using, for example, ultraviolet light (UV) treatment. In some embodiments, after the microlenses 220 are formed, the carrier substrate 400 (reference Fig.15 ) is peeled off from the image sensing device 100, and the image sensing device 100 can be subjected to subsequent processes, such as packaging.

[0124] Figures 17 to 28 1 shows a method 100 for manufacturing an image sensing device at various intermediate stages of manufacturing according to some embodiments of the present disclosure. For simplicity, some components of the image sensing device 100 are omitted. The illustration is merely exemplary and is not intended to limit the specific contents recited in the appended claims. It should be understood that in Figures 17 to 28 There may be additional steps before, during, and after the steps shown, and in other embodiments of the method, some of the steps described below may be replaced or eliminated. The order of the steps / processes may be interchanged. As described above, the image sensing device 100 may include a pixel array region 102, a black level correction (BLC) region 104, a cutting road region 106, and an alignment mark region 108. Figures 17 to 28 The dashed lines in indicate the approximate boundaries between regions 102-108.

[0125] refer to Fig.17 . A photosensitive region 122 is formed in the substrate 110. As previously described, the substrate 110 may include, for example, an active layer of a doped or undoped bulk silicon or semiconductor-on-insulator (SOI) substrate. For example, the photosensitive region 122 is formed by implanting appropriate impurity ions into the substrate 110 from the front surface 110A of the substrate 110. Before or after the formation of the photosensitive region 122, an isolation structure 132 and an isolation layer 134 may be formed on the front surface 110A of the substrate 110.

[0126] In the present embodiment, before or after the formation of the photosensitive region 122, an ion implantation process is performed on the front surface 110A of the substrate 110 in the black level correction region 104, thereby forming a doped region 110D in the substrate 110 in the black level correction region 104. The doped region 110D may be located in a portion of the black level correction region 104 adjacent to the pixel array region 102, and another portion of the black level correction region 104 is away from the pixel array region 102 without the doped region 110D. With this configuration, some photosensitive regions 122 may be free from the doped region 110D. Therefore, even if some photosensitive pixels 120B in the doped region 110D may not generate a suitable reference black level signal, other photosensitive pixels 120B free from the doped region 110D may generate a signal suitable for the reference black level signal.

[0127] In some embodiments, the doped region 110D may extend from the front surface 110A of the substrate 110 toward the back surface 110B of the substrate 110. In some embodiments, the doped region 110D also exists in the substrate 110 in the pixel array region 102. In some embodiments, the photosensitive region 122 is an n-type region formed in a p-type semiconductor layer, and the doped region 110D is implanted with an n-type dopant (e.g., phosphorus). In some embodiments, the photosensitive region 122 is a p-type region formed in an n-type semiconductor layer, and the doped region 110D is implanted with a p-type dopant (e.g., boron). In other words, the doped region 110D and the photosensitive region 122 have the same conductivity type. Figure 1A As shown, from a top view, the doped region 110D may have a ring or closed loop shape. In some embodiments, the dose of the ion implantation process may be about 100E2 to about 100E5 atoms / cm 2 In some embodiments, the dopant concentration of the doped region 110D is lower than the dopant concentration of the photosensitive region 122. In some embodiments, the dopant concentration of the doped region 110D is higher than the dopant concentration of the photosensitive region 122.

[0128] In this embodiment, after or before the formation of the doped region 110D, a transfer gate transistor (not shown) and a floating diffusion capacitor (not shown) may be formed on the front surface 110A of the substrate 110, thereby forming a photosensitive pixel 120 (including photosensitive pixels 120A and 120B). The photosensitive pixel 120 may include a corresponding photosensitive region 122, a corresponding transfer gate transistor (not shown), and a corresponding floating diffusion capacitor (not shown). In each photosensitive pixel 120, a first source / drain region of a corresponding transfer gate transistor is electrically coupled to a corresponding photosensitive region 122, and a second source / drain region of a corresponding transfer gate transistor is electrically coupled to a corresponding floating diffusion capacitor. In the previous Figure 5 and Figure 7 Other details of the photosensitive pixel 120, the isolation structure 132 and the doped region 110D are discussed in detail and are not repeated here for the sake of brevity.

[0129] refer to Fig.18 . After the formation of the doped region 110D and the photosensitive pixel 120, an internal connection structure 150 can be formed on the front surface 110A of the substrate 110 to form a circuit with the photosensitive pixel 120. The internal connection structure 150 can include an interlayer dielectric layer 152 and / or an intermetallic dielectric layer 154, which includes conductive features (such as wires and vias, including copper, aluminum, tungsten, combinations thereof, and the like), which can be formed using any suitable method, such as inlay, dual inlay or other similar methods. For example, the internal connection structure 150 includes a wire 154M as shown. The interlayer dielectric layer 152 and the intermetallic dielectric layer 154 can include a low-k dielectric material disposed between such conductive features. In some embodiments, before forming the internal connection structure 150, on the front surface 110A of the substrate 110, in addition to forming the photosensitive pixel 120 including the photosensitive region 122, the transfer gate transistor and the floating diffusion capacitor (not shown), one or more active and / or passive devices may be formed. It will be understood by those skilled in the art that the above examples are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. For a given application, other circuits may be used as appropriate.

[0130] refer to Fig.19 . Fig.18 The structure is flipped and bonded to the carrier substrate 400, so that the front surface 110A of the substrate 110 faces the carrier substrate 400, and the rear surface 110B of the substrate 110 is exposed for subsequent processes. Various bonding techniques can be used to achieve Fig.18The structure of the carrier substrate 400 is bonded to the carrier substrate 400. In these embodiments, the carrier substrate 400 provides temporary support and is removed from the image sensing device 100 (refer to Fig.28 ) peel off the carrier substrate 400. After bonding the image sensing device 100 and the carrier substrate 400, a thinning process may be performed on the rear surface 110B of the substrate 110 to thin the substrate 110. In some embodiments, the thinning process is used to allow more light to pass through the rear surface 110B of the substrate 110 and reach the photosensitive region 122 of the photosensitive pixel 120 without being absorbed by the substrate 110. For other details about the bonding technology, refer to the previous Figure 6 The discussion will not be repeated here.

[0131] refer to Fig. 20 The rear surface 110B of the substrate 110 is patterned to form a plurality of grooves 110T in the substrate 110. In some embodiments, the rear surface 110B of the substrate 110 is patterned using a suitable anisotropic wet etching process, wherein a patterned mask is used as an etching mask. After the etching process, the patterned mask may be removed. For further details on the formation of the grooves 110T in the substrate 110, refer to the previous Figure 8 The discussion will not be repeated here.

[0132] refer to Fig.21 . After the groove 110T is formed, a dielectric layer 160 is formed on the rear surface 110B of the substrate 110 to fill the groove 110T. The dielectric layer 160 may include a charge accumulation layer 162 conformally formed on the rear surface 110B of the substrate 110 and a buffer layer 164 above the charge accumulation layer 162. In some embodiments, the charge accumulation layer 162 and the buffer layer 164 are planarized. With this configuration, portions of the dielectric layers 162 and 164 in the groove of the substrate 110 form an isolation structure 160I between adjacent photosensitive pixels 120. The isolation structure 160I can prevent electrical crosstalk between the photosensitive pixels 120. In some other embodiments, the charge accumulation layer 162 may be omitted. For other details about the formation of the dielectric layer 160, refer to the previous Fig. 9 The discussion will not be repeated here.

[0133] refer to Fig. 22. The dielectric layer 160 is patterned to form one or more grooves 160T1 and 160T2, which expose the rear surface 110B of the substrate 110 in the black level correction area 104. In some embodiments of the present disclosure, the groove 160T1 is located above the doped region 110D of the substrate 110. The etching process for forming the groove 160T1 may damage the substrate 110, thereby causing leakage in the substrate 110 near the groove 160T1. However, since the doped region 110D crosses the groove 160T1 and the doped region 110D has a conductivity type opposite to that of the substrate 110, a depletion region is formed near the PN junction formed between the doped region 110D and the substrate 110, which can reduce the leakage caused by the damage of the groove etching process. The groove 160T2 can be used for alignment correction during the photolithography process. For other details about the patterned dielectric layer 160, refer to the previous Fig.10 The discussion will not be repeated here.

[0134] refer to Fig.23 . A light blocking layer 170 is formed on the dielectric layer 160. The light blocking layer 170 may be a metal layer. In some embodiments, the light blocking layer 170 is made of a reflective metal material or a light absorbing material. For example, the light blocking layer 170 may include aluminum, copper, nickel, tungsten, alloys thereof, and the like, and may be formed using physical vapor deposition, electroplating, or the like. In some embodiments, the light blocking layer 170 may fill one or more grooves 160T1, thereby forming one or more light blocking structures 174E in the grooves 160T1. For other details about the formation of the light blocking layer 170, refer to the previous Fig.11 The discussion will not be repeated here.

[0135] refer to Fig.24 The patterned light blocking layer 170 (see Fig.11 ) are a light blocking grid 172 in the pixel array area 102, a light blocking element 174 in the black level correction area 104, and a light blocking element 178 in the alignment mark area 108. The patterning process produces openings 170O1 and 170O2 in the light blocking layer 170, and the dielectric layer 160 is exposed through the openings 170O1 and 170O2. The patterning process may include suitable photolithography and etching processes. In some embodiments, the black level correction area 104 and the alignment mark area 108 are protected from etching, and the layers therein are not etched. Through the patterning process, the light blocking grid 172 may have an opening 170O1 aligned with the corresponding photosensitive pixel 120A. The light blocking element 174 blocks light that would otherwise be received by the reference photosensitive pixel 120B. In some embodiments, the opening 170O2 is aligned with the wire 154M in the cutting road area 106. The light blocking element 178 may be used as an alignment mark in subsequent processes.

[0136] In some embodiments, the light blocking element 174 in the black level correction region 104 has a light blocking structure 174E, which is located adjacent to the pixel array region 102. The lower surface of the light blocking structure 174E is lower than the lower surface of the light blocking grid 172. With this configuration, the light blocking structure 174E can block lateral light, thereby preventing the light from propagating toward the black level correction region 104.

[0137] The light blocking element 174 can be electrically coupled to the substrate 110, for example, electrically coupled to the substrate 110 through a light blocking structure 174E. For example, the light blocking structure 174E contacts the rear surface 110B of the substrate 110. This electrical coupling provides the light blocking layer 170 with a ground potential. In this embodiment, the light blocking grid 172 and the light blocking element 174 can be electrically coupled to each other. In some other embodiments, the light blocking grid 172 can be electrically isolated from the light blocking element 174. In an alternative embodiment, the entire light blocking layer 170 in the pixel array area 102 is removed through a patterning process. For other details about the patterned light blocking layer 170, refer to the previous Fig.12 The discussion will not be repeated here.

[0138] refer to Fig.25 A dielectric layer 180 is formed on the light blocking grid 172 and the light blocking element 174, and the dielectric layer 180 fills the openings 170O1 and 170O2. Subsequently, the dielectric layer 180 is planarized using a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or the like. For other details about the formation of the dielectric layer 180, refer to the previous Fig.13 The discussion will not be repeated here.

[0139] refer to Fig.26 An etching process is performed to remove a portion of the dielectric layer 180, a portion of the dielectric layer 160, and a portion of the substrate 110 in the scribe line region 106, thereby forming an opening O1 in the scribe line region 106. The opening O1 extends from the rear surface 110B of the substrate 110 toward the front surface 110A of the substrate 110. Subsequently, a buffer oxide layer 190 is formed on the remaining portion of the dielectric layer 180 in the regions 102, 104, and 108, and the buffer oxide layer 190 extends into the opening O1 in the scribe line region 106.

[0140] refer to Fig. 27. The buffer oxide layer 190 and the underlying dielectric material (for example, the isolation layer 134 and the interlayer dielectric layer 152) in the scribe line region 106 are patterned to expose the conductive layer 154M of the internal connection structure 150. Subsequently, a bonding pad 200 is formed on the internal connection structure 150, so that the bonding pad 200 is electrically coupled to the exposed conductive wire 154M and is separated from the side wall of the substrate 110 by the buffer oxide layer 190. The bonding pad 200 is used to form an electrical connection, such as a wire bond (not shown), and is electrically coupled to the circuit and the photosensitive pixel 120. The bonding pad 200 can be coupled to the photosensitive pixel 120 through the internal connection structure 150.

[0141] refer to Fig.28 . A color filter layer 210 may be formed over the dielectric layer 180 in the pixel array region 102. In some embodiments, the color filter layer 210 includes a plurality of color filter elements 212, each aligned with a respective active light-sensing pixel 120A. In some embodiments, an array of microlenses 220 is formed over the color filter layer 210 and aligned with respective color filter elements 212 and respective active light-sensing pixels 120A. In some embodiments, after forming the microlenses 220, a carrier substrate 400 (see Fig. 27 ) is peeled off from the image sensing device 100, and the image sensing device 100 can be subjected to subsequent processes, such as packaging. For other details about the formation of the color filter layer 210 and the microlens 220, refer to the previous Fig.16 The discussion will not be repeated here.

[0142] Fig.29 is a schematic cross-sectional view of an image sensing device according to some embodiments of the present disclosure. Fig.16 and Fig. 27 In the embodiment, except that the doped region 110D is omitted in the substrate 110 (refer to Fig.16 ). In some embodiments, Fig.29 The image sensing device can be used in Figures 5 to 16 The process flow shown is formed by skipping Figure 7 In some other embodiments, Fig.29 The image sensing device can be used in Figures 17 to 28 The process flow shown is formed while skipping Fig.17 The ion implantation step of the doped region 110D shown in FIG. Figures 5 to 28 The discussion is similar and therefore will not be repeated here for the sake of brevity.

[0143] Based on the above discussion, it can be seen that the present disclosure provides some advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are disclosed here, and not all embodiments require specific advantages. One of the advantages of the present case is that the long strip of metal structure in the black level correction area can prevent light from propagating laterally from the pixel array area to the black level correction area. Another advantage of the present case is that the long strip of metal structure can laterally surround or surround the entire pixel array area, thereby improving the ability to block light. Another advantage of the present case is that the long strip of metal structure can contact the substrate, so that the long strip of metal structure and the metal grid extending from the long strip of metal structure are grounded. Another advantage of the present case is that an additional doped region is formed in the substrate, and the doped region is parallel to the long strip of metal structure, which reduces the leakage caused by substrate damage caused by the etching process of forming a groove, and the groove is used to receive the long strip of metal structure.

[0144] Some embodiments of the present disclosure provide a method for manufacturing an image sensing device. The method includes forming a plurality of photosensitive pixels on a substrate; depositing a dielectric layer on the substrate; etching the dielectric layer to form a first groove in the dielectric layer, the first groove laterally surrounding the plurality of photosensitive pixels; forming a light-blocking structure in the first groove, so that the light-blocking structure laterally surrounds the plurality of photosensitive pixels.

[0145] In some embodiments, the dielectric layer is etched so that a portion of the substrate is exposed in the first groove.

[0146] In some embodiments, the light blocking structure is formed to contact the portion of the substrate in the first groove.

[0147] In some embodiments, the method further includes forming a plurality of reference photosensitive pixels around the plurality of photosensitive pixels, wherein the light blocking structure is formed so that the light blocking structure overlaps the plurality of reference photosensitive pixels.

[0148] In some embodiments, forming the light blocking structure includes depositing a metal layer on the dielectric layer and in the first groove; and patterning the metal layer to form the light blocking structure.

[0149] In some embodiments, the metal layer is patterned to form a metal grid on the plurality of photosensitive pixels.

[0150] In some embodiments, the metal layer is patterned so that a lower surface of the light-blocking structure is lower than a lower surface of the metal grid.

[0151] In some embodiments, the method further includes forming a doped region in the substrate, wherein the doped region is parallel to the first trench when viewed from a top view, and the doped region and the substrate have opposite conductivity types.

[0152] In some implementations, the light blocking structure is formed so as to contact the doped region.

[0153] In some implementations, the light blocking structure is formed so as to be separated from the doped region.

[0154] In some embodiments, the method further includes etching a second recess in the substrate before depositing the dielectric layer, wherein the dielectric layer is deposited such that the dielectric layer fills the second recess in the substrate.

[0155] Some embodiments of the present disclosure provide a method for manufacturing an image sensing device. The method includes forming a plurality of photosensitive pixels in a substrate through a front surface of the substrate; forming a doped region in the substrate, wherein the doped region laterally surrounds the plurality of photosensitive pixels of the substrate; depositing a dielectric layer on a rear surface of the substrate, wherein the rear surface of the substrate is opposite to the front surface of the substrate; etching the dielectric layer to form a first groove, wherein the first groove overlaps the doped region; and forming a light blocking structure in the first groove.

[0156] In some embodiments, etching the dielectric layer causes the first groove to be parallel to the doped region.

[0157] In some embodiments, the doped region is formed by ion implantation on the rear surface of the substrate.

[0158] In some embodiments, the doped region is formed by ion implantation on the front surface of the substrate.

[0159] In some embodiments, the dielectric layer is etched to expose the doped region in the substrate.

[0160] In some embodiments, the doped region and the substrate are of opposite conductivity types.

[0161] Some embodiments of the present disclosure provide an image sensing device, comprising a substrate, a plurality of photosensitive pixels, an internal connection structure, a dielectric layer, and a light-blocking element. The photosensitive pixels are located in the substrate. The internal connection structure is located on a first side of the substrate. The dielectric layer is located on a second side of the substrate, wherein the second side of the substrate is relative to the first side of the substrate. The light-blocking element has a first portion extending on an upper surface of the dielectric layer and a second portion extending in the dielectric layer, wherein the second portion of the light-blocking element laterally surrounds the plurality of photosensitive pixels.

[0162] In some embodiments, the image sensing device further includes a grid structure extending from the light blocking element to the plurality of photosensitive pixels.

[0163] In some embodiments, the image sensing device further includes a doped region located in the substrate and extending parallel to the second portion of the light blocking element when viewed from a top view.

[0164] The above summarizes the features of multiple embodiments, and those with ordinary knowledge in the art can better understand the multiple aspects of the present disclosure. Those with ordinary knowledge in the art should understand that the present disclosure can be used as a basis for designing or modifying other processes or structures to achieve the same purpose and / or the same benefits mentioned in the embodiments. Those with ordinary knowledge in the art should also understand that these equivalent structures do not exceed the spirit and scope of the present disclosure, and various changes, substitutions, and transformations can be made. Here, the spirit and scope of the present disclosure covers these changes, substitutions, and transformations.

Claims

1. A method for manufacturing an image sensing device, characterized in that: Include: Forming a plurality of photosensitive pixels and a plurality of reference photosensitive pixels around the plurality of photosensitive pixels on a substrate; Depositing a dielectric layer on the substrate; etching the dielectric layer to form a first groove in the dielectric layer, wherein the first groove laterally surrounds the plurality of photosensitive pixels; and A light blocking structure is formed in the first groove, so that the light blocking structure laterally surrounds the plurality of photosensitive pixels, and a lowest surface of the light blocking structure directly contacts the substrate and overlaps the plurality of reference photosensitive pixels in a top view.

2. The method according to claim 1, characterized in that The dielectric layer is etched so that a portion of the substrate in the first groove is exposed.

3. The method according to claim 2, characterized in that The light blocking structure formed therein contacts the portion of the substrate in the first groove.

4. The method according to claim 1, characterized in that: The dielectric layer is deposited so as to form an isolation structure between the plurality of photosensitive pixels and two adjacent ones of the plurality of photosensitive pixels.

5. The method according to claim 1, characterized in that The forming of the light blocking structure comprises: Depositing a metal layer on the dielectric layer and in the first groove; and The metal layer is patterned to form the light blocking structure.

6. The method according to claim 5, characterized in that The metal layer is patterned to form a metal grid on the plurality of photosensitive pixels.

7. The method according to claim 6, characterized in that The metal layer is patterned so that the lowest surface of the light-shielding structure is lower than a lower surface of the metal grid.

8. The method according to claim 1, characterized in that Also includes: A doping region is formed in the substrate, wherein the doping region is parallel to the first groove when viewed from the top view, and the doping region and the substrate have opposite conductivity types.

9. The method according to claim 8, characterized in that The light blocking structure is formed so as to contact the doped region.

10. The method according to claim 8, characterized in that The light blocking structure is formed so as to be separated from the doped region.

11. The method according to claim 1, characterized in that: Also includes: A second recess is etched in the substrate before depositing the dielectric layer, wherein the dielectric layer is deposited such that the dielectric layer fills the second recess in the substrate.

12. A method for manufacturing an image sensing device, characterized in that: Include: In a substrate, a plurality of photosensitive pixels and a plurality of reference photosensitive pixels around the plurality of photosensitive pixels are formed through a front surface of the substrate; In the substrate, a doped region is formed, wherein the doped region laterally surrounds the plurality of photosensitive pixels of the substrate; Depositing a dielectric layer on a rear surface of the substrate, wherein the rear surface of the substrate is opposite to the front surface of the substrate; Etching the dielectric layer to form a first groove, wherein the first groove overlaps the doped region and exposes the substrate; and A light-blocking structure is formed in the first groove, so that a lowest surface of the light-blocking structure directly contacts the substrate and overlaps the plurality of reference light-sensitive pixels in a top view.

13. The method according to claim 12, characterized in that The dielectric layer is etched to form the first groove parallel to the doped region.

14. The method according to claim 12, characterized in that The doped region is formed by performing ion implantation on the rear surface of the substrate.

15. The method according to claim 12, characterized in that The doped region is formed by performing ion implantation on the front surface of the substrate.

16. The method according to claim 12, characterized in that The dielectric layer is etched to expose the doped region in the substrate.

17. The method according to claim 12, characterized in that The doped region and the substrate are of opposite conductivity types.

18. An image sensing device, characterized in that: Include: a substrate; A plurality of photosensitive pixels and a plurality of reference photosensitive pixels around the plurality of photosensitive pixels are located in the substrate; an inner connection structure located on a first side of the substrate; a dielectric layer located on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate; and A light blocking element having a first portion extending on an upper surface of the dielectric layer and a second portion extending in the dielectric layer, wherein the second portion of the light blocking element laterally surrounds the multiple photosensitive pixels, a lowest surface of the second portion of the light blocking element is lower than the upper surface of the dielectric layer and higher than the multiple reference photosensitive pixels, and the second portion of the light blocking element overlaps the multiple reference photosensitive pixels in a top view.

19. The image sensing device according to claim 18, wherein: Also includes: A grid structure extends from the light blocking element to the plurality of light-sensitive pixels.

20. The image sensing device according to claim 18, wherein: Also includes: A doped region is located in the substrate and extends parallel to the second portion of the light blocking element when viewed from the top view.

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