Analog-to-digital conversion apparatus and method of operation

Abstract

An analog-to-digital conversion apparatus includes a first stage converter that performs a first analog-to-digital conversion on an input analog signal during a first stage period, a second stage converter that receives a first residue amplified by a first gain from the first stage converter and performs a second analog-to-digital conversion during a second stage period, and recombination logic that combines a first output signal from the first stage converter and a second output signal from the second stage converter into an output digital signal corresponding to the input analog signal. The second stage converter generates a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle of the second stage period, and generates the second output signal of a second sub-cycle following the first sub-cycle based on the second stage feedback signal.

Description

Technical Field

[0001] This disclosure relates to analog-to-digital conversion devices, and more specifically, to analog-to-digital conversion devices with high speed and / or high resolution. Background Technology

[0002] In many electronic device applications, analog-to-digital converters are devices configured to convert analog signals into digital signals, and are an indispensable piece of intellectual property for these applications.

[0003] (IP) components. An analog-to-digital converter (ADC) is a device that receives an input signal in analog form representing continuous values ​​and converts it into a signal in digital form (n bits) representing discrete values.

[0004] According to some examples, in precision measurement systems, electronic devices include one or more sensors for measurement, and these sensors generate analog signals. In order to perform subsequent processing using a microcomputer or similar device in the precision measurement system, it is necessary to convert the analog values ​​into digital values. As another example, in a mobile device receiver, the analog signal generated by the antenna is input to an analog-to-digital converter, converted into a digital signal, and then output.

[0005] When a continuous analog signal is converted into a digital signal, errors may occur during the quantization of the analog signal (quantization error).

[0006] Factors that measure the performance of analog-to-digital converters (ADCs) include conversion bandwidth and dynamic range (signal-to-noise ratio). The bandwidth of an ADC is primarily specified by its sampling rate, while the dynamic range is affected by factors such as resolution, linearity, and accuracy. The dynamic range of an ADC can be represented by its effective number of bits. Summary of the Invention

[0007] This disclosure provides an analog-to-digital converter with high accuracy and low power consumption.

[0008] This disclosure also provides an analog-to-digital converter with high speed and high resolution.

[0009] However, the aspects of this disclosure are not limited to those expressly set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of the inventive concept.

[0010] According to some example embodiments of this disclosure, an analog-to-digital conversion device may include: a first-stage converter configured to perform a first analog-to-digital conversion on an input analog signal during a first-stage cycle and configured to output a first output signal and a first residual; a second-stage converter configured to receive the first residual amplified by a first gain, configured to perform a second analog-to-digital conversion during a second-stage cycle, and configured to output a second output signal; and a recombining logic circuit configured to combine the first output signal and the second output signal and output an output digital signal corresponding to the input analog signal. The second-stage converter is configured to generate a second-stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second-stage cycle, and is configured to generate a second output signal for a second sub-cycle following the first sub-cycle based on the second-stage feedback signal.

[0011] According to some example embodiments of this disclosure, a wireless communication device may include: a low-noise amplifier configured to amplify a radio frequency (RF) signal received via an antenna; a mixer configured to down-convert the amplified RF signal to a baseband frequency range; a low-pass filter configured to filter the signal down-converted by the mixer, and an analog-to-digital converter configured to receive an input analog signal from the low-pass filter and to convert the input analog signal into an output digital signal; and a digital signal processor configured to process the output digital signal.

[0012] According to some example embodiments of this disclosure, an analog-to-digital conversion device may include: a successive approximation register (SAR) converter configured to perform a first analog-to-digital signal conversion on an input analog signal during a first period and configured to output a first output signal and a first residual; a first transmission circuit configured to amplify the first residual by a first gain; a plurality of Δ-∑(DS) converters, each DS converter configured to perform a second analog-to-digital conversion based on the amplified first residual and a DS feedback signal during a second period, and each DS converter configured to generate a second output signal; a plurality of first switches, each connected between the first transmission circuit and a corresponding DS converter among the plurality of DS converters, each first switch configured to be controlled by an enable signal and each first switch configured to send the amplified first residual to the corresponding DS converter in a time-interleaved manner; and a recombination logic circuit configured to combine the first output signal and the second output signal generated by the plurality of DS converters to output an output digital signal. Each of the plurality of DS converters includes a second transmission circuit configured to amplify the second output signal by a first gain to generate a DS feedback signal.

[0013] According to some example embodiments of this disclosure, an analog-to-digital conversion device may include: a plurality of open-loop converters, each open-loop converter configured to convert an input analog signal and output a first output signal and a first residual from a first output terminal; a first buffer connected to the first output terminal and configured to buffer the first residual; at least one Δ∑(DS) converter configured to perform a Δ-∑ conversion on the buffered first residual and configured to output a second output signal and a DS feedback signal; and recombining logic circuitry configured to combine the first output signal and the second output signal into an output digital signal. Each of the at least one DS converter includes a second buffer configured to send the second output signal as a DS feedback signal.

[0014] According to some example embodiments of this disclosure, an analog-to-digital conversion method may include: performing a first analog-to-digital conversion on an input analog signal to generate a first output signal and a first residual signal; amplifying the first residual signal once by a first gain; transmitting the amplified first residual signal based on an enable signal; performing a second analog-to-digital conversion based on the amplified first residual signal and a DS feedback signal to generate a second output signal; and combining the first output signal and the second output signal to output an output digital signal. The DS feedback signal may be a signal generated based on amplifying the second output signal twice by a first gain.

[0015] According to some example embodiments of this disclosure, an analog-to-digital conversion method includes: performing a first analog-to-digital conversion on an input analog signal based on an applied sampled signal to generate a first output signal and a first residual; amplifying the first residual by a first gain; performing a second analog-to-digital conversion on the amplified first residual based on an applied enable signal to generate a second output signal; and combining the first output signal and the second output signal to output an output digital signal. The second output signal can be generated by performing an analog conversion on the second output signal of a first sub-operation cycle and subtracting a second amplified first feedback signal from the first residual based on an inverted enable signal, and the second amplified first feedback signal can be amplified by a first gain. Attached Figure Description

[0016] The above and other embodiments and features of this disclosure will become more apparent from examples of embodiments thereof described in detail with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a block diagram illustrating an analog-to-digital conversion device according to some example embodiments.

[0018] Figure 2 This is a diagram illustrating the operation of an analog-to-digital conversion device according to some example embodiments.

[0019] Figure 3 It is shown in detail Figure 1 The first level diagram.

[0020] Figure 4 It is shown in detail Figure 1 The diagram shows the second-stage converter.

[0021] Figure 5A and Figure 5B Examples of transmission circuits that can be used to implement a first transmission circuit and a second transmission circuit according to some example embodiments are shown.

[0022] Figure 6A and Figure 6B A first transmission circuit and a second transmission circuit according to some example embodiments are shown.

[0023] Figure 7 This is a block diagram illustrating an analog-to-digital conversion device according to some example embodiments.

[0024] Figure 8 This is a timing diagram used to illustrate an analog-to-digital conversion method according to some example embodiments.

[0025] Figure 9 This is a block diagram illustrating an analog-to-digital conversion device according to some example embodiments.

[0026] Figure 10 This is a diagram illustrating a wireless communication device using an analog-to-digital converter according to some example embodiments.

[0027] Figure 11 Examples of eNBs according to some embodiments are shown.

[0028] Figure 12 This is a block diagram of an electronic device in a network environment according to some example embodiments. Detailed Implementation

[0029] Hereinafter, some exemplary embodiments based on the concept of the present invention will be described with reference to the accompanying drawings.

[0030] This disclosure (but not necessarily an inventive concept) assumes that the final output signal DO of the digital conversion is K bits, or of length K bits (where K is a natural number of 1 or greater). The first stage performs analog-to-digital conversion on M bits starting from the most significant bit (MSB), and the second stage performs analog-to-digital conversion on the remaining bits after M bits (i.e., N bits starting from the least significant bit (LSB), where K = M + N. That is, K is greater than M or N, K is a natural number, and M and N are rational numbers of 0 or greater.

[0031] Figure 1 This is a block diagram illustrating an analog-to-digital conversion device according to some example embodiments. Figure 2 This is a diagram illustrating the operation of an analog-to-digital conversion device according to some example embodiments. Figure 3 It is shown in detail Figure 1 The first level of the diagram, Figure 4 It is shown in detail Figure 1 The diagram shows the second-stage converter.

[0032] Reference Figure 1 According to some embodiments, the analog-to-digital conversion device 1 may include a first-stage converter 100, a first transmission circuit (AMP1) 200, a first switch SW1, a second-stage converter 300, a second transmission circuit (AMP2) 400, a second switch SW2, and a reconfiguration logic circuit 500.

[0033] The first-stage converter 100 can be configured to process the input analog signal V. IN Performs a first analog-to-digital conversion and can be configured to output a first output signal D1 and a first residual E. Q1 Both. The first output signal D1 can be output to the reconfiguration logic circuit 500. The first residual E Q1 It can be output to the first transmission circuit 200.

[0034] The first transmission circuit 200 is configured to amplify and output the first residual E received from the first-stage converter 100. Q1 The first transmission circuit 200 can amplify the first residual E at a first gain α. Q1 According to some example embodiments, the first gain α may have a value of 1, and in some example embodiments, the first gain α may have a value greater than or less than 1. The output of the first transmission circuit 200 may be referred to as the amplified first residual αE. Q1 .

[0035] The first switch SW1 connects the first transmission circuit 200 and the second-stage converter 300. In other words, the first terminal of the first switch SW1 can be connected to the first transmission circuit 200, and the second terminal of the first switch SW1 can be connected to the second-stage converter 300. The first switch SW1 operates according to the enable signal T. residue ( Figure 1 (Not shown in the image) is used to switch. Enable signal T residue It can be activated after the first-stage converter 100 has completed or ended its operation and before the second-stage converter 200 has started or been initiated. That is, the enable signal T residue This can be a signal used to start the operation of the second-stage converter 300. The logic value of the enable signal can be an "on" value or an "off" value, where the on value indicates that the signal is enabled and the off value indicates that the signal is disabled.

[0036] The second-stage converter 300 is connected between the second terminal of the first switch SW1 and the recombination logic circuit 500, and can be configured to receive the amplified first residual αE from the first transmission circuit 200 via the first switch SW1. Q1 (like Figure 1 (As shown). The second-stage converter 300 can be configured to amplify the first residual αE. Q1 A second analog-to-digital (ADC) signal conversion is performed, and the result of the second ADC is output as a second output signal D2 to the reconfiguration logic circuit 500. Additionally, the second-stage converter 300 is configured to output the second output signal D2 to the second transmission circuit 400.

[0037] The second transmission circuit 400 is connected between the second-stage converter 300 and the second switch SW2, and is configured to amplify the received second output signal D2 by a second gain and output the amplified signal to the second switch SW2. In some example embodiments, the second gain may have the same value as the first gain α, but this disclosure is not limited thereto. According to some example embodiments, the second transmission circuit 400 may be a replica or copy of the first transmission circuit 200. The input and output terminals of the second transmission circuit 400 may be connected to different nodes of the second-stage converter 300. The signal amplified by the second transmission circuit 400 may be input to the second-stage converter 300 as a feedback signal via the second switch SW2.

[0038] The reconfiguration logic circuit 500 can combine the first output signal D1 and the second output signal D2 to generate the output digital signal D0.

[0039] According to some example embodiments, the first-stage converter 100 can be an open-loop converter, and the second-stage converter 300 can be a closed-loop converter.

[0040] While using an open-loop converter can reduce overall power consumption, additional or separate calibration may be required because the accuracy of the gain in the residual amplifier circuit can degrade. On the other hand, a closed-loop converter, due to its feedback structure, can exhibit increased accuracy while adjusting the ratio of the sampling capacitor to the feedback capacitor. However, in high-speed applications, closed-loop converters can introduce considerable power consumption and processing speeds that can be slow, potentially unacceptably so.

[0041] Figure 1 The analog-to-digital converter 1 shown can be implemented as a pipeline structure. That is, the analog-to-digital converter 1 can be arranged such that in the first stage converter 100 during the first stage cycle T SAR After the first analog-to-digital conversion is performed during the second stage, the second-stage converter 300 can perform the second-stage cycle T. DSM During this period, a second analog-to-digital conversion is performed based on the output of the first-stage converter 100. The first-stage converter 100 and the second-stage converter 300 can perform the first and second analog-to-digital conversions respectively according to their respective sub-operation loops. Hereinafter, the sub-operation loop T of the first-stage converter 100... SAR.CONV This can be referred to as the first-level sub-loop, and the second-level converter 300's sub-operation loop T.DSM.CONV It can be called a second-level sub-loop, but in some cases, for the sake of convenience, each sub-loop can be called in other ways.

[0042] According to some example embodiments, a preceding stage may include at least one open-loop converter, and a subsequent stage may include at least one closed-loop converter. As described herein, an analog-to-digital converter combining open-loop and closed-loop converters may have increased, higher, or higher resolution and may be able to process input analog signals at increased, higher, or higher speeds. If multiple open-loop converters are present in the preceding stage, they may be connected in series with each other, according to some example embodiments. If multiple closed-loop converters are present in the subsequent stage, they may be connected in parallel with each other, according to some example embodiments.

[0043] That is, in some example embodiments, the analog-to-digital conversion device 1 may include multiple stages, and each stage may be configured to amplify and pass the residual (residual voltage) remaining after conversion from the previous stage to the next stage. In some example embodiments, the residual may be the quantization error of that stage. The preceding stage may be configured to output a bit close to or closer to the most significant bit (MSB), and the following stage may be configured to output a bit close to or closer to the least significant bit (LSB).

[0044] More specifically, in Figure 2 In the example shown, it is assumed that the analog-to-digital converter has a 3-bit resolution, the first-stage converter (stage 1) has a 2-bit resolution, and the second-stage converter (stage 2) has a 1-bit resolution. This disclosure is not limited to this example.

[0045] The first-stage converter (stage 1) first divides the entire segment into two bits, that is, a total of four bits (=2). 2 The four segments are 00, 01, 10, and 11. The first-stage converter then searches among these four segments to find the segment to which the input analog signal belongs. In the example shown, the input analog signal is first determined to belong to 10 (D1), and the residual is passed so that the second-stage converter (stage 2) can determine a more specific value.

[0046] The second-stage converter (stage 2) divides the segment corresponding to 10 into one bit, that is, two (=2) 1 Regions 0 and 1, and in the example shown, a more specific value of 1 is determined based on the region (D2) to which the received residual belongs.

[0047] continue Figure 2 For example, the reconfiguration logic circuit then outputs a digital signal 101 (D0). In some example embodiments, the reconfiguration logic circuit outputs a digital signal (D0) in combination with the input analog signal.

[0048] Multiple levels are possible Figure 2 The operation shown, and / or depending on the resolution of each level, may result in more or fewer bits of digital output signal. Similarly, the exemplary embodiments of the present invention are not limited to those described above. Figure 2 Examples shown and described.

[0049] In some example embodiments, the first-stage converter 100 may be a successive approximation converter. For example, Figure 3 An embodiment is described in which the first-stage converter 100 is implemented as a successive approximation converter. Figure 3 In this first-stage converter 100, an input analog signal V can be applied. IN As input, an analog-to-digital conversion can be performed to output a first output signal D1 and a first residual E. Q1 The analog-to-digital conversion performed by the first-stage converter 100 can be as described above. Figure 1 The first analog-to-digital conversion discussed.

[0050] More specifically, according to some example embodiments, the first-stage converter 100 may include a sample-and-hold circuit 110, a comparator 130, SAR logic circuitry 140, and a SAR digital-to-analog converter (DAC) 150. According to some embodiments, the first-stage converter 100 may also include a first computing unit 120.

[0051] Upon receiving the input analog signal V IN At that time, the sample-and-hold circuit 110 can perform sampling according to the sampling frequency fs and can output a held signal. The sample-and-hold circuit 110 can perform sampling according to the sampled signal T. sample And then it was activated.

[0052] According to some example embodiments, the first calculation unit 120 and comparator 130 can output a result obtained by comparing the output signal of the sample-and-hold circuit 110 with the value stored in the SAR DAC 150 in the previous first-stage sub-cycle, i.e., a first feedback signal (d). The result (b) obtained by comparison can be output to the SAR logic circuit 140. In some example embodiments, when the sampling signal is enabled, if the output (a) of the sample-and-hold circuit 110 is greater than the value (d) stored in the SAR DAC 150 in the previous first-stage sub-cycle, the SAR logic circuit 140 can perform counting, convert the count value to an analog value via the SAR DAC 150 during the sub-cycle within the first-stage operating segment, and store it as a comparison reference for the next sub-cycle. The first-stage converter 100 can repeatedly perform the above process, and when the first-stage cycle ends, the first-stage converter 100 can be configured to output the counting result at the end of the first-stage cycle as a first output signal D1 to the recombination logic circuit 500. Furthermore, the first-stage converter 100 can be configured to output the result obtained by comparing the output signal (a) at the end of the first-stage cycle with the value stored in the SAR DAC 150 of the first-stage sub-cycle immediately preceding the end to the first residual.

[0053] That is, the first-stage converter 100 can be configured to combine or compute the sampled input analog signal (a) and the first feedback signal (d) to output a first output signal D1 and a first residual signal E. Q1 .

[0054] The SAR logic circuit 140 can count the output signal (b) of the comparator 130 according to the first-level sub-cycle to generate a first output signal D1. At this time, the first output signal D1 can be a digital signal.

[0055] The SAR DAC 150 can convert the first output signal D1 generated by the SAR logic circuit 140 into an analog signal and output it as the first feedback signal (d).

[0056] The first-stage converter 100 described above illustrates an example of a SAR converter. However, this disclosure is not limited thereto, and according to various example embodiments, the first-stage converter 100 may use a SAR converter with a different structure or an open-loop converter of a type other than SAR.

[0057] In some example embodiments, the second-stage converter 300 may be a Δ-Σ modulation-based converter, i.e., a Δ-Σ converter. A Δ-Σ converter can have increased, higher, or higher resolution through oversampling. The Δ-Σ converter can be configured to correct accumulated errors in the input data, convert the errors into a digital signal, and reflect the converted digital signal in the input data.

[0058] Figure 4 The second-stage converter 300 shown is an example of a Δ-Σ converter and may include a loop filter circuit 320, a quantization circuit 330, a DS logic circuit 340, and a DS DAC 350. The second-stage converter 300 may also include a second computing unit.

[0059] The second calculation unit 310 can calculate the amplified second feedback signal (i) and the amplified first residual αE. Q1 The signal is combined, and the result (e) can be output to the loop filter circuit 320. The loop filter circuit 320 can filter the received signal (e) and can obtain samples several times to accumulate the error for correcting the error of the initially obtained signal (e). That is, the loop filter circuit 320 can perform oversampling (i.e., sampling multiple times) to obtain the second output signal D2.

[0060] According to some example embodiments, in the loop filter circuit 320, it can serve as a signal transfer function. Apply the first residual αE amplified by the function H(s) Q1 And it can be used as a noise transfer function. Apply the second residual E to the second-stage converter 300 Q2 .

[0061] Quantization circuit 330 digitizes and outputs the accumulated error (g). In some embodiments, quantization circuit 330 may have an N-bit resolution (where N is a natural number). According to some example embodiments, quantization circuit 330 may be implemented as a comparator circuit. Quantization circuit 330 may compare the output signal (f) of loop filter circuit 320 with a second reference voltage V. REF The comparison is performed, and an output signal (g) can be output based on the comparison result. (See reference...) Figure 2 In the example shown, the quantization circuit 330 can compare the output signal (f) with the second reference voltage V. REF It compares the results and can output 1.

[0062] Second reference voltage V REF It can vary according to the full-scale input voltage range of the second-stage converter 300. That is, Figure 2 The ranges of the minimum value Min2 and the maximum value Max2 shown can be determined based on the second reference voltage V. REF To set. According to some example embodiments, the second reference voltage V REF It can be connected to the first reference voltage V of the first-stage converter 100 REF same.

[0063] The DS logic circuit 340 stores the output signal (g) of the quantization circuit 330 and then outputs a digitized second output signal D2. According to some embodiments, the DS logic circuit 340 may include a low-pass filter LPF and a decimator, and may be configured to filter noise in the high-frequency band, thin out redundant data obtained through oversampling, and reduce the data to the desired sampling frequency band.

[0064] The DS DAC 350 outputs a second feedback signal (h), which can be obtained by converting the digital output signal (g) of the quantization circuit 330 into an analog signal. The output second feedback signal (h) can be output to the second transmission circuit 400.

[0065] The second transmission circuit 400 operates according to the inverting enable signal at the second gain α. DSM The second feedback signal (h) is amplified. The second feedback signal (h), amplified by the second gain, can withstand the analog signal (i.e., the first residual αE) obtained through oversampling for error correction. Q1 Subtraction is performed using subtraction. That is, the error is obtained through subtraction.

[0066] In other words, it can be at least partially based on the second gain α. DSM The second feedback signal (h) obtained by amplifying the second output signal D2 of the previous cycle is used to calculate the second output signal D2 of the second-stage converter 300. In some example embodiments, the second gain α DSM The gain is the same as the first gain α, but this disclosure is not limited thereto. The gain will be specifically explained by the following equation.

[0067] The second transmission circuit 400 can be the same as or identical to the first transmission circuit 200. That is, the second transmission circuit 400 can be a copy of the first transmission circuit. Figures 5A to 6B An example illustrating the transmission circuit.

[0068] The second switch SW2 can be connected between the output terminal of the second transmission circuit 400 and the input terminal of the loop filter circuit 320 (e.g., via the second calculation unit 310), and can be activated according to the inverting enable signal ( / T). residue The second feedback signal, amplified by the second gain, is sent to the loop filter circuit 320. The inverting enable signal ( / T) residue () is the opposite of the enable signal and can be activated from the beginning or initiation of the second-level operation segment to the end or completion of the second-level operation segment.

[0069] The operation of analog-to-digital conversion device 1 according to some embodiments will be described more mathematically below.

[0070] When an input analog signal V is applied INAt that time, the first-stage converter 100 performs a first analog-to-digital conversion to output a first output signal D1 and a first residual E. Q1 First residual E Q1 The first output signal D1 is output to the first transmission circuit 200 and then to the reconfiguration logic circuit 500. The first output signal D1 is a signal that includes input analog signal V... IN The signal V is obtained by converting the digital signal into M bits starting from MSB out of a total of K bits. IN ' and the first residual E Q1 As shown in equation (1).

[0071] D1 = V IN ′+E Q1 Equation (1)

[0072] The second-stage converter 300 receives the amplified first residual αE via the first switch SW1. Q1 The second analog-to-digital conversion is performed to output the conversion result as the second output signal D2. The second output signal D2 is obtained by amplifying the first residual αE as shown in equation (2). Q1 The signal is obtained by digital conversion from each bit in the total K bits, from LSB to the highest Nth bit (i.e., from the (KM)th bit to the least significant bit (LSB)), and includes the amplified first residual αE. Q1 Second residual E Q2 As mentioned earlier, K is a natural number greater than M, and K is equal to the sum of M and N.

[0073] D2=-αE Q1 +E Q2 Equation (2)

[0074] The recombining logic circuit 500 combines the first output signal D1 and the second output signal D2 and outputs the combined signal as the final output signal D. O .

[0075] As an example, suppose the second output signal D2 reflects the second gain α D The signal, and finally output signal D. O It can be arranged as shown in equation (3) below.

[0076]

[0077] Referring to equation (3), the final output signal D O By adjusting the gain α in the digital domain D The second output signal D2, which corresponds to the first gain α in the analog domain, is added to the first residual applied for accuracy.

[0078] Ideally, in the second-stage converter 300, when the first residual E in equation (3) Q1 coefficient When convergence to 0, only the second residual EQ2 is retained.

[0079] Therefore, considering high-speed environments, the overall performance of the analog-to-digital conversion device 1 can be determined at least in part based on identifying an appropriate gain α, applying gain α in the first transmission circuit 200, and transmitting gain α within a given sampling period.

[0080] If the gain α is the same as the gain α in the first transmission circuit 200 DSM The second output signal D2(α) applied in the second-stage converter 300 D =α=α DSM Then, the applied first residual αE can be generated to offset it. Q1 The second output signal D2.

[0081] In this case, the final output signal D O It can be arranged as shown in equation (4) below.

[0082]

[0083] Referring to equation (4), if the transfer function H(S) has an infinite value, then in the final output signal D O The third quantization error E is almost non-existent. Q2 However, the gain α is reflected in the first residual E. Q1 Above, and in the final output signal D O The middle can be set according to (1-α)E Q1 The first residual E appears Q1 However, if the same gain α is applied to the second output signal D2, the gain α will be different. DSM (α=α DSM If the transfer function H(S) has an infinite value, then the final output signal D can also be obtained from the condition that the transfer function H(S) has an infinite value. O Remove the first residual E Q1 .

[0084] The second transmission circuit 400 may have a gain α DSM And according to gain α DSM The analog output signal (h) of the second-stage converter 300 is amplified and output to the second computing unit 310 (i), as shown in equation (5).

[0085] i = α DSM Equation (5)

[0086] The second calculation unit 310 is based on the first residual E of the current cycle. Q1The first residual E from the previous cycle Q1 The output signals (i) of the second amplification unit 360 are added together and output to the loop filter circuit 320 (e), as in equation (6).

[0087] e = αE Q1 +i Equation (6)

[0088] Since the second-stage converter 300 has a second transmission circuit 400 in the feedback path corresponding to the first transmission circuit 200, the performance limiting factors caused by the first transmission circuit 200 can be removed or mitigated. More specifically, when rearranged again, the second output signal D2 is represented as in equation (7).

[0089]

[0090] Referring to equation (7), when the gain α DSM Same as gain α (α = α) DSM And when H(s) is ideally infinite, the first residual E Q1 Second residual E Q2 The coefficients converge to 0. That is, if the first gain at the output of the first stage is equal to the second gain at the feedback path of the second stage, then the analog-to-digital converter 1 can have a higher output digital signal resolution for the input analog signal.

[0091] Figure 5A and Figure 5B Examples of transmission circuits that can be used to implement a first transmission circuit 200 and a second transmission circuit 400 according to some example embodiments are shown.

[0092] Reference Figure 5A According to some example embodiments, the first transmission circuit 200 and the second transmission circuit 400 may be NMOS source follower circuits. The NMOS source follower circuits 200 and 400 may include an input transistor M1 and a current source transistor M2 connected in series between a power supply terminal VDD and a ground power supply terminal GND. An input signal IN may be applied to the gate of transistor M1, and a predetermined bias voltage V corresponding to the current source may be applied. b The signal can be applied to the gate of transistor M2. The output of NMOS source follower circuits 200 and 400 can be the output voltage OUT located between the power supply terminal VDD and the ground power supply terminal GND at the point or node where one end of transistor M1 connects to one end of transistor M2. When the input signal IN is applied to the gate of transistor M2 according to the characteristics of the source follower, the signal is output to the source, and the input voltage IN and the output voltage OUT of the NMOS source follower become almost the same. That is, the gain can ideally be 1 (-) or almost 1 in practical implementation.

[0093] Reference Figure 5B According to some example embodiments, the first transmission circuit 200 and the second transmission circuit 400 can be PMOS source follower circuits. PMOS source follower circuits 200 and 400 may include a current source transistor M1 and an input transistor M2 connected in series between a power supply terminal VDD and a ground power supply terminal GND. That is, the transistors may be connected in the reverse order compared to an NMOS source follower. If a bias voltage is applied to the gate of the current source transistor M1 and an input signal IN is applied to the input transistor M2, the PMOS source follower circuits 200 and 400 may output an output signal OUT. (Detailed operation is described below.) Figure 5A Since the same information is available in Chinese, for the sake of brevity, repeated explanations will not be provided.

[0094] Figure 6A and Figure 6B Examples of transmission circuits that can be used to implement a first transmission circuit 200 and a second transmission circuit 400 according to some example embodiments are shown.

[0095] According to some example embodiments, the first transmission circuit 200 and the second transmission circuit 400 may be preamplifiers.

[0096] Reference Figure 6A A dynamic preamplifier can be used as some example embodiments of a preamplifier. In the illustrated dynamic preamplifier, transistors M3 and M1 are connected in series between the power supply terminal VDD and node N1. Transistors M4 and M2 are also connected in series between the power supply terminal VDD and node M1, so the series connection of M3 / M1 is parallel to the series connection of M4 / M2. Transistor M6 can be connected between node N1 (i.e., one end of transistor M1 and one end of transistor M2) and the ground power supply terminal GND.

[0097] The clock signal CLK is applied to the gates of transistors M3, M4, and M6, and the input signals INP and INN of transmission circuits 200 and 400 can be applied to the gates of transistors M1 and M2. The output signals OUTN and OUTP of transmission circuits 200 and 400 can be output through the output node bn between one end of transistor M3 and the other end of transistor M1, and the output node bp between one end of transistor M4 and the other end of transistor M2.

[0098] The dynamic preamplifier sends the input signals INP and INN to the output signals OUTN and OUTP, while transistors M3, M4, and M6 are turned on according to the clock signal. Since transistor M6 of the dynamic preamplifier is turned on according to the clock signal CLK, current flows through the dynamic preamplifier only during amplification (i.e., only when the clock signal is high), and the dynamic preamplifier operates dynamically. That is, the input signals INP and INN can be buffered according to the settings of transistors M1 through M4 and M6, and the amplification gain can be predetermined to obtain the output signals OUTN and OUTP.

[0099] Reference Figure 6B A static preamplifier can be used as some example embodiments of a preamplifier. In the static preamplifier shown, transistors M3 and M1 are connected in series between the power supply terminal VDD and node N1. Transistors M4 and M2 are also connected in series between the power supply terminal VDD and node N1, so the series connection of M3 / M1 and the series connection of M4 / M2 are in parallel. Transistor M6 can be connected between node N1 (i.e., one end of transistor M1 and one end of transistor M2) and the ground power supply terminal GND.

[0100] Output nodes bn and bp are connected to the gates of transistors M3 and M4, and are subjected to a constant voltage V. BP The input signals INP and INN of transmission circuits 200 and 400 can be applied to the gates of transistors M1 and M2. The output signals OUTN and OUTP of transmission circuits 200 and 400 can be output through the output node bn between one end of transistor M3 and the other end of transistor M1, and the output node bp between one end of transistor M4 and the other end of transistor M2. Since a constant bias voltage other than the clock signal is applied to the gate of transistor M6, a constant current always flows through the static preamplifier. That is, with the static preamplifier always on, the input signals INP and INN can be buffered according to the settings of transistors M1 through M4 and M6, and the gain can be predetermined to obtain the output signals OUTN and OUTP.

[0101] Figure 7 This is a block diagram illustrating an analog-to-digital conversion device according to some example embodiments.

[0102] Reference Figure 7 According to some example embodiments, the analog-to-digital conversion device 1' may include a first-stage converter 100, a first transmission circuit 200, a plurality of second-stage converters 300, and a reconfiguration logic circuit 500.

[0103] The first-stage converter 100 can process the input analog signal V. INPerform a first analog-to-digital conversion to output a first output signal D1 and a first residual E. Q1 .

[0104] The first transmission circuit 200 can amplify the signal by a first gain α and output the first residual E. Q1 In some example embodiments, the first gain α may have a value of 1, and in some example embodiments, the first gain α may have a value less than or greater than 1. The output of the first transmission circuit 200 may be an amplified first residual αE. Q1 .

[0105] In a plurality of second-stage converters 300, each of the second-stage converters 301_1 to 301_N can be connected in parallel between the output terminal of the first transmission circuit 200 and the input terminal of the reassembly logic circuit 500. Each of the second-stage converters 301_1 to 301_N can sequentially receive the amplified first residual αE from the first transmission circuit 200 at different timings. Q1 It can also perform a second analog-to-digital conversion. That is, it can receive the amplified first residual αE in a time-interleaved manner. Q1 Although not shown, the first switch SW1 may be further included between the first transmission circuit 200 and the corresponding second-stage converters 301_1 to 301_N to receive input in a time-interleaved manner, such as... Figure 1 As shown, and can be determined according to the enable signal T residue The first residual αE of the receiver amplification Q1 .

[0106] Since each second-stage converter 301 operates in a closed loop and can operate at a lower speed than the first-stage converter 100, multiple second-stage converters 301_1 to 301_N can be connected and operated in a time-interleaved manner according to the desired speed and resolution characteristics of the analog-to-digital conversion device 1'.

[0107] The first residual αE of the receiver amplification in each of the second-stage converters 301_1 to 301_N is... Q1 The input can perform a second analog-to-digital conversion to output a second output signal D2, as shown in the reference. Figure 2 and Figure 4 And its detailed description.

[0108] According to some example embodiments, each of the second-stage converters 301_1 to 301_N may include a second transmission circuit 400, which may differ from the referenced one. Figure 1The following are example embodiments discussed. Each second transmission circuit 400 can amplify the second output signal D2 by a second gain. According to some embodiments, the second gain can be the same value as the first gain α. According to some embodiments, the second transmission circuit 400 can be a replica of the first transmission circuit 200. The input and output terminals of the second transmission circuit 400 can be connected to different nodes of the second-stage converter 300, respectively. The second output signal D2 can be input to the second-stage converter 300 as a feedback signal amplified by the second gain.

[0109] According to some example embodiments, the first-stage converter 100 can be an open-loop converter, and the second-stage converter 300 can be a closed-loop converter.

[0110] Figure 8 This is a timing diagram illustrating an analog-to-digital conversion method according to some example embodiments. An analog-to-digital conversion device in which four second-stage converters 300 are connected in parallel to a first-stage converter 100 will be described as an example, but this disclosure is not limited thereto.

[0111] Reference Figure 8 When the sampled signal is applied to the analog-to-digital converter (T) sample , ①), the first-stage converter 100 in the first stage period (T SAR During the first analog-to-digital conversion, the process continues until the next sampled signal (T) is received. s According to the first-level sub-operation loop (T) SAR.conv , ) Perform the first analog-to-digital conversion until the enable signal T is received. residue The enable signal T is applied to the first switch. residue It is a signal applied after the first-level operation is completed and before the second-level operation begins, and it is a signal used to notify the second-level converter that the operation has started.

[0112] When the first-stage converter performs the first analog-to-digital conversion (ADC) S0, an enable signal is applied to a first switch CH0 connected to any one of the plurality of second-stage converters, which is either not performing a second ADC operation when the enable signal is applied to the first switch, or has just completed a second ADC operation. The amplified first residual from the first-stage converter is sent to the second-stage converter T connected to the first switch CH0. DSM.CH0 And the second-stage converter begins performing the second analog-to-digital conversion. At this time, in the second-stage converter T of CH0... DSM.CH0 During operation, an inverting enable signal can be applied to the second switch, and the input signal for the second analog-to-digital converter continues to be supplied to it. That is, the inverting enable signal is related to the enable signal T. residue The opposite signal, and can be obtained from t4 (t4 is the time T of t3). residue(the time CH0 is disabled) until T reappears residue It remains on when CH0 is active.

[0113] The second-level sub-loop (T) can be repeated. DSM.conv , Simultaneously, a second analog-to-digital conversion is performed until the first residual, amplified during the second-stage period (t4 to t19 in the example shown), becomes the preset resolution (i.e., from the (KM)th bit to the least significant bit (LSB)).

[0114] If the first-stage converter performs the first analog-to-digital conversion (ADC) of S1, an enable signal is applied to a first switch CH1 connected to any of the remaining second-stage converters, which either was not performing a second ADC operation when the enable signal was applied to the first switch, or had just completed a second ADC operation. The amplified first residual from the first-stage converter is sent to the second-stage converter T connected to the first switch CH1. DSM.CH1 The second-stage converter then begins performing the second analog-to-digital conversion.

[0115] Similarly, the second-stage converter T is connected to each of the first switches CH2 and CH3. DSM.CH2 T DSM.CH3 The second analog-to-digital conversion is also started according to the enable signal to be applied to the first switch.

[0116] At this time, the enable signal applied to the first switch can be a second-stage converter T configured to connect to each of the first switches CH0 to CH3. DSM.CH0 To T DSM.CH3 The timing is interleaved, so the control signals for the second analog-to-digital conversion start at different times.

[0117] Figure 9 This is a block diagram illustrating an analog-to-digital conversion device according to some example embodiments.

[0118] Reference Figure 9 According to some embodiments, the analog-to-digital conversion device 1" may include a plurality of first-stage converters 101-1 to 101-M, a single first transmission circuit 200, at least one second-stage converter 300, and reconfiguration logic circuitry. Figure 9 (Not shown in the image).

[0119] Each of the first-stage converters 101-1 to 101-M can process the input analog signal V IN Perform a first analog-to-digital conversion to output a first output signal D1, and output the corresponding first residual E. QM For example, the first stage converter 101-1 in the first stage converter can output the first residual E. Q1The second first-stage converter 101-2 in the first-stage converter can output the first residual E. Q2 Furthermore, the Mth first-stage converter 101-M in the first-stage converter can output the first residual E. QM Multiple first-stage converters 100 can be connected in series to increase resolution, while also operating faster as open-loop converters.

[0120] The first transmission circuit 200 can amplify the signal by a first gain α and output the first residual E. QM In some example embodiments, the first gain α may have a value of 1; in other example embodiments, the first gain α may have a value greater than or less than 1. Only one first transmission circuit 200 may be connected to the last stage of a plurality of first-stage converters 101-1 to 101-M connected in series, because the first transmission circuit 200 may increase the operating efficiency of the second-stage converter 300.

[0121] It can be connected to at least one second-stage converter 300.

[0122] According to some example embodiments, when multiple second-stage converters 300 are as referred to Figure 7 and Figure 8 In the example embodiments described, when connected in the same manner, each of the second-stage converters 301_1 to 301_N can be connected in parallel between the output terminal of the first transmission circuit 200 and the input terminal of the reconfiguration logic circuit. Each of the second-stage converters 301_1 to 301_N can sequentially receive the amplified first residual αE from the first transmission circuit 200 at different timings. QM And perform a second analog-to-digital conversion. That is, the amplified first residual αE can be received in a time-interleaved manner. QM Although not shown, according to some example embodiments, a switch or transistor may further be included between the first transmission circuit 200 and the corresponding second-stage converters 301_1 to 301_N to receive input in a time-interleaved manner, and may receive an amplified first residual αE according to an enable signal. QM .

[0123] The first residual αE of the receiver amplification in each of the second-stage converters 301_1 to 301_N is... QM The input is processed and a second analog-to-digital conversion is performed to output a second output signal D2, as shown in the reference. Figure 2 and Figure 4 And its detailed description. According to some example embodiments, each of the second-stage converters 301_1 to 301_N may include a second transmission circuit 400, and therefore may differ from the referenced one. Figure 1 The example implementation described.

[0124] According to some example embodiments, the first-stage converter 100 can be an open-loop converter, and the second-stage converter 300 can be a closed-loop converter.

[0125] Figure 10 This is a diagram illustrating a wireless communication device 1000 employing an analog-to-digital conversion device according to some example embodiments. For example, the analog-to-digital conversion device could be... Figure 1 Analog-to-digital converter 1. Figure 7 Analog-to-digital converter 1' or Figure 9 Analog-to-digital converter 1".

[0126] Reference Figure 10 The wireless communication device 1000 may include an antenna 10, a low-noise amplifier 20, a mixer 30, a low-pass filter 40, an analog-to-digital converter 60, and a digital signal processor (DSP) 50.

[0127] The low-noise amplifier (LNA) 20 amplifies the RF signal received through the antenna 10. The mixer 30 down-converts the amplified RF signal to baseband based on the sampled frequency signal fs. The low-pass filter 40 performs low-pass filtering on the down-converted signal.

[0128] Analog-to-digital converter 60 receives a low-pass filtered input analog signal and converts it into an output digital signal. Analog-to-digital converter 60 can be... Figure 1 The analog-to-digital converter 1 shown Figure 7 Analog-to-digital converter 1' or Figure 9 The analog-to-digital converter 1”. According to some embodiments, the input analog signal may be a signal with a frequency of 500 MHz or higher. According to some example embodiments, the output digital signal may have a resolution of 10 bits or higher.

[0129] The digital signal processor 50 can process and output digital signals for use in other applications.

[0130] Figure 11 An example eNB according to some embodiments is shown.

[0131] The eNB 2000 provides wireless broadband access to the network to multiple User Equipments (UEs) within its coverage area via a base station. UEs may include mobile devices such as small businesses, enterprises, WiFi hotspots, residences, mobile phones, wireless laptops, and wireless PDAs.

[0132] Base stations may provide wireless access according to one or more wireless communication protocols, such as 5G 3GPP NR (New Radio Interface / Access), LTE (Long Term Evolution), LTE-A (LTE-Advanced), High-Speed ​​Packet Access (HSPA), Wi-Fi 802.11a / b / g / n / ac, etc. For convenience, the terms "eNodeB" and "eNB" are used in this disclosure to refer to network infrastructure components that provide wireless access to remote terminals.

[0133] like Figure 11 As shown, the eNB 2000 includes several antennas 2205a to 2205n, several RF transceivers 2210a to 2210n, transmit (TX) processing circuitry 2215, and receive (RX) processing circuitry 2220. The number of antennas and RF transceivers can be large. The eNB 2000 also includes a controller / processor 2225, a memory 2230, and a backhaul or network interface 2235.

[0134] RF transceivers 2210a to 2210n receive incoming RF signals from antennas 2205a to 2205n, such as signals transmitted by electronic devices on a network (not shown) or user equipment (UE) (not shown). RF transceivers 2210a to 2210n down-convert the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are sent to RX processing circuitry 2220, which generates a baseband signal processed by filtering, decoding, and / or digitizing the baseband or IF signals. RX processing circuitry 2220 sends the processed baseband signal to controller / processor 2225 for further processing. RF transceivers 2210a to 2210n may include any analog-to-digital conversion device disclosed herein, including those based on… Figures 1 to 10 Those shown and described herein are examples of embodiments for converting analog signals to digital signals and / or converting digital signals to analog signals.

[0135] TX processing circuit 2215 receives analog or digital data (e.g., voice data, web data, email, or interactive video game data) from controller / processor 2225. TX processing circuit 215 decodes, multiplexes, and / or digitizes the outgoing baseband data to generate processed baseband or IF signals. RF transceivers 2210a to 2210n receive the outgoing processed baseband or IF signals from TX processing circuit 2215 and up-convert the baseband or IF signals into RF signals transmitted via antennas 2205a to 2205n.

[0136] The controller / processor 2225 may include one or more processors or other processing devices that control the overall operation of the eNB 2000. For example, the controller / processor 2225 may control the reception of forward channel signals and the transmission of reverse channel signals via RF transceivers 2210a to 2210n, RX processing circuitry 2220, and TX processing circuitry 2215, according to known principles. The controller / processor 2225 may also support additional functions, such as more advanced wireless communication functions. For example, the controller / processor 2225 may provide beamforming or directional routing operations (including applying different weights) to effectively redirect signals emanating from multiple antennas 2205a to 2205n in a desired direction. Various other functions may be supported at the eNB 2000 via the controller / processor 2225.

[0137] The controller / processor 2225 can also execute programs and other processes residing in the memory 2230, such as an operating system (OS). The controller / processor 2225 can move data into and out of the memory 2230 as needed by the running processes.

[0138] The controller / processor 2225 is also connected to the backhaul or network interface 2235. The backhaul or network interface 2235 allows the eNB2000 to connect via a backhaul link or network (…). Figure 11 (Not shown) Interface 2235 can communicate with other devices or systems. Interface 2235 can support communication via any suitable wired or wireless connection. For example, when the eNB 2000 is implemented as part of a cellular communication system (e.g., supporting 5G, LTE, or LTE-A), interface 2235 can allow the eNB 2000 to communicate with another eNB via a wired or wireless backhaul connection. When the eNB 2000 is implemented as an access point, interface 2235 can allow the eNB 2000 to communicate with a large-scale network via a wired or wireless local area network or a wired or wireless connection (e.g., the Internet). Interface 2235 includes any suitable architecture supporting communication via wired or wireless connections, such as Ethernet or RF transceivers.

[0139] The memory 2230 is coupled to the controller / processor 2225. A portion of the memory 2230 may include RAM, and another portion of the memory 2230 may include flash memory or another ROM.

[0140] Figure 12 This is a block diagram of an electronic device in a network environment 3000 according to some embodiments.

[0141] Reference Figure 12In network environment 3000, electronic device 3101 can communicate with electronic device 3102 via a first network 3198 (e.g., a short-range wireless communication network), or with electronic device 3104 or server 3108 via a second network 3199 (e.g., a long-range wireless communication network). According to some example embodiments, electronic device 3101 can communicate with electronic device 3104 via server 3108. According to some example embodiments, electronic device 3101 may include a processor 3120, a memory 3130, an input device 3150, a sound output device 3155, a display device 3160, an audio module 3170, a sensor module 3176, an interface 3177, a connection terminal 3178, a tactile module 3179, a camera module 3180, a power management module 3188, a battery 3189, a communication module 3190, a subscriber identification module 3196, and / or an antenna module 3197. In some example embodiments, at least one component (e.g., display device 3160 or camera module 3180) may be omitted from electronic device 3101, or one or more other components may be added. In some example embodiments, some components may be implemented as a single integrated circuit or component. For example, sensor module 3176 (e.g., fingerprint sensor, iris sensor, or illuminance sensor) may be implemented while being at least partially integrated with display device 3160 (e.g., display). For example, sensor module 3176 may be embedded in display device 3160.

[0142] For example, processor 3120 may execute software (e.g., program 3140) to control at least one other component (e.g., hardware or software component) of electronic device 3101 connected to processor 3120, and may perform various data processing and calculations. According to some example embodiments, as at least part of data processing or calculation, processor 3120 may load commands or data received from other components (e.g., sensor module 3176 or communication module 3190) into volatile component memory 3132, process the commands or data stored in volatile component memory 3132, and store the resulting data in non-volatile memory 3134. According to some example embodiments, processor 3120 may include a main processor 3121 (e.g., central processing unit or application processor) and a coprocessor 3123 (e.g., graphics processing unit, image signal processor, sensor hub processor, or communication processor) that may operate independently of and / or together with the main processor 3121. Alternatively or additionally, the coprocessor 3123 may be configured to use lower power consumption than the main processor 3121 and / or be dedicated to specified functions. The coprocessor 3123 may be implemented separately from the main processor 3121 or as part of the main processor 3121.

[0143] For example, the coprocessor 3123 may replace the main processor 3121 when the main processor 3121 is inactive (e.g., in a sleep state), or, together with the main processor 3121, control at least some functions or states related to at least one of the constituent elements of the electronic device 3101 (e.g., display device 3160, sensor module 3176, or communication module 3190) when the main processor 3121 is active (e.g., application execution). According to some example embodiments, the coprocessor 3123 (e.g., an image signal processor or a communication processor) may be implemented as part of another functionally related constituent element (e.g., camera module 3180 or communication module 3190).

[0144] The memory 3130 may store various data used by at least one component of the electronic device 3101 (e.g., processor 3120 or sensor module 3176). For example, the data may include software (e.g., one or more programs 3140) and input or output data of commands associated therewith. The memory 3130 may include volatile memory 3132 or non-volatile memory 3134.

[0145] One or more programs 3140 may be stored as software in memory 3130 and may include, for example, an operating system 3142, middleware 3144, or application program 3146.

[0146] Input device 3150 can receive commands or data from a source outside electronic device 3101 (e.g., a user) to be used by at least one component of electronic device 3101 (e.g., processor 3120). For example, input device 3150 may include a microphone, mouse, or keyboard.

[0147] The sound output device 3155 can output sound signals to the outside of the electronic device 3101. For example, the sound output device 3155 may include a speaker or a receiver. The speaker can be used for general purposes (e.g., multimedia playback or recording playback), and the receiver can be used to receive incoming calls. According to some example embodiments, the receiver may be implemented separately from the speaker or as part of the speaker.

[0148] Display device 3160 can visually provide information to a destination (e.g., a user) outside of electronic device 3101. For example, display device 3160 may include a display, a holographic device, and / or a projector, and may include control circuitry for controlling display device 3160. According to some example embodiments, display device 3160 may include touch circuitry configured to detect touch or sensor circuitry (e.g., a pressure sensor) configured to measure the intensity of the force generated by touch.

[0149] The audio module 3170 can convert sound into electrical signals and / or convert electrical signals into sound. According to an embodiment, the audio module 3170 can acquire sound through the input device 3150, or output sound through the sound output device 3155 or through an external electronic device (e.g., electronic device 3102) (e.g., a speaker or headphones) directly or wirelessly connected to the electronic device 3101.

[0150] Sensor module 3176 detects the operating state (e.g., power or temperature) or external environmental state (e.g., user state) of electronic device 3101, and can generate electrical signals or data values ​​corresponding to the detected state. According to some example embodiments, sensor module 3176 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an accelerometer, a grip force sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0151] Interface 3177 may support one or more specified protocols that can be used for direct or wireless connection of electronic device 3101 to external electronic device (e.g., electronic device 3102). According to embodiments, interface 3177 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface.

[0152] Connection terminal 3178 may include a connector for physical connection of electronic device 3101 to an external electronic device (e.g., electronic device 3102). According to some example embodiments, connection terminal 3178 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0153] The haptic module 3179 can convert electrical signals into mechanical stimulation (e.g., vibration or motion) or electrical stimulation that a user can perceive through touch or kinesthesia. According to some example embodiments, the haptic module 3179 may include a motor, a piezoelectric element, or an electrical stimulator.

[0154] Camera module 3180 can capture still or moving images. According to some example embodiments, camera module 3180 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0155] The power management module 3188 manages the power supplied to the electronic device 3101. According to some example embodiments, the power management module 3188 may be implemented as at least part of a power management integrated circuit (PMIC).

[0156] Battery 3189 may supply power to at least one component of electronic device 3101. According to some example embodiments, battery 3189 may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0157] Communication module 3190 can support the establishment of a direct (e.g., wired) or wireless communication channel between electronic device 3101 and external electronic devices (e.g., electronic device 3102, electronic device 3104, or server 3108), and can control the performance of communication through the established communication channel. Communication module 3190 can operate independently of processor 3120 (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) or wireless communication. According to some example embodiments, communication module 3190 may include wireless communication module 3192 (e.g., cellular communication module, short-range wireless communication module, or Global Navigation Satellite System (GNSS) communication module) or wired communication module 3194 (e.g., local area network (LAN) communication module or power line communication module). Each of these communication modules 3192 and 3194 can communicate with external electronic devices via a first network 3198 (e.g., a short-range wired and / or wireless communication network such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA)) or a second network 3199 (e.g., a long-range wired and / or wireless communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN)). Several types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module 3192 can use subscriber information (e.g., the International Mobile Subscriber Identifier (IMSI) stored in the subscriber identification module 3196) to identify and authenticate electronic devices 3101 in communication networks such as the first network 3198 or the second network 3199.

[0158] Antenna module 3197 can transmit or receive signals or power to or from an external device (e.g., an external electronic device). According to some example embodiments, antenna module 3197 may include one or more antennas (not shown), thus at least one antenna suitable for a communication scheme used in a communication network such as a first network 3198 or a second network 3199 can be selected, for example, by communication module 3190. Signals or power can be transmitted or received between communication module 3190 and the external electronic device via at least one selected antenna. Antenna module 3197 may include one or more analog-to-digital conversion devices, including one or more analog-to-digital conversion devices according to the inventive concept disclosed herein, some example embodiments of which are referred to herein. Figures 1 to 10 It has been described.

[0159] At least some of the constituent components are connected to each other through communication schemes between peripheral devices (e.g., buses, general purpose input and output (GPIO), serial peripheral interfaces (SPI), or mobile industrial processor interfaces (MIPI)) and can exchange signals (e.g., commands or data) with each other.

[0160] The electronic device according to the various example embodiments disclosed herein can be any of a variety of forms of device. For example, the electronic device according to this disclosure can be or may include a mobile communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. This document is not limited to the electronic devices described above.

[0161] As used herein, the term "module" can include units implemented as hardware, software, and / or firmware, and is used interchangeably with terms such as logic, logic block, component, or circuit. A module can be a monolithically configured component or the smallest unit or part of a component that performs one or more of its functions. For example, according to some example embodiments, a module may be implemented as an application-specific integrated circuit (ASIC).

[0162] The various example embodiments described herein can be implemented as software (e.g., program 3140) including one or more commands stored in a storage medium (e.g., internal memory 3136 or external memory 3138), which can be read by a machine (e.g., electronic device 3101). For example, a processor (e.g., processor 3120) of the machine (e.g., electronic device 3101) can invoke and execute at least one of the one or more stored commands from the storage medium.

[0163] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the exemplary embodiments of the inventive concept disclosed herein are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. An analog-to-digital converter, comprising: A first-stage converter is configured to perform a first analog-to-digital conversion on an input analog signal during a first-stage cycle and is configured to output a first output signal and a first residual. A first transmission circuit is configured to amplify the first residual by a first gain; Multiple second-stage converters, each configured to receive a first residual amplified by a first gain, configured to perform a second analog-to-digital conversion during a second-stage period, and configured to output a second output signal; A plurality of first switches, each first switch being connected between the first transmission circuit and a corresponding second-stage converter among the plurality of second-stage converters, each first switch being configured to be controlled by an enable signal that enables each of the plurality of second-stage converters in a time-interleaved manner; as well as A reconfigurable logic circuit is configured to combine the first output signal and the second output signal, and is configured to output a digital signal corresponding to the input analog signal. The second-stage converter is configured to generate a second-stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second-stage cycle, and is configured to generate a second output signal of a second sub-cycle following the first sub-cycle based on the second-stage feedback signal.

2. The analog-to-digital converter according to claim 1, further comprising: A second transmission circuit is connected between the input terminal and the output terminal of the second-stage converter and is configured to output the second-stage feedback signal obtained by amplifying the second output signal according to the first gain to the input terminal of the second-stage converter. as well as The second switch is turned on according to an inverted enable signal that is opposite to the enable signal.

3. The analog-to-digital converter according to claim 2, wherein, The first transmission circuit and the second transmission circuit each include a source follower circuit.

4. The analog-to-digital converter according to claim 1, wherein, The enable signal is off during the first cycle and on when the second cycle begins.

5. The analog-to-digital converter according to claim 1, wherein, The first-stage converter is a successive approximation register analog-to-digital converter, and wherein the first-stage converter includes: A sample-and-hold circuit is configured to sample the input analog signal based on a sampled signal; A comparator configured to compare a sampled input analog signal based on a first-stage feedback signal to output the first residual and a pre-output signal; A successive approximation register logic circuit is configured to count the pre-output signal to generate the first output signal; and A successive approximation register digital-to-analog converter is configured to convert the first output signal within the first stage cycle to generate the first stage feedback signal.

6. The analog-to-digital converter according to claim 1, wherein, The second-stage converter is a ΔΣ converter, and wherein the second-stage converter includes: A loop filter circuit is configured to filter a signal obtained by combining an amplified first residual and an amplified second-stage feedback signal. A quantization circuit is configured to digitally convert the output signal of the loop filter circuit. A ΔΣ logic circuit, configured to count the output of the quantization circuit to generate the second output signal; and A ΔΣ digital-to-analog converter is configured to convert the output of the quantization circuit to output the second-stage feedback signal.

7. The analog-to-digital converter according to claim 2, wherein, Each of the plurality of first switches is connected to at least two of the plurality of second-level converters.

8. A wireless communication device, comprising the analog-to-digital converter according to claim 1, wherein the wireless communication device further comprises: A low-noise amplifier configured to amplify radio frequency signals received via an antenna; A mixer configured to downconvert an amplified radio frequency signal to the baseband frequency range; A low-pass filter is configured to filter the signal down-converted by the mixer; as well as A digital signal processor, configured to process the output digital signal, The analog-to-digital converter is configured to receive the input analog signal from the low-pass filter and to convert the input analog signal into the output digital signal.

9. An analog-to-digital converter, comprising: A successive approximation register converter is configured to perform a first analog-to-digital conversion on an input analog signal during a first time period and is configured to output a first output signal and a first residual. A first transmission circuit is configured to amplify the first residual by a first gain; A plurality of Δ-Σ converters, each Δ-Σ converter being configured to perform a second analog-to-digital conversion based on an amplified first residual based on a Δ-Σ feedback signal during a second time period, and each Δ-Σ converter being configured to generate a corresponding second output signal, wherein each of the plurality of Δ-Σ converters includes a second transmission circuit configured to amplify the second output signal by a first gain to generate the Δ-Σ feedback signal; A plurality of first switches are connected between the first transmission circuit and a corresponding Δ-Σ converter among the plurality of Δ-Σ converters. Each first switch is configured to be controlled by an enable signal and each first switch is configured to send an amplified first residual to the corresponding Δ-Σ converter in a time-interleaved manner; and The recombining logic circuit is configured to combine a first output signal and a second output signal generated by the plurality of Δ-Σ converters to output a digital signal.

10. The analog-to-digital converter according to claim 9, wherein, Each of the plurality of Δ-Σ converters further includes: a second switch connected between the second transmission circuit of the Δ-Σ converter and the input terminal of the Δ-Σ converter, and enabled according to an inverting enable signal.

11. The analog-to-digital converter according to claim 10, wherein, Each of the plurality of Δ-∑ converters includes: A loop filter circuit is configured to filter a signal obtained by combining the first residual and the Δ-∑ feedback signal; A quantization circuit is configured to perform digital conversion on the output signal of the loop filter circuit; A Δ-∑ logic circuit, configured to count the output of the quantization circuit to generate the second output signal; and A Δ-∑ digital-to-analog converter is configured to perform an analog conversion on the output of the quantization circuit to output the Δ-∑ feedback signal.

12. The analog-to-digital converter according to claim 9, wherein, The enable signal is a signal set to an on value after the first time period and before the second time period.

13. The analog-to-digital converter according to claim 9, wherein, The first transmission circuit and the second transmission circuit are identical.

14. The analog-to-digital converter according to claim 9, wherein, The successive approximation register converter includes: A sample-and-hold circuit is configured to receive and sample the input analog signal; A comparator is configured to compare the sampled input analog signal based on the successive approximation register feedback signal to output the first residual and the pre-output signal; A successive approximation register logic circuit is configured to count the pre-output signal to generate the first output signal; and A successive approximation register digital-to-analog converter is configured to convert the first output signal within the first time period to generate the successive approximation register feedback signal.

15. An analog-to-digital converter, comprising: Multiple open-loop converters, each open-loop converter being configured to convert an input analog signal and being configured to output a first output signal and a first residual from a first output terminal; A first buffer is connected to the first output terminal and is configured to buffer the first residual; At least one Δ∑ converter is configured to perform a Δ∑ conversion on a first residual of a buffer and is configured to output a second output signal and a Δ∑ feedback signal; as well as A recombining logic circuit is configured to combine the first output signal and the second output signal into an output digital signal. Each of the at least one Δ∑ converter includes a second buffer configured to send the second output signal as a Δ∑ feedback signal. The analog-to-digital conversion device further includes: A first switch, connected between the first buffer and each of the at least one Δ∑ converter, wherein the first switch is controlled according to an enable signal, and wherein the first switch is configured to send a first residual of the buffer to the at least one Δ∑ converter in a time-interleaved manner; and A second switch is connected between the second buffer and the input terminal of the at least one Δ∑ converter and is controlled according to an inverting enable signal.

16. The analog-to-digital converter according to claim 15, wherein, The multiple open-loop converters are connected in series. Specifically, a first open-loop converter among the plurality of open-loop converters is configured to determine at least two or more bits and a previous residual starting from the high-order bit, and a second open-loop converter connected to the output of the first open-loop converter is configured to determine at least two or more bits and a subsequent residual starting from the bits determined by the first open-loop converter, based on the previous residual. The first output signal and the first residual are output from the last open-loop converter among the plurality of open-loop converters.

17. The analog-to-digital converter according to claim 15, wherein, The first buffer and each of the second buffers are source follower circuits.

18. The analog-to-digital converter according to claim 15, wherein, The at least one Δ∑ converter includes a plurality of Δ∑ converters connected in parallel, and Each Δ∑ converter is configured to output a second output signal generated by performing a Δ-∑ conversion based on a first residual of the buffer and the Δ∑ feedback signal.

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