Semiconductor devices and methods including body contact dopant diffusion barrier superlattices with reduced contact resistance and related methods

Abstract

A semiconductor device can include a semiconductor layer (401), spaced apart source and drain regions (402, 403) in the semiconductor layer and a channel region (430) extending therebetween, and a gate (408) on the channel region. The semiconductor device can also include a body contact in the semiconductor layer, and the body contact includes a body contact dopant diffusion barrier superlattice (425) extending through the body contact to divide the body contact into a first body contact region (421) and a second body contact region (422), wherein the second body contact region has the same conductivity as the first body contact region and a higher dopant concentration than the first body contact region. The body contact dopant diffusion barrier superlattice can include a plurality of stacked groups of layers each, wherein each group of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of the adjacent base semiconductor portions.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices having enhanced contact structures and related methods.

[0002] background

[0003] Structures and techniques have been proposed to enhance the performance of semiconductor devices, for example, by increasing carrier mobility. For instance, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxable silicon, with the strained material layers also including impurity-free regions (which would otherwise cause performance degradation). The biaxial strain generated in the upper silicon layer alters carrier mobility, enabling higher speed and / or lower power devices. U.S. Patent Application No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter also based on similar strained silicon technology.

[0004] Takagi's U.S. Patent No. 6,472,685B2 discloses a semiconductor device comprising silicon and carbon layers sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer receive tensile strain. Electrons with smaller effective mass and confined within the second silicon layer by the electric field applied to the gate are thus claimed to have higher mobility in an n-channel MOSFET.

[0005] U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which multiple layers (less than eight monolayers) are alternately and epitaxially grown, and which contain fractional or binary or binary compound semiconductor layers. The direction of the main current is perpendicular to the layers of the superlattice.

[0006] US Patent No. 5,357,119 by Wang et al. discloses a Si-Ge short-period superlattice with high mobility achieved by reducing alloy scattering in a superlattice. Following these methods, US Patent No. 5,683,934 by Candelaria discloses an enhanced mobility MOSFET comprising a channel layer comprising an alloy of silicon and a second material, the second material being present in the silicon lattice at a percentage that places the channel layer under tensile stress.

[0007] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barrier regions. Each barrier region consists of alternating layers of SiO2 / Si, having a thickness typically ranging from 2 to 6 monolayers. A much thicker portion of silicon is sandwiched between the barrier regions.

[0008] Tsu's article, titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in Applied Physics and Materials Science & Processing (pp. 391-402), discloses a silicon-oxygen semiconductor-atomic superlattice (SAS). The disclosed Si / O superlattice can be used in silicon quantum and light-emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. The current in the diode structure is vertical, i.e., perpendicular to the layers of the SAS. The disclosed SAS may comprise semiconductor layers separated by adsorbed materials such as oxygen atoms and CO molecules. The growth of silicon beyond the adsorbed oxygen monolayer is described as epitaxy with a considerably low defect density. One SAS structure includes a 1.1 nm thick silicon portion (approximately eight atomic layers of silicon), and another structure has twice this silicon thickness. The article titled "Chemical Design of Direct-Gap Light-Emitting Silicon" by Luo et al., published in Physical Review Letters, Volume 89, Issue 7 (August 12, 2002), also discusses Tsu's light-emitting SAS structure.

[0009] US Patent No. 7,105,895 by Wang et al. discloses thin silicon and barrier structural units of oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby reducing the vertical DC current through the lattice by more than four orders of magnitude. The insulating / barrier layer allows for the deposition of low-defect epitaxial silicon adjacent to the insulating layer.

[0010] UK patent application 2,347,520, published by Mears et al., discloses the principles of aperiodic photonic bandgap (APBG) structures applicable to electronic bandgap engineering. Specifically, the application discloses the ability to adjust material parameters such as the band minimum location and effective mass to produce new aperiodic materials with desired bandgap characteristics. It also discloses that other parameters such as electrical conductivity, thermal conductivity, dielectric constant, or magnetic permeability can be designed into the material.

[0011] Furthermore, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices, comprising depositing a layer of silicon and at least one other element on a silicon substrate, wherein the deposited layer is substantially defect-free so that substantially defect-free epitaxial silicon can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements (preferably containing oxygen) is adsorbed onto the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier composite material.

[0012] Despite the existence of such pathways, further enhancements are expected for achieving improved performance in semiconductor devices using advanced semiconductor materials and processing techniques.

[0013] Overview

[0014] A semiconductor device may include a semiconductor layer, spaced-apart source and drain regions within the semiconductor layer, a channel region extending therebetween, and a gate on the channel region. The semiconductor device may also include a body contact in the semiconductor layer, and the body contact includes a body contact dopant diffusion barrier superlattice extending through the body contact to divide the body contact into a first body contact region and a second body contact region, wherein the second body contact region has the same conductivity as the first body contact region but a higher dopant concentration. The body contact dopant diffusion barrier superlattice may include multiple stacked layers, each layer comprising multiple stacked base semiconductor monolayers defining base semiconductor portions, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion.

[0015] In one example embodiment, the source and drain regions and the body contact may be located on the top side of the semiconductor layer. According to another example embodiment, the source and drain regions may be located on the top side of the semiconductor layer, and the body contact may be located on the back side of the semiconductor layer opposite to the top side.

[0016] In one example embodiment, the second body contact region may be flush with the second surface of the semiconductor layer. According to another example, the second body contact region may be raised above the second surface of the semiconductor layer. Furthermore, the first body contact region may contain a different material than the second body contact region. For example, the first body contact region may contain silicon, and the second body contact region may contain silicon-germanium. According to another example, the first body contact region may contain silicon-germanium, and the second body contact region may contain silicon.

[0017] Additionally, the semiconductor device may include a metal contact portion on the second body contact region. By way of example, the metal contact portion may comprise at least one of titanium, cobalt, nickel, and platinum. Also by way of example, the base semiconductor monolayer may comprise silicon, and the at least one non-semiconductor monolayer may comprise oxygen.

[0018] A method of manufacturing a semiconductor device may include forming spaced-apart source and drain regions in a semiconductor layer, having an extending channel region therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer, and the body contact including a body contact dopant diffusion barrier superlattice extending through the body contact to divide the body contact into a first body contact region and a second body contact region, wherein the second body contact region has the same conductivity as the first body contact region but a higher dopant concentration. The body contact dopant diffusion barrier superlattice may include each of a plurality of stacked layers, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining base semiconductor portions, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion.

[0019] In one example embodiment, the source and drain regions and the body contact may be located on the top side of the semiconductor layer. According to another example embodiment, the source and drain regions may be located on the top side of the semiconductor layer, and the body contact may be located on the back side of the semiconductor layer opposite to the top side.

[0020] In one example embodiment, the second body contact region may be flush with the second surface of the semiconductor layer. According to another example, the second body contact region may be raised above the second surface of the semiconductor layer. Furthermore, the first body contact region may contain a different material than the second body contact region. For example, the first body contact region may contain silicon, and the second body contact region may contain silicon-germanium. According to another example, the first body contact region may contain silicon-germanium, and the second body contact region may contain silicon.

[0021] Additionally, the semiconductor device may include a metal contact portion on the second body contact region. By way of example, the metal contact portion may comprise at least one of titanium, cobalt, nickel, and platinum. Also by way of example, the base semiconductor monolayer may comprise silicon, and the at least one non-semiconductor monolayer may comprise oxygen.

[0022] Brief description of the attached diagram

[0023] Figure 1 This is a greatly enlarged schematic cross-sectional view of a superlattice used in a semiconductor device according to an example embodiment.

[0024] Figure 2 yes Figure 1 A perspective view of a portion of the superlattice shown in the image.

[0025] Figure 3 This is a significantly enlarged schematic cross-sectional view of another embodiment of the superlattice according to the example implementation.

[0026] Figure 4A It is composed of bulk silicon in existing technologies and such Figure 1-2 The diagram shows the calculated band structure of the γ point (G) of the 4 / 1Si / O superlattice.

[0027] Figure 4B It is composed of bulk silicon in existing technologies and such Figure 1-2 The diagram shows the band structure calculated at the Z point of the 4 / 1Si / O superlattice.

[0028] Figure 4C It is composed of bulk silicon in existing technologies and such Figure 3 The diagram shows the calculated band structure of the 5 / 1 / 3 / 1Si / O superlattice at the γ and Z points.

[0029] Figure 5 This is a schematic cross-sectional view of a semiconductor device comprising a dopant diffusion barrier superlattice that separates source and drain regions to provide reduced source and drain contact resistance.

[0030] Figure 6 It is a schematic cross-sectional view of a semiconductor device including source and drain regions separated by a superlattice of their respective dopant diffusion barriers, and providing reduced source and drain contact resistance.

[0031] Figures 7A-7C These are a series of schematic cross-sectional views illustrating a method for manufacturing a semiconductor device having interim source and drain superlattice layers, thereby providing Schottky barrier height modulation by controlling the formation of interface insulators.

[0032] Figure 8-9 It is a schematic cross-sectional view of an example semiconductor device including source and drain regions separated by their respective superlattices and having different upper and lower semiconductor source / drain material and metal contact regions.

[0033] Figure 10 It is a perspective view of a FINFET that includes source and drain regions separated by their respective superlattices and provides reduced source and drain contact resistance.

[0034] Figure 11 yes Figure 10 A cross-sectional view of the FINFET obtained along line AA.

[0035] Figure 12 Is it used with Figures 7A-7C Formed by a similar method shown in the image Figure 10 Alternative implementations of the FINFET are shown in the cross-sectional view obtained along line AA.

[0036] Figure 13 and 14These include and Figure 8 and 9 The device has a similar source and drain structure. Figure 10 Alternative implementations of the FINFET are shown in the cross-sectional view obtained along line AA.

[0037] Figure 15 It is a series of schematic atomic-level diagrams illustrating the use of data from... Figure 1-4C The non-semiconductor insertion layer of the MST film shown in the figure is Figure 5-14 The implementation scheme provides a way to reduce the Schottky barrier height to the metal-semiconductor contact with the dopant in close proximity.

[0038] Figure 16 This is a schematic cross-sectional view of a semiconductor device including a body contact portion having a dopant diffusion-blocking superlattice to provide reduced contact resistance, according to an example embodiment.

[0039] Figure 17 This is a schematic cross-sectional view of a semiconductor device including a back-side body contact portion with a dopant diffusion-blocking superlattice to provide reduced contact resistance, according to an example embodiment.

[0040] Figure 18 This is a cross-sectional view of an alternative contact structure that can be used to provide reduced contact resistance according to the example implementation.

[0041] Detailed description

[0042] The exemplary embodiments will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments are shown. However, embodiments may be implemented in many different forms and should not be construed as limiting to the specific embodiments listed herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete. The same numbers always refer to the same elements, and apostrophes and multiple apostrophes are used to indicate similar elements in different embodiments.

[0043] Generally, this disclosure relates to the use of enhanced superlattice materials in the source and drain regions to reduce the Schottky barrier height and thereby reduce the source and drain contact resistance. The enhanced semiconductor superlattice is also referred to as an "MST" layer or "MST technology" in this disclosure and the accompanying drawings.

[0044] More specifically, MST technology involves advanced semiconductor materials such as superlattices 25, as further described below. The applicant theoretically states (and does not wish to be bound by it): some superlattices as described herein reduce the effective mass of charge carriers, and this thereby leads to higher carrier mobility. Various definitions from the literature are used to describe the effective mass. As a measure of effective mass improvement, the applicant uses the "conductivity reciprocal effective mass tensor" for electrons and holes respectively. and The definition is as follows:

[0045]

[0046] For electrons and:

[0047]

[0048] For holes, where f is a Fermi-Dirac distribution, E F Here, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, and the exponents i and j refer to the Cartesian coordinates x, y, and z. The integral is performed in the Brillouin zone (BZ) and summed in the energy bands where the energies are greater than and less than the Fermi energies of electrons and holes, respectively.

[0049] The applicant defines the reciprocal effective mass tensor of conductivity as follows: the larger the tensor component of the conductivity of a material, the larger the value of the corresponding component of the reciprocal effective mass tensor. Furthermore, the applicant theoretically states (without wishing to be bound by this) that the superlattice described herein establishes the value of the reciprocal effective mass tensor of conductivity, thereby enhancing the conductivity properties of the material, for example, the preferred direction commonly used for carrier transport. The reciprocal of the appropriate tensor element is called the effective mass of conductivity. In other words, to characterize the structure of semiconductor materials, the effective mass of electron / hole conductivity, as described above and calculated in the expected carrier transport direction, is used to distinguish the improved materials.

[0050] The applicant identified improved materials or structures for use in semiconductor devices. More specifically, the applicant identified materials or structures having band structures for which the effective mass of appropriate electron and / or hole conductivity is significantly less than that of silicon. In addition to the enhanced mobility properties of these structures, they can also be formed or used in such a way that they provide piezoelectric, thermoelectric, and / or ferroelectric properties, which are advantageous for use in a variety of different types of devices, as will be discussed further below.

[0051] Now for reference Figure 1 and 2 The material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 comprises multiple layers 45a-45n arranged in a stacked relationship, as detailed in the specific reference. Figure 1 A schematic cross-sectional view is probably the best way to understand it.

[0052] Each layer group 45a-45n of the superlattice 25 illustratively includes multiple stacked base semiconductor monolayers 46 (defining respective base semiconductor portions 46a-46n) and band-changing layers 50 thereon. For clarity, the band-changing layers 50 in... Figure 1 The middle part is represented by dots.

[0053] The band-changing layer 50 illustratively comprises a non-semiconductor monolayer confined within a crystal lattice of adjacent basic semiconductor portions. The phrase "confined within a crystal lattice of adjacent basic semiconductor portions" implies that at least some semiconductor atoms from the opposing basic semiconductor portions 46a-46n are chemically bonded together through the non-semiconductor monolayer 50 between them, such as... Figure 2 As shown in the diagram. Generally, this construction is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n via atomic layer deposition, such that not all (i.e., less than all or 100% coverage) of the available semiconductor bonding sites are pollulated with bonds to the non-semiconductor atoms, as will be discussed further below. Thus, as another monolayer 46 of semiconductor material is deposited on or above the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0054] In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that the reference herein to non-semiconductor or semiconductor monolayer means that the material used for the monolayer is non-semiconductor or semiconductor if formed in a bulk form. That is, a single monolayer of a material such as silicon may not necessarily exhibit the same properties as it would if formed in a bulk or relatively thick layer, as those skilled in the art will understand.

[0055] The applicant theoretically states (and does not wish to be bound by this) that the band-changing layer 50 and the adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower effective mass of conductivity suitable for charge carriers in the parallel layer direction than would exist otherwise. Alternatively, this parallel direction is orthogonal to the stacking direction. The band-changing layer 50 also causes the superlattice 25 to have a common band structure, which simultaneously advantageously acts as an insulator between vertical regions or layers above and below the superlattice.

[0056] Furthermore, this superlattice structure can advantageously serve as a barrier to dopant and / or material diffusion between the vertical layers above and below the superlattice 25. These properties thus advantageously enable the superlattice 25 to provide an interface of high-k dielectrics, which not only reduces the diffusion of high-k materials into the channel region, but also advantageously reduces unwanted scattering effects and improves device mobility, as those skilled in the art will understand.

[0057] It is also theoretically demonstrated that semiconductor devices including superlattice 25 can enjoy higher carrier mobility based on a lower conductivity effective quality than would be possible in other ways. In some embodiments, and as a result of the bandgap engineering achieved by the present invention, superlattice 25 may also have a substantially direct bandgap that can be particularly advantageous for, for example, optoelectronic devices.

[0058] The superlattice 25 also illustratively includes a capping layer 52 on the upper layer group 45n. The capping layer 52 may comprise a plurality of basic semiconductor monolayers 46. The capping layer 52 may have between 2 and 100 basic semiconductor monolayers, and more preferably between 10 and 50 monolayers.

[0059] Each basic semiconductor portion 46a-46n may contain a basic semiconductor selected from Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductor also includes Group IV-IV semiconductors, as those skilled in the art will understand. More specifically, the basic semiconductor may contain at least one of, for example, silicon and germanium.

[0060] Each bandgap layer 50 may, for example, comprise a non-semiconductor selected from oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor is also expected to be thermally stable by the deposition of the next layer to facilitate fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound, as those skilled in the art will understand, that is compatible with the given semiconductor processing. More particularly, the base semiconductor may comprise at least one of, for example, silicon and germanium.

[0061] It should be noted that the term monolayer means including both a single atomic layer and a single molecular layer. It should also be noted that the band-changing layer 50 provided by a single monolayer also means including a monolayer in which not all possible sites are occupied (i.e., there is less than 100% coverage). For example, see special reference. Figure 2 The atomic diagram illustrates a 4 / 1 repeating structure with silicon as the basic semiconductor material and oxygen as the band-changing material. In the illustrated example, only half of the possible sites are occupied for oxygen.

[0062] In other embodiments and / or using different materials, as those skilled in the art will understand, this occupancy may not be as pronounced. Indeed, it can even be seen in this schematic diagram that the individual oxygen atoms in a given monolayer are not precisely aligned along a flat plane, as those skilled in the art of atomic deposition will also understand. By way of example, the preferred occupancy range is from about one-eighth to one-half of all possible oxygen sites, but other amounts may be used in some embodiments.

[0063] Silicon and oxygen are currently widely used in conventional semiconductor processing, and therefore manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Therefore, as those skilled in the art will understand, semiconductor devices comprising superlattice 25 according to the present invention can be readily adopted and implemented.

[0064] Theoretically speaking (the applicant does not wish to be bound by this): For superlattices such as Si / O superlattices, the number of silicon monolayers should ideally be seven or less so that the superlattice's band structure remains relatively uniform or common throughout, thus achieving the desired advantages. For Si / O in... Figure 1 and 2 The 4 / 1 repeating structure shown has been modeled to indicate enhanced electron and hole mobility in the X direction. For example, the calculated effective conductivity mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4 / 1 SiO superlattice it is 0.12 in the X direction, resulting in a ratio of 0.46. Similarly, calculations for holes yield a value of 0.36 for bulk silicon and 0.16 for the 4 / 1 Si / O superlattice, resulting in a ratio of 0.44.

[0065] While such orientation preference characteristics may be desired in some semiconductor devices, other devices can benefit from a more uniform increase in mobility in any direction parallel to the layer set. As those skilled in the art will understand, it may also be advantageous to have increased mobility for both electrons and holes, or only one of these types of charge carriers.

[0066] For the 4 / 1Si / O embodiment of superlattice 25, the lower effective conductivity mass can be less than two-thirds of the effective conductivity mass that would otherwise occur, and this applies to both electrons and holes. Of course, superlattice 25 may also contain at least one type of conductivity dopant, as those skilled in the art will also understand.

[0067] Actually, now refer to another source. Figure 3 Now, another embodiment of the superlattice 25' with different properties according to the invention is described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is illustrated. More specifically, the lowest basic semiconductor portion 46a' has three monolayers and the second lowest basic semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. The band-changing layers 50' may each comprise a single monolayer. For such a Si / O superlattice 25', the enhancement of carrier mobility is independent of the orientation in the layer plane. Figure 3 Other elements not specifically mentioned are similar to those in the above references. Figure 1 Those points have already been discussed and do not need to be discussed further here.

[0068] In some device implementations, all the base semiconductor portions of the superlattice may be of the same number of monolayer thicknesses. In other implementations, at least some of the base semiconductor portions may be of different numbers of monolayer thicknesses. In still other implementations, all the base semiconductor portions may be of different numbers of monolayer thicknesses.

[0069] exist Figures 4A-4C The diagram presents the band structure calculated using density functional theory (DFT). It is well known in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands larger than the band gap can be shifted using appropriate "scissors correction." However, the shapes of the known bands are much more reliable. The vertical energy axis should be explained in this regard.

[0070] Figure 4A Display by Figure 1 The figure shows the band structure calculated from the γ point (G) of the 4 / 1 Si / O superlattice 25 (represented by dotted lines) and bulk silicon (represented by continuous lines). The directions relate to the unit cell of the 4 / 1 Si / O structure and not to the conventional unit cell of Si; however, the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and thus shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will understand that the Si bands in the figure are folded to represent their orientation in the appropriate reciprocal lattice direction for the 4 / 1 Si / O structure.

[0071] It can be seen that, compared to bulk silicon (Si), the conduction band minimum of the 4 / 1Si / O structure is located at point γ, while the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction, which we call point Z. Due to band splitting caused by perturbations introduced by the additional oxygen layer, it can also be noted that the curvature of the conduction band minimum of the 4 / 1Si / O structure is greater than that of Si.

[0072] Figure 4B The figure shows the band structure calculated from the Z-point of the bulk silicon (continuous line) and the 4 / 1Si / O superlattice 25 (dotted line). This figure illustrates the increased curvature of the valence band in the (100) direction.

[0073] Figure 4C Display by Figure 3The band structure was calculated for both the 25' superlattice 5 / 1 / 3 / 1 Si / O structure (dotted line) and bulk silicon (continuous line) at points γ and Z. Due to the symmetry of the 5 / 1 / 3 / 1 Si / O structure, the band structures calculated in the (100) and (010) directions are equivalent. Therefore, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that in the 5 / 1 / 3 / 1 Si / O example, the conduction band minimum and valence band maximum are both at or near point Z.

[0074] Although the increased curvature represents a reduced effective mass, it can be appropriately compared and differentiated through calculations using the conductivity reciprocal effective mass tensor. This leads the applicant to further theoretically demonstrate that the 5 / 1 / 3 / 1 superlattice 25' should be essentially a direct bandgap. As those skilled in the art will understand, the appropriate matrix elements used for the optical transition are another indicator of the distinction between direct and indirect bandgap behavior.

[0075] The structure and formation of an example MST material have now been described. Various embodiments of semiconductor devices and their fabrication methods will now be described, which advantageously provide metal-silicon contacts with adjacent dopants using the MST material described above. In a background manner, in semiconductor devices, electrons typically transfer between a semiconductor (e.g., silicon) and a conductive metal “interconnect” that transfers charge between semiconductor devices. The resistance between the semiconductor and the metal increases the energy required and reduces the maximum speed of computation and other functions performed using the circuitry of the device. Therefore, it is advantageous to minimize this resistance.

[0076] When electrons transfer between a metal and a semiconductor, such as silicon, a potential barrier exists that the electrons encounter. This barrier is commonly referred to as the "Schottky barrier." Electrons can have enough kinetic energy to overcome the Schottky barrier directly, or electrons with lower kinetic energy can tunnel between the metal and semiconductor through a quantum mechanical tunneling effect. The thinner the Schottky barrier is spatially, the more likely such tunneling is to occur. A common way to reduce the barrier is to increase the electric field. Higher levels of ionized impurities ("dopants") typically produce a higher electric field and thus increase the likelihood of tunneling, thereby increasing the electron flux between the metal and semiconductor and thus reducing the effective resistance. However, in addition to increasing the electric field, high impurity levels can further reduce the Schottky barrier itself by reducing the effective bandgap of the semiconductor directly adjacent to the metal-semiconductor interface (and via other chemical effects). This effect is evident from density functional theory calculations.

[0077] For example, an oxygen insertion (OI) layer (or other non-semiconductor layer) provided in an MST film can result in a lower Schottky barrier and / or a thinner barrier by trapping dopants. Density functional theory calculations show that the OI layer provides a favorable substitution of silicon atoms for specific dopant atoms within one or two atomic layers of the OI layer. By trapping dopants directly adjacent to the metal-semiconductor interface, such as those separated from the metal-semiconductor interface by one or two atomic layers, the OI layer can thus result in a relatively high concentration of dopants directly adjacent to the metal-semiconductor interface, thereby increasing the electric field and additionally reducing the Schottky barrier.

[0078] In addition to capturing dopants, OI layers can also immobilize point defects that otherwise facilitate dopant diffusion. Therefore, while an OI layer immediately adjacent to the metal-semiconductor layer captures dopants directly adjacent to the interface, additional OI layers further from the interface but still adjacent can capture point defects that otherwise facilitate dopant diffusion away from the interface. Thus, it is advantageous to have more than one, such as two, three, or four OI layers adjacent to the interface.

[0079] Generally, the embodiments described herein use one or more oxygen insertion (“OI” or “MST”) layers very close to the metal-semiconductor interface, along with high (e.g., more than 10 nm) layers close to the metal-silicon interface (e.g., less than 1 nm). 21 / cm 3 Ionized impurities (such as boron, phosphorus, arsenic, antimony, indium, or gallium) that constitute 2% of the crystal sites in the silicon lattice. Examples of metals include aluminum, tungsten, nickel, titanium, copper, cobalt, indium, gold, platinum, erbium, ytterbium, and any compounds of these metals with silicon or germanium.

[0080] Because the OI layer can provide advantageous substitution of silicon atoms for dopant atoms at a distance of one or two atomic layers, the most advantageous spacing between the OI layer and the metal-semiconductor interface is one or two atomic layers, thereby allowing high concentrations of dopants to be trapped up to and directly adjacent to the metal-semiconductor interface. However, other spacings, such as three or four atomic layers, can also provide benefits. Additionally, including an extra oxygen insertion layer besides this first oxygen insertion layer can be advantageous.

[0081] exist Figure 15 Figure 500 illustrates an example of this approach, where: Si = silicon atom, M = metal atom (e.g., titanium), O = oxygen atom, and D = dopant atom (e.g., boron). The oxygen atom depicted represents a portion of the oxygen insertion layer, where oxygen is bonded to adjacent silicon atoms. While oxygen atoms are necessarily present in the OI layer, nitrogen atoms (not shown in the figure) may also be present. The presence of nitrogen can be beneficial, for example, for dopant trapping or the thermal stability of the OI layer.

[0082] Similarly, the dopants shown replace silicon atoms in the crystalline lattice, rather than occupying "interstitial" sites or forming dopant clusters (so they would not contribute to free carriers in the semiconductor). However, although the figures show alternative dopants, high concentrations of dopants trapped near the metal-semiconductor interface can reduce the Schottky barrier in the case of alternating atomic configurations. The positions of the dopants in the figures are schematic representations for illustrative purposes. The actual distribution of dopant atoms will be partially random, influenced by the specific atomic configuration of oxygen atoms and the local bonding of atoms. The illustrated configurations represent the distance of atoms from the metal-semiconductor interface, not the specific locations of atoms within the layer. The illustrated configurations are as follows:

[0083] (a) The OI layer is in contact with the metal to capture the dopants below the OI layer;

[0084] (b) An OI layer separated from the metal by a silicon atom layer, capturing dopants above and below the OI layer;

[0085] (c) An OI layer separated from the metal by two atomic layers, capturing dopants above and below the OI layer;

[0086] (d) An OI layer separated from the metal by three atomic layers, capturing dopants above and below the OI layer, but not reaching the metal interface itself in this example;

[0087] (e) An OI layer separated from the metal by four atomic layers, capturing dopants above and below the OI layer, but not reaching the metal interface itself in this example.

[0088] In addition to these constructions, additional constructions with multiple OI layers are also possible, such as a layer separated from the metal-semiconductor interface by two silicon layers, and an additional layer separated by four additional atomic layers. These multilayers can provide dopant trapping at and below the metal-semiconductor interface; the former contributes to a lower chemical Schottky barrier and a higher electric field, while the latter primarily contributes to a higher electric field. The embodiments described herein are generally defined by the presence of a layer adjacent to the metal-semiconductor interface along with a high concentration of dopant, but additional layers or dopant atoms not adjacent to one (or more) OI layers are not excluded. Specific advantages of additional OI layers are that they can improve structural stability, for example, by preventing oxygen loss from the layer closest to the metal-semiconductor interface, or by trapping point defects that otherwise would cause dopant atoms to be lost from the region adjacent to the metal-semiconductor interface.

[0089] Now for reference Figure 5The superlattice structures described above can be advantageously used in semiconductor devices to provide reduced source / drain contact resistance by applying the principles described above. In typical semiconductor processing, reducing the metal-semiconductor contact area requires a lower contact resistivity (e.g., ρ). c <1E-8ohm.cm 2 Contact resistivity is determined by two parameters, namely:

[0090] N D : Concentration of active dopant at the metal / semiconductor interface; and

[0091] ΦF Bo : The height of the Schottky barrier at the metal / semiconductor interface.

[0092] Furthermore, the metal-semiconductor Schottky barrier height is "pinned" for different metals. Additionally, depending on thickness, band gap, and dielectric constant, interfacial insulators can "depin" the Fermi level.

[0093] exist Figure 5 In the semiconductor device 100 (FET) shown, the dopant diffusion barrier superlattice 125 (e.g.) Figure 1-4C The types described above are used to advantageously increase the surface dopant concentration, thereby allowing higher N2 concentrations during in-situ doping of the epitaxial process by preventing diffusion into the channel region 130 of the device. D More specifically, device 100 illustratively includes a semiconductor layer or substrate 101, and spaced-apart source and drain regions 102, 103 formed in the semiconductor layer, and a channel region 130 extending therebetween. A dopant diffusion barrier superlattice 125 illustratively extends through the source region 102 to divide the source region into a lower source region 104 and an upper source region 105, and also extends through the drain region 103 to divide the drain region into a lower drain region 106 and an upper drain region 107.

[0094] The dopant diffusion barrier superlattice 125 can also be conceptually considered as a source dopant barrier superlattice within the source region 102, a drain dopant barrier superlattice within the drain region 103, and a bulk dopant barrier superlattice beneath the channel 130, although in this configuration all three are provided as a continuous film by a single blanket deposition of MST material across the substrate 101. The semiconductor material defining the upper source / drain regions 105, 107 and the channel region 130 can be epitaxially grown on the dopant barrier superlattice 125 as a thick superlattice capping layer or a bulk semiconductor layer, as discussed further above. In the illustrated example, the upper source / drain regions 105, 107 may each be flush with the upper surface of this semiconductor layer (i.e., they are implanted into this layer).

[0095] Thus, the upper source / drain regions 105, 107 can advantageously have the same conductivity as the lower source / drain regions 104, 106, but with a higher dopant concentration. In the illustrated example, the upper source / drain regions 105, 107 and the lower source / drain regions 104, 106 are N-type for N-channel devices, but these regions can also be P-type for P-channel devices (this also applies to other constructions described herein). Surface dopant can be introduced, for example, by ion implantation. However, dopant diffusion is reduced by the MST film material of the diffusion-blocking superlattice 125 because it captures point defects / gap formations caused by ion implantation that affect dopant diffusion immediately.

[0096] The semiconductor device 100 also illustratively includes a gate 108 on a channel region 130. The gate illustratively includes a gate insulating layer 109 and a gate electrode 110. Sidewall spacers 111 are also provided in the illustrative example.

[0097] Now for reference Figure 6 According to another example embodiment, a semiconductor device 200 (FET) illustratively includes a semiconductor layer or substrate 201, and spaced-apart source and drain regions 202, 203 and a channel region 230 extending therebetween. In the illustrated embodiment, a source diffusion barrier superlattice 225s illustratively extends through the source region 202 to divide the source region into a lower source region 204 and an upper source region 205. Similarly, a drain diffusion barrier superlattice 225d extends through the drain region 203 to divide the drain region into a lower drain region 206 and an upper drain region 207. Alternatively, consider raising each of the upper source and drain regions 205, 207 above the upper surface of the semiconductor layer 201, and without... Figure 5As in the example, a superlattice extends between the source and drain regions 202, 203 (i.e., below the gate 208). The gate 208 illustratively includes a gate insulator 209 and a gate electrode 210, and may also provide a gate sidewall spacer 211.

[0098] In this embodiment, surface dopant can be introduced into the upper source / drain regions 205, 207 by selectively growing an MST film followed by the formation of an in-situ doped epi film. Here again, the MST material of the source / drain dopant diffusion barrier superlattice 225s, 225b advantageously helps prevent dopant diffusion into the channel region 230, and thus allows for a higher surface dopant concentration as noted above.

[0099] Now according to the reference Figures 7A-7C Another example implementation described herein may be applicable to Figure 5 The semiconductor device 100 shown undergoes further processing steps to modulate the Schottky barrier height by controlling the thickness and composition of the interface insulator. Using conventional metal contacts, excessively thick source / drain insulators result in high contact resistivity due to high tunneling resistance. However, the superlattice 125' advantageously provides the desired non-semiconductor (e.g., oxygen) dosage control for Fermi level depinning and tunneling resistance. After forming the gate 108' on the channel region 130', co-implantation of N, C, or F can further modulate the insulator composition to a lower dielectric constant (e.g., using C and F for low-k ILD films to modulate the SiO2 composition), such as... Figure 7A The description states that the MST film of the superlattice 125' effectively accumulates these elements in the surface region. It should be noted that in some embodiments, N and C can be introduced into the silicon surface in gaseous form (e.g., N2 annealing or CO, CH4 annealing) instead of co-implantation.

[0100] Then heat treatment and metal deposition can be performed. Figures 7B-7C Heat treatment causes non-semiconductor atoms (oxygen in this example) from the non-semiconductor monolayer of the dopant diffusion barrier superlattice 125' to move upwards. These non-semiconductor atoms react with the metal to form respective source and drain contact insulating interfaces 140', 141' between the upper source and drain regions and adjacent portions of the metal layers 142', 143' formed by metal deposition. In other words, because oxygen atoms separate from the superlattice 125' in the source and drain regions and move upwards to form contact insulating interfaces 140', 141', the defining superlattice layer separating the lower / upper source regions 104', 105' and the lower / upper drain regions 106', 107' no longer exists (see [link to relevant documentation]). Figure 7B ).

[0101] According to one example implementation, Co / Co can be carried out at temperatures in the range of approximately +200 to 400°C. 0.75 Ti 0.25 (2nm) Metal deposition takes approximately 10 minutes to form source and drain contact insulating interfaces 140', 141' and metal layers 142', 143'. In addition, in some embodiments, additional metal deposition (e.g., Co) may be performed to form upper source / drain metal contact layers 144', 145' in the semiconductor device 100'.

[0102] Now for reference Figure 8 Another example embodiment similar to semiconductor device 200 is described. In this illustrated example, the source and drain dopant diffusion-blocking superlattices 225s', 225d' advantageously provide Schottky barrier height modulation via heteroepitaxial film integration. More specifically, the lower source and drain regions 204', 206' comprise a different material than the upper source and drain regions 205', 207'. In this example, the lower source and drain regions 204', 206' are silicon, and the upper source and drain regions 205', 207' are SiGeC, but different materials may be used in different embodiments.

[0103] Because MST materials effectively integrate heteroepitaxial semiconductor materials, the introduction of C (1-2%) into Si or SiGe on Si can cause a shift in the positive conduction band. More specifically, this is effective for reducing the Schottky barrier height in the SiGeC / MST / n+Si structure.

[0104] For further reference Figure 9 Another similar semiconductor device 200” advantageously provides Schottky barrier height modulation via heteroepitaxial film integration. In the illustrated example, the semiconductor layer / substrate 201” is silicon-germanium, and the lower source / drain regions 204”, 206” are p+SiGe. However, the upper source / drain regions 205”, 207” are also silicon, and a respective platinum contact layer 242”, 243” is formed on each upper source / drain region. The upper source / drain regions 205”, 207” can be formed with a relatively thin epitaxial silicon layer (e.g., 2-5 nm). Here again, the MST material effectively integrates the heteroepitaxial semiconductor material, and the strained Si on SiGe (or Ge) can advantageously cause a negative valence band shift. As a result, the illustrated s-Si / MST / p+SiGe structure can also effectively reduce the Schottky barrier height.

[0105] Now turn around Figure 10Furthermore, some of the planar FET structures described above can be advantageously implemented in vertical semiconductor devices. Example FINFET 300 illustratively includes a semiconductor layer or substrate 301 (e.g., silicon), an insulating layer 350 (e.g., SiO2) on the substrate, and one or more semiconductor fins 351 extending vertically upward from the substrate through the insulating layer.

[0106] In each semiconductor fin 351, spaced-apart source and drain regions 302 and 303 are formed, along with a channel region 330 extending between them. A source dopant diffusion-barrier superlattice 325s extends through source region 302, dividing the source region into a lower source region 304 and an upper source region 305, and a drain dopant diffusion-barrier superlattice 325d extends through drain region 303, dividing the drain region into a lower drain region 306 and an upper drain region 307. Figure 6 Similar to the implementation scheme, the upper source / drain regions 305 and 307 have the same conductivity and a higher dopant concentration (N++) as the lower source / drain regions 304 and 306 (N+). Furthermore, the upper source / drain regions 305 and 307 extend above the upper surface of the semiconductor fin 351. That is, superlattices 325s and 325d can be formed on the top of the semiconductor fin 351, and the upper source / drain regions 305 and 307 can be epitaxially grown on their respective superlattices. In this regard, the upper source / drain regions 305 and 307 can be implanted with dopant, or they can be in-situ doped epitaxial layers as described above.

[0107] The FINFET 300 also illustratively includes a gate 308 covering the channel region 330 of the fin 351. The gate 308 illustratively includes a gate insulator 309 and a gate electrode 310 on the gate insulator.

[0108] In another example implementation, the FINFET 300' can be used with the above reference. Figures 7A-7C The process described is similar to fabrication, including heat treatment and metal deposition to define the upper source / drain regions 305', 307' and metal layers 342', 343' (e.g., CoTi). xThe source / drain insulating layers 340' and 341' are located between the lower metal layers 342' and 343'. In some embodiments, upper metal layers 344' and 345' (e.g., Co) may also be formed on the lower metal layers 342' and 343'. Here again, the thermal treatment causes the source / drain dopants to block the upward movement of non-semiconductor atoms in the superlattice layer, resulting in no superlattice being left between the upper source / drain regions 305' and 307' and the lower source / drain regions 304' and 306' in the final FINFET 300'. Here again, this approach advantageously provides Schottky barrier height modulation by controlling the thickness and composition of the interface insulators 340' and 341'.

[0109] For further reference Figure 13 Provided with the above Figure 8 A similar FINFET 300” implementation is used, wherein the source and drain doped barrier superlattices 325s”, 325d” advantageously provide Schottky barrier height modulation via heteroepitaxial film integration. More specifically, the lower source and drain regions 304”, 306” comprise different materials than the upper source and drain regions 305”, 307”. In this example, the lower source and drain regions 304”, 306” are silicon, and the upper source and drain regions 305”, 307” are SiGeC, but different materials may be used in different implementations. Similarly, in the illustrated example, the lower metal layers 342”, 342” are titanium, and the upper metal layers 344”, 345” are cobalt.

[0110] exist Figure 14 In another example shown, with Figure 9 Similar to the implementation, the FINFET 300”’ can also provide Schottky barrier height modulation via heteroepitaxial film integration. In the illustrated example, the semiconductor fin 351” is silicon germanium, and the lower source / drain regions 304”, 306” are P+SiGe. However, the upper source / drain regions 305”, 307” are silicon, and a respective platinum contact layer 342”, 343” is formed on each upper source / drain region. Here again, the upper source / drain regions 305”, 307” can be formed with a relatively thin epitaxial silicon layer (e.g., 2-5nm).

[0111] In the examples described above, dopant-blocking superlattices are shown in both the source and drain regions of the illustrated device. However, it should be noted that in some embodiments, not both the source and drain regions need to have dopant-blocking superlattices. That is, in some embodiments, a dopant-blocking superlattice may exist only in one of the source or drain regions.

[0112] Furthermore, now turning Figure 16In some embodiments, in addition to or instead of in the source / drain regions, a dopant-blocking superlattice may be introduced into the body contact to provide reduced body contact resistance. In the illustrated example, semiconductor device 400 (here, a planar FET) includes a semiconductor layer or substrate 401, spaced-apart source and drain regions 402, 403 (in this example having their respective lightly doped source / drain extensions 404, 405) within semiconductor layer 401, a channel region 430 extending therebetween, and a gate 408 having sidewall spacers 411 on the channel region. As described similarly above, gate 408 illustratively includes a gate insulator 409 and a gate electrode 410. Semiconductor device 400 also illustratively includes a body contact 420 in semiconductor layer 401, and said body contact 420 includes a body contact dopant diffusion blocking superlattice 425 extending through the body contact to divide the body contact into a first body contact region 421 and a second body contact region 422. As described above, the second body contact region 422 has the same conductivity as the first body contact region 421 but a higher dopant concentration. Again, the dopant diffusion barrier superlattice 425 of the body contact can be similar to those superlattice structures described above, and the materials used for the first and second body contact regions 421, 422 and the dopant concentrations within them can also be similar to those described above, thereby providing the desired reduction in contact resistance.

[0113] exist Figure 17 In another example device 400' shown, a similar construction is provided, which has a back-side body contact portion 420' instead of Figure 16 The top or front body contact portion 420 is shown in the image. The remaining components are similar to those in the reference image. Figure 16 Those discussed and therefore need not be discussed further herein. It should be noted that in the back-side embodiment, the first and second regions 421', 422' are vertically flipped relative to the first and second regions 421, 422 in the device 400, because they are on opposite sides of the device 400'.

[0114] Turn now Figure 18Another example contact structure 500 is now described, which may also be used in some embodiments of source / drain, body, or other contacts to provide a reduced Schottky barrier height and thereby a reduced contact resistance. The contact 500 is formed in a semiconductor layer 501. The contact 500 illustratively includes one or more oxygen monolayers 550 constrained within the crystal lattice of adjacent semiconductor portions 546a, 546b of the semiconductor layer 501. One (or more) oxygen monolayers 550 are spaced apart from the surface of the semiconductor layer 501 by one to four monolayers (four monolayers are shown spaced apart in semiconductor portion 546b in the illustrative example). Furthermore, a metal layer 531 (which may include the same metal discussed above) is formed on the surface of the semiconductor layer 501 above one (or more) oxygen monolayers 550. The contact 500 may be formed on the semiconductor layer or substrate 521.

[0115] By way of example, the dopant concentration in part 546b (i.e., between one (or more) oxygen monolayers 550 and metal layer 531) can be 1 × 10⁻⁶. 21 atoms / cm 3 Or even higher (although lower concentrations may be used in different implementations). Alternatively, consider a dopant concentration in the example construction that advantageously occupies the equivalent of approximately 2% of the crystal sites in a silicon lattice. This is based on an estimate of the maximum distance range within which the oxygen monolayer can directly trap dopants (e.g., boron) close enough to the metal to directly reduce the Schottky barrier of the contact, rather than reducing diffusion, while otherwise maintaining the conventional doped metal-semiconductor interface in a bulk-line environment for the dopant atoms, and at the minimum dopant concentration where the benefits will be realized.

[0116] Many modifications and other embodiments of the invention will arise for those skilled in the art from the teachings presented in the foregoing description and the accompanying drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. Semiconductor devices, including: Semiconductor layer; The semiconductor layer contains spaced-apart source and drain regions and a channel region extending between them. The gate in the channel region; and The semiconductor layer has a body contact portion, and the body contact portion includes a body contact portion dopant diffusion barrier superlattice extending through the body contact portion to divide the body contact portion into a first body contact region and a second body contact region, wherein the second body contact region has the same conductivity as the first body contact region and a higher dopant concentration than the first body contact region. The dopant diffusion barrier superlattice of the body contact portion comprises multiple stacked layers, each layer comprising multiple stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of an adjacent base silicon portion. The second body contact area is flush with the top surface or the bottom surface of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein the source region, the drain region, and the body contact are on the top side of the semiconductor layer.

3. The semiconductor device of claim 1, wherein the source region and the drain region are on the top side of the semiconductor layer, and the body contact is on the back side of the semiconductor layer opposite to the top side.

4. The semiconductor device of claim 1, wherein the first body contact region comprises a material different from the second body contact region.

5. The semiconductor device of claim 4, wherein the first body contact region comprises silicon; and wherein the second body contact region comprises silicon-germanium.

6. The semiconductor device of claim 4, wherein the first body contact region comprises silicon germanium; and wherein the second body contact region comprises silicon.

7. The semiconductor device according to claim 1, further comprising a metal contact portion on the second body contact region.

8. The semiconductor device of claim 7, wherein the metal contact comprises at least one of titanium, cobalt, nickel and platinum.

9. A method for manufacturing a semiconductor device, comprising: Spaced-out source and drain regions are formed in the semiconductor layer, with an extended channel region between them; A gate is formed in this channel region; and A body contact is formed in the semiconductor layer, and the body contact includes a body contact dopant diffusion barrier superlattice extending through the body contact to divide the body contact into a first body contact region and a second body contact region, wherein the second body contact region has the same conductivity as the first body contact region and a higher dopant concentration than the first body contact region. The dopant diffusion barrier superlattice of the body contact portion comprises multiple stacked layers, each layer comprising multiple stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of an adjacent base silicon portion. The second body contact area is flush with the top surface or the bottom surface of the semiconductor layer.

10. The method of claim 9, wherein the source region, the drain region, and the body contact are on the top side of the semiconductor layer.

11. The method of claim 9, wherein the source region and the drain region are on the top side of the semiconductor layer, and the body contact is on the back side of the semiconductor layer opposite to the top side.

12. The method of claim 9, wherein the first body contact region comprises a material different from the second body contact region.

13. The method of claim 12, wherein the first body contact region comprises silicon; and wherein the second body contact region comprises silicon germanium.

14. The method of claim 12, wherein the first body contact region comprises silicon germanium; and wherein the second body contact region comprises silicon.

15. The method of claim 9, further comprising a metal contact portion on the second body contact area.

16. The method of claim 15, wherein the metal contact comprises at least one selected from titanium, cobalt, nickel, and platinum.

Images