Semiconductor devices including source / drain dopant diffusion barrier superlattice to reduce contact resistance and related methods

Abstract

The semiconductor device (100) may include a semiconductor layer (101), spaced-apart source and drain regions (102, 103) in the semiconductor layer with a channel region (130) extending therebetween, and at least one dopant diffusion barrier superlattice (125) dividing at least one of the source and drain regions into a lower region (104, 106) and an upper region (105, 107), wherein the upper region has the same conductivity as the lower region and a higher dopant concentration than the lower region. The at least one dopant diffusion barrier superlattice comprises a plurality of stacked layer groups, wherein each layer group comprises a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. The semiconductor device may also include a gate (109, 110) on the channel region.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor devices having enhanced contact configurations and related methods.

[0002] background

[0003] Structures and techniques have been proposed to enhance the performance of semiconductor devices, for example by enhancing the mobility of carriers. For example, U.S. Patent Application No. 2003 / 0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium and relaxed silicon and the strained material layers also include impurity-free regions (which would otherwise cause performance degradation). The biaxial strain produced in the upper silicon layer changes the carrier mobility, making higher speed and / or lower power devices possible. U.S. Patent Application No. 2003 / 0034529 published by Fitzgerald et al. discloses a CMOS inverter also based on similar strained silicon technology.

[0004] Takagi's U.S. Patent No. 6,472,685B2 discloses a semiconductor device including silicon and carbon layers sandwiched between silicon layers so that the conduction band and the valence band of the second silicon layer receive tensile strain. Electrons having a smaller effective mass and caused by an electric field applied to a gate are confined in the second silicon layer, so it is claimed that the n-channel MOSFET has a higher mobility.

[0005] US Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which multiple layers (less than eight monolayers) are alternately and epitaxially grown and contain fractional or binary or binary compound semiconductor layers. The direction of the main current is perpendicular to the layers of the superlattice.

[0006] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. In line with these approaches, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material, the second material being present in the silicon lattice at a percentage substitutional level that places the channel layer under tensile stress.

[0007] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating layers of SiO2 / Si, with a thickness typically in the range of 2 to 6 monolayers. Much thicker portions of silicon are sandwiched between the barriers.

[0008] An article also by Tsu entitled "Phenomena in silicon nanostructure devices" and published online by Applied Physics and Materials Science & Processing on September 6, 2000, pages 391-402, discloses semiconductor-atomic superlattices (SAS) of silicon and oxygen. The disclosed Si / O superlattice can be used in silicon quantum and light-emitting devices. In particular, a green electroluminescent diode structure was constructed and tested. The current in the diode structure is vertical, that is, perpendicular to the layer of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed substances such as oxygen atoms and CO molecules. The silicon growth beyond the adsorbed oxygen monolayer is described as epitaxy with a relatively low defect density. One SAS structure includes a 1.1nm thick silicon portion (which is about eight atomic layers of silicon), and another structure has twice this silicon thickness. Tsu's light-emitting SAS structure is also discussed in an article by Luo et al. entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002).

[0009] Wang et al., US Patent No. 7,105,895 discloses a thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen barrier structure unit, thereby reducing the vertical current flowing through the lattice by more than four orders of magnitude. The insulating layer / barrier layer allows low-defect epitaxial silicon to be deposited next to the insulating layer.

[0010] Mears et al. published British patent application 2,347,520 discloses that the principles of aperiodic photonic bandgap (APBG) structures can be applied to electronic bandgap engineering. In particular, the application discloses that material parameters such as band minimum position, effective mass, etc. can be adjusted to produce new aperiodic materials with desired band structure properties. It is disclosed that other parameters such as electrical conductivity, thermal conductivity and dielectric constant or magnetic permeability can also be designed in the material.

[0011] In addition, U.S. Pat. No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for a semiconductor device, comprising depositing a layer of silicon and at least one additional element on a silicon substrate, whereby the deposited layer is substantially free of defects so that substantially defect-free epitaxial silicon can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably including oxygen, is adsorbed on the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier composite.

[0012] Notwithstanding such avenues, further enhancements may be desirable to achieve improved performance using advanced semiconductor materials and processing techniques in semiconductor devices.

[0013] Overview

[0014] A semiconductor device may include a semiconductor layer, spaced-apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion barrier superlattice dividing at least one of the source and drain regions into a lower region and an upper region, wherein the upper region has the same conductivity as the lower region and a higher dopant concentration than the lower region. The at least one dopant diffusion barrier superlattice comprises a plurality of stacked layer groups, wherein each layer group comprises a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion. The semiconductor device may also include a gate on the channel region.

[0015] More particularly, the at least one dopant diffusion barrier superlattice may include a respective dopant diffusion barrier superlattice for each of the source and drain regions.The semiconductor device may also include a bulk dopant diffusion barrier superlattice in the semiconductor layer extending between the source and drain regions.

[0016] In one example embodiment, the upper region may be flush with the upper surface of the semiconductor layer. According to another example embodiment, the upper region may be elevated above the upper surface of the semiconductor layer. In addition, the lower region may include a different material than the upper region. By way of example, the lower region may include silicon and the upper region may include silicon germanium. According to another example, the lower region may include silicon germanium and the upper region may include silicon.

[0017] The semiconductor layer may further include a metal contact on the upper region. By way of example, the metal contact may include at least one of titanium, cobalt, nickel, and platinum. Also by way of example, the base semiconductor monolayer may include silicon, and the at least one non-semiconductor monolayer may include oxygen.

[0018] A method for manufacturing a semiconductor device may include forming spaced-apart source and drain regions in a semiconductor layer with an extended channel region therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion barrier superlattice, wherein the upper region has the same conductivity as the lower region and a higher dopant concentration than the lower region. The dopant diffusion barrier superlattice may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion. The method may also include forming a gate on the channel region.

[0019] More particularly, each of the source and drain regions may be divided into a lower region and an upper region by respective dopant diffusion barrier superlattices. In addition, the method may further include forming a bulk dopant diffusion barrier superlattice in the semiconductor layer extending between the source and drain regions and comprising respective multiple stacked layer groups, wherein each layer group comprises multiple stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion.

[0020] In one example embodiment, the upper region may be flush with the upper surface of the semiconductor layer. According to another example embodiment, the upper region may be elevated above the upper surface of the semiconductor layer. The lower region may comprise a different material than the upper region. By way of example, the lower region may comprise silicon and the upper region may comprise silicon germanium. In another example embodiment, the lower region may comprise silicon germanium and the upper region may comprise silicon.

[0021] The method may further include forming a metal contact on the upper region. By way of example, the metal contact may include at least one of titanium, cobalt, nickel, and platinum. Also by way of example, the base semiconductor monolayer may include silicon, and the at least one non-semiconductor monolayer may include oxygen.

[0022] BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device according to an example embodiment.

[0024] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of a superlattice is shown in FIG.

[0025] Figure 3 is a greatly enlarged schematic cross-sectional illustration of another embodiment of a superlattice according to an example embodiment.

[0026] Figure 4A It is made of bulk silicon and Figure 1-2 The calculated band structure diagram of the γ point (G) of the 4 / 1Si / O superlattice is shown in FIG.

[0027] Figure 4B It is made of bulk silicon and Figure 1-2 The calculated band structure diagram of the 4 / 1Si / O superlattice at point Z is shown in Figure .

[0028] Figure 4C It is made of bulk silicon and Figure 3 The calculated band structure diagram of the γ and Z points of the 5 / 1 / 3 / 1Si / O superlattice is shown in Figure .

[0029] Figure 5 is a schematic cross-sectional view of a semiconductor device including a dopant diffusion barrier superlattice that separates source and drain regions to provide reduced source and drain contact resistance.

[0030] Figure 6 is a schematic cross-sectional view of a semiconductor device including source and drain regions separated by respective dopant diffusion barrier superlattices and providing reduced source and drain contact resistance.

[0031] Figures 7A-7C is a series of schematic cross-sectional diagrams illustrating a method of fabricating a semiconductor device having interim source and drain superlattice layers to provide Schottky barrier height modulation by controlling interfacial insulator formation.

[0032] Figure 8-9 is a schematic cross-sectional view of an example semiconductor device including source and drain regions separated by respective superlattices and having distinct upper and lower semiconductor source / drain materials and metal contact regions.

[0033] Fig.10 is a perspective view of a FINFET including source and drain regions separated by respective superlattices and providing reduced source and drain contact resistance.

[0034] Fig.11 yes Fig.10 A cross-sectional view of a FINFET taken along line AA.

[0035] Fig.12 Is used with Figures 7A-7C A similar method as shown in Fig.10 A cross-sectional view of an alternative embodiment of a FINFET taken along line AA.

[0036] Fig.13 and 14 They include and Figure 8and 9 The source and drain configurations of the devices are similar Fig.10 A cross-sectional view of an alternative embodiment of a FINFET taken along line AA.

[0037] Fig.15 is a series of schematic atomic-level diagrams that illustrate the use of Figure 1-4C The non-semiconducting insertion layer of the MST film shown in Figure 5-14 Embodiments of the present invention provide a means of providing a metal-semiconductor contact with a closely adjacent dopant with reduced Schottky barrier height.

[0038] Fig.16 is a schematic cross-sectional view of a semiconductor device including a body contact having a dopant diffusion barrier superlattice to provide reduced contact resistance according to an example embodiment.

[0039] Fig.17 is a schematic cross-sectional view of a semiconductor device including a backside body contact with a dopant diffusion barrier superlattice to provide reduced contact resistance according to an example embodiment.

[0040] Fig.18 is a cross-sectional view of an alternative contact structure that may be used to provide reduced contact resistance according to an example embodiment.

[0041] Detailed Description

[0042] Example embodiments will now be described more completely below with reference to the accompanying drawings in which example embodiments are shown. However, the embodiments can be implemented in many different forms and should not be construed as being limited to the specific embodiments listed herein. On the contrary, these embodiments are provided so that the disclosure will be comprehensive and complete. The same numbers always refer to the same elements, and primes and multiple primes are used to represent similar elements in different embodiments.

[0043] In general, the present disclosure relates to the use of enhanced superlattice materials in source and drain regions to reduce Schottky barrier height and thereby reduce source and drain contact resistance. The enhanced semiconductor superlattice is also referred to as an "MST" layer or "MST technology" in the present disclosure and drawings.

[0044] More particularly, the MST technique involves advanced semiconductor materials such as superlattices 25 described further below. Applicants theoretically state (without wishing to be bound thereto) that some superlattices as described herein reduce the effective mass of carriers and this thereby results in higher carrier mobility. Effective mass is described using various definitions in the literature. As a measure of the improvement in effective mass, Applicants use the "conductivity reciprocal effective mass tensor" for electrons and holes, respectively. and The definition is as follows:

[0045]

[0046] For electronics and:

[0047]

[0048] For holes, where f is the Fermi–Dirac distribution, E F is the Fermi energy, T is the temperature, E(k,n) is the energy of the electron in the state corresponding to wave vector k and the nth energy band, and the indices i and j refer to the Cartesian coordinates x, y and z, integrated over the Brillouin zone (BZ) and summed over the energy bands with energies greater and less than the Fermi energy of electrons and holes, respectively.

[0049] Applicants define the conductivity reciprocal effective mass tensor as such that the greater the tensor component of the conductivity of a material, the greater the value of the corresponding component of the conductivity reciprocal effective mass tensor. Again, Applicants theoretically state (without wishing to be bound thereby) that the superlattice described herein establishes the value of the conductivity reciprocal effective mass tensor to enhance the conductive properties of the material, such as the preferred direction for carrier transport in general. The reciprocal of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass of electrons / holes, as described above and calculated in the expected carrier transport direction, is used to distinguish improved materials.

[0050] Applicants have identified improved materials or structures for use in semiconductor devices. More particularly, Applicants have identified materials or structures having band structures for which the appropriate conductivity effective mass of electrons and / or holes is significantly less than that of silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a way that they provide piezoelectric, pyroelectric, and / or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

[0051] Reference now Figure 1 and 2 , the material or structure is in the form of a superlattice 25, whose structure is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in a stacked relationship, as specifically referenced Figure 1 It may be best understood by a schematic cross-sectional view of FIG.

[0052] Each layer group 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 (defining respective base semiconductor portions 46a-46n) and an energy band altering layer 50 thereon. For clarity of illustration, the energy band altering layer 50 is Figure 1 Indicated by dots and strokes.

[0053] The band-changing layer 50 illustratively includes a non-semiconductor monolayer that is constrained within the crystal lattice of the adjacent base semiconductor portion. By "constrained within the crystal lattice of the adjacent base semiconductor portion" is meant that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together by the non-semiconductor monolayer 50 therebetween, such as Figure 2 . In general, such a configuration is made possible by controlling the amount of non-semiconductor material deposited on semiconductor portions 46a-46n by atomic layer deposition techniques so that less than all (i.e., less than full or 100% coverage) of the available semiconductor binding sites are filled (polulated) with the binding of non-semiconductor atoms, as will be discussed further below. Thus, as additional monolayers 46 of semiconductor material are deposited on or over non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining vacant binding sites of semiconductor atoms below the non-semiconductor monolayer.

[0054] In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that references herein to non-semiconductor or semiconductor monolayers mean that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material such as silicon may not necessarily exhibit the same properties as it would if it were formed in a bulk or relatively thick layer, as will be understood by those skilled in the art.

[0055] Applicants have theoretically stated (without wishing to be bound thereto) that the band altering layer 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower conductivity effective mass for carriers in a parallel layer direction than would otherwise exist. Considered another way, this parallel direction is orthogonal to the stacking direction. The band altering layer 50 may also cause the superlattice 25 to have a common band structure, which also advantageously acts as an insulator between vertical regions or layers above and below the superlattice.

[0056] In addition, such a superlattice structure may also advantageously act as a barrier to dopant and / or material diffusion between vertical layers above and below the superlattice 25. These properties may therefore advantageously enable the superlattice 25 to provide a high-K dielectric interface that not only reduces diffusion of high-K materials into the channel region, but may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

[0057] It is also theoretically demonstrated that semiconductor devices including superlattice 25 can enjoy higher carrier mobility based on a lower conductivity effective mass than would otherwise exist. In some embodiments, and as a result of the band engineering enabled by the present invention, superlattice 25 can also have a substantially direct band gap that can be particularly beneficial, for example, in optoelectronic devices.

[0058] Superlattice 25 also illustratively includes a cap layer 52 on upper layer group 45n. Cap layer 52 may include a plurality of base semiconductor monolayers 46. Cap layer 52 may have between 2 and 100 base semiconductor monolayers, and more preferably between 10 and 50 monolayers.

[0059] Each base semiconductor portion 46a-46n may include a base semiconductor selected from the group consisting of: a Group IV semiconductor, a Group III-V semiconductor, and a Group II-VI semiconductor. Of course, the term Group IV semiconductor also includes Group IV-IV semiconductors, as will be understood by those skilled in the art. More specifically, the base semiconductor may include, for example, at least one of silicon and germanium.

[0060] Each band-changing layer 50 may, for example, comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor is also desirably thermally stable through the deposition of the next layer to facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise, for example, at least one of silicon and germanium.

[0061] It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It should also be noted that the band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer in which not all possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to Figure 2 Atomic diagram of a 4 / 1 repeating structure illustrating silicon as the base semiconductor material and oxygen as the band-changing material. In the illustrated example only half of the possible sites for oxygen are occupied.

[0062] In other embodiments and / or using different materials, as will be appreciated by those skilled in the art, this half occupancy need not be the case. Indeed, even in this schematic it can be seen that the individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane, as will be appreciated by those skilled in the art of atomic deposition. By way of example, a preferred occupancy range is from about one eighth to one half of all possible oxygen sites, although other numbers may be used in some embodiments.

[0063] Silicon and oxygen are currently widely used in conventional semiconductor processing, and thus manufacturers will readily be able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Thus, as will be appreciated by those skilled in the art, semiconductor devices including superlattice 25 according to the present invention may be readily adopted and implemented.

[0064] From a theoretical point of view (applicants do not wish to be bound by this): for a superlattice such as a Si / O superlattice, the number of silicon monolayers should desirably be seven or less so that the energy bands of the superlattice are relatively uniform or common throughout to achieve the desired advantages. Figure 1 and 2 The 4 / 1 repeating structure shown in has been modeled to demonstrate enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4 / 1 SiO superlattice in the X direction it is 0.12, resulting in a ratio of 0.46. Similarly, calculations for holes yield values ​​of 0.36 for bulk silicon and 0.16 for the 4 / 1 Si / O superlattice, resulting in a ratio of 0.44.

[0065] While such a directional preferential feature may be desirable in some semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the layer group. As will be appreciated by those skilled in the art, it may also be beneficial to have increased mobility for both electrons and holes or only one of these types of carriers.

[0066] The lower conductivity effective mass for the 4 / 1 Si / O embodiment of the superlattice 25 can be less than two-thirds of the conductivity effective mass that would otherwise occur, and this applies to both electrons and holes. Of course, the superlattice 25 can also include at least one type of conductivity dopant therein, as will also be understood by those skilled in the art.

[0067] In fact, now refer to Figure 3 , another embodiment of a superlattice 25' having different properties according to the present invention is now described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is illustrated. More specifically, the lowest base semiconductor portion 46a' has three monolayers and the second lowest base semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. The band-changing layers 50' may each comprise a single monolayer. For such a superlattice 25' comprising Si / O, the enhancement of carrier mobility is independent of the orientation in the plane of the layers. Figure 3 Those other elements not specifically mentioned are similar to those in the above reference Figure 1 those discussed and need not be discussed further here.

[0068] In some device embodiments, all base semiconductor portions of the superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be different numbers of monolayers thick. In still other embodiments, all base semiconductor portions may be different numbers of monolayers thick.

[0069] exist Figures 4A-4C In Figure 1, the band structure calculated using density functional theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands larger than the band gap can be offset by appropriate "scissors correction". However, the shape of the known bands is much more reliable. The vertical energy axis should be interpreted in this regard.

[0070] Figure 4A Displayed by Figure 1 Calculated band structures for the γ point (G) of the 4 / 1 Si / O superlattice 25 (represented by dotted lines) and bulk silicon (represented by continuous lines) shown in FIG. The directions relate to the unit cell of the 4 / 1 Si / O structure and not to the conventional unit cell of Si, but the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si and therefore shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the Si bands in the figure are folded to represent them in the appropriate reciprocal lattice directions for the 4 / 1 Si / O structure.

[0071] It can be seen that the conduction band minimum of the 4 / 1 Si / O structure is located at the γ point compared to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction, which we call the Z point. It can also be noted that the curvature of the conduction band minimum of the 4 / 1 Si / O structure is larger compared to that of Si due to the band splitting caused by the perturbation introduced by the additional oxygen layer.

[0072] Figure 4B The band structures calculated from the Z point of bulk silicon (continuous line) and the 4 / 1 Si / O superlattice 25 (dotted line) are shown. This figure illustrates the increased curvature of the valence band in the (100) direction.

[0073] Figure 4C Displayed by Figure 3The calculated band structures for both the γ and Z points of the 5 / 1 / 3 / 1 Si / O structure (dotted line) and bulk silicon (continuous line) of the superlattice 25'. Due to the symmetry of the 5 / 1 / 3 / 1 Si / O structure, the calculated band structures in the (100) and (010) directions are identical. It is therefore expected that the conductivity effective mass and mobility are isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that both the conduction band minimum and the valence band maximum are at or near the Z point in the 5 / 1 / 3 / 1 Si / O example.

[0074] While increased curvature is an indication of reduced effective mass, appropriate comparison and identification can be made through conductivity reciprocal effective mass tensor calculations. This leads Applicants to further theoretically demonstrate that the 5 / 1 / 3 / 1 superlattice 25' should be substantially direct bandgap. As will be appreciated by those skilled in the art, the appropriate matrix elements for optical transitions is another indicator of the distinction between direct and indirect bandgap behavior.

[0075] Having now described the structure and formation of example MST materials, various embodiments of semiconductor devices and methods of their manufacture will now be described which advantageously provide metal-silicon contacts with proximate dopants using the MST materials described above. By way of background, in semiconductor devices electrons are typically transferred between a semiconductor (e.g., silicon) and a conductive metal "interconnect" that transfers charge between semiconductor devices. The resistance between the semiconductor and the metal increases the energy required and reduces the maximum speed of computing and other functions performed by circuits using the device. It is therefore advantageous to minimize this resistance.

[0076] When electrons are transferred between metals and semiconductors such as silicon, there is a potential barrier that the electrons encounter. This potential barrier is generally referred to as a "Schottky barrier". Electrons may have enough kinetic energy to directly overcome the Schottky barrier, or electrons with lower kinetic energy may be transmitted between metals and semiconductors by quantum mechanical tunneling. The thinner the Schottky barrier is spatially, the more likely such a tunneling effect is. A common way to achieve reduced potential barriers is to increase the electric field. Higher levels of ionized impurities ("dopants") generally produce higher electric fields and therefore increase the possibility of tunneling, thereby increasing the electron flux between metals and semiconductors, thereby reducing effective resistance. However, in addition to increasing the electric field, high impurity levels can additionally reduce the Schottky barrier itself by reducing the effective band gap of the semiconductor directly adjacent to the metal-semiconductor interface (and via other chemical effects). This effect is apparent from density functional theory calculations.

[0077] For example, an oxygen insertion (OI) layer (or other non-semiconductor layer) provided in an MST film can result in a lower Schottky and / or thinner barrier by trapping dopants. Density functional theory calculations show that the OI layer provides a favorable substitution of silicon atoms by specific dopant atoms within one or two atomic layers of the OI layer. By trapping dopants that are directly adjacent to the metal-semiconductor interface, such as separated from the metal-semiconductor interface by one or two atomic layers, the OI layer can thus result in a relatively higher concentration of dopants directly adjacent to the metal-semiconductor interface, thereby increasing the electric field and additionally reducing the Schottky barrier.

[0078] In addition to trapping dopants, the OI layer can pin them by trapping point defects that would otherwise aid in the diffusion of dopants. So, while an OI layer immediately adjacent to the metal-semiconductor layer can trap dopants directly adjacent to the interface, additional OI layers farther from the interface but still immediately adjacent to the interface can trap point defects that would otherwise aid in the diffusion of dopants away from the interface. Thus, it can be beneficial to have more than one, e.g., two, three, or four, OI layers immediately adjacent to the interface.

[0079] In general, embodiments described herein use one or more oxygen insertion ("OI" or "MST") layers in close proximity to the metal-semiconductor interface in conjunction with a high (e.g., greater than 10 nm) distance to the metal-silicon interface. 21 / cm 3 Ionized impurities such as boron, phosphorus, arsenic, antimony, indium, or gallium that are present in the silicon lattice (or 2% of the crystalline sites in the silicon lattice). Examples of metals include aluminum, tungsten, nickel, titanium, copper, cobalt, indium, gold, platinum, erbium, ytterbium, and compounds of any of these metals with silicon or germanium.

[0080] Because the OI layer can provide a favorable replacement of dopant atoms for silicon atoms one or two atomic layers away, the most favorable spacing of the OI layer from the metal-semiconductor interface is one or two atomic layers, allowing for trapping of high concentrations of dopants up to and directly adjacent to the metal-semiconductor interface. However, other spacings, such as three or four atomic layers, can also provide benefits. Additionally, it can be beneficial to include additional oxygen insertion layers in addition to this first oxygen insertion layer.

[0081] exist Fig.15 An example of such an approach is shown in the diagram 500 of , where: Si = silicon atom, M = metal atom (e.g. titanium), O = oxygen atom, and D = dopant atom (e.g. boron). The oxygen atoms plotted are part of an oxygen insertion layer, where the oxygen is bonded to an adjacent silicon atom. While oxygen atoms are necessarily present in the OI layer, nitrogen atoms, which are not shown in the diagram, may additionally be present. The presence of nitrogen may be beneficial, for example, for trapping of dopants or thermal stability of the OI layer.

[0082] Similarly, the dopants shown replace silicon atoms in the crystal lattice, rather than occupying "interstitial" positions or in dopant clusters (so that they will not contribute to free carriers in the semiconductor). However, although alternative dopants are shown in the figure, high concentrations of dopants trapped near the metal-semiconductor interface can reduce the Schottky barrier in the case of alternating atomic configurations. The positions of the dopants in the figure are schematic representations for illustrative purposes. The actual distribution of dopant atoms will be partially random, affected by the specific atomic configuration of the oxygen atoms and the local bonding of the atoms. The illustrated configuration represents the distance of the atoms from the metal-semiconductor interface, rather than the specific location of the atoms within the layer. The illustrated configuration is as follows:

[0083] (a) The OI layer contacts the metal, trapping the dopants beneath the OI layer.

[0084] (b) An OI layer separated from the metal by a single layer of silicon atoms, trapping dopants above and below the OI layer;

[0085] (c) An OI layer separated from the metal by two atomic layers, trapping dopants above and below the OI layer;

[0086] (d) An OI layer separated from the metal by three atomic layers, trapping dopants above and below the OI layer, but not reaching the metal interface itself in this example;

[0087] (e) An OI layer separated from the metal by four atomic layers, trapping dopants above and below the OI layer, but not reaching the metal interface itself in this example.

[0088] In addition to these configurations, additional configurations with multiple OI layers are also possible, such as a layer separated from the metal-semiconductor interface by two silicon layers, and an additional layer separated by an additional four atomic layers. These multiple layers can provide dopant capture at the metal-semiconductor interface and also below the metal-semiconductor interface, the former contributing to chemical Schottky barrier reduction and higher electric field, the latter mainly contributing to higher electric field. The embodiments listed herein are generally defined by the presence of a layer adjacent to the metal-semiconductor interface together with a high concentration of dopants, but do not exclude additional layers or dopant atoms that are not adjacent to one (or more) OI layers. The specific advantage of additional OI layers is that these additional layers can improve structural stability, such as blocking the loss of oxygen from the layer closest to the metal-semiconductor interface, or capturing point defects that would otherwise cause the loss of dopant atoms from the region adjacent to the metal-semiconductor interface.

[0089] Reference now Figure 5The superlattice structure described above can be advantageously used in semiconductor devices to provide reduced source / drain contact resistance by applying the principles described above. In typical semiconductor processing, the reduction of the metal-semiconductor contact area requires a lower contact resistivity (e.g., p c <1E-8ohm.cm 2 ). The contact resistivity is determined by two parameters, which are:

[0090] N D : the active dopant concentration at the metal / semiconductor interface; and

[0091] ΦF Bo : Schottky barrier height at the metal / semiconductor interface.

[0092] Furthermore, the metal-semiconductor Schottky barrier height is "pinned" for different metals. Furthermore, depending on the thickness, band gap and dielectric constant, the interfacial insulator can "depin" the Fermi level.

[0093] exist Figure 5 In the semiconductor device 100 (FET) shown in FIG. 1 , a dopant diffusion barrier superlattice 125 (eg, Figure 1-4C 1) are used to advantageously increase the surface dopant concentration thereby allowing for higher N in-situ doping during epitaxial processing by preventing diffusion into the channel region 130 of the device. D More particularly, device 100 illustratively includes a semiconductor layer or substrate 101, and spaced-apart source and drain regions 102, 103 formed in the semiconductor layer with a channel region 130 extending therebetween. Dopant diffusion barrier superlattice 125 illustratively extends through source region 102 to separate the source region into a lower source region 104 and an upper source region 105, and also extends through drain region 103 to separate the drain region into a lower drain region 106 and an upper drain region 107.

[0094] The dopant diffusion blocking superlattice 125 may also be conceptually considered as a source dopant blocking superlattice within the source region 102, a drain dopant blocking superlattice within the drain region 103, and a bulk dopant blocking superlattice below the channel 130, although in this configuration all three are provided by a single blanket deposition of the MST material as a continuous film across the substrate 101. The semiconductor material above the dopant blocking superlattice 125 in which the upper source / drain regions 105, 107 and the channel region 130 are defined may be epitaxially grown as a thick superlattice cap or bulk semiconductor layer on the dopant blocking superlattice 125, as discussed further above. In the illustrated example, the upper source / drain regions 105, 107 may each be flush with the upper surface of this semiconductor layer (i.e., they are implanted into this layer).

[0095] As such, the upper source / drain regions 105, 107 may advantageously have the same conductivity as the lower source / drain regions 104, 106, yet have a higher dopant concentration. In the illustrated example, the upper source / drain regions 105, 107 and the lower source / drain regions 104, 106 are N-type for an N-channel device, but these regions may also be P-type for a P-channel device (this also applies to other configurations described herein). Surface dopants may be introduced by, for example, ion implantation. However, dopant diffusion is reduced by the MST film material of the diffusion barrier superlattice 125 because it captures point defects / gaps caused by ion implantation that mediate dopant diffusion.

[0096] The semiconductor device 100 also illustratively includes a gate 108 on the channel region 130. The gate illustratively includes a gate insulating layer 109 and a gate electrode 110. Sidewall spacers 111 are also provided in the illustrated example.

[0097] Reference now Figure 6 According to another example embodiment, a semiconductor device 200 (FET) illustratively includes a semiconductor layer or substrate 201, and spaced-apart source and drain regions 202, 203 with a channel region 230 extending therebetween. In the illustrated embodiment, a source diffusion barrier superlattice 225s illustratively extends through the source region 202 to divide the source region into a lower source region 204 and an upper source region 205. Similarly, a drain diffusion barrier superlattice 225d extends through the drain region 203 to divide the drain region into a lower drain region 206 and an upper drain region 207. Alternatively, consider that the upper source and drain regions 205, 207 are each elevated above the upper surface of the semiconductor layer 201, and there is no such Figure 5The gate 208 illustratively includes a gate insulator 209 and a gate electrode 210, and gate sidewall spacers 211 may also be provided.

[0098] In this embodiment, surface dopants in the upper source / drain regions 205, 207 may be introduced by selectively growing an MST film followed by in-situ doped epi film formation. Here again, the MST material of the source / drain dopant diffusion barrier superlattice 225s, 225b advantageously helps prevent dopant diffusion into the channel region 230 and thus allows for higher surface dopant concentrations as noted above.

[0099] Now follow the reference Figures 7A-7C Another example embodiment described herein may be Figure 5 The semiconductor device 100 shown in FIG. 1 is subjected to further processing steps to perform Schottky barrier height modulation by controlling the thickness and composition of the interface insulator. Using conventional metal contacts, excessively thick source / drain insulators result in high contact resistivity due to high tunneling resistance. However, the superlattice 125' advantageously provides the desired non-semiconductor (e.g., oxygen) dose control for Fermi level depinning and tunneling resistance. After forming the gate 108' on the channel region 130', co-implantation of N, C, or F can further modulate the insulator composition to a lower dielectric constant (e.g., using C and F for low-k ILD films to modulate the SiO2 composition), such as Fig. 7A The MST film of the superlattice 125' effectively accumulates these elements into the surface region. It should be noted that in some embodiments, N and C can be introduced into the silicon surface by gaseous form (eg, N2 annealing or CO, CH4 annealing) instead of co-implantation.

[0100] Heat treatment and metal deposition can then be performed ( Figure 7B-7C ). The heat treatment causes non-semiconductor atoms (oxygen in this example) from the non-semiconductor monolayer of the dopant diffusion barrier superlattice 125' to move upward, and the non-semiconductor atoms react with the metal to form respective source and drain contact insulating interfaces 140', 141' between the upper source and drain regions and adjacent portions of the metal layers 142', 143' formed by metal deposition. In other words, because the oxygen atoms separate from the superlattice 125' in the source and drain regions and move upward to form the contact insulating interfaces 140', 141', there is no longer a defined superlattice layer separating the lower / upper source regions 104', 105' and the lower / upper drain regions 106', 107' (see Figure 7B ).

[0101] According to an exemplary embodiment, the Co / Co reaction may be performed at a temperature in the range of about +200 to 400°C. 0.75 Ti 0.25 (2nm) metal deposition for about 10 minutes forms source and drain contact insulating interfaces 140', 141' and metal layers 142', 143'. In addition, in some embodiments, additional metal deposition (eg, Co) may be performed to form upper source / drain metal contact layers 144', 145' in semiconductor device 100'.

[0102] Reference now Figure 8 Another example embodiment similar to the semiconductor device 200 is described. In this illustrated example, the source and drain dopant diffusion barrier superlattice 225s', 225d' advantageously provides Schottky barrier height modulation via heteroepitaxial film integration. More particularly, the lower source and drain regions 204', 206' include a different material than the upper source and drain regions 205', 207'. In this example, the lower source and drain regions 204', 206' are silicon and the upper source and drain regions 205', 207' are SiGeC, but different materials may be used in different embodiments.

[0103] Since MST materials effectively integrate heteroepitaxial semiconductor materials, C (1-2%) introduced into Si or SiGe on Si can cause a positive conduction band deviation. More specifically, this is a SiGeC / MST / n+Si structure that is effective for reducing the Schottky barrier height.

[0104] Additional references Fig. 9 , another similar semiconductor device 200" advantageously provides Schottky barrier height modulation via heteroepitaxial film integration. In the illustrated example, the semiconductor layer / substrate 201" is silicon germanium, and the lower source / drain regions 204", 206" are P+SiGe. However, the upper source / drain regions 205", 207" are also silicon, and respective platinum contact layers 242", 243" are formed on each upper source / drain region. The upper source / drain regions 205", 207" can be formed of a relatively thin epitaxial silicon layer (e.g., 2-5 nm). Here again, the MST material effectively integrates the heteroepitaxial semiconductor material, and the strained Si on the SiGe (or Ge) can advantageously induce a negative valence band deviation. As a result, the illustrated s-Si / MST / p+SiGe structure can also effectively reduce the Schottky barrier height.

[0105] Now turn to Fig.10, some of the planar FET configurations described above may also be advantageously implemented in vertical semiconductor devices. Example FINFET 300 illustratively includes a semiconductor layer or substrate 301 (e.g., silicon), an insulating layer 350 (e.g., SiO2) on the substrate, and one or more semiconductor fins 351 extending vertically upward from the substrate through the insulating layer.

[0106] Spaced-apart source and drain regions 302, 303 with a channel region 330 extending therebetween are formed in each semiconductor fin 351. A source dopant diffusion barrier superlattice 325s extends through the source region 302 to divide the source region into a lower source region 304 and an upper source region 305, and a drain dopant diffusion barrier superlattice 325d extends through the drain region 303 to divide the drain region into a lower drain region 306 and an upper drain region 307. Figure 6 , the upper source / drain regions 305, 307 have the same conductivity as the lower source / drain regions 304, 306 (N+) and a higher dopant concentration (N++). In addition, the upper source / drain regions 305, 307 extend above the upper surface of the semiconductor fin 351. That is, the superlattice 325s, 325d can be formed on top of the semiconductor fin 351, and the upper source / drain regions 305, 307 can be epitaxially grown on the respective superlattices. In this regard, the upper source / drain regions 305, 307 can be implanted with dopants, or they can be epitaxial layers doped in situ as described above.

[0107] FINFET 300 also illustratively includes a gate 308 covering the channel region 330 of fin 351. Gate 308 illustratively includes a gate insulator 309 and a gate electrode 310 on the gate insulator.

[0108] According to another example embodiment, the FINFET 300' may be used as described above with reference to Figures 7A-7C 305 ′, 307 ′ and metal layers 342 ′, 343 ′ (eg, CoTi 306 ′) are respectively formed on the upper source / drain regions 305 ′, 307 ′ and the metal layers 342 ′, 343 ′. x) between the source / drain insulating layer 340', 341'. In some embodiments, an upper metal layer 344', 345' (e.g., Co) may also be formed on the lower metal layer 342', 343'. Here again, the thermal treatment causes the source / drain dopant to block the upward movement of non-semiconductor atoms in the superlattice layer, resulting in no superlattice left between the upper source / drain region 305', 307' and the lower source / drain region 304', 306' in the final FINFET 300'. Here again, this approach advantageously provides Schottky barrier height modulation by controlling the thickness and composition of the interface insulator 340', 341'.

[0109] Additional references Fig.13 , provide the above Figure 8 300'' is a FINFET similar to an embodiment of the present invention, wherein the source and drain dopant blocking superlattices 325s'', 325d'' advantageously provide Schottky barrier height modulation via heteroepitaxial film integration. More particularly, the lower source and drain regions 304'', 306'' include a different material than the upper source and drain regions 305'', 307''. In this example, the lower source and drain regions 304'', 306'' are silicon and the upper source and drain regions 305'', 307'' are SiGeC, but different materials may be used in different embodiments. Likewise, in the illustrated example the lower metal layer 342'', 342'' is titanium and the upper metal layer 344'', 345'' is cobalt.

[0110] exist Fig.14 In another example shown in Fig. 9 Similar to the embodiments of the present invention, FINFET 300'' can also provide Schottky barrier height modulation via heteroepitaxial film integration. In the illustrated example, the semiconductor fin 351' is silicon germanium, and the lower source / drain regions 304", 306" are P+SiGe. However, the upper source / drain regions 305", 307" are silicon, and a respective platinum contact layer 342", 343" is formed on each upper source / drain region. Here again, the upper source / drain regions 305", 307" can be formed of a relatively thin epitaxial silicon layer (e.g., 2-5nm).

[0111] In the examples described above, dopant blocking superlattices are shown in both the source and drain regions of the illustrated device. However, it should be noted that in some embodiments both the source and drain regions do not necessarily need to have dopant blocking superlattices. That is, in some embodiments the dopant blocking superlattice may be in only one of the source or drain regions.

[0112] In addition, now turn to Fig.16In some embodiments, in addition to or instead of in the source / drain regions, a dopant blocking superlattice may be introduced into the body contact to provide reduced body contact resistance. In the illustrated example, a semiconductor device 400 (here a planar FET) includes a semiconductor layer or substrate 401, spaced-apart source and drain regions 402, 403 in the semiconductor layer 401 (which in this example have respective lightly doped source / drain extensions 404, 405) with a channel region 430 extending therebetween, and a gate 408 with sidewall spacers 411 on the channel region. The gate 408 illustratively includes a gate insulator 409 and a gate electrode 410, as similarly described above. The semiconductor device 400 also illustratively includes a body contact 420 in the semiconductor layer 401, and the body contact 420 includes a body contact dopant diffusion blocking superlattice 425 extending through the body contact to divide the body contact into a first body contact region 421 and a second body contact region 422. As similarly described above, the second body contact region 422 has the same conductivity and a higher dopant concentration as the first body contact region 421. Here again, the body contact dopant diffusion barrier superlattice 425 can be similar to those superlattice structures described above, and the materials used for the first and second body contact regions 421, 422 and the dopant concentrations within the first and second body contact regions 421, 422 can also be similar to those described above to provide the desired contact resistance reduction.

[0113] exist Fig.17 In another example device 400' shown in FIG. 1 , a similar configuration is provided with a backside body contact 420' instead of Fig.16 The top or front side body contact portion 420 is shown in FIG. The remaining components are similar to those of reference Fig.16 Those discussed and therefore require no further discussion herein.It should be noted that in the backside embodiment the first and second regions 421 ', 422' are flipped vertically relative to the first and second regions 421 , 422 in the device 400 as they are on opposite sides of the device 400'.

[0114] Now turn to Fig.18, another example contact structure 500 is now described, which may also be used in some embodiments of source / drain, body or other contacts to provide reduced Schottky barrier height and thereby provide reduced contact resistance. The contact 500 is formed in the semiconductor layer 501. The contact illustratively includes one or more oxygen monolayers 550 constrained within the crystal lattice of adjacent semiconductor portions 546a, 546b of the semiconductor layer 501. The one (or more) oxygen monolayers 550 are spaced apart from the surface of the semiconductor layer 501 by one to four monolayers (a spacing of four monolayers is shown in the semiconductor portion 546b in the illustrated example). In addition, a metal layer 531 (which may include the same metal discussed above) is formed on the surface of the semiconductor layer 501 above the one (or more) oxygen monolayers 550. The contact 500 may be formed on the semiconductor layer or substrate 521.

[0115] By way of example, the dopant concentration in portion 546b (i.e., between one (or more) oxygen monolayers 550 and metal layer 531) may be 1×10 21 atoms / cm 3 or greater (although lower concentrations may also be used in different embodiments). Alternatively, consider that in the example configuration the dopant atoms may advantageously occupy a dopant concentration equivalent to approximately 2% of the crystalline sites in the silicon lattice. This is based on an estimate of the maximum distance range over which the oxygen monolayer can directly capture the dopant (e.g., boron) close enough to the metal to directly reduce the Schottky barrier of the contact, rather than reducing diffusion, while otherwise maintaining a conventional doped metal-semiconductor interface in the case of a bulk-line environment for the dopant atoms, and a minimum concentration of dopant where a benefit will be realized.

[0116] Many modifications and other embodiments of the present invention will occur to those skilled in the art having benefit of the foregoing description and the teachings presented in the related drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. Semiconductor devices, including: Semiconductor layer; spaced-apart source and drain regions in the semiconductor layer and a channel region extending therebetween; at least one dopant diffusion barrier superlattice that separates at least one of the source and drain regions into a lower region and an upper region, wherein the upper region has the same conductivity as the lower region and a higher dopant concentration than the lower region; The at least one dopant diffusion barrier superlattice comprises a plurality of stacked layer groups, each layer group comprising a plurality of stacked base silicon monolayers defining base silicon portions, and at least one oxygen monolayer confined within the crystal lattice of adjacent base silicon portions; and A gate is located on the channel region. 2 . The semiconductor device of claim 1 , wherein the at least one dopant diffusion barrier superlattice comprises a respective dopant diffusion barrier superlattice for each of the source and drain regions.

3. The semiconductor device according to claim 1 further comprises a body dopant diffusion barrier superlattice extending in the semiconductor layer between the source and drain regions and comprising respective multiple stacked layer groups, each layer group comprising multiple stacked base silicon monolayers defining base silicon portions, and at least one oxygen monolayer constrained within the crystal lattice of adjacent base silicon portions. The semiconductor device according to claim 1 , wherein the upper region is flush with an upper surface of the semiconductor layer. The semiconductor device according to claim 1 , wherein the upper region is elevated above an upper surface of the semiconductor layer. The semiconductor device according to claim 1 , wherein the lower region comprises a different material from the upper region. 7 . The semiconductor device of claim 6 , wherein the lower region comprises silicon and the upper region comprises silicon germanium. 8 . The semiconductor device of claim 6 , wherein the lower region comprises silicon germanium and the upper region comprises silicon. 9 . The semiconductor device according to claim 1 , further comprising a metal contact on the upper region.

10. The semiconductor device according to claim 9, wherein the metal contact comprises at least one of titanium, cobalt, nickel and platinum.

11. A method for manufacturing a semiconductor device, comprising: forming spaced-apart source and drain regions with a channel region extending therebetween in the semiconductor layer, dividing at least one of the source and drain regions into a lower region and an upper region by a dopant diffusion barrier superlattice, wherein the upper region has the same conductivity as the lower region and a higher dopant concentration than the lower region, the dopant diffusion barrier superlattice comprising a plurality of stacked layer groups, wherein each layer group comprises a plurality of stacked base silicon monolayers defining base silicon portions, and at least one oxygen monolayer confined within the crystal lattice of adjacent base silicon portions; and A gate is formed on the channel region.

12. The method of claim 11, wherein each of the source and drain regions is divided into a lower region and an upper region by a respective dopant diffusion barrier superlattice.

13. The method of claim 11 further comprising forming a bulk dopant diffusion barrier superlattice in the semiconductor layer extending between the source and drain regions and comprising respective multiple stacked layer groups, each layer group comprising multiple stacked base silicon monolayers defining base silicon portions, and at least one oxygen monolayer confined within the crystal lattice of adjacent base silicon portions. The method according to claim 11 , wherein the upper region is flush with an upper surface of the semiconductor layer. The method of claim 11 , wherein the upper region is elevated above an upper surface of the semiconductor layer.

16. The method of claim 11, wherein the lower region comprises a different material than the upper region.

17. The method of claim 16, wherein the lower region comprises silicon and the upper region comprises silicon germanium.

18. The method of claim 16, wherein the lower region comprises silicon germanium and the upper region comprises silicon.

19. The method of claim 11, further comprising forming a metal contact on the upper region.

20. The method of claim 19, wherein the metal contact comprises at least one of titanium, cobalt, nickel, and platinum.

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