A digitally assisted DC offset elimination circuit and digital control method thereof

Abstract

The present invention relates to the field of integrated circuits, and in particular to a digitally assisted direct current offset elimination circuit and a digital control method thereof. The direct current offset elimination circuit comprises a variable gain amplifier, a comparator with a rail-to-rail input voltage range, a digital control module and an 11-bit digital-to-analog converter. An electrical signal is input into the variable gain amplifier. The comparator with the rail-to-rail input voltage range samples a differential voltage output by the variable gain amplifier within a given time window, and records the polarity and corresponding times of the sampled differential voltage in the digital control module. The digital control module selects a direct current compensation mode and updates the differential voltage according to the recorded information, and uses the updated differential voltage as an input of the 11-bit digital-to-analog converter. The output end of the 11-bit digital-to-analog converter is connected to the input end of the variable gain amplifier. The present invention can effectively eliminate the direct current offset of a receiver.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a digitally assisted direct current offset elimination circuit and a digital control method thereof. Background Art

[0002] With the rapid development of wireless communication standards, for wireless transceiver chip systems, the zero intermediate frequency structure eliminates the need for off-chip filters compared to the superheterodyne structure, and the on-chip low-noise amplifier and mixer interface do not require 50 ohm matching, making it easier to optimize power consumption, noise and linearity. The receiver chip as a whole has the advantage of high integration, and is therefore more favored by modern wireless communication systems.

[0003] However, the design of zero-IF receiver chips also has some unique problems and challenges. Among them, the DC offset problem caused by local oscillator leakage, mixer self-mixing or baseband circuit mismatch can cause the baseband output of the receiver chip to saturate in the worst case, making it impossible to detect the signal normally.

[0004] In the past, some circuit technologies have been applied to the DC offset elimination of zero-IF receivers, including AC-coupled baseband circuits and adding low-pass filtering to the feedback servo loop. All these methods face the problems of large chip area required for the circuit and difficulty in compromising the signal high-pass bandwidth and the response speed of the DC offset elimination loop. Summary of the invention

[0005] In order to effectively eliminate the DC offset of a receiver while better avoiding the problems caused by a traditional DC offset elimination circuit, the present invention proposes a digitally assisted DC offset elimination circuit and a digital control method thereof. The digitally assisted DC offset elimination circuit includes a variable gain amplifier, a comparator with a rail-to-rail input voltage range, a digital control module and an 11-bit digital-to-analog converter. An electrical signal is input to the variable gain amplifier. The comparator with a rail-to-rail input voltage range samples the output differential voltage of the variable gain amplifier within a given time window, and records the polarity and corresponding number of the sampled differential voltage in the digital control module. The digital control module selects a DC compensation mode and updates the differential voltage according to the recorded information, and uses the updated differential voltage as the input of the 11-bit digital-to-analog converter. The output end of the 11-bit digital-to-analog converter is connected to the input end of the variable gain amplifier.

[0006] Furthermore, the DC offset voltage of the receiver is eliminated by controlling an 11-bit digital-to-analog converter through a DC offset elimination digital control module.

[0007] Furthermore, the 11-bit digital-to-analog converter adopts a segmented structure, including a 4-bit highest segment, a 4-bit second highest segment and a 3-bit lowest segment, and the highest segment and the second highest segment are implemented in a unit element array, wherein 16 unit current sources constitute the highest segment, and currents of 15 of the 16 unit current sources of the highest segment flow to the analog differential output terminal, and currents of the remaining one flow to the resistor arrays of the second highest segment and the lowest segment for further diversion; 15 unit resistor arrays constitute the second highest segment; and the lowest segment adopts a binary-weighted resistor array structure.

[0008] Furthermore, the digital control module includes a divider, a first compensator, a second compensator, a third compensator, a fourth compensator and four judges. The digital control module calculates the compensation coefficient through the divider according to the polarity and the corresponding number of occurrences of the differential voltage output by the variable gain amplifier in the time window by the rail-to-rail comparator. If the compensation coefficient is less than the conventional positive compensation threshold, if so, it is input into the first compensator for compensation; otherwise, continue to judge whether the compensation coefficient is less than the fast positive compensation threshold, if so, it is input into the second compensator for compensation; otherwise, continue to judge whether the compensation coefficient is greater than the fast negative compensation threshold, if so, it is input into the third compensator for compensation; otherwise, continue to judge whether the compensation coefficient is greater than the conventional negative compensation threshold, if so, it is input into the fourth compensator for compensation, otherwise no compensation is performed.

[0009] Furthermore, when the first compensator performs compensation, it determines whether the value of the state machine S is 0. If so, the value of the register is initialized, and the value of the state is increased by 1 to end the compensation. Otherwise, the value of the register is increased by 2. (10-S) , and then determine whether the updated value of the state machine is greater than 9. If so, the compensation ends. Otherwise, the value of the state machine is increased by 1 and the compensation ends.

[0010] When the second compensator performs compensation, the value of the register is increased by 1;

[0011] When the third compensator performs compensation, it determines whether the value of the state machine S is 0. If so, the register value is initialized and the value of the state machine S is increased by 1. Otherwise, the register value is increased by 2. (10-S) , and then determine whether the updated value of the state machine is greater than 9. If so, the compensation ends. Otherwise, the value of the state machine is increased by 1 and the compensation ends.

[0012] When the fourth compensator performs compensation, the value of the register is reduced by 1 and then the compensation is terminated.

[0013] Furthermore, the electrical signal is filtered by a low-pass filter before being input into the variable gain amplifier.

[0014] The present invention also provides a digital control method for a digitally assisted DC offset cancellation circuit, comprising any one of the above digitally assisted DC offset cancellation circuits, such as Figure 3 , specifically including the following steps:

[0015] S1, initialize the state machine and set S=0;

[0016] S2. If the ratio of the number of times the positive polarity of the differential voltage appears to the total number of counts is less than 1 / 8, determine whether S is equal to 0;

[0017] S3, if it is equal to 0, the register value is initialized to 1, and return to step S2;

[0018] S4, otherwise the register increases by 2 (10-S) , that is, S = S + 2 (10-S) , and determine whether the value of S is greater than 9, if so, return to step S1, otherwise set S = S + 1, and return to step S2;

[0019] S5. If the ratio of the number of times the differential voltage positive polarity occurs to the total number of counts is greater than 1 / 8 and less than 3 / 8, register S=S+1, and return to step S2;

[0020] S6. If the ratio of the number of times the differential voltage positive polarity occurs to the total number of counts is greater than 7 / 8, determine whether the register value S is 0;

[0021] S7, if it is equal to 0, the register value is initialized to 1, and return to step S2;

[0022] S8, otherwise the register increases by 2 (10-S) , that is, S = S + 2 (10-S) , and determine whether the value of S is greater than 9, if so, return to step S1, otherwise set S = S + 1, and return to step S2;

[0023] S9, if the ratio of the number of times the differential voltage positive polarity occurs to the total number of counts is greater than 5 / 8 and less than 7 / 8, set the register value S=S-1 and return to step S2;

[0024] S10. Otherwise, directly save the value of the register and return to step S1.

[0025] Compared with the prior art, the present invention effectively eliminates the DC offset of the receiver while better avoiding the problems brought about by the traditional DC offset elimination circuit, such as the large chip area required for the circuit and the difficulty in compromising the signal high-pass bandwidth and the response speed of the DC offset elimination loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a DC offset elimination circuit proposed by the present invention;

[0027] Figure 2 A schematic diagram of a digital-to-analog converter in a DC offset elimination circuit of the present invention;

[0028] Figure 3 This is the digital control flowchart of the DC offset cancellation circuit of the present invention. Detailed implementation manners

[0029] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0030] The present invention provides a digitally assisted DC offset cancellation circuit, which includes a variable gain amplifier, a comparator with a rail-to-rail input voltage range, a digital control module, and an 11-bit digital-to-analog converter. An electrical signal is input to the variable gain amplifier. The comparator with a rail-to-rail input voltage range samples the differential voltage output by the variable gain amplifier within a given time window, and records the polarity and the corresponding number of times of the sampled differential voltage in the digital control module. The digital control module selects a DC compensation method according to the recorded information and updates the differential voltage, and uses the updated differential voltage as the input of the 11-bit digital-to-analog converter. The output terminal of the 11-bit digital-to-analog converter is connected to the input terminal of the variable gain amplifier.

[0031] In this embodiment, the digital control module includes a divider, a first compensator, a second compensator, a third compensator, a fourth compensator, and four judges. The digital control module calculates a compensation coefficient through the divider according to the polarity and the corresponding number of occurrences of the differential voltage output by the variable gain amplifier within the time window by the rail-to-rail comparator. If the compensation coefficient is less than the conventional positive compensation threshold, it is input to the first compensator for compensation; otherwise, it continues to judge whether the compensation coefficient is less than the fast positive compensation threshold. If so, it is input to the second compensator for compensation; otherwise, it continues to judge whether the compensation coefficient is greater than the fast negative compensation threshold. If so, it is input to the third compensator for compensation; otherwise, it continues to judge whether the compensation coefficient is greater than the conventional negative compensation threshold. If so, it is input to the fourth compensator for compensation; otherwise, no compensation is performed.

[0032] When performing DC offset cancellation in this embodiment, an 11-bit counter is used to count according to the output of the rail-to-rail comparator within a preset time window, so as to obtain the polarity and the corresponding number of occurrences of the differential voltage output by the variable gain amplifier within this time window, and define (the number of occurrences of positive polarity / the total number of counting times) = MSR. The digital control module adopts four DC offset compensation methods according to the value of MSR, including:

[0033] 1.0 < MSR < the conventional positive compensation threshold, conventional positive compensation; preferably, the conventional positive compensation threshold is 1 / 8;

[0034] 2. Conventional positive compensation threshold < MSR < Fast positive compensation threshold: Fast positive compensation; Preferably, the conventional positive compensation threshold is 1 / 8;

[0035] 3. Fast positive compensation threshold < MSR < Conventional negative compensation threshold: Conventional negative compensation; Preferably, the conventional negative compensation threshold is 5 / 8;

[0036] 4. Fast negative compensation threshold < MSR < 1: Fast negative compensation; Preferably, the fast negative compensation threshold is 7 / 8.

[0037] The digital controller updates the value of the register accordingly according to the current compensation method, assigns the updated register value to the input of the digital-to-analog converter, waits for the outputs of the digital-to-analog converter and the variable gain amplifier to stabilize, and then counts the output of the comparator again within the same given time window, repeating the above operations to count the polarity and occurrence times of the output voltage of the variable gain amplifier.

[0038] The above digital control strategy can make the value of MSR quickly converge to the range from the conventional negative compensation threshold to the fast positive compensation threshold, and at the same time, the output DC offset voltage of the receiver also converges to an acceptable range. The boundary MSR values of different compensation methods can also be flexibly set through corresponding specific registers to achieve the best compromise between the convergence speed and accuracy.

[0039] To further illustrate the circuit of the present invention, as Figure 1 , in this embodiment, the RF input signal and the local oscillator signal are mixed and divided into two paths to be input to the low-pass filter for filtering. The output of the filter is connected to the input end of the variable gain amplifier and the output end of the digital-to-analog converter. The output end of the variable gain amplifier is used as the output end of the DC offset circuit of the present invention and is connected to the input end of the rail-to-rail input comparator. The output end of the rail-to-rail input comparator is connected to a digital control module, that is, the DC offset cancellation digital control module in the figure. The output end of the digital control module is used as the input end of the digital-to-analog converter.

[0040] As Figure 2, the DC offset voltage can be eliminated by controlling an 11-bit D / A converter through the DC offset elimination digital control module. D<10:0> is the 11-bit digital input of the D / A converter, and Voutp and Voutn are the analog differential outputs of the D / A converter. The D / A converter adopts a segmented structure, which is divided into three segments: the highest segment with 4 bits, the second highest segment with 4 bits, and the lowest segment with 3 bits. The highest segment and the second highest segment are implemented in a unit cell array. 16 unit current sources form the highest segment, which is controlled by the digital bit A<15:0>. 15 unit resistor arrays form the second highest segment, which is controlled by the digital bit B<14:0>. A<15:0> and B<14:0> are generated by the digital inputs D<10:7> and D<6:3> of the D / A converter respectively, and are decoded by the thermometer decoder 1 and thermometer decoder 2 inside the D / A converter. Under the control of A<15:0>, the current of 15 of the 16 unit current sources in the highest segment flows to the analog differential output terminal Voutp or Voutn, and the current of the remaining one flows to the resistor array of the second highest segment and the lowest segment for further diversion. The lowest segment adopts a binary weighted resistor array structure, which is directly controlled by the lowest three bits D<2:0> of the digital input of the digital-to-analog converter.

[0041] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A digitally assisted DC offset cancellation circuit, characterized in that: It includes a variable gain amplifier, a comparator with a rail-to-rail input voltage range, a digital control module and an 11-bit digital-to-analog converter. An electrical signal is input into the variable gain amplifier. The comparator with a rail-to-rail input voltage range samples the output differential voltage of the variable gain amplifier within a given time window, and records the polarity and corresponding times of the sampled differential voltage in the digital control module. The digital control module selects a DC compensation mode and updates the differential voltage according to the recorded information, and uses the updated differential voltage as the input of the 11-bit digital-to-analog converter. The output end of the 11-bit digital-to-analog converter is connected to the input end of the variable gain amplifier. The digital control module includes a divider, a first compensator, a second compensator, a third compensator, a fourth compensator and four judges. The digital control module calculates the compensation coefficient through the divider according to the polarity and the corresponding number of occurrences of the differential voltage output by the variable gain amplifier in the time window by the rail-to-rail comparator. If the compensation coefficient is less than the conventional positive compensation threshold, if so, it is input into the first compensator for compensation; otherwise, it continues to judge whether the compensation coefficient is less than the fast positive compensation threshold, if so, it is input into the second compensator for compensation; otherwise, it continues to judge whether the compensation coefficient is greater than the fast negative compensation threshold, if so, it is input into the third compensator for compensation; otherwise, it continues to judge whether the compensation coefficient is greater than the conventional negative compensation threshold, if so, it is input into the fourth compensator for compensation, otherwise no compensation is performed.

2. A digitally assisted DC offset cancellation circuit according to claim 1, characterized in that: The DC offset voltage of the receiver is eliminated by controlling an 11-bit digital-to-analog converter through the DC offset elimination digital control module.

3. A digitally assisted DC offset cancellation circuit according to claim 2, characterized in that: The 11-bit digital-to-analog converter adopts a segmented structure, including a 4-bit highest segment, a 4-bit second highest segment and a 3-bit lowest segment. The highest segment and the second highest segment are implemented in a unit element array, where 16 unit current sources constitute the highest segment, and 15 of the 16 unit current sources in the highest segment flow currents to the analog differential output terminal, and the current of the remaining one flows to the resistor array of the second highest segment and the lowest segment for further diversion; 15 unit resistor arrays constitute the second highest segment; the lowest segment adopts a binary-weighted resistor array structure.

4. The digitally assisted DC offset cancellation circuit according to claim 1, characterized in that: When the first compensator performs compensation, it determines whether the value of the state machine S is 0. If so, the register value is initialized, and the state value is increased by 1 to end the compensation. Otherwise, the register value is increased by 2. (10-S) , and then determine whether the updated value of the state machine is greater than 9. If so, the compensation ends. Otherwise, the value of the state machine is increased by 1 and the compensation ends. When the second compensator performs compensation, the value of the register is increased by 1; When the third compensator performs compensation, it determines whether the value of the state machine S is 0. If so, the register value is initialized and the value of the state machine S is increased by 1. Otherwise, the register value is increased by 2. (10-S) , and then determine whether the updated value of the state machine is greater than 9. If so, the compensation ends. Otherwise, the value of the state machine is increased by 1 and the compensation ends. When the fourth compensator performs compensation, the value of the register is reduced by 1 and then the compensation is terminated.

5. The digitally assisted DC offset cancellation circuit according to claim 1, characterized in that: The electrical signal is filtered through a low-pass filter before being input into the variable gain amplifier.

6. A digital control method for a digitally assisted DC offset cancellation circuit, characterized in that: A digitally assisted DC offset cancellation circuit comprising any one of claims 1 to 5, wherein a digital control method thereof comprises the following steps: S1, initialize the state machine and set S=0; S2. If the ratio of the number of times the positive polarity of the differential voltage appears to the total number of counts is less than 1 / 8, determine whether S is equal to 0; S3, if it is equal to 0, the register value is initialized to 1, and return to step S2; S4, otherwise the register increases by 2 (10-S) , that is, S = S + 2 (10-S) , and determine whether the value of S is greater than 9, if so, return to step S1, otherwise set S = S + 1, and return to step S2; S5. If the ratio of the number of times the differential voltage positive polarity occurs to the total number of counts is greater than 1 / 8 and less than 3 / 8, register S=S+1, and return to step S2; S6. If the ratio of the number of times the differential voltage positive polarity occurs to the total number of counts is greater than 7 / 8, determine whether the register value S is 0; S7, if it is equal to 0, the register value is initialized to 1, and return to step S2; S8, otherwise the register increases by 2 (10-S) , that is, S = S + 2 (10-S) , and determine whether the value of S is greater than 9, if so, return to step S1, otherwise set S = S + 1, and return to step S2; S9, if the ratio of the number of times the differential voltage positive polarity occurs to the total number of counts is greater than 5 / 8 and less than 7 / 8, set the register value S=S-1 and return to step S2; S10. Otherwise, directly save the value of the register and return to step S1.

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