Neural network circuits and neural network systems

Abstract

This application provides a neural network circuit, including: a first sample-and-hold circuit that generates a first analog voltage based on a first output current output by a first neural network array; a reference voltage generation circuit that generates a reference voltage based on a first control signal, wherein the first control signal is determined according to a first calculation precision; a first comparison circuit connected to the first sample-and-hold circuit and the reference voltage generation circuit respectively, and outputting a first level signal based on the first analog voltage and the reference voltage; and a first output circuit that samples the first level signal based on a second control signal and outputs a first calculation result that meets the first calculation precision, wherein the second control signal is used to control the sampling frequency of the first level signal. The sampling frequency of the first output circuit and the duration of the first level signal can be adjusted to meet the precision requirements of the neural network, thereby avoiding problems such as low precision failing to meet the calculation precision or high precision leading to power consumption waste.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence, specifically to a neural network circuit and a neural network system. Background Technology

[0002] Neural networks are tools for realizing artificial intelligence, characterized by high computational demands and memory-intensive processing of input data. One method to improve the processing efficiency of neural networks is to deploy them using an in-memory computing architecture. This method leverages the characteristic that weights remain constant during computation, pre-writing the weights into the computing storage medium and simultaneously performing weight storage and computation, thereby reducing the time and energy consumption associated with data exchange and computation.

[0003] In in-memory computing architectures, the neural network computing array is the core module of the neural network circuit. A neural network computing array, also called a computing array, is typically a multiply-accumulate computing array constructed from non-volatile storage media, containing several rows and columns. Rows can also be called word lines, and columns can be called bit lines. The intersections of rows and columns are the computing storage units of the computing array, simply called cells. During neural network computation, weights are pre-stored in the cells in the form of electrical conductance. Input data is processed by a digital-to-analog converter (DAC) and enters the computing array in the form of voltage. Subsequently, the voltage passes through the corresponding conductance to form currents that converge in the same column. The sum of these currents can be used to represent the accumulated result of the product of the input data and the weights. The currents also need to be processed by an analog-to-digital converter (ADC) to be converted back into digital signals.

[0004] Since the accuracy of DACs and ADCs is fixed, they cannot adapt to changes in the computational accuracy of neural networks. Therefore, existing neural network circuits may have problems such as low accuracy failing to meet computational requirements or high accuracy leading to wasted power consumption. Summary of the Invention

[0005] This application provides a neural network circuit and a neural network system, which can adjust the output precision of the neural network circuit according to the computational precision of the neural network, so that the output precision of the neural network circuit adapts to the changes in the computational precision of the neural network.

[0006] In a first aspect, a neural network circuit is provided, comprising: a first neural network computing array, including a first set of computing units, the first set of computing units being used to perform neural network calculations on a first portion of input data according to weights to obtain a first output current; a first sample-and-hold circuit connected to the first set of computing units, used to generate a first analog voltage according to the first output current; a reference voltage generation circuit, used to generate a reference voltage according to a first control signal, the first control signal being determined according to a first calculation precision, wherein the first control signal changes with the change of the first calculation precision; a first comparison circuit, respectively connected to the first sample-and-hold circuit and the reference voltage generation circuit, used to output a first level signal according to the first analog voltage and the reference voltage; and a first output circuit, used to sample the first level signal according to a second control signal and output a first calculation result, wherein the first calculation result is a calculation result that satisfies the first calculation precision, and the second control signal is used to control the frequency at which the first output circuit samples the first level signal.

[0007] When the value of the first output current changes, the accuracy of the first calculation also changes. For example, the larger the first output current, the greater the accuracy requirement of the neural network. The neural network circuit can improve the accuracy of the first calculation result by increasing the sampling frequency of the first output circuit and increasing the duration of the first level signal, so as to meet the accuracy requirements of the neural network and avoid problems such as low accuracy failing to meet the calculation accuracy or high accuracy leading to wasted power consumption.

[0008] Optionally, the neural network circuit further includes a parameter adjustment circuit for generating the first control signal and the second control signal based on the first calculation accuracy.

[0009] Optionally, when the first analog voltage is higher than the reference voltage, the first level signal is a high level signal; when the first analog voltage is lower than the reference voltage, the first level signal is a low level signal.

[0010] Optionally, the first neural network computing array further includes a second set of computing units, which are used to perform neural network calculations on the second part of the data according to weights to obtain a second output current; the neural network circuit further includes: a second sample-and-hold circuit connected to the second set of computing units, used to generate a second analog voltage according to the second output current; a second comparison circuit connected to the second sample-and-hold circuit and the reference voltage generation circuit respectively, used to output a second level signal according to the second analog voltage and the reference voltage; and a second output circuit used to sample the second level signal according to the second control signal and output a second calculation result, wherein the second calculation result is a calculation result that meets the first calculation accuracy, and the second control signal is used to control the frequency at which the second output circuit samples the second level signal.

[0011] Multiple computing units can share a single parameter adjustment circuit and a reference voltage generation circuit, thereby saving components and power consumption.

[0012] Optionally, the neural network circuit further includes a second neural network computing array, the first output circuit being connected to the input terminal of the second neural network computing array, the second neural network computing array being used to perform calculations on the data input to the second neural network computing array based on weights, wherein the data input to the second neural network computing array includes the first calculation result, and the first calculation result is a pulse signal.

[0013] When the first calculation result is a pulse signal, the first calculation result can be used by other calculation arrays without conversion processing, without the need for registers and shift accumulators, thus saving the devices and power consumption required for conversion processing.

[0014] Optionally, the reference voltage is a ramp voltage.

[0015] Optionally, the starting voltage of the reference voltage is controlled by the first control signal.

[0016] When the starting voltage of the ramp voltage is the same as the starting voltage of the first analog voltage, the first level signal (COMP_OUT) output by the first comparator circuit maintains a ReLU function relationship with the input current (Current_IN) of the first sample-and-hold circuit, so that the first comparator circuit has the function of the ReLU function. Therefore, this embodiment can realize the function of the ReLU function without additional components.

[0017] Optionally, the parameter adjustment circuit is further configured to: generate a third control signal based on the first calculation accuracy, the third control signal being used to control the reference current of the operational amplifier OPA in the first sample-and-hold circuit, so as to control the accuracy of the first analog voltage and the power consumption of the first sample-and-hold circuit.

[0018] The OPA operates under the control signal generated by the parameter adjustment circuit. This control signal controls the OPA's reference current, reducing power consumption while meeting the accuracy requirements of the output voltage of the first sample-and-hold circuit.

[0019] Optionally, the parameter adjustment circuit is further configured to: control the start sampling time of the first output circuit.

[0020] When the initial sampling time of the first output circuit is not offset, the output result of the first output circuit and the output current of the first sample-and-hold circuit exhibit a normal ReLU function relationship; when the initial sampling time of the first output circuit is offset, the output result of the first output circuit and the output current of the first sample-and-hold circuit exhibit a biased ReLU function relationship; therefore, this embodiment can achieve the function of a normal ReLU function or a biased ReLU function without additional components.

[0021] In a second aspect, a neural network system is provided, comprising: a neural network circuit as described in any implementation of the first aspect; a memory for storing input data; and a processor for reading the input data from the memory and inputting the input data into the neural network circuit, so that the neural network circuit performs neural network calculations on the input data.

[0022] When the value of the first output current changes, the first calculation accuracy also changes. For example, the larger the first output current, the greater the accuracy requirement of the neural network. The neural network circuit can improve the accuracy of the first calculation result by increasing the sampling frequency of the first output circuit and increasing the duration of the first level signal, so as to meet the accuracy requirements of the neural network. Therefore, the neural network system containing this neural network circuit can avoid problems such as low accuracy failing to meet the calculation accuracy or high accuracy leading to power consumption waste.

[0023] Optionally, the memory is also used to store a computer program. The processor is further used to retrieve the computer program from the memory to program the neural network computation array in the neural network circuit, the programming being used to configure the weights of the neural network. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a neural network system provided in this application;

[0025] Figure 2 This is a schematic diagram of a portion of a neural network layer in a neural network provided in this application;

[0026] Figure 3 This is a schematic diagram of the structure of a neural network circuit provided in this application;

[0027] Figure 4 This is a schematic diagram of the structure of a computing array provided in this application;

[0028] Figure 5 This is a schematic diagram of the operating timing of a neural network circuit provided in this application;

[0029] Figure 6 This is a schematic diagram of another neural network circuit provided in this application;

[0030] Figure 7 This is a schematic diagram of a method for generating a level signal provided in this application;

[0031] Figure 8 This is a schematic diagram of another method for generating a level signal provided in this application;

[0032] Figure 9 This is a schematic diagram of another method for generating a level signal provided in this application;

[0033] Figure 10 This is a schematic diagram of the output result of a comparator circuit provided in this application;

[0034] Figure 11 This is a schematic diagram of the output result of an output circuit provided in this application;

[0035] Figure 12 This is a schematic diagram of a neural network circuit containing multiple sets of computing units provided in this application;

[0036] Figure 13 This is a schematic diagram of a neural network circuit suitable for multilayer neural networks provided in this application;

[0037] Figure 14 This is a schematic diagram of the operating timing of another neural network circuit provided in this application. Detailed Implementation

[0038] To facilitate understanding of the technical solution of this application, the concepts involved in this application will be briefly introduced first.

[0039] Artificial neural networks (ANNs), also known simply as neural networks (NNs) or neural network-like systems, are mathematical or computational models in machine learning and cognitive science that mimic the structure and function of biological neural networks (the central nervous system of animals, especially the brain) to estimate or approximate functions. Artificial neural networks can include convolutional neural networks (CNNs), deep neural networks (DNNs), multilayer perceptrons (MLPs), and other types of neural networks. Figure 1 This is a schematic diagram of the structure of a neural network system provided in an embodiment of the present invention. Figure 1 As shown, the neural network system 100 may include a host 105 and a neural network circuit 110. The neural network circuit 110 is connected to the host 105 via a host interface. The host interface may include a standard host interface and a network interface. For example, the host interface may include a peripheral component interconnect express (PCIe) interface. Figure 1 As shown, the neural network circuit 110 can be connected to the host 105 via the PCIe bus 106. Therefore, data can be input to the neural network circuit 110 via the PCIe bus 106, and processed data can be received from the neural network circuit 110 via the PCIe bus 106. Furthermore, the host 105 can monitor the operating status of the neural network circuit 110 via the host interface.

[0040] The host 105 may include a processor 1052 and memory 1054. It should be noted that, in addition to... Figure 1 In addition to the devices shown, the host 105 may also include a communication interface and other devices such as a disk as external storage, without limitation.

[0041] Processor 1052 is the core of the host 105's processing and control unit. Processor 1052 may include multiple processor cores. Processor 1052 can be a very large-scale integrated circuit. An operating system and other software programs are installed on processor 1052, enabling it to control memory 1054, cache, disk, and peripheral devices (such as…). Figure 1Access to the neural network circuit in the processor 1052. It is understood that, in this embodiment of the invention, the Core in the processor 1052 may be, for example, a central processing unit (CPU) or other application-specific integrated circuits (ASICs).

[0042] Memory 1054 is the main memory of host 105. Memory 1054 is connected to processor 1052 via a double data rate (DDR) bus. Memory 1054 is typically used to store various running software, input and output data, and information exchanged with external storage in the operating system. To improve the access speed of processor 1052, memory 1054 needs to have a high access speed. In traditional computer system architectures, dynamic random access memory (DRAM) is typically used as memory 1054. Processor 1052 can access memory via the memory controller (… Figure 1 (Not shown) High-speed access memory 1054, performing read and write operations on any storage unit in memory 1054.

[0043] The neural network circuit 110 is a chip array composed of multiple neural network chips. For example, such as... Figure 1 As shown, the neural network circuit 110 includes multiple neural network chips (C) 115 for data processing and multiple routers (R) 120. For ease of description, the neural network chip 115 in this embodiment is simply referred to as chip 115. Multiple chips 115 are interconnected via routers 120. For example, one chip 115 can be connected to one or more routers 120. Multiple routers 120 can form one or more network topologies. Data transmission between chips 115 can be achieved through these various network topologies.

[0044] Figure 1 The neural network system 100 shown is an example of the neural network system provided in this application and should not be construed as limiting the scope of protection of this application. The neural network system applicable to this application may also contain more or fewer circuits, such as the individual neural network chips being directly connected without the need for a router.

[0045] Those skilled in the art will understand that a neural network can include multiple neural network layers. In this embodiment of the invention, a neural network layer is a logical layer concept; one neural network layer refers to one neural network operation to be performed. Each layer of neural network computation is implemented by computation nodes. Neural network layers can include convolutional layers, pooling layers, etc. Figure 2 As shown, a neural network can include n neural network layers (also known as an n-layer neural network), where n is an integer greater than or equal to 2.

[0046] Figure 2 This shows a portion of a neural network layer. For example... Figure 2 As shown, the neural network 200 may include a first layer 202, a second layer 204, a third layer 206, a fourth layer 208, a fifth layer 210, and an nth layer 212. The first layer 202 can perform convolution operations; the second layer 204 can perform pooling operations on the output data of the first layer 202; the third layer 206 can perform convolution operations on the output data of the second layer 204; the fourth layer 208 can perform convolution operations on the output of the third layer 206; and the fifth layer 210 can perform summation operations on the output data of the second layer 204 and the output data of the fourth layer 208, and so on. It is understood that... Figure 2 This is just a simple example and explanation of neural network layers, and does not restrict the specific operations of each neural network layer. For example, the fourth layer 208 can also be a pooling operation, and the fifth layer 210 can also be a convolution operation or a pooling operation, or other neural network operations.

[0047] In some neural networks, after the calculation of the i-th layer is completed, the calculation result of the i-th layer is temporarily stored in a preset cache. When performing the calculation of the (i+1)-th layer, the calculation unit needs to reload the calculation result of the i-th layer and the weights of the (i+1)-th layer from the preset cache for calculation. Here, the i-th layer can be any layer in the neural network. In this embodiment of the invention, due to the neural network circuit of the neural network system (such as...) Figure 1 The neural network chip C in the diagram uses a computing array built with non-volatile storage media. Therefore, weights can be configured on the cells of the computing array before computation, and the computation results can be directly sent to the next layer for pipelined computation. Thus, each layer of the neural network only needs to cache a small amount of data; for example, each layer only needs to cache enough input data for one window computation.

[0048] Neural network circuits containing computing arrays, such as Figure 3 As shown. The neural network circuit 300 includes:

[0049] The input circuit 301 is used to store the input data of the neural network and send it to the driving circuit 302;

[0050] The driving circuit 302, connected to the input circuit 301, is used to convert the input data into a voltage signal that can be applied to the first computing array 303.

[0051] The first computing array 303 is connected to the driving circuit 302 and is used to generate an output current based on the voltage signal input to the driving circuit 302 and the pre-stored weights.

[0052] The first sample-and-hold circuit 305 is connected to the first group of computing units of the first computing array 303 and is used to generate a first analog voltage based on the first output current; wherein, the first group of computing units may belong to one column of computing units or multiple columns of computing units.

[0053] The parameter adjustment circuit 304 is connected to the input circuit 301 and the first sample-and-hold circuit 305, and is used to adjust the parameters of each circuit in the neural network circuit 300 by means of control signals, for example, to generate the first control signal and the second control signal described below.

[0054] The reference voltage generation circuit 306 is connected to the parameter adjustment circuit 304 and is used to generate a reference voltage (e.g., a ramp voltage) according to a first control signal, wherein the first control signal is determined according to a first calculation precision, and the first control signal changes with the change of the first calculation precision;

[0055] The first comparison circuit 307 is connected to the first sample and hold circuit 305 and the reference voltage generation circuit 306 respectively, and is used to output a first level signal according to the first analog voltage and the reference voltage.

[0056] The first output circuit 308 is connected to the first comparison circuit 307 and the parameter adjustment circuit 304 respectively. It is used to sample the first level signal according to the second control signal and output the first calculation result. The first calculation result is a calculation result that meets the first calculation accuracy. The second control signal is used to control the frequency at which the first output circuit 308 samples the first level signal.

[0057] The circuits in the neural network circuit 300 other than the input circuit 301, the driving circuit 302 and the first computing array 303 can be called the neuron core circuit.

[0058] It should be noted that the division of circuit modules in this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The above-mentioned circuits and the connections between circuits are examples and not limitations. Those skilled in the art can modify the neural network circuit 300 without creative effort.

[0059] In some cases, a circuit may be integrated into another circuit, and the connection relationship changes accordingly. For example, the driving circuit 302 may be integrated into the input circuit 301, in which case the first calculation array 303 is connected to the input circuit 301; the first comparison circuit 307 may be integrated into the first sample-and-hold circuit 305, in which case the first output circuit 308 and the reference voltage generation circuit 306 are respectively connected to the first sample-and-hold circuit 305.

[0060] In other cases, some circuits may be removed. For example, parameter adjustment circuit 304 may be removed, and other circuits in neural network circuit 300 may operate based on externally input control signals or internally preset information.

[0061] Furthermore, in this application, terms such as "first" and "second" are used to refer to different individuals belonging to the same type of object. For example, the first comparison circuit 307 and the second comparison circuit described below refer to two different comparison circuits. Apart from this, there are no other limitations.

[0062] Neural network circuit 300 can be Figure 1 A submodule of the neural network circuit 110 in the neural network system 100 shown (i.e., the neural network circuit 300 is) Figure 1 In the neural network chip C), when the neural network system 100 performs neural network calculations, it can first program the first calculation array 303, that is, complete the mapping of the weights of the neural network to the conductance values.

[0063] Subsequently, the input circuit 301 can send the input data to the drive circuit 302 in a time-division manner, sending 1 bit of information per clock cycle. For example, if the input data is 10, the input circuit 301 can send 1 for 10 consecutive clock cycles, and then send 0. This output method is called rate-coding.

[0064] The driving circuit 302 can convert 1 and 0 into voltage signals and apply the voltage signals to the first computing array 303. At the same time, the first sample-and-hold circuit 305 accumulates the current output by the first group of computing units of the first computing array 303 over time until the input data is completely input.

[0065] The first computing array 303 can operate simultaneously with the driving circuit 302. Below, in conjunction with... Figure 4 This describes the working process of the first computing array 303 performing calculations based on the neural network weights and input data.

[0066] Weights are typically used to represent the importance of input data to output data. In neural networks, weights are usually represented by a matrix. As shown in Table 1, the j-row, k-column matrix can be a weight of a neural network layer, where each element represents a weight value.

[0067] Table 1

[0068]

[0069] In this embodiment, the weights can be pre-configured on the first computation array. For example, elements of a matrix are configured in cells of the computation array, with one element configured in each cell. Thus, the input data and the matrix representing the weights can be multiplied and added using the computation array.

[0070] The structure of a computing array is as follows Figure 4 As shown. A computing array can include multiple units, such as G. 1,1 G 2,1 The cells are located at the intersection of rows and columns. If a computational array includes 1000 rows and 1000 columns, then the number of cells in the computational array is one million. In this embodiment of the invention, the weights shown in Table 1 can be changed during the configuration of the neural network from... Figure 4 The bit lines of the computation array shown (e.g.) Figure 4 (As shown in input port 402) The input is processed in the calculation array so that each weight value in the weights is assigned to the corresponding cell. For example, the weight values ​​W in Table 1 0,0 Configured to Figure 4 G 1,1 In Table 1, the weight values ​​W 1,0 Configured to Figure 4 G 2,1 In this system, each weight value corresponds to a cell, and each weight value is stored in the cell in the form of electrical conductance. During neural network computation, input data is fed through the word lines of the computation array (e.g., ...). Figure 4 The input port 404 shown is used to input the computation array. Input data can be represented by voltages (such as V1, V2, V3, and V4), allowing the input data to be multiplied by the weight values ​​stored in the cells. The resulting calculation is output as current from the output of each column of the computation array (e.g., ...). Figure 4 The output port 406 shown is the output port.

[0071] The current value of each column output can be calculated using the formula I = GV. For example, the current value of the first column output is denoted as I1. .

[0072] A computational array that stores weights can also be called a synaptic array. Figure 4The computing array shown is a 1T1R array, where 1T1R means that each unit has one transmitter and one receiver. Optionally, the computing array suitable for this application can also be a 1T2R, 2T2R, or other types of array.

[0073] After the first sample-and-hold circuit 305 finishes processing the output current of the first calculation array 303, the first comparator circuit 307 and the reference voltage generation circuit 306 begin to operate. At the same time, the first output circuit 308 also starts to operate.

[0074] The timing sequence of each circuit in the neural network circuit 300 is as follows: Figure 5 As shown.

[0075] The accuracy requirement of the neural network varies with the magnitude of the current output by the first set of computing units. The greater the current output by the first set of computing units, the greater the accuracy requirement of the neural network. The parameter adjustment circuit 304 can improve the accuracy of the first calculation result by increasing the sampling frequency of the first output circuit 308 and increasing the duration of the first level signal through control signals, so as to meet the accuracy requirement of the neural network.

[0076] For example, when the accuracy requirement of the neural network changes from computational accuracy A to computational accuracy B (computational accuracy B is higher than computational accuracy A), the parameter adjustment circuit 304 can generate control signal X1 and control signal X2 according to the computational accuracy B; control signal X1 controls the reference voltage generation circuit 306 to generate a reference voltage, so that the first comparison circuit 307 generates a voltage signal with a longer duration after comparing the first analog voltage and the reference voltage, thus enabling the first output circuit 308 to sample more information; control signal X2 can control the first output circuit 308 to increase the sampling frequency, thereby sampling more information per unit time.

[0077] For example, when the accuracy requirement of the neural network changes from computational accuracy A to computational accuracy C (computational accuracy C is lower than computational accuracy A), the parameter adjustment circuit 304 can generate control signals X3 and X4 according to the computational accuracy C. Control signal X3 controls the reference voltage generation circuit 306 to generate a reference voltage, so that the first comparison circuit 307 generates a voltage signal with a shorter duration after comparing the first analog voltage and the reference voltage. In this way, the power consumption of the neural network circuit 300 can be reduced while the first output circuit 308 samples enough information. Control signal X4 controls the first output circuit 308 to reduce the sampling frequency, thereby reducing the power consumption of the neural network circuit 300 while sampling enough information per unit time.

[0078] Therefore, the neural network circuit 300 can adapt to changes in the computational precision of the neural network, avoiding problems such as insufficient computational precision due to low precision or wasted power consumption due to high precision.

[0079] Figure 6 This is a schematic diagram of an optional structure for a neural network circuit 300.

[0080] Figure 6 In addition to sending input data to the first computing array, the input circuit 601 also sends information for parameter control to the parameter adjustment circuit 604, such as output range information, starting voltage information, and accuracy information. The parameter adjustment circuit 604 includes various functional circuits, such as an output range adjustment circuit, a starting voltage control circuit, and an accuracy adjustment circuit.

[0081] Output range information, such as the number of rows opened in the first computing array and algorithm requirements, is used by the output range adjustment circuit to obtain the output range information from the output circuit and generate a control signal K for controlling the switched capacitor. The control signal K is used to control the switching group (K) in the first sample-and-hold circuit. i0 K i1 and K i2 The switches in the switch group are connected to the integrating capacitor.

[0082] The first sample-and-hold circuit 605 may include an operational amplifier (OPA) and an integrating capacitor. The integrating capacitor is as follows: Figure 6 C in i0 C i1 and C i2 As shown. The integrating capacitor integrates the input current (i.e., the first output current of the first computing array), and its output voltage is linearly related to the input current, i.e.,

[0083] Where S&H_OUT is the output voltage (first analog voltage) of the first sample-and-hold circuit 605, Current_IN is the input current of the first sample-and-hold circuit 605, and A is the linearity coefficient. When the switches in the switching group are closed and opened, the size of the integrating capacitor of the first sample-and-hold circuit 605 changes. The integrating capacitor controlled by the switching group can scale the ratio of the input current to the output voltage of the first sample-and-hold circuit 605. The linearity coefficient A is the scaling factor of the input current to the output voltage of the first sample-and-hold circuit 605.

[0084] The OPA operates under the control signal L generated by the accuracy adjustment circuit. The control signal L controls the reference current of the OPA, reducing power consumption while meeting the accuracy requirements of the output voltage of the first sample-and-hold circuit 605. After the reference current decreases, the current of the OPA amplifier decreases due to the mirroring effect of the current mirror, thereby reducing the power consumption of the first sample-and-hold circuit 605.

[0085] Figure 6 RST_integ is the reset switch, EN_integ is the enable switch, and V... CLP This refers to the clamping voltage. All three features are optional implementations.

[0086] The accuracy information mentioned above is used by the parameter adjustment circuit 604 to generate control signals. These control signals include, for example, the control signal L generated by the OPA current controller and the clock control signals (CLK_ramp and CLK_out) generated by the frequency divider after frequency modulation of the neural network system's clock signal (CLK). The OPA current controller and the frequency divider can be referred to as the accuracy adjustment module. The function of the control signal L has been described above; the function of the clock control signal will be described in detail below.

[0087] The clock control signal K is used to control the ramp voltage generated by the ramp voltage generation circuit 606, which is an example of the reference voltage generation circuit 306 described above. The ramp voltage output by the ramp voltage generation circuit 606 and the first analog voltage output by the first sample-and-hold circuit 605 are used by the first comparator circuit 607 to generate a first level signal.

[0088] The working principle of the first comparator circuit 607 is as follows:

[0089] When the first analog voltage is higher than the ramp voltage, the first level signal is a high level signal;

[0090] When the first analog voltage is lower than the ramp voltage, the first level signal is a low level signal.

[0091] Figures 7 to 9 Here are several examples of a first comparator circuit generating a first-level signal based on a ramp voltage and a first analog voltage. Here, V represents voltage, t represents time, S&H_OUT represents the first analog voltage output by the first sample-and-hold circuit 605, Ramp_OUT represents the ramp voltage output by the ramp voltage generation circuit 606, COMP_OUT represents the first-level signal output by the first comparator circuit 607, and Neuron_OUT represents the first calculation result obtained by the first output circuit 608 from sampling the first-level signal. Figures 7 to 9 In all cases, the value of the first analog voltage is the same.

[0092] Figure 7 The slope of Ramp_OUT is less than Figure 8 The slope of Ramp_OUT, when S&H_OUT are the same, Figure 7 The duration of COMP_OUT in the middle is longer than Figure 8The duration of COMP_OUT; assuming the first output circuit 608 samples COMP_OUT at the same frequency. Figure 7 The information content of Neuron_OUT is greater than Figure 8 The information content of Neuron_OUT. The slope of the ramp voltage is controlled by the clock control signal CLK_ramp, thus it can be seen that the parameter adjustment circuit 604 can control... Figure 6 The output accuracy of the neural network circuit shown is as follows. Furthermore, the longer the duration of the high-level signal, the greater the power consumption; therefore, the parameter adjustment circuit 604 can also control the output accuracy by controlling the slope of the ramp voltage. Figure 6 The power consumption of the neural network circuit shown.

[0093] Figure 7 The slope of Ramp_OUT in Figure 9 The slopes of Ramp_OUT are the same in both cases, therefore... Figure 7 The duration of COMP_OUT and Figure 9 The duration of COMP_OUT is the same; Figure 7 The first output circuit 608 samples COMP_OUT at a frequency greater than [missing information]. Figure 9 The frequency at which the first output circuit 608 samples COMP_OUT is therefore... Figure 7 The information content of Neuron_OUT is greater than Figure 9 The information content of Neuron_OUT. The sampling frequency of the first output circuit 608 is controlled by the clock control signal CLK_out, thus it can be seen that the parameter adjustment circuit 604 can control... Figure 6 The output accuracy of the neural network circuit shown is [not specified]. Furthermore, the higher the sampling frequency, the greater the power consumption; therefore, the parameter adjustment circuit 604 can also control the [not specified] by controlling the sampling frequency. Figure 6 The power consumption of the neural network circuit shown.

[0094] The parameter adjustment circuit 604 can be controlled by both CLK_ramp and CLK_out. Figure 6 The output accuracy and power consumption of the neural network circuit shown can also be controlled by CLK_ramp or CLK_out, which can reduce power consumption while meeting the output accuracy requirements of the neural network circuit.

[0095] Optionally, in addition to controlling the output accuracy of the neural network circuit, the parameter adjustment circuit 604 can also control the starting sampling time of the first output circuit 608.

[0096] like Figure 6As shown, after the starting voltage control circuit obtains the starting voltage information from the input circuit 601, it outputs a voltage signal and applies it to the DAC of the ramp voltage generation circuit 606 to control the starting voltage of the ramp voltage. This DAC is a segmented capacitor type DAC used to generate the ramp voltage. C0~C9 are the segmented capacitors in this DAC, and C1~C9 can be connected to ground (GND) under the control of the switch. The ramp voltage generation circuit 606 also includes a counter. The bit width of this counter is, for example, 8 bits, and it can output 256 control signals under the control of CLK_ramp, as shown in S1~S8. S1~S8 are used to control the switches corresponding to C1~C9 to adjust the slope of the ramp voltage.

[0097] When the starting voltage of the ramp voltage is the same as the starting voltage of the first analog voltage, the first comparator circuit 607 can output as follows: Figure 10 The COMP_OUT shown indicates that COMP_OUT and the input current Current_IN of the first sample-and-hold circuit 605 maintain a ReLU function relationship, and the first comparator circuit 607 has the function of the ReLU function.

[0098] When the first output circuit 608 delays the start sampling time under the control of the parameter adjustment circuit 604, the relationship between Neuron_OUT and Current_IN generated by the first output circuit 608 is as follows: Figure 11 As shown, the ReLU function relationship is positively biased. The aforementioned delay refers to starting sampling after receiving the control signal from the parameter adjustment circuit 604, without sampling the first level signal before the control signal. Optionally, the first output circuit 608 can also advance the starting sampling time under the control of the parameter adjustment circuit 604, so that Neuron_OUT and Current_IN exhibit a negatively biased ReLU function relationship.

[0099] Figure 6 The neural network circuit shown also includes a first output circuit 608, which can output two results: a data signal Y1 from the counter and a pulse signal Y0, where Y0 can be generated based on Y1. When the counter's bit width is 8 bits, Y1 can have 8 selectable precisions, such as... Figure 6 As shown in <0:7>.

[0100] The input signal of the first computing array is typically a pulse signal. When the result output by the first output circuit 608 is used as the input signal of other computing arrays, the first output circuit 608 can output Y0. Thus, the result output by the first output circuit 608 can be used by other computing arrays without requiring conversion processing. Therefore, there is no need to use devices such as registers and shift accumulators, thereby saving the devices and power consumption required for conversion processing. This embodiment is an example. Figure 13 As shown, when the first output circuit 1308 outputs Y0, Y0 can be directly loaded onto the second computing array 13114 by the driving circuit 1313 of the second neural network circuit. Therefore, Figure 13 The input circuit 1312 of the second neural network circuit is an optional module.

[0101] If the result output by the first output circuit 608 is no longer used as the input signal for other computing arrays, then the first output circuit 608 can output Y1.

[0102] The preceding text details the processing steps of the first computing array when outputting a single output current (i.e., the first output current). When the first computing array can output multiple output currents, the neural network circuit provided in this application... Figure 12 As shown.

[0103] Figure 12 In the first computing array 1203, there are multiple sets of computing units, such as a first set of computing units and a second set of computing units. The first set of computing units and the second set of computing units perform calculations on different input data according to weights and output different output currents. The second set of computing units outputs a second output current to the second sample-and-hold circuit 1209. Under the control of control signals L and K, the second sample-and-hold circuit 1209 converts the second output current into a second analog voltage. The second comparison circuit 1210 outputs a second level signal based on the second analog voltage and a reference voltage (e.g., a ramp voltage). The second output circuit 1211 samples the second level signal to generate a second calculation result.

[0104] Figure 12 In the first computing array 1203, different groups of computing units use different sample-and-hold circuits, comparison circuits, and output circuits, while the parameter adjustment circuit 1204 and the reference voltage generation circuit 1206 are shared by all groups of computing units, thereby saving components and power consumption.

[0105] Figure 12 The neural network circuit shown is suitable for single-layer neural networks. Optionally, it can also be used in... Figure 12 Other circuits are connected to the neural network circuit shown to meet the requirements of a multi-layer neural network.

[0106] Figure 13 A circuit suitable for multi-layer neural networks is shown. The first neural network circuit is, for example,... Figure 12 The circuit shown has an input bit width of M for the first neural network circuit and a size of M for the first computing array. The second neural network circuit has N output neurons (i.e., N output circuits); the second neural network circuit has an input bit width of N, and the second computation array has a size of N. K, there are K output neurons (i.e., K output circuits). The output neurons of the second neural network circuit can also be connected to other neural network circuits.

[0107] Figure 13 The operating timing sequence of the circuit shown is as follows Figure 14 As shown. When the reference voltage generation circuit, comparator circuit, and output circuit of the first neural network circuit are working, the input circuit, driver circuit, computation array, and sample-and-hold circuit of the second neural network circuit are also working. An optional workflow is as follows:

[0108] 1-S1, the first step of the first neural network circuit, the input circuit 1301 of the first neural network circuit outputs the input data in a rate-encoded manner, and the required time is determined by the amount of data and the signal bit width;

[0109] 1-S2, the second step of the first neural network circuit: the driving circuit 1302, the first computing array 1303 and each sample-and-hold circuit of the first neural network circuit start to work. The first computing array 1303 performs multiplication and addition operations on the input data and the weights stored in the first computing array 1303. The operation result is output after being processed by each sample-and-hold circuit.

[0110] 1-S3, the third step of the first neural network circuit, the reference voltage generation circuit 1306, each comparison circuit and each output circuit start working and output the first calculation result;

[0111] 2-S1, the first step of the second neural network circuit, the input circuit 1312 of the second neural network circuit samples the first calculation result of the first neural network circuit and outputs the sampling result;

[0112] 2-S2, the second step of the second neural network circuit, the driving circuit 1313 of the second neural network circuit converts the sampling result of the previous step into an analog voltage signal and applies it to the second computing array 1314. The second computing array 1314 performs multiplication and addition operations on the input data and the weights stored in the second computing array 1314. The operation result is output after being processed by each sample-and-hold circuit; 1-S3, the time of 2-S1 and 2-S2 coincides;

[0113] 2-S3, the third step of the second neural network circuit, the reference voltage generation circuit 1317 of the second neural network circuit, each comparison circuit and each output circuit start working and output the second calculation result;

[0114] The neural network system then outputs the final calculation result.

[0115] Figure 13In the circuit shown, the precision of the first neural network circuit and the second neural network circuit can be represented by N1 and N2, respectively. The first neural network circuit can output 2... N1 2 pulses, where each pulse serves as an input to the second neural network circuit; for each input, the second neural network circuit can output 2. N2 Therefore, the output precision of the second neural network circuit is (N1+N2) bits. For example, if the slope voltage precision of both the first and second neural network circuits is 8 bits, then N1 and N2 are both 1~8 bits, and the output precision of the second neural network circuit ranges from 2 to 16 bits.

[0116] The foregoing has detailed examples of neural network circuits and systems provided in this application, including the corresponding hardware structures and / or software modules for performing various functions. Those skilled in the art will readily recognize that, in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] In the several embodiments provided in this application, the systems, apparatuses, and methods disclosed can be implemented in other ways. For example, some features of the method embodiments described above can be ignored or not performed. The apparatus embodiments described above are merely illustrative; the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Multiple units or components can be combined or integrated into another system. Furthermore, the coupling between units or components can be direct coupling or indirect coupling, including electrical, mechanical, or other forms of connection.

[0118] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0119] In summary, the above description is merely a preferred embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A neural network circuit, characterized in that, include: The first neural network computing array includes a first set of computing units, which are used to perform neural network computing on a first part of the input data according to weights to obtain a first output current. A first sample-and-hold circuit, connected to the first set of computing units, is used to generate a first analog voltage based on the first output current; A reference voltage generation circuit is used to generate a reference voltage according to a first control signal, wherein the first control signal is determined according to a first calculation precision, and wherein the first control signal changes with the change of the first calculation precision. In order to improve the first calculation precision, the first control signal is configured to increase the duration of the first level signal, and in order to reduce the first calculation precision, the first control signal is configured to decrease the duration of the first level signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit respectively, and is used to output the first level signal according to the first analog voltage and the reference voltage. A first output circuit is configured to sample the first level signal according to a second control signal and output a first calculation result, wherein the first calculation result is a calculation result that satisfies the first calculation accuracy, and the second control signal is configured to control the sampling frequency of the first output circuit sampling the first level signal. To improve the first calculation accuracy, the second control signal is configured to increase the sampling frequency, and to reduce the first calculation accuracy, the second control signal is configured to decrease the sampling frequency.

2. The neural network circuit according to claim 1, characterized in that, Also includes: A parameter adjustment circuit is used to generate the first control signal and the second control signal based on the first calculation accuracy.

3. The neural network circuit according to claim 1, characterized in that: When the first analog voltage is higher than the reference voltage, the first level signal is a high level signal; When the first analog voltage is lower than the reference voltage, the first level signal is a low level signal.

4. The neural network circuit according to claim 1, characterized in that: The first neural network computing array further includes a second set of computing units, which are used to perform neural network calculations on the second part of the data according to the weights to obtain the second output current; The neural network circuit also includes: The second sample-and-hold circuit, connected to the second set of calculation units, is used to generate a second analog voltage based on the second output current; The second comparator circuit is connected to the second sample-and-hold circuit and the reference voltage generation circuit respectively, and is used to output a second level signal according to the second analog voltage and the reference voltage. The second output circuit is used to sample the second level signal according to the second control signal and output a second calculation result, wherein the second calculation result is a calculation result that meets the first calculation accuracy, and the second control signal is used to control the frequency at which the second output circuit samples the second level signal.

5. The neural network circuit according to claim 1, characterized in that, It also includes a second neural network computing array, wherein the first output circuit is connected to the input terminal of the second neural network computing array, and the second neural network computing array is used to perform calculations on the data input to the second neural network computing array based on weights, wherein the data input to the second neural network computing array includes the first calculation result, and the first calculation result is a pulse signal.

6. The neural network circuit according to any one of claims 1 to 5, characterized in that, The reference voltage is a ramp voltage.

7. The neural network circuit according to claim 6, characterized in that, The starting voltage of the ramp voltage is controlled by the first control signal.

8. The neural network circuit according to claim 2, characterized in that, The parameter adjustment circuit is also used for: A third control signal is generated based on the first calculation accuracy. The third control signal is used to control the reference current of the operational amplifier (OPA) in the first sample-and-hold circuit, so as to control the accuracy of the first analog voltage and the power consumption of the first sample-and-hold circuit.

9. The neural network circuit according to claim 2, characterized in that, The parameter adjustment circuit is also used for: Control the start sampling time of the first output circuit.

10. A neural network system, characterized in that, include: The neural network circuit as described in any one of claims 1 to 9; Memory, used to store input data; A processor is configured to read the input data from the memory and input the input data into the neural network circuit so that the neural network circuit performs neural network calculations on the input data.

11. The neural network system according to claim 10, characterized in that, The memory is also used for: storing computer programs; The processor is further configured to: retrieve the computer program from the memory to program the neural network computing array in the neural network circuit, wherein the programming is used to configure the weights of the neural network.

Images