Semiconductor device and method for forming the same

Abstract

Embodiments of the present invention relate to semiconductor devices and methods for forming the same. The semiconductor device includes a first conductive component and a second conductive component. A first passivation layer is located between the first conductive component and the second conductive component. The second passivation layer is located between the first conductive component and the second conductive component and above the first passivation layer. The lowest portion of the interface where the first passivation layer contacts the second passivation layer is located below 40% or above 60% of the height of the first conductive component.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Contacts are used to establish electrical connections among or between different components in a semiconductor device. For example, contacts are used to connect one metal layer to another metal layer or another device layer that is otherwise electrically isolated from each other, such as by a dielectric material separating the metal layers. Summary of the invention

[0003] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a first conductive component; a second conductive component; a first passivation layer located between the first conductive component and the second conductive component; and a second passivation layer located between the first conductive component and the second conductive component and above the first passivation layer, wherein the lowest portion of the interface where the first passivation layer contacts the second passivation layer is located below 40% or above 60% of the height of the first conductive component.

[0004] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first conductive component; a second conductive component; a first passivation layer located between the first conductive component and the second conductive component; a second passivation layer located between the first conductive component and the second conductive component and above the first passivation layer; and a third passivation layer located between the first conductive component and the second conductive component and above the second passivation layer, wherein: the lowest portion of the interface where the first passivation layer contacts the second passivation layer is below 40% of the height of the first conductive component, and the lowest portion of the interface where the second passivation layer contacts the third passivation layer is above 60% of the height of the first conductive component.

[0005] According to another aspect of the present invention, a method for forming a semiconductor device is provided, comprising: forming a conductive layer; removing a portion of the conductive layer to define a recess between a first conductive component formed by the conductive layer and a second conductive component formed by the conductive layer; forming a first passivation layer in the recess between the first conductive component and the second conductive component; and forming a second passivation layer in the recess between the first conductive component and the second conductive component and above the first passivation layer, wherein the lowest portion of the interface where the first passivation layer contacts the second passivation layer is located below 40% or above 60% of the height of the first conductive component. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 10 is an illustration of a semiconductor device at various stages of fabrication in accordance with some embodiments. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0009] In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relation terms are intended to encompass different orientations of the device in use or operating processes. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein should be interpreted accordingly.

[0010] A technique for manufacturing a semiconductor device is provided herein. In some embodiments, a multi-stage deposition process is performed to form a dielectric barrier structure, the dielectric barrier structure including a plurality of passivation layers located between adjacent conductive components. Metal contraction in the conductive components induces tensile strain in the region between the conductive components. In some embodiments, the passivation layers are deposited in such a manner as to provide an interface between the passivation layers that is not located in a stress concentration region where tensile stress is highest. It has been found that in some embodiments, the stress concentration region with the greatest tensile stress corresponds to an extension region from about 40% of the height of the conductive component to about 60% of the height of the conductive component. In some embodiments, the interface between the passivation layers is positioned below 40% or above 60% of the height of the conductive component.

[0011] Go to Figure 1, showing a plurality of layers used in forming a semiconductor device 100 according to some embodiments. A plurality of layers are formed over a semiconductor layer 105. In some embodiments, the semiconductor layer 105 is part of a substrate, including an epitaxial layer, a single crystalline semiconductor material (such as but not limited to Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, and InP), a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the semiconductor layer 105 includes crystalline silicon. In some embodiments, the plurality of layers include a device layer 110, a first metallization layer 115, and a second metallization layer 116. In some embodiments, the device layer 110 includes an integrated circuit element, such as a FinFET transistor 2. In some embodiments, the device layer 110 includes other circuit elements not shown separately, such as planar transistors, capacitors, resistors, or other suitable devices. In some embodiments, the first metallization layer 115 and the second metallization layer 116 represent routing layers (e.g., under bump metallization (UBM) layers) for routing electrical signals between layers of the semiconductor device 100 located below the first metallization layer 115 and layers of the semiconductor device 100 located above the first metallization layer 115. In some embodiments, one or more additional metallization layers are formed between the device layer 110 and the first metallization layer 115. Thus, the first metallization layer 115 may be an M1 layer (i.e., the first metallization layer closest to the device layer 110) or an Mx layer, where x is an integer greater than or equal to 2. In some embodiments, one or more additional metallization layers are formed above the second metallization layer 116.

[0012] In some embodiments, the fin 4 is formed in the semiconductor layer 105 by etching a trench in the semiconductor layer 105 using a patterned hard mask. Thus, the fin 4 is formed by the semiconductor layer 105. In some embodiments, the fin 4 is formed (such as grown), for example, above the semiconductor layer 105. Typically, the fin 4 defines an active area for forming a device (such as a FinFET transistor 2). In some embodiments, an isolation structure 6 such as a shallow trench isolation (STI) is formed near the FinFET transistor 2 to isolate the FinFET transistor 2 from adjacent devices by forming a recess in the semiconductor layer 105 and filling the recess with a dielectric material. In some embodiments, the isolation structure 6 includes silicon oxide or other suitable materials.

[0013] In some embodiments, a gate structure 8 is formed over the fin 4. According to some embodiments, the gate structure 8 is formed by forming a sacrificial gate structure including a sacrificial gate dielectric layer, a sacrificial polysilicon layer, and a hard mask layer over the fin 4 and the isolation structure 6. In some embodiments, a patterning process is performed to pattern a hard mask layer corresponding to the pattern of the gate structure to be formed, and an etching process is performed using the patterned hard mask layer. The sacrificial polysilicon layer and the sacrificial gate dielectric layer are etched to define a sacrificial gate structure. In some embodiments, the remaining portion of the hard mask layer forms a capping layer over the sacrificial gate structure. In some embodiments, the sacrificial gate structure is subsequently replaced by a gate structure 8 including a gate dielectric layer and a gate electrode (not shown separately).

[0014] In some embodiments, the gate dielectric layer includes a high-k dielectric material. As used herein, the term "high-k dielectric" refers to a material having a dielectric constant k greater than or equal to about 3.9, which is the k value of SiO2. The material of the high-k dielectric layer can be any suitable material. Examples of materials for the high-k dielectric layer include, but are not limited to, Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2O x N y , HfO x N y 、ZrO x N y 、La2O x N y 、TiO x N y 、SrTiO x N y 、SrTiO x N y 、SiN x , silicates thereof, and alloys thereof. Each value of x is independently 0.5 to 3, and each value of y is independently 0 to 2. In some embodiments, the gate dielectric layer includes a native oxide layer including silicon dioxide formed on the exposed surface of the fin 4 by exposing the semiconductor device 100 to oxidation at various points in the process flow. In some embodiments, an additional dielectric material layer (e.g., silicon dioxide, high-k dielectric material, or other suitable material) is formed over the native oxide to form the gate dielectric layer.

[0015] In some embodiments, the gate electrode includes a barrier layer, one or more work function material layers, a seed layer, a metal fill layer, or other suitable layers. In some embodiments, the metal fill layer includes tungsten (W) or other suitable materials. In some embodiments, one or more layers of the replacement gate dielectric layer and the gate electrode are deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable processes.

[0016] In some embodiments, sidewall spacers 10 are formed near the gate structure 8. In some embodiments, the sidewall spacers 10 are formed by depositing a spacer layer on the gate structure 8 and performing an anisotropic etching process to remove horizontal portions of the spacer layer. In some embodiments, the sidewall spacers 10 include silicon nitride or other suitable materials.

[0017] In some embodiments, after forming the gate structure 8, a source / drain region 12 is formed in the fin 4. For example, in some embodiments, a portion of the fin 4 is doped by an implantation process to form the source / drain region 12 in the fin 4, and in some embodiments, an etching process is performed to recess the fin 4 adjacent to the sidewall spacer 10, and an epitaxial growth process is performed to form the source / drain region 12.

[0018] In some embodiments, the device layer 110 includes a first dielectric layer 120. In some embodiments, the first dielectric layer 120 includes silicon dioxide or a low-k material. In some embodiments, the first dielectric layer 120 includes one or more layers of low-k dielectric material. The k value (dielectric constant) of the low-k dielectric material is less than 3.9. Some low-k dielectric materials have a k value less than about 3.5 and may have a k value less than about 2.5. In some embodiments, the material for the first dielectric layer 120 includes at least one of Si, O, C, or H, such as SiCOH and SiOC, or other suitable materials. Organic materials such as polymers may be used for the first dielectric layer 120. In some embodiments, the first dielectric layer 120 includes one or more layers of carbon-containing materials, organosilicate glass, porogen-containing materials, or combinations thereof. In some embodiments, the first dielectric layer 120 includes nitrogen. In some embodiments, the first dielectric layer 120 is formed by using, for example, at least one of plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), or spin coating techniques.

[0019] In some embodiments, a gate contact 122 is formed in the first dielectric layer 120 to contact the gate structure 8 or the gate electrode of the gate structure 8. In some embodiments, a recess is etched in the first dielectric layer 120 using a patterned etching mask to expose the gate structure 8 and form a conductive material in the recess to form the gate contact 122. In some embodiments, the conductive material includes tungsten, aluminum, copper, cobalt, or other suitable materials. In some embodiments, the gate contact 122 includes multiple layers, such as a barrier layer, a seed layer, and a conductive filling layer.

[0020] In some embodiments, the first metallization layer 115 includes a second dielectric layer 125. In some embodiments, the second dielectric layer 125 includes silicon dioxide or a low-k material. In some embodiments, the second dielectric layer 125 includes one or more layers of low-k dielectric material. In some embodiments, the material for the second dielectric layer 125 includes at least one of Si, O, C, or H, such as SiCOH and SiOC, or other suitable materials. Organic materials such as polymers can be used for the second dielectric layer 125. In some embodiments, the second dielectric layer 125 includes one or more layers of carbon-containing materials, organic silicate glass, porogen-containing materials, or combinations thereof. In some embodiments, the second dielectric layer 125 includes nitrogen. In some embodiments, the second dielectric layer 125 is formed by using at least one of, for example, PECVD, LPCVD, ALCVD, or spin coating techniques. In some embodiments, the second dielectric layer 125 includes the same material composition as the first dielectric layer 120. In some embodiments, an etch stop layer may be formed between the first dielectric layer 120 and the second dielectric layer 125 to provide etch control when forming the conductive feature 130 as described below. In some embodiments, the material composition of the second dielectric layer 125 is selected to have a different etch selectivity relative to the first dielectric layer 120. In some such embodiments, the second dielectric layer 125 may directly contact the first dielectric layer 120.

[0021] In some embodiments, the first conductive component 130 is located in the second dielectric layer 125 in contact with the gate contact 122. In some embodiments, the first conductive component 130 includes a metal. In some embodiments, the metal includes tungsten, aluminum, copper, cobalt, or other suitable materials. In some embodiments, the first conductive component 130 includes a silicide material. In some embodiments, the first conductive component 130 includes multiple layers, such as a barrier layer, a seed layer, and a conductive fill layer. In some embodiments, the first conductive component 130 includes a line feature, the line feature having a width in a horizontal plane (extending left and right on the page) and an axial length greater than the width (extending inward and outward of the page). In some embodiments, the first conductive component 130 includes a through-hole feature, the through-hole feature having a width to length ratio of less than about 5 in a horizontal plane. In some embodiments, the first conductive component 130 is formed by using a damascene process, the damascene process is performed by using a patterned etching mask to etch a recess in the second dielectric layer 125 and fill the recess with the material of the first conductive component 130. In some embodiments, the material of the first conductive component 130 overfills the recess, and a planarization process is performed to remove the portion outside the recess. In some embodiments, the planarization process includes a chemical mechanical planarization (CMP) process.

[0022] In some embodiments, the second metallization layer 116 includes a third dielectric layer 126. In some embodiments, the third dielectric layer 126 includes silicon dioxide or a low-k material. In some embodiments, the third dielectric layer 126 includes one or more layers of low-k dielectric material. In some embodiments, the material for the third dielectric layer 126 includes at least one of Si, O, C, or H, such as SiCOH and SiOC, or other suitable materials. Organic materials such as polymers can be used for the third dielectric layer 126. In some embodiments, the third dielectric layer 126 includes one or more layers of carbon-containing materials, organic silicate glass, porogen-containing materials, or combinations thereof. In some embodiments, the third dielectric layer 126 includes nitrogen. In some embodiments, the third dielectric layer 126 is formed by using, for example, at least one of PECVD, LPCVD, ALCVD, or spin coating techniques. In some embodiments, the third dielectric layer 126 includes the same material composition as at least one of the first dielectric layer 120 or the second dielectric layer 125. In some embodiments, an etch stop layer may be formed between the second dielectric layer 125 and the second dielectric layer 125 to provide etching control when forming the conductive feature 131 as described below. In some embodiments, the material composition of the third dielectric layer 126 is selected to have a different etching selectivity relative to the second dielectric layer 125. In some such embodiments, the third dielectric layer 126 may directly contact the second dielectric layer 125.

[0023] In some embodiments, the second conductive component 131 is located in the third dielectric layer 126 in contact with the first conductive component 130. In some embodiments, the second conductive component 131 includes a metal. In some embodiments, the metal includes tungsten, aluminum, copper, cobalt, or other suitable materials. In some embodiments, the second conductive component 131 includes a silicide material. In some embodiments, the second conductive component 131 includes the same material composition as the first conductive component 130. In some embodiments, the second conductive component 131 includes multiple layers, such as a barrier layer, a seed layer, and a conductive fill layer. In some embodiments, the second conductive component 131 includes a line feature, the line feature having a width in the horizontal plane (extending left and right on the page) and an axial length greater than the width (extending into and out of the page). In some embodiments, the second conductive component 131 includes a through-hole feature, the ratio of the width to the length of the through-hole feature in the horizontal plane is less than about 5. In some embodiments, the second conductive component 131 is formed by using a damascene process, which etches a recess in the third dielectric layer 126 using a patterned etching mask and fills the recess with the material of the second conductive component 131. In some embodiments, the material of the second conductive component 131 overfills the recess, and a planarization process is performed to remove a portion outside the recess. In some embodiments, the planarization process includes a chemical mechanical planarization (CMP) process.

[0024] refer to Figure 2 According to some embodiments, a glue layer 140 is formed over the third dielectric layer 126 and the second conductive component 131, a conductive layer 145 is formed over the glue layer 140, and a hard mask layer 150 is formed over the conductive layer 145. In some embodiments, the glue layer 140 includes TaO, TiO, TiN, or other suitable materials. In some embodiments, the glue layer 140 is formed by at least one of CVD, LPCVD, PECVD, ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques. In some embodiments, the conductive layer 145 includes tungsten, aluminum, or other suitable materials. In some embodiments, the conductive layer 145 is formed to have a height 146 greater than or equal to 20 kiloangstroms. In some embodiments, a ratio between a height 148 of at least one of the first conductive feature 130 or the second conductive feature 131 and a height 146 of the conductive layer 145 is between about 5,000 angstroms and about 10,000 angstroms or between about 7,000 angstroms and about 8500 angstroms. In some embodiments, the conductive layer 145 is formed by at least one of CVD, ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, electroplating, chemical plating, or other suitable techniques. In some embodiments, the hard mask layer 150 includes silicon nitride or other suitable materials.

[0025] refer to Figure 3 According to some embodiments, hard mask layer 150 and conductive layer 145 are patterned. In some embodiments, conductive features 145A, 145B, 145C are defined from conductive layer 145 by patterning. In some embodiments, conductive features 145A, 145B, 145C include line features. In some embodiments, the line features have a Figure 3 In some embodiments, due to the patterning of the conductive layer 145, a recess 147 is defined between the conductive components 145A, 145B, 145C. In some embodiments, at least one of the conductive components 145A, 145B, 145C covers the second conductive component 131.

[0026] In some embodiments, the hard mask layer 150 and the conductive layer 145 are patterned using a subtractive etching process or other suitable etching process by forming one or more layers of a lithographic stack. In some embodiments in which a lithographic stack is formed, the lithographic stack includes a bottom anti-reflective coating (BARC) formed above the hard mask layer 150. In some embodiments, the BARC layer is a polymer layer applied using a spin coating process. In some embodiments, the lithographic stack includes an organic planarization layer (OPL) formed above the BARC layer. In some embodiments, the OPL layer includes a photosensitive organic polymer applied using a spin coating process. In some embodiments, the OPL layer includes a dielectric layer. In some embodiments, the lithographic stack includes a photoresist layer above the OPL layer. In some embodiments, the photoresist layer includes an electromagnetic radiation sensitive material, and the properties of the photoresist layer (such as solubility) are affected by electromagnetic radiation. The photoresist layer is a negative photoresist or a positive photoresist. In some embodiments, electromagnetic radiation is also applied to a portion of the OPL layer, and the electromagnetic radiation patterns the photoresist layer to change the etching selectivity of the irradiated portion of the OPL layer relative to the non-irradiated portion. In some embodiments, a radiation source and a mask are used to expose the photoresist layer to define a pattern in the photoresist layer. In some embodiments, portions of the photoresist layer are removed to define a patterned photoresist layer. In some embodiments, the underlying OPL layer and BARC layer are etched using the patterned photoresist layer as a template to form a patterned mask on the hard mask layer 150, and an etching process is performed to pattern the hard mask layer 150. Then, the photolithography stack is removed, and an etching process is performed using the patterned hard mask layer 150 to etch the conductive layer 145 to define conductive features 145A, 145B, 145C.

[0027] In some embodiments, glue layer 140 is etched by the etching process used to etch conductive layer 145 or by another subsequent etching process to expose the top surface of third dielectric layer 126. In some embodiments, glue layer 140 is not etched or is only partially etched and the top surface of third dielectric layer 126 is not exposed.

[0028] refer to Figure 4 According to some embodiments, the hard mask layer 150 is removed, an encapsulation layer 153 is formed on the conductive components 145A, 145B, 145C, and a first passivation layer 155A is formed on the encapsulation layer 153. Embodiment. In some embodiments, the encapsulation layer 153 and the first passivation layer 155A are formed in a recess 147 defined between the respective conductive components 145A, 145B, 145C. In some embodiments, the encapsulation layer 153 is an adjacent sidewall surface of the conductive components 145A, 145B, 145C. In some embodiments, the encapsulation layer 153 is formed so that the sidewall of the first passivation layer 155A is located in the recess 147 and is spaced apart from the sidewalls of the conductive components 145A, 145B, 145C by the encapsulation layer 153. In some embodiments, the encapsulation forming layer 153 is formed such that the bottom surface of the first passivation layer 155A located in the recess 147 is separated from the top surface of the third dielectric layer 126 by the encapsulation layer 153. In some embodiments, the encapsulation layer 153 includes SiN, TaN, TiN or other suitable materials. In some embodiments, the encapsulation layer 153 is formed by at least one of CVD, ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, electroplating, chemical plating or other suitable techniques. In some embodiments, the thickness of the encapsulation layer 153 is between about 1 nm and 5 nm.

[0029] In some embodiments, the encapsulation layer 153 is omitted. In some embodiments, an etching process is performed after the encapsulation layer 153 is formed and before the first passivation layer 155A is formed. For example, in some embodiments, a horizontal surface of the encapsulation layer 153 adjacent to the glue layer 140 is removed before the first passivation layer 155A is formed, and the first passivation layer 155A is formed to contact the top surface of the third dielectric layer 126. In some embodiments, the hard mask layer 150 is not removed before the encapsulation layer 153 or the first passivation layer 155A is formed, and therefore, the top surfaces of the conductive features 145A, 145B, 145C are spaced apart from the bottom surface of the substrate by the hard mask layer 150.

[0030] In some embodiments, the first passivation layer 155A includes silicon dioxide. In some embodiments, the first passivation layer 155A is formed using a high density plasma (HDP) process. In some embodiments, the HDP process uses precursor gases including silane (SiH4), oxygen, and argon. In some embodiments, the HDP process includes a deposition component and a sputtering component, in which the material is formed on the surface of the semiconductor device, and in which the deposited material is removed or repositioned. In some embodiments, the sputtering component removes material from the upper sidewall of the recess 147 and redeposits the material in the lower region of the recess 147. In some embodiments, the ratio of deposition to sputtering depends on the gas ratio adopted during deposition. In some embodiments, argon and oxygen serve as sputtering sources. In some embodiments, a specific value of the gas ratio is determined based on the aspect ratio of the recess 147. In some embodiments, the HDP process is performed at a temperature of about 350-450°C.

[0031] Figure 4 A tensile stress curve 160 is included, which shows stress along the X direction 162 due to contraction of the conductive features 145A, 145B, 145C due to temperature changes during manufacturing or operation of the semiconductor device 100. In some embodiments, the thermal expansion coefficient of the conductive features 145A, 145B, 145C is greater than the thermal expansion coefficient of the first passivation layer 155A. In some embodiments, tensile stress is generated in the X, Y, and Z directions when the conductive features 145A, 145B, 145C contract relative to adjacent materials. Figure 4 As shown, the X direction 162 is the horizontal direction, the Y direction is the vertical direction, and the Z direction is the direction into the page. In some embodiments, the conductive component 145A and the conductive component 145B generate tensile stress in opposite directions, such as Figure 4 Similarly, the conductive component 145B and the conductive component 145C generate tensile stress in opposite directions, as shown in FIG. Figure 4 As shown by the arrows in . As a result, the tensile stress in the X direction 162 applied to the area between the conductive members 145A, 145B, 145C is additive. Generally, the tensile stresses in the Y and Z directions are not additive.

[0032] According to some embodiments, the tensile stress in the X direction varies from an angle from the center point 165 of the associated conductive component 145A, 145B, 145C according to the following relationship:

[0033] σ(Θ)=σ·cos(Θ).

[0034] As the angle increases, the tensile stress in the X direction decreases. When θ is zero, it means that the tensile stress in the X direction is maximum at the height of the center point 165. The stress concentration area 170 is defined between about 40% and 60% of the height of the conductive components 145A, 145B, 145C.

[0035] refer to Figure 5 According to some embodiments, a second passivation layer 155B is formed over the first passivation layer 155A. In some embodiments, the second passivation layer 155B is the same material as the first passivation layer 155A. In some embodiments, the second passivation layer 155B is a different material from the first passivation layer 155A. In some embodiments, the second passivation layer 155B and the first passivation layer 155A include silicon dioxide.

[0036] In some embodiments, the deposition parameters of the HDP process for forming the second passivation layer 155B are the same as the deposition parameters for forming the first passivation layer 155A. In some embodiments, the deposition parameters of the HDP process for forming the second passivation layer 155B are modified to change the ratio of deposition to sputtering. In some embodiments, the thickness of the second passivation layer 155B is greater than the thickness of the first passivation layer 155A. In some embodiments, the deposition time of the HDP process during the formation of the second passivation layer 155B is increased relative to the deposition time of the HDP process during the formation of the first passivation layer 155A to provide an increased thickness of the second passivation layer 155B.

[0037] like Figure 5As shown, according to some embodiments, a first interface 175 is defined between the first passivation layer 155A and the second passivation layer 155B. In some embodiments, the first interface 175 is located in the region between the conductive components 145A, 145B, 145C and is substantially parallel to the upper surface of the semiconductor layer 105. In some embodiments, the first interface 175 represents the lowest portion of the interface between the first passivation layer 155A and the second passivation layer 155B located between the conductive components 145A, 145B, 145C. In some embodiments, the first interface 175 is located outside the stress concentration region 170. In some embodiments, the first interface 175 is located at a height less than 40% of the height 177 of the conductive components 145A, 145B, 145C. For example, in an embodiment where the height 177 of the conductive features 145A, 145B, 145C is about 30 kiloangstroms, the height 174 of the first passivation layer 155A from the top surface of the glue layer 140 to the lowest portion of the first interface 175 between the first passivation layer 155A and the second passivation layer 155B may be about 10 kiloangstroms, and thus the lowest portion of the first interface 175 is positioned at a height of about 33% of the height 177 of the conductive features 145A, 145B, 145C. In some embodiments, the height 177 of the conductive features 145A, 145B, 145C is at least 20 kiloangstroms.

[0038] Reference Figure 6 According to some embodiments, a third passivation layer 155C is formed on the second passivation layer 155B. In some embodiments, the third passivation layer 155C is the same material as the second passivation layer 155B. In some embodiments, the third passivation layer 155C is the same material as the first passivation layer 155A. In some embodiments, the third passivation layer 155C is a different material from at least one of the second passivation layer 155B or the first passivation layer 155A. In some embodiments, the first passivation layer 155A, the second passivation layer 155B, and the third passivation layer 155C include silicon dioxide.

[0039] In some embodiments, the deposition parameters for forming the third passivation layer 155C are the same as the deposition parameters for forming the second passivation layer 155B. In some embodiments, the deposition parameters for forming the third passivation layer 155C are modified to change the deposition to sputtering ratio. In some embodiments, the thickness of the third passivation layer 155C is greater than the thickness of the second passivation layer 155B. In some embodiments, the deposition time of the HDP process is increased relative to the deposition time of the HDP process during the formation of the second passivation layer 155B to provide an increased thickness of the third passivation layer 155C.

[0040] like Figure 6As shown, according to some embodiments, a second interface 180 is defined between the second passivation layer 155B and the third passivation layer 155C. In some embodiments, the second interface 180 is located in the region between the conductive components 145A, 145B, 145C and is generally parallel to the upper surface of the semiconductor layer 105. In some embodiments, the second interface 180 represents the lowest portion of the semiconductor layer 105. The interface between the second passivation layer 155B and the third passivation layer 155C located between the conductive components 145A, 145B, 145C. In some embodiments, the second interface 180 is located outside the stress concentration region 170. In some embodiments, the second interface 180 is located at a height greater than 60% of the height of the conductive components 145A, 145B, 145C. For example, in an embodiment where the height 177 of the conductive features 145A, 145B, 145C is about 30 kiloangstroms and the height 174 of the first passivation layer 155A is about 10 kiloangstroms from the top surface of the glue layer 140 to the location of the first interface 175 between the first passivation layer 155A and the second passivation layer 155B at the lowest portion, the height 178 of the second passivation layer 155B from the lowest portion of the first interface 175 between the first passivation layer 155A and the second passivation layer 155A to the lowest portion of the second interface 180 between the second passivation layer 155B and the third passivation layer 155C may be about 10-15 kiloangstroms. Therefore, in such an example, the lowest portion of the second interface 180 is located at a height of about 66% to about 83% of the height 177 of the conductive features 145A, 145B, 145C.

[0041] According to some embodiments, providing the first interface 175 and the second interface 180 outside the stress concentration region 170 mitigates the formation of stress cracks in the passivation layers 155A, 155B, 155C, 155D between the conductive features 145A, 145B, 145C. In some embodiments, different numbers of passivation layers 155A, 155B, 155C, 155D are employed. In some embodiments, the lowest portion of the interface between the passivation layers 155A, 155B, 155C, 155D or additional passivation layers (if present) is not located in the stress concentration region 170.

[0042] refer to Figure 7According to some embodiments, a fourth passivation layer 155D is formed on the third passivation layer 155C. In some embodiments, the fourth passivation layer 155D is the same material as at least one of the first passivation layer 155A, the second passivation layer 155B, or the third passivation layer 155C. In some embodiments, the fourth passivation layer 155D is a different material from at least one of the first passivation layer 155A, the second passivation layer 155B, or the third passivation layer 155C. In some embodiments, the first passivation layer 155A, the second passivation layer 155B, the third passivation layer 155C, and the fourth passivation layer 155D include silicon dioxide.

[0043] In some embodiments, the deposition parameters for forming the fourth passivation layer 155D are the same as the deposition parameters for forming the third passivation layer 155C. In some embodiments, the deposition parameters for forming the fourth passivation layer 155D are modified relative to the deposition parameters for forming the third passivation layer 155C to change the deposition to sputtering ratio. In some embodiments, the thickness of the fourth passivation layer 155D is different from the thickness of the third passivation layer 155C. In some embodiments, the deposition time of the HDP process is increased relative to the deposition time of the HDP process during the formation of the third passivation layer 155C to provide an increased thickness of the fourth passivation layer 155D relative to the thickness of the third passivation layer 155C.

[0044] like Figure 7 As shown, according to some embodiments, a third interface 185 is defined between the third passivation layer 155C and the fourth passivation layer 155D. In some embodiments, the third interface 185 is located in the region between the conductive components 145A, 145B, 145C and is substantially parallel to the upper surface of the semiconductor layer 105. In some embodiments, the third interface 185 represents the lowest portion of the interface between the third passivation layer 155C and the fourth passivation layer 155D located between the conductive components 145A, 145B, and 145C. In some embodiments, the third interface 185 is located outside the stress concentration region 170. In some embodiments, the third interface 185 is located at or above the top surface of the conductive components 145A, 145B, 145C. In some embodiments, the third interface 185 is located below the top surface of the conductive components 145A, 145B, 145C.

[0045] refer to Figure 8According to some embodiments, a nitride layer 200 is formed over the fourth passivation layer 155D. In some embodiments, the material for the nitride layer 200 includes at least one of silicon nitride (SIN) or silicon oxynitride (SION). In some embodiments, the nitride layer 200 is formed by using, for example, at least one of PECVD, LPCVD, ALCVD, or spin coating techniques. In some embodiments, at least one of the nitride layers 200 prevents or reduces exposure of the integrated circuit element to moisture, prevents or reduces mechanical damage to the integrated circuit element, or prevents or reduces radiation damage to the integrated circuit element.

[0046] like Figure 8 As shown, according to some embodiments, a fourth interface 190 is defined between the fourth passivation layer 155D and the nitride layer 200. In some embodiments, the fourth interface 190 is located in the region between the conductive components 145A, 145B, 145C and is substantially parallel to the upper surface of the semiconductor layer 105. In some embodiments, the fourth interface 190 represents the lowest portion of the interface between the fourth passivation layer 155D and the nitride layer 200 located between the conductive components 145A, 145B, and 145C. In some embodiments, the fourth interface 190 is located outside the stress concentration region 170. In some embodiments, the fourth interface 190 is located at or above the top surface of the conductive components 145A, 145B, 145C. In some embodiments, the fourth interface 190 is located below the top surface of the conductive components 145A, 145B, 145C.

[0047] refer to Fig. 9 According to some embodiments, photolithography and etching are performed to remove portions of the nitride layer 200, portions of the fourth passivation layer 155D, portions of the third passivation layer 155C, portions of the second passivation layer 155B, portions of the first passivation layer 155A, and portions of the encapsulation layer 153 to define a recess 206, and an under bump metallization (UBM) layer 205 is formed in the recess 206 and above the nitride layer 200. In some embodiments, a top surface of the conductive feature 145A is exposed through the recess 206. In some embodiments, the UBM layer 205 contacts the conductive feature 145A. In some embodiments, the UBM layer 205 includes multiple layers of conductive materials, such as at least one layer of a titanium layer, a copper layer, or a nickel layer. In some embodiments, at least one layer of the UBM layer 205 is formed using a plating process (e.g., electrochemical plating), but other formation processes, such as sputtering, evaporation, or chemical plating processes, may be used depending on the formation material.

[0048] refer to Fig.10According to some embodiments, a conductive pillar 210 is formed over the UBM layer 205. In some embodiments, a conductive material is deposited in the recess 206 by evaporation, electroplating, or screen printing to form the conductive pillar 210 over the UBM layer 205. In some embodiments, the conductive material includes any one of a plurality of metals or metal alloys. In some embodiments, a portion of the UBM layer 205 not covered by the conductive pillar 210 is removed by an etching process that etches the exposed portion of the UBM layer 205 to expose the nitride layer 200. In some embodiments, the remaining portion of the UBM layer 205 under the conductive pillar 210 is disposed adjacent to the sidewalls of the nitride layer 200, the fourth passivation layer 155D, the third passivation layer 155C, the second passivation layer 155B, the first passivation layer 155A, and the encapsulation layer 153 defining the recess 206. In some embodiments, the UBM layer 205 is disposed between the top surface of the nitride layer 200 and the conductive pillar 210. In some embodiments, the conductive pillar 210 is a copper pillar. In some embodiments, the conductive pillars 210 are solder pillars, wherein the solder is reflowed by heating to form solder bumps.

[0049] In some embodiments, the metal shrinkage in the conductive features 145A, 145B, 145C induces tensile stress in the stress concentration region 170 between the conductive features. In some embodiments, the passivation layers 155A, 155B, 155C, 155D are deposited in such a manner that the interfaces 175, 180, 185 provided between the passivation layers 155A, 155B, 155C, 155D are not located in the stress concentration region 170 where the tensile stress is highest. It has been found that in some embodiments, the stress concentration region 170 where the tensile stress is greatest corresponds to a region extending from about 40% of the height of the conductive features 145A, 145B, 145C to about 60% of the height of the conductive features 145A, 145B, 145C. In some embodiments, the interfaces 175 , 180 , 185 between the passivation layers 155A, 155B, 155C, 155D are positioned below 40% or above 60% of the height of the conductive features 145A, 145B, 145C.

[0050] In some embodiments, the semiconductor device includes a first conductive component and a second conductive component. The first passivation layer is located between the first conductive component and the second conductive component. The second passivation layer is located between the first conductive component and the second conductive component and above the first passivation layer. The lowest part of the interface where the first passivation layer contacts the second passivation layer is located below 40% or above 60% of the height of the first conductive component.

[0051] In some embodiments, the semiconductor device includes an encapsulation layer over the first conductive component and the second conductive component. The first passivation layer is over the encapsulation layer.

[0052] In some embodiments, the semiconductor device includes a nitride layer over the second passivation layer and an under bump metallurgy (UBM) layer extending through the nitride layer.

[0053] In some embodiments, the semiconductor device includes an under bump metallurgy (UBM) layer contacting a sidewall of the second passivation layer.

[0054] In some embodiments, the semiconductor device includes an under bump metallurgy (UBM) layer extending through the second passivation layer and the first passivation layer and contacting at least one of the first conductive component or the second conductive component.

[0055] In some embodiments, the first passivation layer and the second passivation layer have the same material composition.

[0056] In some embodiments, the semiconductor device includes a first conductive component and a second conductive component. A first passivation layer is located between the first conductive component and the second conductive component. The second passivation layer is located between the first conductive component and the second conductive component and above the first passivation layer. A third passivation layer is located between the first conductive component and the second conductive component and above the second passivation layer. The lowest portion of the interface where the first passivation layer contacts the second passivation layer is located below 40% of the height of the first conductive component. The lowest portion of the interface where the second passivation layer contacts the third passivation layer is located above 60% of the height of the first conductive component.

[0057] In some embodiments, the first passivation layer, the second passivation layer, and the third passivation layer include the same material composition.

[0058] In some embodiments, the first passivation layer, the second passivation layer, and the third passivation layer include silicon dioxide.

[0059] In some embodiments, the semiconductor device includes an encapsulation layer over the first conductive component and the second conductive component. The first passivation layer is over the encapsulation layer.

[0060] In some embodiments, the semiconductor device includes a nitride layer over the third passivation layer and an under bump metallurgy (UBM) extending through the nitride layer, the third passivation layer, the second passivation layer, and the first passivation layer to contact at least one of the first conductive component or the second conductive component.

[0061] In some embodiments, the semiconductor device includes a fourth passivation layer over the third passivation layer.

[0062] In some embodiments, the semiconductor device includes a nitride layer over the third passivation layer.

[0063] In some embodiments, the first conductive component and the second conductive component include metal.

[0064] In some embodiments, a method of forming a semiconductor device includes: forming a conductive layer; removing a portion of the conductive layer to define a recess between a first conductive component formed by the conductive layer and a second conductive component formed by the conductive layer. Forming a first passivation layer in the recess between the first conductive component and the second conductive component. Forming a second passivation layer in the recess between the first conductive component and the second conductive component and above the first passivation layer. The lowest portion of the interface where the first passivation layer contacts the second passivation layer is located below 40% or above 60% of the height of the first conductive component.

[0065] In some embodiments, at least one of forming the first passivation layer or forming the second passivation layer includes performing a high density plasma deposition process.

[0066] In some embodiments, a method of forming a semiconductor device includes: forming a third passivation layer in a recess between a first conductive component and a second conductive component and above the second passivation layer. The lowest portion of an interface where the first passivation layer contacts the second passivation layer is located below 40% of a height of the first conductive component. The lowest portion of an interface where the second passivation layer contacts the third passivation layer is located above 60% of a height of the first conductive component.

[0067] In some embodiments, a method of forming a semiconductor device includes forming an encapsulation layer over a first conductive component and a second conductive component. A first passivation layer is over the encapsulation layer.

[0068] In some embodiments, a method of forming a semiconductor device includes: etching a second passivation layer and a first passivation layer to define a second recess; and forming an under bump metallurgy (UBM) layer in the second recess.

[0069] In some embodiments, the first passivation layer and the second passivation layer include the same material composition.

[0070] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art may better understand the various aspects of the present disclosure. Those of ordinary skill in the art should understand that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the various embodiments described herein. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may be variously modified, substituted, and altered herein without departing from the spirit and scope of the present disclosure.

[0071] Although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some embodiments.

[0072] Various operations of the embodiments are provided herein. The order of describing some or all operations should not be interpreted as implying that these operations are necessarily related to the order. With the benefit of this description, alternative sequencing will be appreciated. In addition, it will be understood that not all operations must be present in each embodiment provided herein. Moreover, it will be understood that not all operations are required in some embodiments.

[0073] It should be understood that, for example, for the purpose of simplicity and ease of understanding, the layers, components, elements, etc. depicted herein are shown with specific dimensions relative to each other (such as structural dimensions or directions), and in some embodiments, their actual dimensions are substantially different from those shown herein. In addition, there are a variety of techniques for forming the layers, regions, components, elements, etc. mentioned herein, such as etching techniques, planarization techniques, implantation techniques, doping techniques, at least one of spin coating techniques, sputtering techniques, growth techniques, or deposition techniques (such as CVD).

[0074] In addition, "exemplary" is used herein to represent examples, instances, explanations, etc., and is not necessarily advantageous. As used in the present application, "or" is intended to represent inclusive "or" rather than exclusive "or". In addition, "a" used in the present application and the present disclosure is generally interpreted as meaning "one or more", unless otherwise specified or clearly pointed to the singular form from the context. Moreover, at least one of A and B, etc. generally represents A or B, or both A and B. In addition, to a certain extent, the use of "including", "having", "having" or its variants is intended to be inclusive, similar to belonging to "comprising". Unless otherwise specified, "first", "second", etc. do not imply time, space, order, etc. On the contrary, these terms are only used as identifiers, names, etc. of parts, elements, items, etc. For example, the first element and the second element generally correspond to element A and element B or two different elements or two consistent elements or the same element.

[0075] In addition, although the present disclosure has been shown and described with respect to one or more embodiments, based on the reading and understanding of this specification and the accompanying drawings, those of ordinary skill in the art will think of equivalent changes and modifications. The present disclosure includes all such modifications and changes, and is limited only by the scope of the components. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe such components are intended to correspond to any components that perform the specified functions of the components. The described components (e.g., functionally equivalent) are not structurally equivalent to the disclosed structures. In addition, although the specific components of the present disclosure may have been disclosed with respect to only one embodiment in several embodiments, such components may be combined with one or more other components of other embodiments as may be desired and advantageous according to any given or specific application.

Claims

1. A semiconductor device, comprising: a first conductive member; a second conductive member; a first passivation layer, located between the first conductive component and the second conductive component and covering the first conductive component and the second conductive component; as well as a second passivation layer, located between the first conductive component and the second conductive component and above the first passivation layer, wherein a lowest portion of a first interface where the first passivation layer contacts the second passivation layer is located below 40% of a height of the first conductive component, a third passivation layer, located between the first conductive component and the second conductive component and above the second passivation layer, wherein the lowest portion of a second interface where the second passivation layer contacts the third passivation layer is located above 60% of the height of the first conductive component, A stress concentration area is defined between 40% and 60% of the height of the first conductive component and the second conductive component, and wherein, between the first conductive component and the second conductive component, the second interface is surrounded by the first interface and the lowest portion of the first interface and the lowest portion of the second interface are located outside the stress concentration area.

2. The semiconductor device according to claim 1, comprising: An encapsulation layer is above the first conductive component and the second conductive component, wherein the first passivation layer is located above the encapsulation layer.

3. The semiconductor device according to claim 1, comprising: a nitride layer, over the second passivation layer; as well as An under bump metallurgy layer extends through the nitride layer.

4. The semiconductor device according to claim 1, comprising: The under bump metallization layer contacts the side wall of the second passivation layer.

5. The semiconductor device according to claim 1, comprising: An under bump metallurgy layer extends through the second passivation layer and the first passivation layer and contacts at least one of the first conductive component or the second conductive component.

6. The semiconductor device according to claim 1, wherein The first passivation layer and the second passivation layer have the same material composition.

7. A semiconductor device comprising: a first conductive member; a second conductive member; a first passivation layer, located between the first conductive component and the second conductive component and covering the first conductive component and the second conductive component; a second passivation layer between the first conductive component and the second conductive component and above the first passivation layer; as well as a third passivation layer located between the first conductive component and the second conductive component and above the second passivation layer, wherein: The lowest portion of the interface where the first passivation layer contacts the second passivation layer is located below 40% of the height of the first conductive component, and The lowest part of the interface where the second passivation layer contacts the third passivation layer is located above 60% of the height of the first conductive component. The first passivation layer, the second passivation layer and the third passivation layer include the same material composition.

8. The semiconductor device according to claim 7, further comprising a stress concentration region defined between 40% and 60% of the height of the first conductive component and the second conductive component, and wherein A lowest portion of an interface where the first passivation layer contacts the second passivation layer is located outside the stress concentration region.

9. The semiconductor device according to claim 7, wherein: The first passivation layer, the second passivation layer, and the third passivation layer include silicon dioxide.

10. The semiconductor device according to claim 7, comprising: An encapsulation layer is above the first conductive component and the second conductive component, wherein the first passivation layer is located above the encapsulation layer.

11. The semiconductor device according to claim 7, comprising: a nitride layer, above the third passivation layer; as well as An under bump metallurgy layer extends through the nitride layer, the third passivation layer, the second passivation layer, and the first passivation layer to contact at least one of the first conductive component or the second conductive component.

12. The semiconductor device according to claim 7, comprising: A fourth passivation layer is over the third passivation layer.

13. The semiconductor device according to claim 7, comprising: A nitride layer is above the third passivation layer.

14. The semiconductor device according to claim 7, wherein: The first conductive member and the second conductive member include metal.

15. A method of forming a semiconductor device, comprising: forming a conductive layer; removing a portion of the conductive layer to define a recess between a first conductive feature formed by the conductive layer and a second conductive feature formed by the conductive layer; forming a first passivation layer in the recess between the first conductive component and the second conductive component; as well as forming a second passivation layer in the recess between the first conductive component and the second conductive component and over the first passivation layer; A third passivation layer is formed in the recess between the first conductive component and the second conductive component and over the second passivation layer, wherein: The lowest portion of the first interface where the first passivation layer contacts the second passivation layer is located below 40% of the height of the first conductive component, and The lowest portion of the second interface where the second passivation layer contacts the third passivation layer is located above 60% of the height of the first conductive component. wherein a stress concentration region is defined between 40% and 60% of the height of the first conductive component and the second conductive component, and wherein, between the first conductive component and the second conductive component, the second interface is surrounded by the first interface and the lowest portion of the first interface and the lowest portion of the second interface are located outside the stress concentration region.

16. The method according to claim 15, wherein: At least one of forming the first passivation layer or forming the second passivation layer includes performing a high density plasma deposition process.

17. The method according to claim 15, wherein: The first passivation layer, the second passivation layer, and the third passivation layer include the same material composition.

18. The method according to claim 15, comprising: An encapsulation layer is formed over the first conductive component and the second conductive component, wherein the first passivation layer is located over the encapsulation layer.

19. The method according to claim 15, comprising: etching the second passivation layer and the first passivation layer to define a second recess; as well as An under bump metallurgy layer is formed in the second recess.

20. The method according to claim 15, wherein: The first passivation layer and the second passivation layer include silicon dioxide.

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