Display device

Abstract

An exemplary embodiment of the present invention relates to a display device, the display device comprising: a first thin-film transistor including a first semiconductor layer and a first gate electrode, the first semiconductor layer including a first channel region, a first source region and a first drain region; a third thin-film transistor including a third semiconductor layer and a third gate electrode, the third semiconductor layer including a third channel region, a third source region and a third drain region, wherein the leakage current of the third thin-film transistor in a cutoff state is less than the leakage current of the first thin-film transistor in a cutoff state; and a pixel electrode connected to one of the first source region and the first drain region, wherein the one of the first source region and the first drain region is connected to the third thin-film transistor.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0016630, filed on February 11, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device, and more particularly to a display device for preventing or minimizing flicker when displaying images at low frequencies. Background Technology

[0004] Display devices are typically used to display a variety of images. A wide range of display devices, including but not limited to electroluminescent displays, liquid crystal displays, light-emitting diode displays, plasma displays, and quantum dot displays, have been developed. In example applications, display devices can be used to display advertising images. Advertising images displayed by a display device can include still images, but not moving images. In contrast to moving images, still images can be a single static image. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a display device is provided, the display device comprising: a first thin-film transistor including a first semiconductor layer and a first gate electrode, the first semiconductor layer including a first channel region, a first source region and a first drain region; a third thin-film transistor including a third semiconductor layer and a third gate electrode, the third semiconductor layer including a third channel region, a third source region and a third drain region, one of the third source region and the third drain region being electrically connected to the first gate electrode, and the other of the third source region and the third drain region being electrically connected to one of the first source region and the first drain region, wherein the leakage current of the third thin-film transistor in the off state is less than the leakage current of the first thin-film transistor in the off state; and a pixel electrode electrically connected to one of the first source region and the first drain region, the first of the first source region and the first drain region being electrically connected to the third thin-film transistor.

[0006] The grain boundary trap density of a portion of the third semiconductor layer may be less than that of the first semiconductor layer.

[0007] The grain boundary trap density of the portion of the third semiconductor layer may be approximately 0.2 to approximately 0.5 times that of the grain boundary trap density of the first semiconductor layer.

[0008] The grain boundary trap density of the portion of the third channel region near the third drain region can be less than the grain boundary trap density of the first semiconductor layer.

[0009] The grain boundary trap density of the third drain region can be less than the grain boundary trap density of the first semiconductor layer.

[0010] The hydrogen concentration in a portion of the third semiconductor layer can be greater than the hydrogen concentration in the first semiconductor layer.

[0011] The hydrogen concentration of the portion of the third semiconductor layer may be approximately 1.5 to approximately 5 times that of the hydrogen concentration of the first semiconductor layer.

[0012] The hydrogen concentration in the portion of the third channel region near the third drain region may be less than the hydrogen concentration in the first semiconductor layer.

[0013] The hydrogen concentration in the third drain region can be less than the hydrogen concentration in the first semiconductor layer.

[0014] A portion of the third semiconductor layer can be treated with hydrogen plasma.

[0015] The portion of the third channel region near the third drain region can be treated with hydrogen plasma.

[0016] The third drain region can be treated with hydrogen plasma.

[0017] A portion of the third semiconductor layer can be crystallized by performing excimer laser annealing multiple times.

[0018] The portion of the third channel region near the third drain region can be crystallized by performing excimer laser annealing multiple times.

[0019] The third drain region can be crystallized by performing excimer laser annealing multiple times.

[0020] The first semiconductor layer may be positioned on the first layer, and the third semiconductor layer may be positioned on the third layer.

[0021] The third layer may overlap with the first layer.

[0022] The third gate electrode can be positioned on the third semiconductor layer.

[0023] The display device may further include a bottom metal layer positioned below the third layer to correspond to the third gate electrode.

[0024] The bottom metal layer can be electrically connected to the third gate electrode.

[0025] The potential of the bottom metal layer can be equal to the potential of the third gate electrode.

[0026] According to an exemplary embodiment of the present invention, a display device is provided, the display device comprising: a driving thin-film transistor including a driving gate electrode, a driving source region, and a driving drain region; a compensation thin-film transistor including a compensation gate electrode, a compensation source region, and a compensation drain region, the compensation drain region being electrically connected to the driving gate electrode, and the compensation source region being electrically connected to the driving drain region, wherein the leakage current of the compensation thin-film transistor in the off state is less than the leakage current of the driving thin-film transistor in the off state; and a pixel electrode electrically connected to the driving drain region and the compensation source region.

[0027] The grain boundary trap density of the compensation semiconductor layer portion of the compensation thin-film transistor can be less than the grain boundary trap density of the driving semiconductor layer of the driving thin-film transistor.

[0028] The hydrogen concentration of the compensation semiconductor layer of the compensation thin-film transistor can be greater than the hydrogen concentration of the driving semiconductor layer of the driving thin-film transistor.

[0029] According to an exemplary embodiment of the present invention, a display device is provided, the display device comprising: a first thin-film transistor including a first terminal, a second terminal and a third terminal; a second thin-film transistor including a fourth terminal, a fifth terminal and a sixth terminal, the fifth terminal being directly connected to the first terminal and the sixth terminal being directly connected to the second terminal, wherein the leakage current of the second thin-film transistor in the off state is less than the leakage current of the first thin-film transistor in the off state; and a pixel electrically connected to the second terminal and the sixth terminal. Attached Figure Description

[0030] The above and other features of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a perspective view of a portion of a display device according to an exemplary embodiment of the present invention.

[0032] Figure 2 This is an exemplary embodiment of the concept of the present invention, including Figure 1 The equivalent circuit diagram of (sub)pixels in a display device;

[0033] Figure 3 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 2 A diagram showing the arrangement of multiple thin-film transistors, capacitors, etc. in a (sub)pixel;

[0034] Figure 4 This is an exemplary embodiment of the concept of the present invention. Figure 3 A cross-sectional view of a portion of the display device;

[0035] Figure 5 It is a graph showing the relationship between brightness change and time in a display device according to a comparative example;

[0036] Figure 6 It is a graph showing the relationship between brightness change and time in a display device according to an exemplary embodiment of the present invention;

[0037] Figure 7 It is a graph showing the relationship between leakage current and drive range;

[0038] Figure 8 Such as exemplary embodiments of the present invention. Figure 3 A layer arrangement diagram of multiple thin-film transistors, capacitors, and other components;

[0039] Figure 9 and Figure 10 It is a graph showing the hydrogen concentration of elements in a display device according to an exemplary embodiment;

[0040] Figure 11 This is a cross-sectional view of a portion of a display device according to another exemplary embodiment of the present invention; and

[0041] Figure 12 This is a cross-sectional view of a portion of a display device according to another exemplary embodiment of the present invention. Detailed Implementation

[0042] Exemplary embodiments of the inventive concept will now be described with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0043] In the accompanying drawings, the same reference numerals may denote the same elements or corresponding elements.

[0044] It will be understood that when a layer, area, or component is referred to as being "formed" "on" another layer, area, or component, the layer, area, or component may be formed directly on the other layer, area, or component, or intermediate layers, areas, or components may exist. For ease of interpretation, the dimensions of elements in the accompanying drawings may be exaggerated or reduced.

[0045] In the examples below, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or can represent different directions that are not perpendicular to each other.

[0046] Figure 1This is a perspective view of a portion of a display device 1 according to an exemplary embodiment of the present invention. Figure 1 As shown, the display device 1 according to this embodiment may include a display area DA and a peripheral area PA. The display device 1 may include a substrate 101 (see...). Figure 4 The shape of the substrate 101 is not limited to... Figure 1 The substrate 101 is a rectangular shape (in the xy-plane) as shown, and can have various shapes such as circular shapes or curved corners. Additionally, the substrate 101 can have bent regions and can be bent within these regions. In other words, the substrate 101 can be flexible.

[0047] The substrate 101 may include glass or metal. Additionally, the substrate 101 may include a variety of flexible, bendable, or rollable materials. For example, the substrate 101 may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate.

[0048] The substrate 101 may have a multilayer structure, comprising two layers including a polymer resin and a barrier layer comprising an inorganic material between the two layers. Various modifications are possible. For example, the barrier layer may include silicon oxide, silicon nitride, and silicon oxynitride.

[0049] Multiple display elements can be positioned within the display area DA. For example, the display elements may include organic light-emitting diodes (OLEDs) (see [link to display area DA]). Figure 2 It can emit red, green, blue, or white light. The (sub)pixels positioned in the display area DA of the display device 1 include organic light-emitting diodes (OLEDs), and also include thin-film transistors, capacitors, etc., for controlling the emission level of the OLEDs. The display area DA can be the area in the display device 1 used to display images.

[0050] Drivers, power lines, etc., can be arranged in the peripheral area PA. Additionally, the peripheral area PA may include pad areas, which are areas where various electronic components, such as driver integrated circuits and printed circuit boards, are electrically attached. Images cannot be displayed in the peripheral area PA.

[0051] Figure 2 It is positioned in accordance with an exemplary embodiment of the present invention. Figure 1The equivalent circuit diagram of a (sub)pixel in the display area DA of the display device 1. The pixel circuit PC located in a (sub)pixel SPX may include multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. The thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and the storage capacitor Cst, may be connected to signal lines SL, SL-1, SL+1, EL, and DL, including a first initialization voltage line VL1 (see...). Figure 3 ) and the second initialization voltage line VL2 (see Figure 3 The initialization voltage line VL and the drive voltage line PL.

[0052] Signal lines SL, SL-1, SL+1, EL, and DL can include scan line SL, previous scan line SL-1, next scan line SL+1, emit control line EL, and data line DL. For example, scan line SL sends scan signal Sn, previous scan line SL-1 sends previous scan signal Sn-1 to first initialization thin-film transistor T4, next scan line SL+1 sends scan signal Sn to second initialization thin-film transistor T7, emit control line EL sends emit control signal En to operation control thin-film transistor T5 and emit control thin-film transistor T6, and data line DL intersects with scan line SL (e.g., ...). Figure 3 (As shown in the diagram) and sends a data signal Dm. The drive voltage line PL can send the drive voltage ELVDD to the drive thin film transistor T1, the first initialization voltage line VL1 can send the initialization voltage Vint to the first initialization thin film transistor T4, and the second initialization voltage line VL2 can send the initialization voltage Vint to the second initialization thin film transistor T7.

[0053] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the bottom electrode Cst1 of the storage capacitor Cst. The driving source region S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL through the operation control thin-film transistor T5, and the driving drain region D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) through the emission control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm depending on the switching operation of the switching thin-film transistor T2, and drives the driving current I... OLED It is supplied to organic light-emitting diodes (OLEDs).

[0054] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL, the switching source region S2 of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain region D2 of the switching thin-film transistor T2 is connected to the driving source region S1 of the driving thin-film transistor T1 and is connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal Sn sent through the scan line SL and performs a switching operation to send the data signal Dm sent through the data line DL to the driving source region S1 of the driving thin-film transistor T1.

[0055] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. The compensation source region S3 of the compensation thin-film transistor T3 is connected to the driving drain region D1 of the driving thin-film transistor T1 and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation drain region D3 of the compensation thin-film transistor T3 is also connected to the bottom electrode Cst1 of the storage capacitor Cst, the first initialization drain region D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn transmitted via the scan line SL, and is connected to the driving thin-film transistor T1 in a diode manner by electrically connecting the driving gate electrode G1 of the driving thin-film transistor T1 to the driving drain region D1 of the driving thin-film transistor T1. The compensation gate electrode G3 of the compensation thin-film transistor T3 can be a dual-gate electrode. The compensation drain region D3 can be directly connected to the driving gate electrode G1 of the driving thin-film transistor T1, and the compensation source region S3 can be directly connected to the driving drain region D1 of the driving thin-film transistor T1.

[0056] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1, the first initialization source region S4 of the first initialization thin-film transistor T4 is connected to the first initialization voltage line VL1, and the first initialization drain region D4 of the first initialization thin-film transistor T4 is connected to the bottom electrode Cst1 of the storage capacitor Cst, the compensation drain region D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1 sent through the previous scan line SL-1, and performs an initialization operation by sending the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1 to initialize the voltage of the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization gate electrode G4 of the first initialization thin-film transistor T4 can be a dual-gate electrode.

[0057] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emitter control line EL, the operation control source region S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain region D5 of the operation control thin film transistor T5 is connected to the drive source region S1 of the drive thin film transistor T1 and the switch drain region D2 of the switch thin film transistor T2.

[0058] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source region S6 of the emission control thin film transistor T6 is connected to the driving drain region D1 of the driving thin film transistor T1 and the compensation source region S3 of the compensation thin film transistor T3, and the emission control drain region D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source region S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0059] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on in response to the emission control signal En sent via the emission control line EL. In this case, the drive voltage ELVDD is sent to the organic light-emitting diode OLED, and the drive current I... OLED It flows through an organic light-emitting diode (OLED).

[0060] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the next scan line SL+1, the second initialization source region S7 of the second initialization thin film transistor T7 is connected to the emission control drain region D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light-emitting diode OLED, and the second initialization drain region D7 of the second initialization thin film transistor T7 is connected to the second initialization voltage line VL2.

[0061] Since the scan line SL is electrically connected to the next scan line SL+1, the same scan signal Sn can be applied to both scan line SL and the next scan line SL+1. Therefore, the second initialization thin-film transistor T7 can be turned on in response to the scan signal Sn sent through the next scan line SL+1, and can perform the operation of initializing the pixel electrodes of the organic light-emitting diode OLED.

[0062] The top electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the common electrode of the organic light-emitting diode (OLED) is connected to the common voltage ELVSS. Therefore, the OLED can receive a driving current I from the driving thin-film transistor T1. OLED It also emits light to display images.

[0063] although Figure 2The diagram shows that the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 each have dual gate electrodes, but the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may each have a single gate electrode.

[0064] Figure 3 This is an exemplary embodiment of the concept of the present invention. Figure 2 An arrangement diagram of the positions of multiple thin-film transistors, capacitors, etc. in a (sub)pixel, and Figure 4 This is an exemplary embodiment of the concept of the present invention. Figure 3 A cross-sectional view of a portion of the display device.

[0065] Driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7 are arranged along semiconductor layer 1130. Some regions of semiconductor layer 1130 can constitute the semiconductor layer for driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7. In other words, some regions of semiconductor layer 1130 can constitute the channel region, source region, or drain region of the thin-film transistor.

[0066] Semiconductor layer 1130 may be formed over substrate 101. Buffer layer 111 may be formed on substrate 101, and semiconductor layer 1130 may be formed on buffer layer 111.

[0067] Buffer layer 111 can reduce or prevent the penetration of foreign matter, moisture, or outside air from under substrate 101 and can provide a flat surface on substrate 101. Buffer layer 111 can include inorganic materials such as oxides or nitrides, organic materials, or organic / inorganic composite materials, and can include a single-layer structure or a multi-layer structure of inorganic and organic materials. For example, buffer layer 111 can have a structure with a first buffer layer 111a and a second buffer layer 111b stacked. The first buffer layer 111a can be in direct contact with substrate 101. In this case, the first buffer layer 111a can include a material different from the material of the second buffer layer 111b. For example, the first buffer layer 111a can include silicon nitride, and the second buffer layer 111b can include silicon oxide.

[0068] As described above, when the first buffer layer 111a comprises silicon nitride, hydrogen can be included simultaneously with the formation of the silicon nitride. Since the carrier mobility of the semiconductor layer 1130 formed on the buffer layer 111a is improved, the electrical characteristics of the thin-film transistor (TFT) can be improved. Alternatively, the semiconductor layer 1130 can comprise a silicon material and can be directly disposed on the second buffer layer 111b. In this case, since the interface bonding characteristics between the silicon-containing semiconductor layer 1130 and the silicon oxide-containing second buffer layer 111b are improved, the electrical characteristics of the thin-film transistor can be improved.

[0069] Semiconductor layer 1130 may include low-temperature polycrystalline silicon (LTPS). Due to the high electron mobility (100 cm⁻¹), polycrystalline silicon... 2 Polycrystalline silicon (PS) offers low power consumption and high reliability (Vs or higher). In another example, semiconductor layer 1130 may comprise amorphous silicon (a-Si) and / or oxide semiconductors. Alternatively, some semiconductor layers in the plurality of thin-film transistors may comprise LTPS, and other semiconductor layers may comprise a-Si and / or oxide semiconductors.

[0070] The first gate insulating layer 112 is positioned on the semiconductor layer 1130. The scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL can be positioned on the first gate insulating layer 112.

[0071] The first gate insulating layer 112 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0072] The regions of scan line SL that overlap with the channel regions of switching thin-film transistor T2 and compensation thin-film transistor T3 may respectively include the switching gate electrode G2 and the compensation gate electrode G3. The region of the preceding scan line SL-1 that overlaps with the channel region of the first initialization thin-film transistor T4 may include the first initialization gate electrode G4, and the region of the next scan line SL+1 that overlaps with the channel region of the second initialization thin-film transistor T7 may include the second initialization gate electrode G7. Additionally, the regions of emitter control line EL that overlap with operation control thin-film transistor T5 and emitter control thin-film transistor T6 may respectively include the operation control gate electrode G5 and the emitter control gate electrode G6.

[0073] The second gate insulating layer 113 can be provided on the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL. The second gate insulating layer 113 may include silicon oxide (SiO2) or silicon nitride (SiN). xThe materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The second gate insulating layer 113 may cover the emitter control gate electrode G6 of the emitter control thin film transistor T6.

[0074] Electrode voltage line HL, first initialization voltage line VL1, and second initialization voltage line VL2 can be arranged on the second gate insulating layer 113. Electrode voltage line HL can cover at least a portion of the driving gate electrode G1 of the driving thin film transistor T1, and can together with the driving gate electrode G1 of the driving thin film transistor T1 form a storage capacitor Cst.

[0075] The bottom electrode Cst1 of the storage capacitor Cst can be formed as a single body with the driving gate electrode G1 of the driving thin-film transistor T1. For example, the driving gate electrode G1 of the driving thin-film transistor T1 can be used as the bottom electrode Cst1 of the storage capacitor Cst. The region of the electrode voltage line HL that overlaps with the driving gate electrode G1 can include the top electrode Cst2 of the storage capacitor Cst. Therefore, the second gate insulating layer 113 can be used as the dielectric layer of the storage capacitor Cst.

[0076] An interlayer insulating layer 115 is positioned on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The interlayer insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0077] Data line DL, drive voltage line PL, first initialization connection line 1173a and second initialization connection line 1173b, node connection line 1174, and connecting metal 1175 can be arranged on the interlayer insulation layer 115. The first initialization connection line 1173a and the second initialization connection line 1173b can be arranged along... Figure 3 The data lines DL and PL are spaced apart from each other along the y-direction. The data lines DL and PL can be adjacent to each other and can extend along the y-direction. The data lines DL, PL, node connection lines 1174, and connection metal 1175 can include conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can have a single-layer or multi-layer structure comprising these materials. For example, the data lines DL, PL, PL, PL, and connection metal 1175 can have a Ti / Al / Ti multi-layer structure.

[0078] The data line DL can be connected to the switching source region S2 of the switching thin-film transistor T2 through contact hole 1154. A portion of the data line DL may include the switching source region S2 of the switching thin-film transistor T2.

[0079] The driving voltage line PL can be connected to the top electrode Cst2 of the storage capacitor Cst through a contact hole 1158 formed in the interlayer insulating layer 115. Therefore, the electrode voltage line HL can have the same voltage level as the driving voltage line PL (e.g., a constant voltage). Additionally, the driving voltage line PL can be connected to the operation control drain region D5 of the operation control thin-film transistor T5 through a contact hole 1155.

[0080] The first initialization voltage line VL1 can be connected to the first initialization thin-film transistor T4 via the first initialization connection line 1173a, and the second initialization voltage line VL2 can be electrically connected to the second initialization thin-film transistor T7 via the second initialization connection line 1173b and vias 1151 and 1152. The first initialization voltage line VL1 can have the same constant voltage (e.g., -2V) as the constant voltage of the second initialization voltage line VL2.

[0081] One end of the node connection line 1174 can be connected to the compensation drain region D3 of the compensation thin film transistor T3 through the contact hole 1156, and the other end of the node connection line 1174 can be connected to the driving gate electrode G1 of the driving thin film transistor T1 through the contact hole 1157.

[0082] The connecting metal 1175 can be connected to the semiconductor layer 1130 of the emission control thin-film transistor T6 through contact holes 1153 passing through the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control thin-film transistor T6 can be electrically connected to the pixel electrode 210 of the organic light-emitting diode OLED through the connecting metal 1175. For example, the pixel electrode 210 of the organic light-emitting diode OLED and the connecting metal 1175 can be in contact with each other on the top side of the interlayer insulating layer 115.

[0083] The planarization layer 117 can be positioned on the data line DL, the driving voltage line PL, the first initialization connection line 1173a and the second initialization connection line 1173b, the node connection line 1174, and the connection metal 1175. The organic light-emitting diode (OLED) can be positioned on the planarization layer 117.

[0084] Despite Figure 2 and Figure 3The structure of a pixel circuit PC is described, but multiple (sub)pixels SPX, each having the same pixel circuit PC, can be arranged in a first direction (x-axis direction) and a second direction (y-axis direction). In this case, the first initialization voltage line VL1, the previous scan line SL-1, the second initialization voltage line VL2, and the next scan line SL+1 can be shared by two pixel circuit PCs that are adjacent to each other in the second direction (y-axis direction).

[0085] In other words, the first initialization voltage line VL1 and the previous scan line SL-1 can be electrically connected to a line arranged in the second direction (y-axis direction). Figure 3 The second initialization thin-film transistor T7 of another pixel circuit PC above the pixel circuit PC shown in the figure. Therefore, the previous scan signal applied to the previous scan line SL-1 can be sent as the next scan signal to the second initialization thin-film transistor T7 of the other pixel circuit PC. In addition, the second initialization voltage line VL2 and the next scan line SL+1 can be electrically connected to the second initialization thin-film transistor T7 adjacent to the pixel circuit PC in the second direction (y-axis direction). Figure 3 The first initialization thin-film transistor T4 is shown below the pixel circuit PC. In this case, the previous scan signal and the initialization voltage can be sent to the first initialization thin-film transistor T4 of the other pixel circuit PC.

[0086] Refer again Figure 4 The planarization layer 117 may have a flat top surface, allowing the pixel electrode 210 to be formed flat. The planarization layer 117 may include organic materials and may include a single-layer or multi-layer structure. The planarization layer 117 may include polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS); polymer derivatives having phenolic groups; acrylic polymers; imide polymers; aryl ether polymers; amide polymers; fluoropolymers; p-xylyl polymers; vinyl alcohol polymers; or mixtures thereof. The planarization layer 117 may include inorganic materials. The planarization layer 117 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). When the planarization layer 117 comprises an inorganic material, chemical planarization polishing can be performed. The planarization layer 117 may comprise both organic and inorganic materials.

[0087] An organic light-emitting diode (OLED) may include a pixel electrode 210, a common electrode 230, and an intermediate layer 220 between the pixel electrode 210 and the common electrode 230, the intermediate layer 220 including an emission layer.

[0088] Pixel electrode 210 can be connected to connection metal 1175 through contact hole 1163, and connection metal 1175 can be connected to the emitter control drain region D6 of emitter control thin-film transistor T6 through contact hole 1153. Pixel electrode 210 may include a (semi-)transparent electrode or a reflective electrode. In an exemplary embodiment of the present invention, pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer, the reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In an exemplary embodiment of the present invention, pixel electrode 210 may include a stacked structure of ITO / Ag / ITO.

[0089] A pixel defining layer 119 can be disposed on a planarization layer 117. The pixel defining layer 119 can define the emission region of a pixel by including an opening that exposes the central portion of the pixel electrode 210. The pixel defining layer 119 can prevent arcing or the like at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the common electrode 230 above the pixel electrode 210. The pixel defining layer 119 can comprise an organic insulating material including polyimide, polyamide, acrylic resin, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), and phenolic resin, and can be formed by spin coating.

[0090] The intermediate layer 220 may include an organic emitting layer. The organic emitting layer may include organic materials that emit red, green, blue, or white light, such as fluorescent or phosphorescent materials. The organic emitting layer may include low molecular weight organic materials or polymer materials. Functional layers may be disposed below and / or on top of the organic emitting layer, and these functional layers may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL). The intermediate layer 220 may be arranged to correspond to a plurality of pixel electrodes 210. However, the intermediate layer 220 is not limited thereto, and layers such as HTL, HIL, ETL, or EIL included in the intermediate layer 220 may be arranged as a single body on the plurality of pixel electrodes 210.

[0091] The common electrode 230 may include a transparent electrode or a reflective electrode. In an exemplary embodiment of the present invention, the common electrode 230 may include a transparent electrode or a semi-transparent electrode, and may include a thin metal layer with a small work function, including Li, Ca, lithium fluoride (LiF) / Ca, LiF / Al, Ag, Mg, and compounds thereof. Additionally, the common electrode 230 may also include a transparent conductive oxide (TCO) layer including ITO, IZO, ZnO, or In2O3. The common electrode 230 may be formed as a single body to correspond to multiple pixel electrodes 210.

[0092] The encapsulation layer 300 can be positioned on the common electrode 230. The encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 320, and an organic encapsulation layer 330 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320.

[0093] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 may include silicon oxide (SiO2) and silicon nitride (SiN). x The organic encapsulation layer 330 may comprise polyethylene terephthalate (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The organic encapsulation layer 330 may comprise polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane (HMDSO), acrylic resin (e.g., polymethyl methacrylate (PMMA), polyacrylic acid, etc.), or any combination thereof.

[0094] In the display device according to this embodiment, one of the compensation source region S3 (e.g., a third source region) and the compensation drain region D3 (e.g., a third drain region) of the compensation thin-film transistor T3 is electrically connected to the driving gate electrode G1 (e.g., a first gate electrode) of the driving thin-film transistor T1, and the other of the compensation source region S3 and the compensation drain region D3 is electrically connected to one of the driving source region S1 (e.g., a first source region) and the driving drain region D1 (e.g., a first drain region) of the driving thin-film transistor T1. The compensation thin-film transistor T3 may be the third thin-film transistor described above, and the driving thin-film transistor T1 may be the first thin-film transistor described above. The pixel electrode 210 is electrically connected to one of the driving source region S1 and the driving drain region D1 of the driving thin-film transistor T1, and the one of the driving source region S1 and the driving drain region D1 of the driving thin-film transistor T1 is connected to the compensation thin-film transistor T3. In addition, the leakage current of the compensation thin-film transistor T3 in the off state is less than the leakage current of the driving thin-film transistor T1 in the off state. For example, the leakage current of the compensation thin-film transistor T3 can be approximately 1.1 × 10⁻⁶. -15A (i.e., approximately 1.1fA), and the leakage current driving the thin-film transistor T1 can be approximately 1.4 × 10⁻⁶. -15 A (i.e., approximately 1.4fA).

[0095] Figure 5 This is a graph showing the relationship between brightness variation and time in a display device according to the comparative example. Typically, the display device displays moving images at 60 Hz. However, when displaying still images such as static, non-moving advertisements, the display device can display the still image at a frequency less than 60 Hz. However, even when displaying still images at a low frequency, flickering occurs on the screen of the display device according to the comparative example.

[0096] Figure 5 The brightness variation is shown when the display device displays a still image at 30 Hz. Figure 5 The image shows a brightness of around 100 at the start of a frame, decreasing over time until the frame ends. Then, at the start of the next frame, the brightness again approaches 100. This increase in brightness at the start of a new frame causes flickering on the screen. More specifically, a large brightness variation occurs because leakage current appears in the compensation thin-film transistor T3, thus changing the voltage at the driving gate electrode G1 of the thin-film transistor T1 connected to the compensation source region S3 or compensation drain region D3 of the compensation thin-film transistor T3. Therefore, the amount of current applied to the organic light-emitting diode (OLED) through the driving thin-film transistor T1 is reduced, and thus the brightness is decreased.

[0097] Figure 6 This is a graph illustrating the relationship between brightness variation and time in a display device according to an exemplary embodiment of the present invention. Figure 5 compared to, Figure 6 The brightness variation is relatively small. Therefore, in the display device according to this embodiment, flicker is minimized or imperceptible even when displaying a still image at a low frequency. This is because the leakage current of the compensation thin-film transistor T3 in the off state is less than the leakage current of the driving thin-film transistor T1 in the off state.

[0098] Figure 7 This is a graph showing the relationship between leakage current and drive range. The horizontal axis represents the leakage current of the thin-film transistor in fA, and the vertical axis represents the drive range of the thin-film transistor in V. The drive range represents the range of the gate voltage that regulates the amount of current flowing between the source and drain electrodes of the thin-film transistor. The amount of current flowing between the source and drain electrodes of the thin-film transistor is regulated by adjusting the voltage (e.g., the gate voltage) between the source and drain electrodes.

[0099] like Figure 7 As shown by points A, B, C, D, E, F, G, and H, the driving range tends to be proportional to the leakage current. In other words, as the leakage current decreases, the driving range narrows. For example, as... Figure 7 As shown, when the leakage current is represented by H, the driving range is approximately 2.0V; when the leakage current is represented by G, the driving range is approximately 2.3V; when the leakage current is represented by F, the driving range is approximately 2.8V; and when the leakage current is represented by C, the driving range is approximately 3V. Since the driving thin-film transistor T1 regulates the brightness of the light emitted from the organic light-emitting diode (OLED) by controlling the amount of current flowing through it, the driving range of T1 should be wide. In contrast, the compensation thin-film transistor T3 is designed to compensate for the threshold voltage of the driving thin-film transistor T1. Since only the on-off state of T3 needs to be compensated, the driving range of the compensation thin-film transistor T3 does not need to be wide.

[0100] Therefore, in the display device according to an exemplary embodiment of the present invention, the influence on the driving gate electrode G1 of the driving thin film transistor T1 can be minimized by reducing the leakage current of the compensation thin film transistor T3 in the off state (compared to the leakage current of the driving thin film transistor T1 in the off state). Thus, screen flicker can be minimized. Furthermore, by widening the driving range of the driving thin film transistor T1, fine brightness variations of the displayed image can be represented over a wide range.

[0101] To ensure that the leakage current of the compensation thin-film transistor T3 in the off-state is less than that of the driving thin-film transistor T1 in the off-state, the grain boundary trap density of at least a portion of the compensation semiconductor layer (e.g., a third semiconductor layer) can be less than the grain boundary trap density of the driving semiconductor layer (e.g., a first semiconductor layer). The compensation semiconductor layer includes a compensation source region S3, a compensation drain region D3, and a compensation channel region between the compensation source region S3 and the compensation drain region D3 of the compensation thin-film transistor T3. The driving semiconductor layer includes a driving source region S1, a driving drain region D1, and a driving channel region between the driving source region S1 and the driving drain region D1 of the driving thin-film transistor T1. The grain boundary trap density (e.g., Ntrap) can include the density of electrical defects, the density of uncoupled bonds in the semiconductor layer, and the density of dangling bonds. When the grain boundary trap density decreases, the leakage current decreases. The grain boundary trap density of at least a portion of the compensation semiconductor layer of the compensation thin-film transistor T3 can be approximately 0.2 to approximately 0.5 times the grain boundary trap density of the driving semiconductor layer of the driving thin-film transistor T1. In other words, the grain boundary trap density of at least a portion of the compensation semiconductor layer of the compensation thin-film transistor T3 can be less than the grain boundary trap density of the driving semiconductor layer of the driving thin-film transistor T1.

[0102] Leakage current can be generated by charge from the portion of the channel region of the semiconductor layer adjacent to the drain region. Therefore, the grain boundary trap density of the portion of the compensation channel region (e.g., the third channel region) adjacent to the compensation drain region D3 (e.g., the third drain region) can be made less than the grain boundary trap density of the driving semiconductor layer (e.g., the first semiconductor layer). This reduces the amount of leakage current generated from the compensation thin-film transistor T3. Alternatively, the grain boundary trap density of the compensation drain region D3 (e.g., the third drain region) can be made less than the grain boundary trap density of the driving semiconductor layer (e.g., the first semiconductor layer). This also reduces the amount of leakage current generated from the compensation thin-film transistor T3.

[0103] In a display device according to an exemplary embodiment of the present invention, the hydrogen concentration of at least a portion of the compensation semiconductor layer may be greater than the hydrogen concentration of the driving semiconductor layer. For example, the hydrogen concentration of at least a portion of the compensation thin-film transistor T3 may be approximately 1.5 to approximately 5 times the hydrogen concentration of the driving semiconductor layer.

[0104] As mentioned above, grain boundary trap density (e.g., Ntrap) can include the uncoupled bond density of a semiconductor layer. A high hydrogen concentration in a semiconductor layer can indicate a low uncoupled bond density. This is because uncoupled bonds are coupled to hydrogen, and therefore the uncoupled bond density becomes low. Therefore, a high hydrogen concentration in a semiconductor layer indicates a low grain boundary trap density, and thus does not indicate... Figure 5 The brightness reduction shown is negligible. In other words, in the display device of this embodiment, there is no significant brightness reduction.

[0105] Leakage current can be generated by charge from the portion of the channel region adjacent to the drain region of the semiconductor layer. Therefore, the hydrogen concentration in the compensation channel region (e.g., the third channel region) adjacent to the compensation drain region D3 (e.g., the third drain region) can be made lower than the hydrogen concentration in the driving semiconductor layer (e.g., the first semiconductor layer). This reduces the amount of leakage current generated from the compensation thin-film transistor T3. Alternatively, the hydrogen concentration in the compensation drain region D3 (e.g., the third drain region) can be made lower than the hydrogen concentration in the driving semiconductor layer (e.g., the first semiconductor layer). This also reduces the amount of leakage current generated from the compensation thin-film transistor T3.

[0106] To allow at least a portion of the compensation semiconductor layer to have a hydrogen concentration approximately 1.5 to 5 times that of the driving semiconductor layer, hydrogen plasma treatment can be performed on at least a portion of the compensation semiconductor layer. By doing so, the hydrogen concentration in a predetermined region of the compensation semiconductor layer increases and the grain boundary trap density decreases because hydrogen is coupled to the dangling bonds of the compensation semiconductor layer through the hydrogen plasma treatment, and therefore the magnitude of the leakage current can be reduced.

[0107] It can be like Figure 8Hydrogen plasma processing is performed over the entire region of the compensation semiconductor layer indicated by region TA1. For example, hydrogen plasma processing can be performed on the compensation drain region D3, the compensation source region S3, and the compensation channel region between the compensation drain region D3 and the compensation source region S3. Additionally, hydrogen plasma processing can be performed on... Figure 8 The portion of the compensation channel region indicated by region TA2 adjacent to the compensation drain region D3 is subjected to hydrogen plasma treatment. Alternatively, hydrogen plasma treatment can be performed on the compensation drain region D3 of the compensation semiconductor layer. Hydrogen plasma treatment may not be performed on the driving semiconductor layer. In fact, where possible, hydrogen plasma treatment can be performed to a minimum. This can further widen the driving range of the driving thin-film transistor T1.

[0108] Alternatively, at least a portion of the compensation semiconductor layer of the compensation thin-film transistor T3 can be crystallized by performing excimer laser annealing multiple times. This is because the leakage current of the thin-film transistor decreases when excimer laser annealing is performed multiple times. Specifically, the portion of the compensation channel region adjacent to the compensation drain region D3 can be crystallized by performing excimer laser annealing multiple times. In an alternative embodiment, the compensation drain region D3 of the compensation semiconductor layer can be subjected to excimer laser annealing multiple times.

[0109] Furthermore, at least a portion of the compensation semiconductor layer of the compensation thin-film transistor T3 can be crystallized by performing excimer laser annealing. Additionally, this at least portion of the compensation semiconductor layer of the compensation thin-film transistor T3 can be treated with hydrogen plasma. Specifically, after crystallizing the portion of the compensation channel region adjacent to the compensation drain region D3 by performing multiple excimer laser annealing operations, this portion can be treated with hydrogen plasma. In an alternative embodiment, the compensation drain region D3 of the compensation semiconductor layer can be subjected to multiple excimer laser annealing operations and hydrogen plasma treatment.

[0110] Figure 9 and Figure 10 This is a graph showing the hydrogen concentration of elements in a display device according to an exemplary embodiment of the present invention. For example... Figure 9 As shown, the hydrogen concentration under medium-intensity hydrogen plasma treatment (medium-intensity PT) is three times that under no hydrogen plasma treatment (untreated). The hydrogen concentration under strong hydrogen plasma treatment (strong PT) is five times that under no hydrogen plasma treatment (untreated). Figure 10The results show the case of performing hydrogen plasma treatment followed by heat treatment at approximately 400 °C for approximately 30 minutes. The results indicate that when a medium-intensity hydrogen plasma treatment (medium-intensity PT) is performed after two excimer laser annealing (two ELA treatments), the hydrogen concentration increases to approximately 1.63 times compared to the case without hydrogen plasma treatment (untreated).

[0111] Figure 11 This is a cross-sectional view of a portion of a display device according to another exemplary embodiment of the present invention. (See diagram below.) Figure 11 As shown, in the display device according to this embodiment, the layer on which the compensation semiconductor layer (e.g., the third semiconductor layer) is located is different from the layer on which the emission control semiconductor layer of the emission control thin-film transistor T6 is located. The layer on which the emission control semiconductor layer of the emission control thin-film transistor T6 is located is the same as the layer on which the driving thin-film transistor T1 is located. Therefore, the layer on which the compensation semiconductor layer (e.g., the third semiconductor layer) is located is different from the layer on which the driving thin-film transistor T1 is located.

[0112] As described above, it is required that the leakage current of the compensation thin-film transistor T3 in the off state is less than that of the driving thin-film transistor T1 in the off state. To achieve this, hydrogen plasma treatment or the like is performed on the semiconductor layer of the compensation thin-film transistor T3. During the hydrogen plasma treatment, the hydrogen plasma treatment should not affect the semiconductor layer of the driving thin-film transistor T1. By making the layer on which the compensation semiconductor layer (e.g., the third semiconductor layer) is located different from the layer on which the driving semiconductor layer of the driving thin-film transistor T1 is located, hydrogen plasma treatment or the like can be selectively performed only on the compensation semiconductor layer.

[0113] like Figure 11 As shown, similar to the emission control semiconductor layer of the emission control thin-film transistor T6, the driving semiconductor layer of the driving thin-film transistor T1 is positioned on the buffer layer 111, which may be the first layer. In the display device according to this embodiment, the third gate insulating layer 114-1 and the fourth gate insulating layer 114-2 are sequentially stacked on the second gate insulating layer 113. The third gate insulating layer 114-1 can directly contact the second gate insulating layer 113. The third gate insulating layer 114-1 and the fourth gate insulating layer 114-2 may each comprise materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0114] A compensation semiconductor layer is positioned between the third gate insulating layer 114-1 and the fourth gate insulating layer 114-2. In other words, the compensation semiconductor layer is positioned on the third gate insulating layer 114-1, which may be a second layer. The third gate insulating layer 114-1 is positioned above the buffer layer 111. The compensation gate electrode G3 is positioned on the fourth gate insulating layer 114-2. An interlayer insulating layer 115 is positioned on the fourth gate insulating layer 114-2 to cover the compensation gate electrode.

[0115] In the display device according to this embodiment, when a compensation semiconductor layer of the compensation thin-film transistor T3 is formed and then hydrogen plasma treatment or the like is performed on at least a portion of the compensation semiconductor layer of the compensation thin-film transistor T3, the impact of the hydrogen plasma treatment on the emission control thin-film transistor T6 or the driving thin-film transistor T1 can be minimized. Furthermore, it is easy to selectively perform excimer laser annealing multiple times on the compensation semiconductor layer of the compensation thin-film transistor T3. It is also possible to selectively perform both excimer laser annealing and hydrogen plasma treatment multiple times on the compensation semiconductor layer of the compensation thin-film transistor T3.

[0116] Furthermore, as shown in another exemplary embodiment of the display device according to the present invention, a cross-sectional view of a portion thereof. Figure 12 As shown, the display device may further include a bottom metal layer BML positioned below the third gate insulating layer 114-1, the bottom metal layer BML corresponding to the third gate electrode. The bottom metal layer BML may be electrically connected to the compensation gate electrode G3 of the compensation thin-film transistor T3, such that the potential of the bottom metal layer BML is equal to the potential of the compensation gate electrode G3. Since the gate voltage is applied from above and below the compensation semiconductor layer, the leakage current of the compensation thin-film transistor T3 can be reduced even further.

[0117] According to an exemplary embodiment of the inventive concept having the structure described above, a display device that prevents or minimizes flicker when displaying images at low frequencies can be realized.

[0118] Although the inventive concept has been described with reference to one or more exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made to one or more exemplary embodiments thereof without departing from the spirit and scope of the inventive concept.

Claims

1. A display device, wherein, The display device includes: A first thin-film transistor includes a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer includes a first channel region, a first source region and a first drain region; A third thin-film transistor includes a third semiconductor layer and a third gate electrode. The third semiconductor layer includes a third channel region, a third source region, and a third drain region. One of the third source region and the third drain region is electrically connected to the first gate electrode, and the other of the third source region and the third drain region is electrically connected to one of the first source region and the first drain region. The leakage current of the third thin-film transistor in the off state is less than the leakage current of the first thin-film transistor in the off state. The data cable is configured to transmit data signals; A second thin-film transistor includes a second semiconductor layer and a second gate electrode. The second thin-film transistor is turned on in response to a scan signal sent to the second gate electrode and performs a switching operation to send the data signal from the data line to the first thin-film transistor; and A pixel electrode is electrically connected to one of the first source region and the first drain region, and the first source region and the first drain region are electrically connected to the third thin-film transistor.

2. The display device according to claim 1, wherein, The grain boundary trap density of a portion of the third semiconductor layer is less than that of the first semiconductor layer.

3. The display device according to claim 2, wherein, The grain boundary trap density of the portion of the third semiconductor layer is 0.2 to 0.5 times that of the grain boundary trap density of the first semiconductor layer.

4. The display device according to claim 2, wherein, The grain boundary trap density of the portion of the third channel region near the third drain region is less than the grain boundary trap density of the first semiconductor layer.

5. The display device according to claim 2, wherein, The grain boundary trap density of the third drain region is less than that of the first semiconductor layer.

6. The display device according to claim 1, wherein, The hydrogen concentration in a portion of the third semiconductor layer is greater than that in the first semiconductor layer.

7. The display device according to claim 6, wherein, The hydrogen concentration of the portion of the third semiconductor layer is 1.5 to 5 times that of the hydrogen concentration of the first semiconductor layer.

8. The display device according to claim 6, wherein, The hydrogen concentration in the portion of the third channel region near the third drain region is less than the hydrogen concentration in the first semiconductor layer.

9. The display device according to claim 6, wherein, The hydrogen concentration in the third drain region is less than the hydrogen concentration in the first semiconductor layer.

10. The display device according to claim 1, wherein, A portion of the third semiconductor layer was treated with hydrogen plasma.

11. The display device according to claim 10, wherein, The portion of the third channel region near the third drain region is treated with hydrogen plasma.

12. The display device according to claim 10, wherein, The third drain region is treated with hydrogen plasma.

13. The display device according to claim 1, wherein, The third semiconductor layer is partially crystallized by performing excimer laser annealing multiple times.

14. The display device according to claim 13, wherein, The portion of the third channel region near the third drain region is crystallized by performing excimer laser annealing multiple times.

15. The display device according to claim 13, wherein, The third drain region is crystallized by performing excimer laser annealing multiple times.

16. The display device according to claim 1, wherein, The first semiconductor layer is positioned on the first layer, and the third semiconductor layer is positioned on the third layer.

17. The display device according to claim 16, wherein, The third layer overlaps with the first layer.

18. The display device according to claim 16, wherein, The third gate electrode is positioned on the third semiconductor layer.

19. The display device according to claim 18, wherein, The display device further includes a bottom metal layer positioned below the third layer to correspond to the third gate electrode.

20. The display device according to claim 19, wherein, The bottom metal layer is electrically connected to the third gate electrode.

21. The display device according to claim 19, wherein, The potential of the bottom metal layer is equal to the potential of the third gate electrode.

22. A display device, wherein, The display device includes: Driving a thin-film transistor includes driving a gate electrode, driving a source region, and driving a drain region; A compensation thin-film transistor includes a compensation gate electrode, a compensation source region, and a compensation drain region, wherein the compensation drain region is electrically connected to the driving gate electrode, and the compensation source region is electrically connected to the driving drain region, wherein the leakage current of the compensation thin-film transistor in the off state is less than the leakage current of the driving thin-film transistor in the off state. The data cable is configured to transmit data signals; A switching thin-film transistor, including a switching gate electrode, a switching source region, and a switching drain region, wherein the switching thin-film transistor is turned on in response to a scan signal sent to the switching gate electrode and transmits the data signal from the data line to the driving thin-film transistor; and The pixel electrode is electrically connected to the driving drain region and the compensation source region.

23. The display device according to claim 22, wherein, The grain boundary trap density of the compensation semiconductor layer portion of the compensation thin-film transistor is less than the grain boundary trap density of the driving semiconductor layer of the driving thin-film transistor.

24. The display device according to claim 22, wherein, The hydrogen concentration in the compensation semiconductor layer of the compensation thin-film transistor is greater than the hydrogen concentration in the driving semiconductor layer of the driving thin-film transistor.

25. A display device, wherein, The display device includes: A first thin-film transistor includes a first terminal, a second terminal, and a third terminal; The second thin-film transistor includes a fourth terminal, a fifth terminal, and a sixth terminal, wherein the fifth terminal is directly connected to the first terminal, and the sixth terminal is directly connected to the second terminal, wherein the leakage current of the second thin-film transistor in the off state is less than the leakage current of the first thin-film transistor in the off state. The line is configured to transmit data signals; A third thin-film transistor, including a seventh terminal, an eighth terminal, and a ninth terminal, is turned on in response to a scan signal and performs a switching operation to send the data signal from the line to the first thin-film transistor; and The pixel is electrically connected to the second terminal and the sixth terminal.

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