Display device and method of manufacturing a display device

Abstract

Embodiments provide a display device and a method of manufacturing a display device, the display device including: an organic light emitting diode; a first transistor driving the organic light emitting diode; a second transistor transmitting a data signal to the first transistor; and a third transistor transmitting a first power voltage to the first transistor, wherein a semiconductor pattern of the first transistor is disposed above a semiconductor pattern of the second transistor, a semiconductor pattern of the third transistor is disposed above the semiconductor pattern of the first transistor, a lower transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor, and an upper transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and interest in Korean Patent Application No. 10-2020-0016878, filed on February 12, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a display device. Background Technology

[0004] With the development of the information society, the requirements for display devices used to display images have increased in various forms. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigators, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, or light-emitting displays. Because in flat panel displays, light-emitting displays include light-emitting elements, and each pixel in the display panel emits light independently through the light-emitting element, light-emitting displays can display images without providing light to the backlight unit of the display panel.

[0005] It will be understood that this background section is partly intended to provide useful background for understanding the technology. However, this background section may also include ideas, concepts, or understandings that were known or understood by a person skilled in the art prior to the corresponding valid application date of the subject matter not disclosed herein. Summary of the Invention

[0006] One aspect of the present invention is to provide a display device capable of achieving high resolution through highly integrated semiconductor elements for driving light-emitting elements.

[0007] Another aspect of the present invention may be to provide a method for manufacturing a display device that can achieve high resolution through highly integrated semiconductor elements for driving light-emitting elements.

[0008] However, the aspects of the invention are not limited to those set forth herein. The above and other aspects of the invention will become more apparent to those skilled in the art from the detailed description of the embodiments given below.

[0009] An embodiment of a display device may include: an organic light-emitting diode (OLED); a first transistor that receives a data signal from a data line and controls a drive current to drive the OLED; a second transistor electrically connected to the data line and a first source / drain electrode of the first transistor, the second transistor transmitting the data signal received from the data line to the first transistor; and a third transistor electrically connected to a first power supply voltage line and the first source / drain electrode of the first transistor, the third transistor transmitting a first power supply voltage from the first power supply voltage line to the first transistor. A semiconductor pattern of the first transistor may be disposed above a semiconductor pattern of the second transistor, and a semiconductor pattern of the third transistor may be disposed above the semiconductor pattern of the first transistor. The display device may further include: a lower transistor insulating film disposed between the semiconductor patterns of the first transistor and the second transistor; and an upper transistor insulating film disposed between the semiconductor patterns of the first transistor and the third transistor.

[0010] The display device may further include: a fourth transistor electrically connected to the gate electrode and the second source / drain electrode of the first transistor, wherein the semiconductor pattern of the fourth transistor may be disposed between the semiconductor pattern of the second transistor and the semiconductor pattern of the third transistor.

[0011] The display device may further include: a sub-gate insulating film, the sub-gate insulating film overlapping the gate electrode of the first transistor and not overlapping the gate electrode of the fourth transistor, wherein the thickness between the gate electrode of the first transistor and the semiconductor pattern of the first transistor may be greater than the thickness between the gate electrode of the fourth transistor and the semiconductor pattern of the fourth transistor.

[0012] The display device may further include: a fifth transistor electrically connected to the gate electrode and the initialization line of the first transistor, the fifth transistor transmitting an initialization voltage from the initialization line to the first transistor, wherein the semiconductor pattern of the fifth transistor may be disposed below the semiconductor pattern of the first transistor.

[0013] The display device may further include: a sixth transistor electrically connected to the second source / drain electrode of the first transistor and the anode electrode of the organic light-emitting diode, the sixth transistor transmitting the driving current from the first transistor to the organic light-emitting diode, wherein the semiconductor pattern of the sixth transistor may be disposed above the semiconductor pattern of the first transistor.

[0014] The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, and the semiconductor pattern of the third transistor may comprise the same material.

[0015] The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, and the semiconductor pattern of the third transistor can constitute a PMOS transistor comprising polysilicon.

[0016] The display device may further include a capacitor, the capacitor comprising: a first electrode electrically connected to the gate electrode of the first transistor; and a second electrode electrically connected to the first power supply voltage line, wherein the capacitor may be disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

[0017] The lower transistor insulating film may include a first interlayer insulating film disposed above the semiconductor pattern of the second transistor, and the upper surface of the first interlayer insulating film may be substantially flat.

[0018] The upper transistor insulating film may include a second interlayer insulating film disposed above the semiconductor pattern of the first transistor, and the upper surface of the second interlayer insulating film may be substantially flat.

[0019] The display device may further include: a first contact pattern disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor, wherein the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor are electrically connected via the first contact pattern.

[0020] The display device may further include a second contact pattern disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor, wherein the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor are electrically connected via the second contact pattern.

[0021] An embodiment of a display device may include: a first transistor, a second transistor, and a third transistor, the first transistor, the second transistor, and the third transistor being disposed on different layers; a capacitor; a first semiconductor layer disposed over a substrate and including a semiconductor pattern of the first transistor; a first gate insulating film disposed over the first semiconductor layer; a first conductive layer disposed over the first gate insulating film and including a gate electrode of the first transistor; a first interlayer insulating film disposed over the first conductive layer; a second semiconductor layer disposed over the first interlayer insulating film and including a semiconductor pattern of the second transistor; a second gate insulating film disposed over the second semiconductor layer; a second conductive layer disposed over the second gate insulating film and including: a gate electrode of the second transistor; and a first electrode of the capacitor, the first electrode of the capacitor being electrically connected to the gate electrode of the second transistor. The display device may further include: a second interlayer insulating film disposed above the second conductive layer; a third conductive layer including a second electrode of the capacitor disposed above the second interlayer insulating film; a third interlayer insulating film disposed above the third conductive layer; a third semiconductor layer disposed above the third interlayer insulating film and including a semiconductor pattern of the third transistor; a third gate insulating film disposed above the third semiconductor layer; and a fourth conductive layer disposed above the third gate insulating film and including a gate electrode of the third transistor.

[0022] The second semiconductor layer may be disposed on the upper surface of the first interlayer insulating film, and the upper surface of the first interlayer insulating film may be substantially flat.

[0023] The display device may further include: a first contact pattern disposed in a first contact hole penetrating the first interlayer insulating film, wherein the upper surface of the first contact pattern and the upper surface of the first interlayer insulating film may be disposed on the same plane.

[0024] The third semiconductor layer may be disposed on the upper surface of the third interlayer insulating film, and the upper surface of the third interlayer insulating film may be substantially flat.

[0025] The display device may further include: a second contact pattern disposed in a second contact hole penetrating the third interlayer insulating film, the second interlayer insulating film and the second gate insulating film, wherein the upper surface of the second contact pattern and the upper surface of the third interlayer insulating film may be disposed on the same plane.

[0026] An embodiment of a method for manufacturing a display device, the display device including a first transistor, a second transistor, and a third transistor respectively disposed on different layers, the embodiment of the method may include: forming a first semiconductor layer on a substrate, the first semiconductor layer including a semiconductor pattern of the first transistor; forming a first gate insulating film on the first semiconductor layer; forming a first conductive layer on the first gate insulating film, the first conductive layer including a gate electrode of the first transistor; forming a first interlayer insulating film on the first conductive layer; forming an upper surface of the first interlayer insulating film to be substantially flat; forming a second semiconductor layer on the upper surface of the first interlayer insulating film, the second semiconductor layer including a semiconductor pattern of the second transistor; and forming a first interlayer insulating film on the second semiconductor layer. A second gate insulating film is formed on the third transistor; a second conductive layer is formed on the second gate insulating film, the second conductive layer including the gate electrode of the third transistor and a first electrode of a capacitor electrically connected to the gate electrode of the third transistor; a second interlayer insulating film is formed on the second conductive layer; a third conductive layer is formed on the second interlayer insulating film, the third conductive layer including the second electrode of the capacitor; a third interlayer insulating film is formed on the third conductive layer; a third semiconductor layer is formed on the third interlayer insulating film, the third semiconductor layer including the semiconductor pattern of the third transistor; a third gate insulating film is formed on the third semiconductor layer; and a fourth conductive layer is formed on the third gate insulating film, the fourth conductive layer including the gate electrode of the third transistor.

[0027] The method may further include: forming the upper surface of the third interlayer insulating film to be substantially flat prior to the formation of the third semiconductor layer, wherein the third semiconductor layer may be disposed above the upper surface of the third interlayer insulating film.

[0028] Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer may include polysilicon, and each of the first transistor, the second transistor, and the third transistor may be a PMOS transistor.

[0029] A display device may be provided that can achieve high resolution through highly integrated semiconductor elements for driving light-emitting elements.

[0030] A method for manufacturing a display device may be provided, which can achieve high resolution through highly integrated semiconductor elements for driving light-emitting elements.

[0031] The effects of the present invention are not limited to the foregoing, and various other effects are expected herein. Attached Figure Description

[0032] The above and other aspects and features of the present invention will become more apparent from the detailed description of embodiments of the invention with reference to the accompanying drawings, in which:

[0033] Figure 1 This is a schematic diagram of a display device according to an embodiment;

[0034] Figure 2 This is a schematic plan view of a display device according to an embodiment;

[0035] Figure 3 This is a schematic block diagram of a display device according to an embodiment;

[0036] Figure 4 This is a schematic circuit diagram of pixels according to an embodiment;

[0037] Figure 5 This is a schematic cross-sectional view of pixels according to an embodiment;

[0038] Figures 6 to 25 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment;

[0039] Figure 26 This is a schematic cross-sectional view of pixels according to another embodiment;

[0040] Figure 27 It is a schematic cross-sectional view of pixels according to another embodiment; and

[0041] Figure 28 This is a schematic cross-sectional view of pixels according to another embodiment. Detailed Implementation

[0042] The invention will now be described more fully below with reference to the accompanying drawings, in which embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0043] It will also be understood that when a layer is referred to as being "on" a substrate or another layer, the layer may be directly on the substrate or another layer, or there may be intermediate layers. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0044] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, a first element discussed below may be referred to as a second element without departing from the teachings of one or more embodiments. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0045] The term “overlapping with” may include “layering,” “stacking,” “face or facing,” “extending above,” “extending below,” “covering or partially covering,” or any other suitable term that will be understood and appreciated by one of ordinary skill in the art. The phrase “not overlapping with” may include “separated from,” “separated from,” “offset from,” or any other suitable equivalent that will be understood and appreciated by one of ordinary skill in the art.

[0046] The phrase “at least one of…” is intended, for the purposes of its meaning and interpretation, to include the meaning of “at least one of… selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0047] The term “and / or” is intended for the purposes of its meaning and interpretation to include any combination of the terms “and” and “or”. For example, “A and / or B” can be understood to mean “A, B or A and B”. The terms “and” and “or” can be used in a connecting or separating sense and can be understood as equivalent to “and / or”.

[0048] Figure 1 This is a schematic diagram of a display device according to an embodiment. Figure 2 This is a schematic plan view of a display device according to an embodiment, and Figure 3 This is a schematic block diagram of a display device according to an embodiment.

[0049] In the accompanying drawings, the first direction DR1 represents the horizontal direction of the display device 1 in a plan view, and the second direction DR2 represents the vertical direction of the display device 1 in a plan view. The third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other in a manner that the first direction DR1 and the second direction DR2 are perpendicular to each other, and the third direction DR3 intersects both the first direction DR1 and the second direction DR2 in a direction that intersects the plane containing the first direction DR1 and the second direction DR2. However, the directions mentioned in the embodiments should be understood as referring to relative directions, and the embodiments are not limited to the mentioned directions.

[0050] Unless otherwise defined, as used herein, “upper,” “upper surface,” and “upper side” as expressed to DR3 by a third party means one side of the display surface of the display panel 10, and “lower,” “lower surface,” and “lower side” as expressed to DR3 by a third party means the opposite side of the display surface of the display panel 10.

[0051] Display device 1 can be a device for displaying moving or still images. Display device 1 can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs).

[0052] The display device 1 according to the embodiment can be formed in a substantially rectangular shape on a plane. The display device 1 can have a rectangular shape with right-angled corners on a plane. However, the present invention is not limited thereto, and the display device 1 can also have a rectangular shape with rounded corners on a plane.

[0053] Display panel 10 may be an organic light-emitting display panel. In the following embodiments, an organic light-emitting display panel is shown as the application of display panel 10; however, the invention is not limited thereto, and various types of display panels, such as liquid crystal display (LCD) panels, quantum dot organic light-emitting display (QD-OLED) panels, quantum dot liquid crystal display (QD-LCD) panels, quantum nano light-emitting display panels (nano NED), and micro light-emitting diodes (micro LED), can be applied. Hereinafter, display device 1 will be described as an organic light-emitting display device, but the invention is not limited thereto.

[0054] Display panel 10 may include a display area DA and a non-display area NDA. Pixels PX may be formed in the display area DA to display images, and the non-display area NDA may be the peripheral area of ​​the display area DA. The display area DA may have a rectangular shape with right-angled corners or a rectangular shape with rounded corners. The display area DA may have a short side and a long side. The short side of the display area DA may be a side extending in a first direction DR1. The long side of the display area DA may be a side extending in a second direction DR2. However, the planar shape of the display area DA is not limited to a rectangular shape, and may have a circular shape, an elliptical shape, or other various shapes.

[0055] In the display area DA, not only can pixels PX be arranged, but also scan lines SL, emitter lines EML, data lines DL, and a first power supply voltage line ELVDL that can be electrically connected to the pixels PX can be arranged. Scan lines SL and emitter lines EML can be arranged parallel to each other in a first direction DR1. Data lines DL can be arranged parallel to each other in a second direction DR2 that intersects the first direction DR1. The first power supply voltage line ELVDL can be arranged parallel to each other in the display area DA in the second direction DR2. The first power supply voltage lines ELVDL arranged parallel to each other in the display area DA in the second direction DR2 can be electrically connected to each other in the non-display area NDA.

[0056] Each of the pixels PX can be electrically connected to at least one of the scan lines SL, at least one of the data lines DL, at least one of the emitter lines EML, and the first power supply voltage line ELVDL. Although in Figure 2 The diagram illustrates that each of the pixels PX can be electrically connected to two scan lines SL, one data line DL, one transmit line EML, and a first power supply voltage line ELVDL, but the invention is not limited thereto. For example, each of the pixels PX can be electrically connected to three scan lines SL instead of two scan lines SL.

[0057] The non-display area NDA can be defined as the area extending from the outside of the display area DA to the edge of the display panel 10. For example, the non-display area NDA can be set to surround the display area DA and can form a border.

[0058] The non-display area NDA may be provided with a scan drive circuit 40 for applying scan signals to the scan line SL, a fan-out line FL between the data line DL and the display drive circuit 20, and a pad DP electrically connected to the display drive circuit 20. The display drive circuit 20 and the pad DP may be located at one side edge of the display panel 10. The pad DP may be located adjacent to one side edge of the display panel 10, rather than adjacent to the display drive circuit 20.

[0059] The scan drive circuit 40 can be electrically connected to the display drive circuit 20 via the scan control line SCL. The scan drive circuit 40 can receive the scan control signal SCS and the transmit control signal ECS from the display drive circuit 20 via the scan control line SCL.

[0060] like Figure 3 As shown, the scan drive circuit 40 may include a scan driver 41 and a transmit control driver 42.

[0061] Scan driver 41 can generate scan signals according to scan control signal SCS, and can sequentially output scan signals to scan lines SL. Transmit control driver 42 can generate transmit signals according to transmit control signal ECS (see reference). Figure 4 (EM in the text), and can transmit signals (refer to) Figure 4 The “EM” in the output is sequentially output to the transmit line EML.

[0062] The scan driving circuit 40 may include thin-film transistors. The thin-film transistors of the scan driving circuit 40 may be formed on the same layer as the thin-film transistors of the pixel PX. Although in Figure 2 The diagram shows that the scan driving circuit 40 can be formed in a non-display area NDA located, for example, on one side of the left side of the display area DA, but the invention is not limited thereto. For example, the scan driving circuit 40 can be formed in non-display areas NDA located, for example, on both sides of the left and right sides of the display area DA.

[0063] like Figure 3 As shown, the display driving circuit 20 may include a timing controller 21, a data driver 22, and a power supply 23.

[0064] The timing controller 21 can receive digital video data DATA and timing signals from the circuit board 30. Based on the timing signals, the timing controller 21 can generate a scan control signal SCS for controlling the operating timing of the scan driver 41, a transmit control signal ECS for controlling the operating timing of the transmit control driver 42, and a data control signal DCS for controlling the operating timing of the data driver 22. The timing controller 21 can output the scan control signal SCS to the scan driver 41 via the scan control line SCL, and can output the transmit control signal ECS to the transmit control driver 42. The timing controller 21 can also output the digital video data DATA and the data control signal DCS to the data driver 22.

[0065] Data driver 22 converts digital video data DATA into analog positive and negative data voltages and outputs these data voltages to data line DL via fan-out line FL. Pixel PX can be selected by the scan signal of scan drive circuit 40, and data voltages can be supplied to the selected pixel PX.

[0066] Power supply 23 can generate the first power supply voltage (refer to...) Figure 4 (in "ELVDD") and the first power supply voltage (refer to) Figure 4 The “ELVDD” in the text is supplied to the first power supply voltage line ELVDL. Additionally, power supply 23 can generate a second power supply voltage (see reference 23). Figure 4 (in "ELVSS") and via the second power supply voltage line (see reference) Figure 4 The “ELVSL” in the reference will be the second power supply voltage (refer to the second power supply voltage). Figure 4 The “ELVSS” in the text is supplied to the light-emitting elements of each pixel PX (see reference). Figure 4 The cathode electrode of OLED (see reference) Figure 5 (CAT in the text). First power supply voltage (refer to...) Figure 4 The “ELVDD” in the text can be used to drive the light-emitting element (see reference). Figure 4 The high potential voltage of "OLED" in the text, and the second power supply voltage (refer to) Figure 4 The “ELVSS” in the text can be used to drive the light-emitting element (see reference). Figure 4 The low potential voltage of OLED (as mentioned in the text). For example, the first power supply voltage (refer to...). Figure 4 The “ELVDD” in the reference can have a voltage higher than the second supply voltage (see reference). Figure 4 The high potential of “ELVSS” in the text.

[0067] The display driving circuit 20 can be formed as an integrated circuit (IC) and can be attached to the display panel 10 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. However, the invention is not limited thereto. For example, the display driving circuit 20 can be attached to a circuit board 30.

[0068] Circuit board 30 can be attached to pad DP using an anisotropic conductive film. Therefore, the leads of circuit board 30 can be electrically connected to pad DP. Circuit board 30 can be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film device.

[0069] Figure 4 This is a schematic circuit diagram of a pixel according to an embodiment.

[0070] Reference Figure 4The circuitry of a pixel PX may include transistors T1 to T7, capacitor Cst, and a light-emitting element (OLED). Data signals DATA, GW (first scan signal), GI (second scan signal), GB (third scan signal), EM (transmission signal), ELVDD (first power supply voltage), ELVSS (second power supply voltage), and VINT (initialization voltage) may be applied to the circuitry of the pixel PX.

[0071] The light-emitting element OLED can be an organic light-emitting diode, which includes an anode electrode (see reference). Figure 5 "ANO" in the text), organic light-emitting layer (refer to) Figure 5 (EL) and cathode electrode (refer to) Figure 5 (CAT in the text).

[0072] The first transistor T1 can be used as a driving transistor, and the second transistor T2 through the seventh transistor T7 can be used as switching transistors. Each of transistors T1 through T7 may include a gate electrode, a first source / drain electrode, and a second source / drain electrode. One of the first source / drain electrode and the second source / drain electrode in each of transistors T1 through T7 may be a source electrode, and the other of the first source / drain electrode and the second source / drain electrode in each of transistors T1 through T7 may be a drain electrode.

[0073] Each of transistors T1 to T7 can be a thin-film transistor. Each of transistors T1 to T7 can be either a PMOS transistor or an NMOS transistor. In an embodiment, the first transistor T1 as a driving transistor, the second transistor T2 as a data transmission transistor, the third transistor T3 as a compensation transistor, the fourth transistor T4 as a first initialization transistor, the fifth transistor T5 as a first light emission control transistor, the sixth transistor T6 as a second light emission control transistor, and the seventh transistor T7 as a second initialization transistor can all be PMOS transistors.

[0074] Despite Figure 4 The diagram illustrates that each of the pixels PX can be a 7T1C (seven transistors—one capacitor) structure having seven transistors T1 to T7 and one capacitor Cst, but the invention is not limited thereto. Each of the pixels PX can include both a transistor and a capacitor. For example, various other modified pixel PX structures, such as 2T1C, 3T1C, and 6T1C structures, can be applied to each of the pixels PX.

[0075] Each component will be described in detail below.

[0076] The gate electrode of the first transistor T1 can be electrically connected to the first electrode of the capacitor Cst. The first source / drain electrode of the first transistor T1 can be electrically connected to the first power supply voltage ELVDD terminal via the fifth transistor T5. The second source / drain electrode of the first transistor T1 can be electrically connected to the anode electrode of the light-emitting element OLED via the sixth transistor T6 (see reference). Figure 5 (referring to "ANO" in the original text). The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2, and can supply the drive current Ids to the light-emitting element OLED.

[0077] The first transistor T1 can control the drive current Ids (i.e., the drain-source current) based on the data voltage applied to the gate electrode. As shown in Equation 1 below, the drive current Ids flowing through the channel region of the first transistor T1 can be proportional to the square of the difference between the gate-source voltage Vsg and the threshold voltage Vth of the first transistor T1.

[0078] [Equation 1]

[0079] Ids = k′ × (Vgs - Vth) 2

[0080] In Equation 1, k' is a scaling factor determined by the structure and physical characteristics of the driving transistor, Vgs is the gate-source voltage of the driving transistor, and Vth is the threshold voltage of the driving transistor.

[0081] The gate electrode of the second transistor T2 can be electrically connected to the first scan signal GW terminal. The first source / drain electrode of the second transistor T2 can be electrically connected to the data signal DATA terminal. The second source / drain electrode of the second transistor T2 can be electrically connected to the first source / drain electrode of the first transistor T1, and can be electrically connected to the first power supply voltage ELVDD terminal via the fifth transistor T5. The second transistor T2 can be turned on according to the first scan signal GW to perform a switching operation that transmits the data signal DATA to the first source / drain electrode of the first transistor T1.

[0082] The gate electrode of the third transistor T3 can be electrically connected to the first scan signal GW terminal. The first source / drain electrode of the third transistor T3 can be electrically connected to the second source / drain electrode of the first transistor T1 and the first source / drain electrode of the sixth transistor T6. Furthermore, the second source / drain electrode of the third transistor T3 can be electrically connected to the first electrode of the capacitor Cst, the first source / drain electrode of the fourth transistor T4, and the gate electrode of the first transistor T1.

[0083] The third transistor T3 can be turned on by the first scan signal GW to connect the gate electrode and the second source / drain electrode of the first transistor T1, thereby connecting the first transistor T1 in a diode manner. Therefore, a voltage difference can be generated between the first source / drain electrode and the gate electrode of the first transistor T1 by the threshold voltage of the first transistor T1, and the data signal DATA, which has been compensated for the threshold voltage, can be supplied to the gate electrode of the first transistor T1, thereby compensating for the threshold voltage deviation of the first transistor T1.

[0084] The gate electrode of the fourth transistor T4 can be electrically connected to the second scan signal GI terminal. The first source / drain electrode of the fourth transistor T4 can be electrically connected to the first electrode of capacitor Cst, the second source / drain electrode of the third transistor T3, and the gate electrode of the first transistor T1. Furthermore, the second source / drain electrode of the first transistor T1 can be electrically connected to the initialization voltage VINT terminal and the first source / drain electrode of the seventh transistor T7. The fourth transistor T4 can be turned on by the second scan signal GI to transmit the initialization voltage VINT to the gate electrode of the first transistor T1, thereby performing the operation of initializing the voltage of the gate electrode of the first transistor T1.

[0085] The gate electrode of the fifth transistor T5 can be electrically connected to the transmit signal EM terminal, the first source / drain electrode of the fifth transistor T5 can be electrically connected to the first power supply voltage line ELVDL, and the second source / drain electrode of the fifth transistor T5 can be electrically connected to the first source / drain electrode of the first transistor T1 and the second source / drain electrode of the second transistor T2. The fifth transistor T5 can be turned on by the transmit signal EM to connect the first source / drain electrode of the first transistor T1 and the first power supply voltage line ELVDL.

[0086] The sixth transistor T6 can be electrically connected between the second source / drain electrode of the first transistor T1 and the anode electrode of the OLED light-emitting element. The gate electrode of the sixth transistor T6 can be electrically connected to the EM terminal for transmitting signals. The first source / drain electrode of the sixth transistor T6 can be electrically connected to the second source / drain electrode of the first transistor T1 and the first source / drain electrode of the third transistor T3. Furthermore, the second source / drain electrode of the sixth transistor T6 can be electrically connected to the anode electrode of the OLED light-emitting element.

[0087] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously according to the emission signal EM, and thus the drive current Ids can flow through the light-emitting element OLED.

[0088] The gate electrode of the seventh transistor T7 can be electrically connected to the third scan signal GB terminal. The first source / drain electrode of the seventh transistor T7 can be electrically connected to the initialization voltage VINT terminal. The second source / drain electrode of the seventh transistor T7 can be electrically connected to the anode electrode of the light-emitting element OLED. The seventh transistor T7 can be turned on according to the third scan signal GB to initialize the anode electrode of the light-emitting element OLED.

[0089] In this embodiment, although the case where the gate electrode of the seventh transistor T7 receives the third scan signal GB is shown, the invention is not limited thereto, and the circuit of the pixel PX can be configured such that the gate electrode of the seventh transistor T7 receives the transmit signal EM.

[0090] Capacitor Cst can be formed between the gate electrode of the first transistor T1 and the first power supply voltage line ELVDL, and can include a first electrode and a second electrode (see reference). Figure 5 (Referring to "151" in the original text). The first electrode of capacitor Cst can be electrically connected to the gate electrode of the first transistor T1, the second source / drain electrode of the third transistor T3, and the first source / drain electrode of the fourth transistor T4, and the second electrode of capacitor Cst (referring to...). Figure 5 The “151” in the figure can be electrically connected to the first power supply voltage line ELVDL. The capacitor Cst can be used to maintain a constant data voltage applied to the gate electrode of the first transistor T1.

[0091] Cathode electrode of OLED (reference) Figure 5 The “CAT” in the diagram can be electrically connected to the second power supply voltage ELVSS terminal. The light-emitting element OLED can receive a drive current Ids from the first transistor T1 and can emit light to display an image.

[0092] The cross-sectional structure of the aforementioned pixel PX will be described in detail below.

[0093] Figure 5 This is a schematic cross-sectional view of pixels according to an embodiment.

[0094] In the following embodiments, although some components are related to Figures 1 to 4 The components mentioned are essentially the same, but new reference numerals are provided to easily describe the arrangement and coupling between the components.

[0095] Reference Figure 5 As mentioned above, a pixel PX may include a transistor (and...) Figure 4 The numbers “T1” through “T7” are the same, and the capacitors (and) Figure 4 (The same as "Cst" in the text) and light-emitting elements (with Figure 4 (The same as "OLED" in the text).

[0096] Each of transistors T1 to T7 may include a conductive layer forming electrodes, a semiconductor pattern forming a channel region, and an insulating layer. The capacitor Cst may include a conductive layer forming electrodes and an insulating layer disposed between the conductive layers. The light-emitting element OLED includes conductive layers forming an anode electrode (ANO) and a cathode electrode (CAT), and an organic light-emitting layer (EL) disposed between the conductive layers. Electrical connections of the components may be performed via lines made of conductive layers and / or vias made of conductive material. The aforementioned conductive material, conductive layers, semiconductor layers, insulating layers, and organic light-emitting layer (EL) may be disposed on a substrate SUB.

[0097] Transistors T1 to T7 can be disposed on three different layers. In this specification, based on the semiconductor patterns ACT1 to ACT7 of transistors T1 to T7, the layer on which the transistors can be disposed can refer to the layer on which the semiconductor patterns ACT1 to ACT7 of transistors T1 to T7 can be disposed. The layer on which the transistors can be disposed may include at least one insulating layer and / or at least one conductive layer. For example, each of transistors T1 to T7 may be disposed above at least one insulating layer and / or at least one conductive layer.

[0098] In other words, the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4 can be disposed on the same layer (e.g., substrate SUB or first semiconductor arrangement layer FS1). The semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3 can be disposed on the same layer (e.g., second interlayer insulating film ILD2 and third conductive layer 130, or second semiconductor arrangement layer FS2), but can be disposed on a different layer than the layer (first semiconductor arrangement layer FS1) on which the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4 can be disposed. The semiconductor pattern ACT5 of the fifth transistor T5, the semiconductor pattern ACT6 of the sixth transistor T6, and the semiconductor pattern ACT7 of the seventh transistor T7 can be disposed on the same layer (e.g., the fourth interlayer insulating film ILD4 and the sixth conductive layer 160, or the third semiconductor arrangement layer FS3), but can be disposed on a layer different from the layer on which the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4 can be disposed (the first semiconductor arrangement layer FS1) and different from the layer on which the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3 can be disposed (the second semiconductor arrangement layer FS2).

[0099] Specifically, the lower transistor insulating film (TIB) can be disposed between the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4, and between the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3. The lower transistor insulating film (TIB) may include, for example, a first gate insulating film GI1, a first interlayer insulating film ILD1, and a second interlayer insulating film ILD2, but is not limited thereto. The lower transistor insulating film (TIB) can insulate the semiconductor patterns ACT2 of the second transistor T2, ACT4 of the fourth transistor T4, ACT1 of the first transistor T1, and ACT3 of the third transistor T3 between the semiconductor patterns ACT2 of the second transistor T2 and ACT4 of the fourth transistor T4, and between the semiconductor patterns ACT1 of the first transistor T1 and ACT3 of the third transistor T3.

[0100] The upper transistor insulating film (TIU) can be disposed between the semiconductor patterns ACT1 of the first transistor T1, ACT3 of the third transistor T3, ACT5 of the fifth transistor T5, ACT6 of the sixth transistor T6, and ACT7 of the seventh transistor T7. The upper transistor insulating film (TIU) may include, for example, a second gate insulating film (GI2), a third interlayer insulating film (ILD3), and a fourth interlayer insulating film (ILD4), but is not limited thereto. The upper transistor insulating film (TIU) can insulate the semiconductor patterns ACT1, ACT3, ACT5, ACT6, and ACT7 of the first transistor T1, third transistor T3, fifth transistor T5, sixth transistor T6, and seventh transistor T7 from each other.

[0101] Even when transistors T1 to T7 are insulated from each other by the lower transistor insulating film TIB and the upper transistor insulating film TIU, transistors T1 to T7 can still be electrically connected to each other by the first contact pattern 131, the second contact pattern 132, the third contact pattern 133, the fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163. Details will be described later.

[0102] The display panel 10 may further include a first semiconductor arrangement layer FS1, a second semiconductor arrangement layer FS2, and a third semiconductor arrangement layer FS3. A second transistor T2 and a fourth transistor T4 may be disposed on the first semiconductor arrangement layer FS1, a first transistor T1 and a third transistor T3 may be disposed on the second semiconductor arrangement layer FS2, and a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 may be disposed on the third semiconductor arrangement layer FS3.

[0103] The first semiconductor arrangement layer FS1 may include the upper surface of the substrate SUB. The first semiconductor arrangement layer FS1 may be flat over the entire surface of the substrate SUB. The second semiconductor arrangement layer FS2 may include the upper surface of the second interlayer insulating film ILD2 and the upper surface of the third conductive layer 130. The second semiconductor arrangement layer FS2 may be flat over the entire surface of the substrate SUB. The third semiconductor arrangement layer FS3 may include the upper surface of the fourth interlayer insulating film ILD4 and the upper surface of the sixth conductive layer 160. The third semiconductor arrangement layer FS3 may be flat over the entire surface of the substrate SUB. However, the invention is not limited thereto, and each of the first semiconductor arrangement layer FS1, the second semiconductor arrangement layer FS2, and the third semiconductor arrangement layer FS3 may not be flat (e.g., completely flat).

[0104] The first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 can be disposed on a flat surface (the surface of the first semiconductor layer FS1, the second semiconductor layer FS2, and the third semiconductor layer FS3), and thus the process of crystallizing the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 can be easily performed.

[0105] The first transistor T1 and the third transistor T3 can be positioned above the second transistor T2 and the fourth transistor T4, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be positioned above the first transistor T1 to the fourth transistor T4. In other words, the second transistor T2 and the fourth transistor T4 can be positioned at the lowest point of the first transistor T1 to the seventh transistor T7, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be positioned at the highest point of the first transistor T1 to the seventh transistor T7. The first transistor T1 and the third transistor T3 can be positioned between the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0106] Among the first transistor T1 to the seventh transistor T7, the second transistor T2 and the fourth transistor T4 can be positioned as the anode ANO furthest from the light-emitting element OLED in the thickness direction (third direction DR3), and among the first transistor T1 to the seventh transistor T7, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be positioned as the anode ANO closest to the light-emitting element OLED in the thickness direction (third direction DR3).

[0107] As described above, since transistors T1 to T7 can be disposed on three different layers (first semiconductor arrangement layer FS1, second semiconductor arrangement layer FS2 and third semiconductor arrangement layer FS3), the area of ​​the plane on which transistors T1 to T7 of a pixel can be disposed can be reduced, and thus the resolution of display device 1 can be achieved at a higher resolution.

[0108] The lamination structure of each configuration of the display panel 10 will be described in detail below.

[0109] The display panel 10 according to an embodiment may include a semiconductor layer, a conductive layer, and an insulating layer disposed on a substrate SUB. The semiconductor layer may include a first semiconductor layer SC1, a second semiconductor layer SC2, and a third semiconductor layer SC3. The conductive layer may include a first conductive layer 110, a second conductive layer 120, a third conductive layer 130, a fourth conductive layer 140, a fifth conductive layer 150, a sixth conductive layer 160, a seventh conductive layer 170, and an eighth conductive layer 180. The insulating layer may include a first gate insulating film GI1, a second gate insulating film GI2, and a third gate insulating film GI3, as well as a first interlayer insulating film ILD1, a second interlayer insulating film ILD2, a third interlayer insulating film ILD3, a fourth interlayer insulating film ILD4, and a fifth interlayer insulating film ILD5.

[0110] The layers of a pixel PX can be arranged in the following order: substrate SUB, first semiconductor layer SC1, first gate insulating film GI1, first conductive layer 110, first interlayer insulating film ILD1, second conductive layer 120, second interlayer insulating film ILD2, third conductive layer 130, second semiconductor layer SC2, second gate insulating film GI2, fourth conductive layer 140, third interlayer insulating film ILD3, fifth conductive layer 150, fourth interlayer insulating film ILD4, sixth conductive layer 160, third semiconductor layer SC3, third gate insulating film GI3, seventh conductive layer 170, fifth interlayer insulating film ILD5, eighth conductive layer 180, via layer VIA, anode electrode ANO, pixel defining layer PDL, organic light-emitting layer EL, and cathode electrode CAT. Each of the above layers can be formed as a single film, or it can be formed as a laminate comprising multiple films. Another layer can be further disposed between the various layers.

[0111] The substrate SUB can support each layer disposed on the substrate SUB. When the display device 1 is a back-emitting or dual-emitting display device, a transparent substrate can be used. When the display device 1 is a front-emitting display device, not only a transparent substrate can be used, but also a translucent or opaque substrate can be used.

[0112] The substrate SUB can be made of an insulating material such as glass, quartz, polymer resin, or combinations thereof. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate SUB may also include metallic materials.

[0113] The substrate SUB can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled up. Examples of materials constituting a flexible substrate include, but are not limited to, polyimide (PI).

[0114] Although not shown in the accompanying drawings, a buffer layer may be further disposed on the substrate SUB. The buffer layer (not shown) may be disposed over the entire surface of the substrate SUB. The buffer layer (not shown) can prevent the diffusion of impurity ions, prevent the penetration of moisture or outside air, and perform surface planarization. The buffer layer may comprise silicon nitride, silicon oxide, or silicon oxynitride.

[0115] A first semiconductor layer SC1 may be disposed above the substrate SUB. The first semiconductor layer SC1 may include a semiconductor pattern ACT2 of a second transistor T2 and a semiconductor pattern ACT4 of a fourth transistor T4. The semiconductor pattern ACT2 of the second transistor T2 may include a channel region CH2 overlapping the gate electrode 111 of the second transistor T2 above it in the thickness direction, a first source / drain region SD21 of the second transistor T2 located on one side of the channel region CH2, and a second source / drain region SD22 of the second transistor T2 located on the other side of the channel region CH2. The semiconductor pattern ACT4 of the fourth transistor T4 may include a channel region CH4 overlapping the gate electrode 112 of the fourth transistor T4 above it in the thickness direction, a first source / drain region SD41 of the fourth transistor T4 located on one side of the channel region CH4, and a second source / drain region SD42 of the fourth transistor T4 located on the other side of the channel region CH4.

[0116] In other words, the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4 can be active layers constituting the first source / drain regions SD21 and SD41, the second source / drain regions SD22 and SD42, and the channel regions CH2 and CH4, and the first source / drain regions SD21 and SD41 and the second source / drain regions SD22 and SD42 can respectively contact the first source / drain electrode and the second source / drain electrode. One of the first source / drain regions SD21 and SD41 and the second source / drain regions SD22 and SD42 can be a source region, and the other of the first source / drain regions SD21 and SD41 and the second source / drain regions SD22 and SD42 can be a drain region. Charge carrier ions can be included in the first source / drain regions SD21 and SD41 and the second source / drain regions SD22 and SD42 of the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4, such that the first source / drain regions SD21 and SD41 and the second source / drain regions SD22 and SD42 can have higher conductivity and lower electrical resistance than the channel regions CH2 and CH4.

[0117] The first semiconductor layer SC1 can be made of polycrystalline silicon, monocrystalline silicon, amorphous silicon, or a combination thereof. When the first semiconductor layer SC1 can be made of polycrystalline silicon, the polycrystalline silicon can be formed by crystallizing the amorphous silicon using crystallization methods such as rapid thermal annealing (RTA), solid-state crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), or sequential lateral solidification (SLS).

[0118] However, the present invention is not limited thereto, and the first semiconductor layer SC1 may include an oxide semiconductor. The oxide may include an oxide selected from at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), and combinations thereof. The oxide may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (IZO).

[0119] A first gate insulating film GI1 can be disposed on the first semiconductor layer SC1. The first gate insulating film GI1 can cover not only the upper surface of the first semiconductor layer SC1, except for the portions where the first contact holes CNT1, CNT2, CNT3, and CNT4 can be formed, but also the side surfaces of the first semiconductor layer SC1. The first gate insulating film GI1 can be disposed substantially above the entire surface of the substrate SUB.

[0120] The first gate insulating film GI1 may include silicon compounds or metal oxides, or combinations thereof. For example, the first gate insulating film GI1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These may be used individually or in combination with each other.

[0121] The first conductive layer 110 may be disposed on the first gate insulating film GI1. The first conductive layer 110 may include the gate electrode 111 of the second transistor T2 and the gate electrode 112 of the fourth transistor T4. The first conductive layer 110 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0122] The first interlayer insulating film ILD1 can be disposed on the first conductive layer 110. The first interlayer insulating film ILD1 can cover not only the upper surface of the first conductive layer 110 except for the portions where the first contact holes CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 can be formed, but also the side surfaces of the first conductive layer 110. The first interlayer insulating film ILD1 can be disposed substantially above the entire surface of the substrate SUB.

[0123] The first interlayer insulating film ILD1 may include silicon compounds or metal oxides, or combinations thereof. For example, the first interlayer insulating film ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These can be used individually or in combination with each other.

[0124] The second conductive layer 120 may be disposed on the first interlayer insulating film ILD1. The second conductive layer 120 may include a data line (DL, hereinafter "121"), a first conductive pattern 122, a second conductive pattern 123, and an initialization line 124.

[0125] Data line 121 can be electrically connected to the first source / drain region SD21 of the second transistor T2 via the first contact hole CNT1. The first contact hole CNT1 penetrates the first interlayer insulating film ILD1 and the first gate insulating film GI1 to expose the first source / drain region SD21 of the second transistor T2. Data line 121 itself can be the first source / drain electrode of the second transistor T2, or a portion of data line 121 can be the first source / drain electrode of the second transistor T2.

[0126] The first conductive pattern 122 can be electrically connected to the second source / drain region SD22 of the second transistor T2 via the second contact hole CNT2, which penetrates the first interlayer insulating film ILD1 and the first gate insulating film GI1 to expose the second source / drain region SD22 of the second transistor T2. The first conductive pattern 122 can be electrically connected together with the first contact pattern 131, which will be described later, to the second source / drain region SD22 of the second transistor T2 and the first source / drain region SD11 of the first transistor T1. The first conductive pattern 122 itself can be the second source / drain electrode of the second transistor T2, or a portion of the first conductive pattern 122 can be the second source / drain electrode of the second transistor T2.

[0127] The second conductive pattern 123 can be electrically connected to the first source / drain region SD41 of the fourth transistor T4 via the third contact hole CNT3, which penetrates the first interlayer insulating film ILD1 and the first gate insulating film GI1 to expose the first source / drain region SD41 of the fourth transistor T4. The second conductive pattern 123 can be electrically connected together with the second contact pattern 132, which will be described later, to the first source / drain region SD41 of the fourth transistor T4 and the second source / drain region SD32 of the third transistor T3. The second conductive pattern 123 itself can be the first source / drain electrode of the fourth transistor T4, or a portion of the second conductive pattern 123 can be the first source / drain electrode of the fourth transistor T4.

[0128] Initialization line 124 can be electrically connected to the second source / drain region SD42 of the fourth transistor T4 via the fourth contact hole CNT4. The fourth contact hole CNT4 penetrates the first interlayer insulating film ILD1 and the first gate insulating film GI1 to expose the second source / drain region SD42 of the fourth transistor T4. Initialization line 124 itself can be the second source / drain electrode of the fourth transistor T4, or a portion of initialization line 124 can be the second source / drain electrode of the fourth transistor T4.

[0129] The second conductive layer 120 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0130] The second interlayer insulating film ILD2 can be disposed on the second conductive layer 120. The second interlayer insulating film ILD2 can cover not only the upper surface of the second conductive layer 120, excluding the portions where the fifth contact hole CNT5, the sixth contact hole CNT6, and the seventh contact hole CNT7 can be formed, but also the side surfaces of the second conductive layer 120. The second interlayer insulating film ILD2 can be disposed substantially above the entire surface of the substrate SUB.

[0131] The upper surface of the second interlayer insulating film ILD2 can be flat without steps. Therefore, the process for crystallizing the second semiconductor layer SC2 disposed on the second interlayer insulating film ILD2 can be easily performed. The details will be described later.

[0132] The second interlayer insulating film (ILD2) may include silicon compounds or metal oxides, or combinations thereof. For example, the second interlayer insulating film (ILD2) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These can be used individually or in combination with each other.

[0133] The third conductive layer 130 may be disposed on the second interlayer insulating film ILD2. The third conductive layer 130 may include a first contact pattern 131, a second contact pattern 132 and a third contact pattern 133.

[0134] The first contact pattern 131 can be disposed in the fifth contact hole CNT5, which penetrates the second interlayer insulating film ILD2 to expose the first conductive pattern 122. The first contact pattern 131 can be electrically connected to the lower first conductive pattern 122 and the upper first source / drain region SD11 of the first transistor T1. Therefore, the first source / drain region SD11 of the first transistor T1 and the second source / drain region SD22 of the second transistor T2 can be electrically connected by the first contact pattern 131 and the first conductive pattern 122. The first contact pattern 131 can be the second source / drain electrode of the second transistor T2, and can also be the first source / drain electrode of the first transistor T1.

[0135] The second contact pattern 132 can be disposed in the sixth contact hole CNT6, which penetrates the second interlayer insulating film ILD2 to expose the second conductive pattern 123. The second contact pattern 132 can be electrically connected to the lower second conductive pattern 123 and the upper second source / drain region SD32 of the third transistor T3. Therefore, the second source / drain region SD32 of the third transistor T3 and the first source / drain region SD41 of the fourth transistor T4 can be electrically connected by the second contact pattern 132 and the second conductive pattern 123. The second contact pattern 132 can be the first source / drain electrode of the fourth transistor T4 and can also be the second source / drain electrode of the third transistor T3.

[0136] The third contact pattern 133 can be disposed in the seventh contact hole CNT7, which penetrates the second interlayer insulating film ILD2 to expose the initialization line 124. The third contact pattern 133 can be electrically connected to the lower initialization line 124 and the upper sixth contact pattern 163. The third contact pattern 133 can be the second source / drain electrode of the fourth transistor T4 and can be the first source / drain electrode of the seventh transistor T7.

[0137] The first contact pattern 131, the second contact pattern 132, and the third contact pattern 133 may be surrounded by the second interlayer insulating film ILD2. The upper surfaces of the first contact pattern 131, the second contact pattern 132, and the third contact pattern 133 may contact each other without any steps with the upper surface of the second interlayer insulating film ILD2. In an embodiment, the upper surfaces of the first contact pattern 131, the second contact pattern 132, and the third contact pattern 133 may be positioned at the same level as the upper surface of the second interlayer insulating film ILD2 and may be substantially positioned on the same plane. For example, as described above, the second semiconductor arrangement layer FS2 may include the upper surface of the second interlayer insulating film ILD2 and the upper surface of the third conductive layer 130, and may be substantially (or completely) flat. Therefore, although the second semiconductor layer SC2 may be disposed above the second interlayer insulating film ILD2 and the third conductive layer 130, the process for crystallizing the second semiconductor layer SC2 can be easily performed.

[0138] The third conductive layer 130 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0139] The second semiconductor layer SC2 can be disposed on the second interlayer insulating film ILD2 and the third conductive layer 130. The second semiconductor layer SC2 can be disposed above the third conductive layer 130 and the second interlayer insulating film ILD2. For example, the second semiconductor layer SC2 can be disposed on the second interlayer insulating film ILD2 while covering at least a portion of the third conductive layer 130.

[0140] The second semiconductor layer SC2 may include a semiconductor pattern ACT1 of the first transistor T1, a semiconductor pattern ACT3 of the third transistor T3, and a first semiconductor connection portion LK1. The semiconductor pattern ACT1 of the first transistor T1 may include a channel region CH1 overlapping the gate electrode 141 of the first transistor T1 above in the thickness direction, a first source / drain region SD11 of the first transistor T1 located on one side of the channel region CH1, and a second source / drain region SD12 of the first transistor T1 located on the other side of the channel region CH1. The semiconductor pattern ACT3 of the third transistor T3 may include a channel region CH3 overlapping the gate electrode 142 of the third transistor T3 above in the thickness direction, a first source / drain region SD31 of the third transistor T3 located on one side of the channel region CH3, and a second source / drain region SD32 of the third transistor T3 located on the other side of the channel region CH3.

[0141] In other words, the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3 can be active layers constituting the first source / drain regions SD11 and SD31, the second source / drain regions SD12 and SD32, and the channel regions CH1 and CH3, and the first source / drain regions SD11 and SD31 and the second source / drain regions SD12 and SD32 can respectively contact the first source / drain electrode and the second source / drain electrode. One of the first source / drain regions SD11 and SD31 and the second source / drain regions SD12 and SD32 can be a source region, and the other of the first source / drain regions SD11 and SD31 and the second source / drain regions SD12 and SD32 can be a drain region. Charge carrier ions can be included in the first source / drain regions SD11 and SD31 and the second source / drain regions SD12 and SD32 of the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3, such that the first source / drain regions SD11 and SD31 and the second source / drain regions SD12 and SD32 can have higher conductivity and lower electrical resistance than the channel regions CH1 and CH3.

[0142] A first semiconductor connection portion LK1 can be disposed between the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3. The first semiconductor connection portion LK1 can electrically connect the second source / drain region SD12 of the first transistor T1 and the first source / drain region SD31 of the third transistor T3. Similar to the first source / drain regions SD11 and SD31 and the second source / drain regions SD12 and SD32 of the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3, the first semiconductor connection portion LK1 can include charge carrier ions, thereby enabling the first semiconductor connection portion LK1 to have high conductivity and low electrical resistance.

[0143] The second semiconductor layer SC2 can be made of polycrystalline silicon, monocrystalline silicon, amorphous silicon, or a combination thereof. When the second semiconductor layer SC2 can be made of polycrystalline silicon, the polycrystalline silicon can be formed by crystallizing amorphous silicon using crystallization methods such as rapid thermal annealing (RTA), solid-state crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), or sequential lateral solidification (SLS).

[0144] The first transistor T1 can be a driving transistor, and the semiconductor pattern ACT1 of the first transistor T1 can be spaced apart from the substrate SUB by a distance, thereby reducing the influence of the substrate SUB on the first transistor T1. Therefore, the display device 1 can be improved.

[0145] However, the present invention is not limited thereto, and the second semiconductor layer SC2 may include an oxide semiconductor. The oxide may include an oxide selected from at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), and combinations thereof. The oxide may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (IZO).

[0146] A second gate insulating film GI2 can be disposed on the second semiconductor layer SC2. The second gate insulating film GI2 can cover not only the upper surface of the second semiconductor layer SC2, excluding the portions where the eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10 can be formed, but also the side surfaces of the second semiconductor layer SC2. Furthermore, the second gate insulating film GI2 can cover at least a portion of the upper surfaces of the first contact pattern 131, the second contact pattern 132, and the third contact pattern 133. The second gate insulating film GI2 can be substantially disposed above the entire surface of the substrate SUB.

[0147] The second gate insulating film GI2 may include silicon compounds or metal oxides, or combinations thereof. For example, the second gate insulating film GI2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These may be used individually or in combination with each other.

[0148] The fourth conductive layer 140 may be disposed on the second gate insulating film GI2. The fourth conductive layer 140 may include the gate electrode 141 of the first transistor T1 and the gate electrode 142 of the third transistor T3.

[0149] The gate electrode 141 of the first transistor T1 can be electrically connected to the first electrode of the capacitor Cst. The first electrode of the capacitor Cst can be formed by the gate electrode 141 of the first transistor T1 itself, or it can be formed by a portion extending from the gate electrode 141 of the first transistor T1. For example, a portion of the pattern of the integrated fourth conductive layer 140 can overlap with the semiconductor pattern ACT1 of the first transistor T1 to serve as the gate electrode 141 of the first transistor T1 at a corresponding site, and another portion of the pattern of the integrated fourth conductive layer 140 can not overlap with the semiconductor pattern ACT1 of the first transistor T1 to serve as the first electrode of the capacitor Cst that overlaps with the second electrode 151 of the capacitor Cst.

[0150] The fourth conductive layer 140 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0151] The third interlayer insulating film ILD3 can be disposed on the fourth conductive layer 140. The third interlayer insulating film ILD3 can cover not only the upper surface of the fourth conductive layer 140 except for the portions where the eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10 can be formed, but also the side surfaces of the fourth conductive layer 140. The third interlayer insulating film ILD3 can be disposed substantially above the entire surface of the substrate SUB.

[0152] The third interlayer insulating film (ILD3) may include silicon compounds or metal oxides, or combinations thereof. For example, the third interlayer insulating film (ILD3) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These can be used individually or in combination with each other.

[0153] A fifth conductive layer 150 may be disposed on the third interlayer insulating film ILD3. The fifth conductive layer 150 may include the second electrode 151 of the capacitor Cst. The second electrode 151 of the capacitor Cst may be electrically connected to the first electrode of the gate electrode 141 of the first transistor T1 below, and the third interlayer insulating film ILD3 is between the second electrode 151 of the capacitor Cst and the first electrode of the capacitor Cst to form the capacitor Cst.

[0154] The capacitor Cst can be disposed on the second transistor T2 and the fourth transistor T4, and can be disposed below the fifth transistor T5 to the seventh transistor T7. For example, the capacitor Cst can be positioned between the second transistor T2 and the fourth transistor T4 and the fifth transistor T5 to the seventh transistor T7.

[0155] The fifth conductive layer 150 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0156] The fourth interlayer insulating film ILD4 can be disposed on the fifth conductive layer 150. The fourth interlayer insulating film ILD4 can cover not only the upper surface of the fifth conductive layer 150, excluding the portions where the eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10 can be formed, but also the side surfaces of the fifth conductive layer 150. The fourth interlayer insulating film ILD4 can be disposed substantially above the entire surface of the substrate SUB.

[0157] The upper surface of the fourth interlayer insulating film ILD4 can be flat without steps. Therefore, the process for crystallizing the third semiconductor layer SC3 disposed on the fourth interlayer insulating film ILD4 can be easily performed. Details will be described later.

[0158] The fourth interlayer insulating film (ILD4) can include silicon compounds or metal oxides. For example, the fourth interlayer insulating film (ILD4) can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These can be used individually or in combination with each other.

[0159] The sixth conductive layer 160 may be disposed on the fourth interlayer insulating film ILD4. The sixth conductive layer 160 may include a fourth contact pattern 161, a fifth contact pattern 162, and a sixth contact pattern 163.

[0160] The fourth contact pattern 161 can be disposed in the eighth contact hole CNT8, which penetrates the fourth interlayer insulating film ILD4 to expose the first source / drain region SD11 of the first transistor T1. The fourth contact pattern 161 can electrically connect the lower first source / drain region SD11 of the first transistor T1 and the upper second semiconductor connection portion LK2. However, the second semiconductor connection portion LK2 can be omitted, and in this case, the fourth contact pattern 161 can directly contact the second source / drain region SD52 of the fifth transistor T5, and can electrically connect the lower first source / drain region SD11 of the first transistor T1 and the lower second source / drain region SD52 of the fifth transistor T5. Therefore, the first source / drain region SD11 of the first transistor T1 and the second source / drain region SD52 of the fifth transistor T5 can be electrically connected by the fourth contact pattern 161. The fourth contact pattern 161 can be the first source / drain electrode of the first transistor T1 and can be the second source / drain electrode of the fifth transistor T5.

[0161] The fifth contact pattern 162 can be disposed in the ninth contact hole CNT9, which penetrates the fourth interlayer insulating film ILD4 to expose the second source / drain region SD12 of the first transistor T1. The fifth contact pattern 162 can be electrically connected to the lower second source / drain region SD12 of the first transistor T1 and the upper third semiconductor connection portion LK3. However, the third semiconductor connection portion LK3 can be omitted, and in this case, the fifth contact pattern 162 can directly contact the first source / drain region SD61 of the sixth transistor T6, and can be electrically connected to the lower second source / drain region SD12 of the first transistor T1 and the lower first source / drain region SD61 of the sixth transistor T6. Therefore, the second source / drain region SD12 of the first transistor T1 and the first source / drain region SD61 of the sixth transistor T6 can be electrically connected by the fifth contact pattern 162. The fifth contact pattern 162 can be the second source / drain electrode of the first transistor T1 and can be the first source / drain electrode of the sixth transistor T6.

[0162] The sixth contact pattern 163 can be disposed in the tenth contact hole CNT10, which penetrates the fourth interlayer insulating film ILD4 to expose the third contact pattern 133. The sixth contact pattern 163 can be electrically connected to the lower third contact pattern 133 and the upper first source / drain region SD71 of the seventh transistor T7. Therefore, the first source / drain region SD71 of the seventh transistor T7 and the second source / drain region SD42 of the fourth transistor T4 can be electrically connected by the sixth contact pattern 163, the third contact pattern 133, and the initialization line 124. The sixth contact pattern 163 can be the second source / drain electrode of the fourth transistor T4 and can also be the first source / drain electrode of the seventh transistor T7.

[0163] The fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163 may be surrounded by the fourth interlayer insulating film ILD4. The upper surfaces of the fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163 may contact each other without any steps with the upper surface of the fourth interlayer insulating film ILD4. In an embodiment, the upper surfaces of the fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163 may be positioned at the same level as the upper surface of the fourth interlayer insulating film ILD4 and may be substantially positioned on the same plane. For example, as described above, the third semiconductor arrangement layer FS3 may include the upper surface of the fourth interlayer insulating film ILD4 and the upper surface of the sixth conductive layer 160, and may be substantially (or completely) flat. Therefore, although the third semiconductor layer SC3 may be disposed above the fourth interlayer insulating film ILD4 and the sixth conductive layer 160, the process for crystallizing the third semiconductor layer SC3 can be easily performed.

[0164] The sixth conductive layer 160 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0165] The third semiconductor layer SC3 can be disposed on the fourth interlayer insulating film ILD4 and the sixth conductive layer 160. The third semiconductor layer SC3 can be disposed above the sixth conductive layer 160 and the fourth interlayer insulating film ILD4. For example, the third semiconductor layer SC3 can be disposed on the fourth interlayer insulating film ILD4 while covering at least a portion of the sixth conductive layer 160.

[0166] The sixth conductive layer 160 may include a semiconductor pattern ACT5 of the fifth transistor T5, a semiconductor pattern ACT6 of the sixth transistor T6, a semiconductor pattern ACT7 of the seventh transistor T7, a second semiconductor connection portion LK2, and a third semiconductor connection portion LK3.

[0167] The semiconductor pattern ACT5 of the fifth transistor T5 may include a channel region CH5 overlapping the gate electrode 171 of the fifth transistor T5 above in the thickness direction, a first source / drain region SD51 of the fifth transistor T5 located on one side of the channel region CH5, and a second source / drain region SD52 of the fifth transistor T5 located on the other side of the channel region CH5. The semiconductor pattern ACT6 of the sixth transistor T6 may include a channel region CH6 overlapping the gate electrode 172 of the sixth transistor T6 above in the thickness direction, a first source / drain region SD61 of the sixth transistor T6 located on one side of the channel region CH6, and a second source / drain region SD62 of the sixth transistor T6 located on the other side of the channel region CH6. The semiconductor pattern ACT7 of the seventh transistor T7 may include a channel region CH7 that overlaps with the gate electrode 173 of the seventh transistor T7 above in the thickness direction, a first source / drain region SD71 of the seventh transistor T7 located on one side of the channel region CH7, and a second source / drain region SD72 of the seventh transistor T7 located on the other side of the channel region CH7.

[0168] In other words, the semiconductor pattern ACT5 of the fifth transistor T5, the semiconductor pattern ACT6 of the sixth transistor T6, and the semiconductor pattern ACT7 of the seventh transistor T7 can be active layers constituting the first source / drain regions SD51, SD61, and SD71, the second source / drain regions SD52, SD62, and SD72, and the channel regions CH5, CH6, and CH7. Furthermore, the first source / drain regions SD51, SD61, and SD71, and the second source / drain regions SD52, SD62, and SD72 can respectively contact the first source / drain electrode and the second source / drain electrode. One of the first source / drain regions SD51, SD61, and SD71, and the second source / drain regions SD52, SD62, and SD72 can be a source region, and the other of the first source / drain regions SD51, SD61, and SD71, and the second source / drain regions SD52, SD62, and SD72 can be a drain region. Charge carrier ions can be included in the first source / drain regions SD51, SD61, and SD71 and the second source / drain regions SD52, SD62, and SD72 of the semiconductor pattern ACT5 of the fifth transistor T5, the semiconductor pattern ACT6 of the sixth transistor T6, and the semiconductor pattern ACT7 of the seventh transistor T7, such that the first source / drain regions SD51, SD61, and SD71 and the second source / drain regions SD52, SD62, and SD72 can have higher conductivity and lower electrical resistance than the channel regions CH5, CH6, and CH7.

[0169] The second semiconductor connection portion LK2 can be disposed on the side surface of the semiconductor pattern ACT5 of the fifth transistor T5. The second semiconductor connection portion LK2 can electrically connect the second source / drain region SD52 of the fifth transistor T5 and the fourth contact pattern 161.

[0170] The third semiconductor connection portion LK3 can be disposed on the side surface of the semiconductor pattern ACT6 of the sixth transistor T6. The third semiconductor connection portion LK3 can electrically connect the first source / drain region SD61 of the sixth transistor T6 and the fifth contact pattern 162.

[0171] Like the first source / drain regions SD51, SD61, and SD71 and the second source / drain regions SD52, SD62, and SD72 of the semiconductor pattern ACT5 of the fifth transistor T5, the semiconductor pattern ACT6 of the sixth transistor T6, and the semiconductor pattern ACT7 of the seventh transistor T7, each of the second semiconductor connection portion LK2 and the third semiconductor connection portion LK3 may include charge carrier ions, such that each of the second semiconductor connection portion LK2 and the third semiconductor connection portion LK3 can have high conductivity and low electrical resistance.

[0172] The third semiconductor layer SC3 can be made of polycrystalline silicon, monocrystalline silicon, or amorphous silicon. When the third semiconductor layer SC3 can be made of polycrystalline silicon, the polycrystalline silicon can be formed by crystallizing the amorphous silicon using crystallization methods such as rapid thermal annealing (RTA), solid-state crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), or sequential lateral solidification (SLS).

[0173] However, the present invention is not limited thereto, and the third semiconductor layer SC3 may include an oxide semiconductor. The oxide may include an oxide selected from at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), and combinations thereof. The oxide may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (IZO).

[0174] A third gate insulating film GI3 can be disposed on the third semiconductor layer SC3. The third gate insulating film GI3 can cover not only the upper surface of the third semiconductor layer SC3, excluding the portions where the eleventh contact hole CNT11, the twelfth contact hole CNT12, and the thirteenth contact hole CNT13 can be formed, but also the side surfaces of the third semiconductor layer SC3. Furthermore, the third gate insulating film GI3 can cover at least a portion of the upper surfaces of the fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163. The third gate insulating film GI3 can be substantially disposed above the entire surface of the substrate SUB.

[0175] The third gate insulating film GI3 may include silicon compounds or metal oxides, or combinations thereof. For example, the third gate insulating film GI3 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These may be used individually or in combination with each other.

[0176] The seventh conductive layer 170 may be disposed on the third gate insulating film GI3. The seventh conductive layer 170 may include the gate electrode 171 of the fifth transistor T5, the gate electrode 172 of the sixth transistor T6, and the gate electrode 173 of the seventh transistor T7. The seventh conductive layer 170 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0177] The fifth interlayer insulating film (ILD5) can be disposed on the seventh conductive layer 170. The fifth interlayer insulating film (ILD5) can cover not only the upper surface of the seventh conductive layer 170, excluding the portions where the eleventh contact hole CNT11, the twelfth contact hole CNT12, and the thirteenth contact hole CNT13 can be formed, but also the side surfaces of the seventh conductive layer 170. The fifth interlayer insulating film (ILD5) can be substantially disposed above the entire surface of the substrate SUB. The fifth interlayer insulating film (ILD5) can include silicon compounds or metal oxides, or combinations thereof. For example, the fifth interlayer insulating film (ILD5) can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These can be used individually or in combination with each other.

[0178] The eighth conductive layer 180 may be disposed on the fifth interlayer insulating film ILD5. The eighth conductive layer 180 may include a first power supply voltage line ELVDL (hereinafter "181"), a third conductive pattern 182, and a fourth conductive pattern 183.

[0179] The first power supply voltage line 181 can be electrically connected to the first source / drain region SD51 of the fifth transistor T5 via the eleventh contact hole CNT11. The eleventh contact hole CNT11 penetrates the fifth interlayer insulating film ILD5 and the third gate insulating film GI3 to expose the first source / drain region SD51 of the fifth transistor T5. The first power supply voltage line 181 itself can be the first source / drain electrode of the fifth transistor T5, or a portion of the first power supply voltage line 181 can be the first source / drain electrode of the fifth transistor T5.

[0180] The third conductive pattern 182 can be electrically connected to the second source / drain region SD62 of the sixth transistor T6 via the twelfth contact hole CNT12. The twelfth contact hole CNT12 penetrates the fifth interlayer insulating film ILD5 and the third gate insulating film GI3 to expose the second source / drain region SD62 of the sixth transistor T6. The third conductive pattern 182 can electrically connect the second source / drain region SD62 of the sixth transistor T6 and the anode electrode ANO. The third conductive pattern 182 itself can be the second source / drain electrode of the sixth transistor T6, or a portion of the third conductive pattern 182 can be the second source / drain electrode of the sixth transistor T6. The third conductive pattern 182 can be the second source / drain electrode of the sixth transistor T6.

[0181] The fourth conductive pattern 183 can be electrically connected to the second source / drain region SD72 of the seventh transistor T7 via the thirteenth contact hole CNT13. The thirteenth contact hole CNT13 penetrates the fifth interlayer insulating film ILD5 and the third gate insulating film GI3 to expose the second source / drain region SD72 of the seventh transistor T7. The fourth conductive pattern 183 can electrically connect the second source / drain region SD72 of the seventh transistor T7 and the anode electrode ANO. The fourth conductive pattern 183 itself can be the second source / drain electrode of the seventh transistor T7, or a portion of the fourth conductive pattern 183 can be the second source / drain electrode of the seventh transistor T7. The fourth conductive pattern 183 can be the second source / drain electrode of the seventh transistor T7.

[0182] A via layer VIA can be disposed on the eighth conductive layer 180. The via layer VIA may comprise an inorganic insulating material or an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or combinations thereof. An anode electrode ANO can be disposed on the via layer VIA. The anode electrode ANO can be a pixel electrode that can be individually disposed for each pixel PX. The anode electrode ANO can be electrically connected to the third conductive pattern 182 via a fourteenth contact hole CNT14, which passes through the via layer VIA to expose the third conductive pattern 182, and the anode electrode ANO can be electrically connected to the fourth conductive pattern 183 via a fifteenth contact hole CNT15, which passes through the via layer VIA to expose the fourth conductive pattern 183.

[0183] The anode electrode (ANO) can have a laminated film structure, in which a high work function material layer of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) and a reflective material layer of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof can be laminated. The high work function material layer can be disposed above the reflective material layer to be closer to the light-emitting layer (EL). The anode electrode (ANO) can have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but the present invention is not limited thereto.

[0184] A pixel defining layer (PDL) may be disposed on the anode electrode (ANO). The PDL may include openings that partially expose the anode electrode (ANO). The PDL may comprise an organic or inorganic insulating material. For example, the PDL may comprise at least one of a polyimide resin, an acrylic resin, a silicone compound, and a polyacrylic resin.

[0185] The light-emitting layer (EL) can be disposed on the anode electrode (ANO) exposed by the pixel-defining layer (PDL). The EL may include an organic material layer. The organic material layer of the EL may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0186] The cathode electrode CAT can be disposed on the light-emitting layer EL. The cathode electrode CAT can be a common electrode that can be completely disposed regardless of the pixel PX. The cathode electrode CAT may include a low work function material layer, including lithium (Li), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al), magnesium (Mg), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), gold (Au), neodymium (Nd), iridium (Ir), chromium (Cr), barium fluoride (BaF), barium (Ba), compounds thereof, or mixtures of the foregoing materials (e.g., a mixture of Ag and Mg). The cathode electrode CAT may also include a transparent metal oxide layer disposed on the low work function material layer.

[0187] An anode (ANO), a light-emitting layer (EL), and a cathode (CAT) can constitute an organic light-emitting element.

[0188] A thin-film encapsulation layer 190 may be disposed on the cathode electrode CAT. The thin-film encapsulation layer 190 may include a first inorganic layer 191, a first organic layer 192, and a second inorganic layer 193. At the ends of the thin-film encapsulation layer 190, the first inorganic layer 191 and the second inorganic layer 193 may be in contact with each other. The first organic layer 192 may be encapsulated by the first inorganic layer 191 and the second inorganic layer 193. Each of the first inorganic layer 191 and the second inorganic layer 193 may each include silicon nitride, silicon oxide, or silicon oxynitride. The first organic layer 192 may include an organic insulating material.

[0189] Hereinafter, a method for manufacturing the display device 1 according to an embodiment will be described.

[0190] Figures 6 to 25 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment.

[0191] Reference Figure 6 The substrate SUB can be prepared, and the substrate SUB is provided with a patterned first semiconductor layer SC1. Specifically, as... Figure 6 As shown, the first semiconductor layer SC1 can be formed by completely depositing the first semiconductor material on the upper surface of the substrate SUB, that is, on the first semiconductor arrangement layer FS1, and then patterning the first semiconductor material by a photolithography process.

[0192] Subsequently, referring to Figure 7 The first gate insulating film GI1 can be formed on the first semiconductor layer SC1, and the first conductive layer 110, including the gate electrode 111 of the second transistor T2 and the gate electrode 112 of the fourth transistor T4, can be formed on the first gate insulating film GI1.

[0193] Specifically, a first gate insulating film GI1 can be formed on the entire surface of a substrate SUB on which a first semiconductor layer SC1 can be formed. Subsequently, the gate electrode 111 of the second transistor T2 and the gate electrode 112 of the fourth transistor T4 can be formed on the first gate insulating film GI1. The gate electrode 111 of the second transistor T2 and the gate electrode 112 of the fourth transistor T4, which can be patterned, can be formed by a mask process. For example, as Figure 7 As shown, the gate electrode 111 of the second transistor T2 and the gate electrode 112 of the fourth transistor T4 can be formed by completely depositing a material layer for the first conductive layer 110 on the first gate insulating film GI1, and then patterning the material layer for the first conductive layer 110 by a photolithography process.

[0194] Subsequently, referring to Figure 8 The first interlayer insulating film ILD1 can be laminated on the first conductive layer 110, and the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3 and the fourth contact hole CNT4 exposing the first semiconductor layer SC1 can be formed.

[0195] Specifically, the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 can be formed by a single mask process. The first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 can be formed simultaneously using the same mask. For example, the first interlayer insulating film ILD1 can be completely deposited on the first gate insulating film GI1, which is formed on the gate electrode 111 of the second transistor T2 and the gate electrode 112 of the fourth transistor T4. Subsequently, a photoresist pattern exposing the portion of the first interlayer insulating film ILD1 can be formed on the first interlayer insulating film ILD1, and the first interlayer insulating film ILD1 and the first gate insulating film GI1 can be etched using this photoresist pattern as an etching mask to form the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 exposing the portion of the first semiconductor layer SC1.

[0196] Subsequently, referring to Figure 9 The second conductive layer 120, including data line 121, first conductive pattern 122, second conductive pattern 123 and initialization line 124, can be formed on the first interlayer insulating film ILD1.

[0197] Specifically, the patternable second conductive layer 120 can be formed by a masking process. For example, the material layer for the second conductive layer 120 can be completely deposited on the first interlayer insulating film ILD1. In the deposition process, the material layer for the second conductive layer 120 can be deposited inside the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. Therefore, each of the data line 121, the first conductive pattern 122, the second conductive pattern 123, and the initialization line 124 can be electrically connected to the first semiconductor layer SC1. Subsequently, a photoresist layer can be applied to the material layer for the second conductive layer 120, the photoresist pattern can be formed via exposure and development, and then the material layer for the second conductive layer 120 can be etched using the photoresist pattern as an etching mask. Afterwards, as... Figure 9 As shown, the photoresist pattern can be removed via a stripping or ashing process to complete the patterned second conductive layer 120.

[0198] Subsequently, referring to Figures 10 to 12 Before polishing, the second interlayer insulating film ILD2a and the third conductive layer 130a can be sequentially formed on the second conductive layer 120 and can be planarized to form the second semiconductor arrangement layer FS2.

[0199] First, a second interlayer insulating film ILD2a, before polishing, can be formed on a first interlayer insulating film ILD1 on which the second conductive layer 120 is provided, and fifth contact holes CNT5, sixth contact holes CNT6, and seventh contact holes CNT7 can be formed to expose the second conductive layer 120. The fifth contact holes CNT5, sixth contact holes CNT6, and seventh contact holes CNT7 can be formed by a mask process. For example, the second interlayer insulating film ILD2a before polishing can be completely deposited on the first interlayer insulating film ILD1 on which the second conductive layer 120 is provided. Subsequently, a photoresist pattern can be formed on the portion of the second interlayer insulating film ILD2a that exposes the second interlayer insulating film ILD2a before polishing, and the second interlayer insulating film ILD2a before polishing can be etched using the photoresist pattern as an etch mask to form the fifth contact holes CNT5, sixth contact holes CNT6, and seventh contact holes CNT7 that expose the portion of the second conductive layer 120.

[0200] After forming the fifth contact hole CNT5, the sixth contact hole CNT6, and the seventh contact hole CNT7, a pre-polishing third conductive layer 130a can be formed on the pre-polishing second interlayer insulating film ILD2a. The pre-polishing third conductive layer 130a can be formed by a deposition process. For example, the material layer for the third conductive layer 130 can be completely deposited on the pre-polishing second interlayer insulating film ILD2a. In the deposition process, the material layer for the third conductive layer 130 can be deposited into the interior of the fifth contact hole CNT5, the sixth contact hole CNT6, and the seventh contact hole CNT7. Therefore, the pre-polishing third conductive layer 130a can be electrically connected to the second conductive layer 120, and after polishing, each of the first contact pattern 131, the second contact pattern 132, and the third contact pattern 133 can be electrically connected to the second conductive layer 120.

[0201] After the formation of the third conductive layer 130a before polishing, the second semiconductor arrangement layer FS2 can be formed. For example... Figure 12As indicated by the downward-pointing arrow, the second semiconductor arrangement layer FS2 can be formed by planarizing the unpolished second interlayer insulating film ILD2a and the unpolished third conductive layer 130a by removing portions of the unpolished second interlayer insulating film ILD2a and the unpolished third conductive layer 130a via chemical mechanical polishing (CMP). The chemical mechanical polishing process for forming the second semiconductor arrangement layer FS2 can be performed using the slurry required to planarize the unpolished second interlayer insulating film ILD2a and the unpolished third conductive layer 130a. Through chemical mechanical polishing, the thickness of the unpolished second interlayer insulating film ILD2a can be reduced, and the first contact pattern 131, the second contact pattern 132, and the third contact pattern 133 can be formed. However, the method for planarizing the unpolished second interlayer insulating film ILD2a and the unpolished third conductive layer 130a is not limited to this. In the case where the second semiconductor layer SC2 comprises an oxide semiconductor, the process for planarizing the second semiconductor arrangement layer FS2 can be omitted.

[0202] Subsequently, referring to Figure 13 The patterned second semiconductor layer SC2 can be formed on the second interlayer insulating film ILD2 and the third conductive layer 130. The patterned second semiconductor layer SC2 can also be disposed on the second semiconductor arrangement layer FS2. For example... Figure 13 As shown, after the material for the second semiconductor layer SC2 can be completely deposited on the second semiconductor arrangement layer FS2, the material for the second semiconductor layer SC2 can be patterned via a photolithography process to form the second semiconductor layer SC2.

[0203] Subsequently, referring to Figure 14 The second gate insulating film GI2 can be formed on the second semiconductor layer SC2, and the fourth conductive layer 140, including the gate electrode 141 of the first transistor T1 and the gate electrode 142 of the third transistor T3, can be formed on the second gate insulating film GI2.

[0204] Specifically, the second gate insulating film GI2 can be formed on the entire surface of the second interlayer insulating film ILD2, on which the second semiconductor layer SC2 can be formed. Subsequently, the gate electrode 141 of the first transistor T1 and the gate electrode 142 of the third transistor T3 can be formed on the second gate insulating film GI2. The gate electrode 141 of the first transistor T1 and the gate electrode 142 of the third transistor T3, which can be patterned, can be formed by a mask process. For example, as Figure 14 As shown, the gate electrode 141 of the first transistor T1 and the gate electrode 142 of the third transistor T3 can be formed by completely depositing a material layer for the fourth conductive layer 140 on the second gate insulating film GI2, and then patterning the material layer for the fourth conductive layer 140 by a photolithography process.

[0205] Subsequently, referring to Figure 15 The third interlayer insulating film ILD3 can be formed on the fourth conductive layer 140, and the fifth conductive layer 150 including the second electrode 151 of the capacitor Cst can be formed on the third interlayer insulating film ILD3.

[0206] Specifically, the third interlayer insulating film ILD3 can be formed on the entire surface of the second gate insulating film GI2, on which the fourth conductive layer 140 can be formed. Then, the second electrode 151 of the capacitor Cst can be formed on the third interlayer insulating film ILD3. For example, as... Figure 15 As shown, the second electrode 151 of the capacitor Cst can be formed by completely depositing a material layer for the fifth conductive layer 150 on the third interlayer insulating film ILD3, and then patterning the material layer for the fifth conductive layer 150 by a photolithography process.

[0207] Subsequently, referring to Figures 16 to 18 Before polishing, the fourth interlayer insulating film ILD4a and the sixth conductive layer 160a can be sequentially formed on the fifth conductive layer 150, and can be planarized to form the third semiconductor arrangement layer FS3.

[0208] First, a fourth interlayer insulating film ILD4a, before polishing, can be formed on a third interlayer insulating film ILD3 to which a fifth conductive layer 150 is provided, and an eighth contact hole CNT8, a ninth contact hole CNT9, and a tenth contact hole CNT10 can be formed to expose the second semiconductor layer SC2. The eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10 can be formed by a mask process. For example, the fourth interlayer insulating film ILD4a before polishing can be completely deposited on the third interlayer insulating film ILD3 to which the fifth conductive layer 150 is provided. Subsequently, a photoresist pattern for the portion exposing the second semiconductor layer SC2 can be formed on the fourth interlayer insulating film ILD4a before polishing, and the fourth interlayer insulating film ILD4a before polishing can be etched using the photoresist pattern as an etch mask to form the eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10 for the portion exposing the second semiconductor layer SC2.

[0209] After forming the eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10, a sixth conductive layer 160a before polishing can be formed on the fourth interlayer insulating film ILD4a before polishing. The sixth conductive layer 160a before polishing can be formed by a deposition process. For example, the material layer for the sixth conductive layer 160 can be completely deposited on the fourth interlayer insulating film ILD4a before polishing. In the deposition process, the material layer for the sixth conductive layer 160 can be deposited inside the eighth contact hole CNT8, the ninth contact hole CNT9, and the tenth contact hole CNT10. Therefore, the sixth conductive layer 160a before polishing can be electrically connected to the second semiconductor layer SC2, and after polishing, each of the fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163 can be electrically connected to the second semiconductor layer SC2.

[0210] After the formation of the sixth conductive layer 160a before polishing, the third semiconductor arrangement layer FS3 can be formed. For example... Figure 18 As indicated by the downward-pointing arrow, the third semiconductor arrangement layer FS3 can be formed by planarizing the unpolished fourth interlayer insulating film ILD4a and the unpolished sixth conductive layer 160a by removing portions of the unpolished fourth interlayer insulating film ILD4a and the unpolished sixth conductive layer 160a via chemical mechanical polishing (CMP). The CMP process for forming the third semiconductor arrangement layer FS3 can be performed using the slurry required to planarize the unpolished fourth interlayer insulating film ILD4a and the unpolished sixth conductive layer 160a. Through CMP, the thickness of the unpolished fourth interlayer insulating film ILD4a can be reduced, and the fourth contact pattern 161, the fifth contact pattern 162, and the sixth contact pattern 163 can be formed. However, the method for planarizing the unpolished fourth interlayer insulating film ILD4a and the unpolished sixth conductive layer 160a is not limited to this. In the case where the second semiconductor layer SC2 comprises an oxide semiconductor, the process for planarizing the third semiconductor arrangement layer FS3 can be omitted.

[0211] Subsequently, referring to Figure 19 The patterned third semiconductor layer SC3 can be formed on the fourth interlayer insulating film ILD4 and the sixth conductive layer 160. The patterned third semiconductor layer SC3 can also be disposed on the third semiconductor arrangement layer FS3. For example... Figure 19 As shown, after the material for the third semiconductor layer SC3 can be completely deposited on the third semiconductor arrangement layer FS3, the material for the third semiconductor layer SC3 can be patterned by photolithography to form the third semiconductor layer SC3.

[0212] Subsequently, referring to Figure 20The third gate insulating film GI3 can be formed on the third semiconductor layer SC3, and the seventh conductive layer 170, including the gate electrode 171 of the fifth transistor T5, the gate electrode 172 of the sixth transistor T6 and the gate electrode 173 of the seventh transistor T7, can be formed on the third gate insulating film GI3.

[0213] Specifically, the third gate insulating film GI3 can be formed on the entire surface of the fourth interlayer insulating film ILD4, on which the third semiconductor layer SC3 can be formed. Subsequently, the gate electrode 171 of the fifth transistor T5, the gate electrode 172 of the sixth transistor T6, and the gate electrode 173 of the seventh transistor T7 can be formed on the third gate insulating film GI3. The gate electrode 171 of the fifth transistor T5, the gate electrode 172 of the sixth transistor T6, and the gate electrode 173 of the seventh transistor T7, which can be patterned, can be formed by a mask process. For example, as Figure 20 As shown, the gate electrode 171 of the fifth transistor T5, the gate electrode 172 of the sixth transistor T6, and the gate electrode 173 of the seventh transistor T7 can be formed by completely depositing a material layer for the seventh conductive layer 170 on the third gate insulating film GI3, and then patterning the material layer for the seventh conductive layer 170 by a photolithography process.

[0214] Subsequently, referring to Figure 21 The fifth interlayer insulating film ILD5 can be laminated on the seventh conductive layer 170, and the eleventh contact hole CNT11, the twelfth contact hole CNT12 and the thirteenth contact hole CNT13 exposing the third semiconductor layer SC3 can be formed.

[0215] Specifically, the eleventh contact hole CNT11, the twelfth contact hole CNT12, and the thirteenth contact hole CNT13 can be formed by a single mask process. The eleventh contact hole CNT11, the twelfth contact hole CNT12, and the thirteenth contact hole CNT13 can be formed simultaneously using the same mask. For example, the fifth interlayer insulating film ILD5 can be completely deposited on the third gate insulating film GI3, on which the gate electrode 171 of the fifth transistor T5, the gate electrode 172 of the sixth transistor T6, and the gate electrode 173 of the seventh transistor T7 can be formed. Subsequently, a photoresist pattern exposing the portion of the fifth interlayer insulating film ILD5 can be formed on the fifth interlayer insulating film ILD5, and the fifth interlayer insulating film ILD5 and the third gate insulating film GI3 can be etched using this photoresist pattern as an etch mask to form the eleventh contact hole CNT11, the twelfth contact hole CNT12, and the thirteenth contact hole CNT13 exposing the portion of the third semiconductor layer SC3.

[0216] Subsequently, referring to Figure 22An eighth conductive layer 180, including a first power supply voltage line 181, a third conductive pattern 182, and a fourth conductive pattern 183, can be formed on the fifth interlayer insulating film ILD5.

[0217] Specifically, the patterned eighth conductive layer 180 can be formed by a masking process. For example, the material layer for the eighth conductive layer 180 can be completely deposited on the fifth interlayer insulating film ILD5. In the deposition process, the material layer for the eighth conductive layer 180 can be deposited inside the eleventh contact hole CNT11, the twelfth contact hole CNT12, and the thirteenth contact hole CNT13. Therefore, each of the first power supply voltage line 181, the third conductive pattern 182, and the fourth conductive pattern 183 can be electrically connected to the third semiconductor layer SC3. Subsequently, a photoresist layer can be applied to the material layer for the eighth conductive layer 180, the photoresist pattern can be formed via exposure and development, and then the material layer for the eighth conductive layer 180 can be etched using the photoresist pattern as an etching mask. Afterwards, as... Figure 22 As shown, the photoresist pattern can be removed via a stripping or ashing process to complete the patterned eighth conductive layer 180.

[0218] Subsequently, referring to Figure 23 The via layer VIA can be laminated on the eighth conductive layer 180, and the fourteenth contact hole CNT14 and the fifteenth contact hole CNT15 exposing the eighth conductive layer 180 can be formed.

[0219] Specifically, the fourteenth contact hole CNT14 and the fifteenth contact hole CNT15 can be formed by a single mask process. The fourteenth contact hole CNT14 and the fifteenth contact hole CNT15 can be formed simultaneously using the same mask. For example, the via layer VIA can be completely deposited on the first power supply voltage line 181, and the third conductive pattern 182 and the fourth conductive pattern 183 can be formed thereon on the fifth interlayer insulating film ILD5. Subsequently, a photoresist pattern exposing the portion of the via layer VIA can be formed on the via layer VIA, and the via layer VIA can be etched using this photoresist pattern as an etching mask to form the fourteenth contact hole CNT14 and the fifteenth contact hole CNT15 exposing the portion of the eighth conductive layer 180.

[0220] Subsequently, referring to Figure 24 The anode electrode ANO can be formed on the via layer VIA.

[0221] Specifically, the anode electrode ANO can be formed by a mask process. For example, the material layer for the anode electrode ANO can be completely deposited on the via layer VIA. In the deposition process, the material layer for the anode electrode ANO can be deposited inside the fourteenth contact hole CNT14 and the fifteenth contact hole CNT15. ​​Therefore, the anode electrode ANO can be connected to the third conductive pattern 182 and the fourth conductive pattern 183. Subsequently, a photoresist layer can be applied to the material layer for the anode electrode ANO, the photoresist pattern can be formed via exposure and development, and then the material layer for the anode electrode ANO can be etched using the photoresist pattern as an etching mask. Afterwards, as... Figure 24 As shown, the photoresist pattern can be removed by a stripping or ashing process to complete the patterned anode electrode ANO.

[0222] Subsequently, referring to Figure 25 A patterned pixel-defined layer (PDL) can be formed on the anode electrode (ANO) on which a via layer (VIA) can be formed.

[0223] The pixel-defined layer (PDL) may include, for example, an organic material comprising a photosensitive material. A patterned pixel-defined layer (PDL) can be formed by applying an organic material layer for the diaphragm and subsequently exposing and developing the organic material layer.

[0224] The pixel defining layer (PDL) can be formed along the boundary of the pixel (PX) and can partially overlap with the anode electrode (ANO). The pixel defining layer (PDL) can be formed to overlap with the fourteenth contact hole (CNT14) and the fifteenth contact hole (CNT15). Even if the anode electrode (ANO) does not completely fill the internal space of the fourteenth contact hole (CNT14) and the fifteenth contact hole (CNT15) and only partially fills them, the pixel defining layer (PDL) can completely fill the internal space of the fourteenth contact hole (CNT14) and the fifteenth contact hole (CNT15).

[0225] The light-emitting layer EL, the cathode electrode CAT, and the thin-film encapsulation layer 190 can be further disposed on the pixel defining layer PDL, but the methods for manufacturing the light-emitting layer EL, the cathode electrode CAT, and the thin-film encapsulation layer 190 are widely known, and therefore a detailed description is omitted.

[0226] Other embodiments will be described below. In the embodiments described below, for components that are the same as those previously described, repeated descriptions will be omitted or simplified, and differences will be described.

[0227] Figure 26 This is a schematic cross-sectional view of pixels according to another embodiment.

[0228] Reference Figure 26The display device 1 in the embodiment and Figure 5 The difference in the embodiment of the display device 1 may be that the fifth conductive pattern 152_1, the sixth conductive pattern 153_1 and the seventh conductive pattern 154_1 may be further configured to be electrically connected between the second source / drain region SD52 of the fifth transistor T5 and the first source / drain region SD11 of the first transistor T1, between the first source / drain region SD61 of the sixth transistor T6 and the second source / drain region SD12 of the first transistor T1, and between the first source / drain region SD71 of the seventh transistor T7 and the second source / drain region SD32 of the third transistor T3.

[0229] Specifically, the display device 1 according to the embodiment may further include a fifth conductive pattern 152_1, a sixth conductive pattern 153_1, and a seventh conductive pattern 154_1. Although not limited thereto, the fifth conductive pattern 152_1, the sixth conductive pattern 153_1, and the seventh conductive pattern 154_1 may be included in the fifth conductive layer 150_1 and may be formed together with the second electrode 151 of the capacitor Cst.

[0230] The fifth conductive pattern 152_1, the sixth conductive pattern 153_1, and the seventh conductive pattern 154_1 can be electrically connected to the second semiconductor layer SC2 via the sixteenth contact hole CNT16, the seventeenth contact hole CNT17, and the eighteenth contact hole CNT18. The sixteenth contact hole CNT16, the seventeenth contact hole CNT17, and the eighteenth contact hole CNT18 penetrate the third interlayer insulating film ILD3 and the second gate insulating film GI2 to expose the second semiconductor layer SC2. Since the fifth conductive pattern 152_1, the sixth conductive pattern 153_1, and the seventh conductive pattern 154_1 can be further configured, the length of the eighth contact hole CNT8_1, the ninth contact hole CNT9_1, and the tenth contact hole CNT10_1 in the thickness direction (third direction DR3) can be reduced, the fifth conductive layer 150_1 can be exposed, and the fourth contact pattern 161_1, the fifth contact pattern 162_1, and the sixth contact pattern 163_1 of the sixth conductive layer 160_1 can be electrically connected to the fifth conductive layer 150_1. Therefore, the second source / drain region SD52 of the fifth transistor T5 and the first source / drain region SD11 of the first transistor T1 can be electrically connected to each other by the fourth contact pattern 161_1 and the fifth conductive pattern 152_1, the first source / drain region SD61 of the sixth transistor T6 and the second source / drain region SD12 of the first transistor T1 can be electrically connected to each other by the fifth contact pattern 162_1 and the sixth conductive pattern 153_1, and the first source / drain region SD71 of the seventh transistor T7 and the second source / drain region SD42 of the fourth transistor T4 can be electrically connected to each other by the sixth contact pattern 163_1, the seventh conductive pattern 154_1 and the initialization line 124.

[0231] Even under these conditions, the area of ​​the plane in which transistors T1 to T7 of a pixel can be disposed can be reduced, and thus the display device 1 can achieve a higher resolution. Furthermore, the length of some contact holes in the thickness direction (third direction DR3) can be reduced, and thus the conductive layer can be more easily formed in the contact holes. Therefore, the electrical connection between transistors T1 to T7 can be more stable.

[0232] Figure 27 This is a schematic cross-sectional view of pixels according to another embodiment.

[0233] Reference Figure 27 The display device 1 in the embodiment and Figure 5 The difference in the embodiment of the display device 1 may be that the sub-gate insulating film GIS_2 may be further disposed on the second gate insulating film GI2.

[0234] Specifically, the display device 1 according to the embodiment may further include a sub-gate insulating film GIS_2 between the gate electrode 141 of the first transistor T1 and the semiconductor pattern ACT1 of the first transistor T1. The sub-gate insulating film GIS_2 may overlap at least with the gate electrode 141 of the first transistor T1 and / or the channel region CH1 of the first transistor T1. In other words, the gate insulating film of the first transistor T1 may include a second gate insulating film GI2 and the sub-gate insulating film GIS_2. Furthermore, the thickness between the gate electrode 141 of the first transistor T1 and the semiconductor pattern ACT1 of the first transistor T1 may be greater than the thickness between the gate electrode 142 of the third transistor T3 and the semiconductor pattern ACT3 of the third transistor T3. Therefore, the driving characteristics of the first transistor T1 as a driving transistor can be improved, while maintaining the switching characteristics of the third transistor T3 as a switching transistor.

[0235] Even under these conditions, the area of ​​the plane in which the transistors T1 to T7 of a pixel can be placed can be reduced, and thus the display device 1 can achieve a higher resolution.

[0236] Figure 28 This is a schematic cross-sectional view of pixels according to another embodiment.

[0237] Reference Figure 28 The display device 1 in the embodiment and Figure 5 The difference in the embodiment of the display device 1 may be that each of the first semiconductor layer SC1_3 and the third semiconductor layer SC3_3 includes an oxide semiconductor.

[0238] Specifically, in the display device 1 according to the embodiment, the second semiconductor layer SC2, which includes the semiconductor pattern ACT1 of the first transistor T1 and the semiconductor pattern ACT3 of the third transistor T3, may include polycrystalline silicon, monocrystalline silicon, amorphous silicon, or a combination thereof, while the first semiconductor layer SC1_3, which includes the semiconductor pattern ACT2 of the second transistor T2 and the semiconductor pattern ACT4 of the fourth transistor T4, and the third semiconductor layer SC3_3, which includes the semiconductor pattern ACT5 of the fifth transistor T5, the semiconductor pattern ACT6 of the sixth transistor T6, and the semiconductor pattern ACT7 of the seventh transistor T7, may include oxide semiconductor.

[0239] The process used to planarize the third semiconductor placement layer FS3 may be unnecessary. For example, the third semiconductor layer SC3_3 can be a third semiconductor placement layer disposed thereon. Figure 5 The “FS3” in the diagram may not be flat. The upper surface of the fourth interlayer insulating film ILD4_3 may have a step, and the upper surface of the fourth interlayer insulating film ILD4_3 and the upper surface of the sixth conductive layer 160_3 may not be substantially on the same plane. Some of the fourth contact pattern 161_3, the fifth contact pattern 162_3, and the sixth contact pattern 163_3 may protrude toward the upper side of the fourth interlayer insulating film ILD4_3.

[0240] The fourth contact pattern 161_3 and the semiconductor pattern ACT5 of the fifth transistor T5 can be electrically connected by the second semiconductor connection portion LK2_3, and at least a portion of the second semiconductor connection portion LK2_3 can be positioned on the fourth contact pattern 161_3. The fifth contact pattern 162_3 and the semiconductor pattern ACT6 of the sixth transistor T6 can be electrically connected by the third semiconductor connection portion LK3_3, and at least a portion of the third semiconductor connection portion LK3_3 can be positioned on the fifth contact pattern 162_3. The sixth contact pattern 163_3 and the semiconductor pattern ACT7 of the seventh transistor T7 can be electrically connected by the fourth semiconductor connection portion LK4_3, and at least a portion of the fourth semiconductor connection portion LK4_3 can be positioned on the sixth contact pattern 163_3.

[0241] Although the accompanying drawings show that the fourth contact pattern 161_3, the fifth contact pattern 162_3, and the sixth contact pattern 163_3 can be directly connected to the second semiconductor connection portion LK2_3, the third semiconductor connection portion LK3_3, and the fourth semiconductor connection portion LK4_3, respectively, the present invention is not limited thereto. For example, the fourth contact pattern 161_3, the fifth contact pattern 162_3, and the sixth contact pattern 163_3 can be omitted. As another example, the fourth contact pattern 161_3, the fifth contact pattern 162_3, and the sixth contact pattern 163_3 can be electrically connected to the semiconductor pattern ACT5 of the fifth transistor T5, the semiconductor pattern ACT6 of the sixth transistor T6, and the semiconductor pattern ACT7 of the seventh transistor T7, respectively, through separate contact holes and conductive layers.

[0242] Furthermore, although not shown in the accompanying drawings, a lower light-shielding pattern may be further disposed below the respective first semiconductor layer SC1_3 and third semiconductor layer SC3_3, which each comprise an oxide semiconductor. The lower light-shielding pattern can be used to prevent light incident from below from being introduced into the semiconductor pattern ACT2 of the second transistor T2, the semiconductor pattern ACT4 of the fourth transistor T4, and the semiconductor patterns ACT5 to ACT7 of the fifth to seventh transistors T7.

[0243] Even under these conditions, the area of ​​the plane in which the transistors T1 to T7 of a pixel can be placed can be reduced, and thus the display device 1 can achieve a higher resolution.

[0244] In summarizing the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the embodiments without substantially departing from the principles of the invention. Therefore, the disclosed embodiments of the invention are to be used merely in a general and descriptive sense and not for limiting purposes.

Claims

1. A display device, wherein, The display device includes: Organic light-emitting diode; A first transistor receives a data signal from a data line and controls a drive current to drive the organic light-emitting diode; A second transistor is electrically connected to the data line and the first source / drain electrode of the first transistor, and the second transistor transmits the data signal received from the data line to the first transistor; A third transistor is electrically connected to a first power supply voltage line and the first source / drain electrode of the first transistor, and the third transistor transmits the first power supply voltage from the first power supply voltage line to the first transistor, wherein... The semiconductor pattern of the first transistor is disposed above the semiconductor pattern of the second transistor, and The semiconductor pattern of the third transistor is disposed above the semiconductor pattern of the first transistor; A lower transistor insulating film, the lower transistor insulating film being disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor; and An upper transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

2. The display device according to claim 1, wherein, The display device further includes: A fourth transistor, which is electrically connected to the gate electrode and the second source / drain electrode of the first transistor, The semiconductor pattern of the fourth transistor is disposed between the semiconductor pattern of the second transistor and the semiconductor pattern of the third transistor.

3. The display device according to claim 2, wherein, The display device further includes: A sub-gate insulating film, which overlaps with the gate electrode of the first transistor but does not overlap with the gate electrode of the fourth transistor. Wherein, the thickness between the gate electrode of the first transistor and the semiconductor pattern of the first transistor is greater than the thickness between the gate electrode of the fourth transistor and the semiconductor pattern of the fourth transistor.

4. The display device according to claim 2, wherein, The display device further includes: A fifth transistor, electrically connected to the gate electrode of the first transistor and the initialization line, transmits an initialization voltage from the initialization line to the first transistor. The semiconductor pattern of the fifth transistor is disposed below the semiconductor pattern of the first transistor.

5. The display device according to claim 4, wherein, The display device further includes: A sixth transistor, electrically connected to the second source / drain electrode of the first transistor and the anode electrode of the organic light-emitting diode (OLED), transfers the drive current from the first transistor to the OLED. The semiconductor pattern of the sixth transistor is disposed above the semiconductor pattern of the first transistor.

6. The display device according to claim 1, wherein, The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, and the semiconductor pattern of the third transistor all comprise the same material.

7. The display device according to claim 6, wherein, The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, and the semiconductor pattern of the third transistor constitute a PMOS transistor comprising polysilicon.

8. The display device according to claim 1, wherein, The display device further includes: a capacitor, the capacitor comprising: A first electrode, electrically connected to the gate electrode of the first transistor; and The second electrode is electrically connected to the first power supply voltage line. The capacitor is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

9. The display device according to claim 1, wherein, The lower transistor insulating film includes a first interlayer insulating film disposed above the semiconductor pattern of the second transistor, and The upper surface of the first interlayer insulating film is flat.

10. The display device according to claim 9, wherein, The upper transistor insulating film includes a second interlayer insulating film disposed above the semiconductor pattern of the first transistor, and The upper surface of the second interlayer insulating film is flat.

11. The display device according to claim 1, wherein, The display device further includes: a first contact pattern disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor. The semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor are electrically connected via the first contact pattern.

12. The display device according to claim 11, wherein, The display device further includes a second contact pattern disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor. The semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor are electrically connected via the second contact pattern.

13. A display device, wherein, The display device includes: A first transistor, a second transistor, and a third transistor, wherein the first transistor, the second transistor, and the third transistor are disposed on different layers; Capacitor; A first semiconductor layer is disposed above a substrate and includes a semiconductor pattern of the first transistor; A first gate insulating film is disposed above the first semiconductor layer; A first conductive layer is disposed above the first gate insulating film and includes the gate electrode of the first transistor; A first interlayer insulating film is disposed above the first conductive layer; A data line and a first conductive pattern are disposed above the first interlayer insulating film and electrically connected to the first semiconductor layer to transmit data signals; A second interlayer insulating film is disposed above the data line and the first conductive pattern; A second semiconductor layer is disposed above the second interlayer insulating film and includes a semiconductor pattern of the second transistor, wherein the semiconductor pattern of the second transistor is electrically connected to the first conductive pattern to receive the data signal; A second gate insulating film is disposed above the second semiconductor layer; A second conductive layer, disposed above the second gate insulating film, includes: The gate electrode of the second transistor; and The first electrode of the capacitor is electrically connected to the gate electrode of the second transistor; A third interlayer insulating film is disposed above the second conductive layer; A third conductive layer, the third conductive layer including a second electrode of the capacitor disposed above the third interlayer insulating film; A fourth interlayer insulating film is disposed above the third conductive layer; A third semiconductor layer is disposed above the fourth interlayer insulating film and includes the semiconductor pattern of the third transistor; A third gate insulating film, the third gate insulating film being disposed above the third semiconductor layer; and A fourth conductive layer is disposed above the third gate insulating film and includes the gate electrode of the third transistor.

14. The display device according to claim 13, wherein, The second semiconductor layer is disposed on the upper surface of the second interlayer insulating film, and The upper surface of the second interlayer insulating film is flat.

15. The display device according to claim 14, wherein, The display device further includes a first contact pattern disposed in a first contact hole penetrating the second interlayer insulating film. The upper surface of the first contact pattern and the upper surface of the second interlayer insulating film are disposed on the same plane.

16. The display device according to claim 14, wherein, The third semiconductor layer is disposed on the upper surface of the fourth interlayer insulating film, and The upper surface of the fourth interlayer insulating film is flat.

17. The display device according to claim 16, wherein, The display device further includes a second contact pattern disposed in a second contact hole penetrating the fourth interlayer insulating film, the third interlayer insulating film, and the second gate insulating film. The upper surface of the second contact pattern and the upper surface of the fourth interlayer insulating film are disposed on the same plane.

18. A method of manufacturing a display device, the display device comprising a first transistor, a second transistor, and a third transistor respectively disposed on different layers, wherein, The method includes: A first semiconductor layer is formed on a substrate, the first semiconductor layer including the semiconductor pattern of the first transistor; A first gate insulating film is formed on the first semiconductor layer; A first conductive layer is formed on the first gate insulating film, the first conductive layer including the gate electrode of the first transistor; A first interlayer insulating film is formed on the first conductive layer; A data line and a first conductive pattern are formed on the first interlayer insulating film, and the data line and the first conductive pattern are electrically connected to the first semiconductor layer to transmit data signals. A second interlayer insulating film is formed on the data line and the first conductive pattern; The upper surface of the second interlayer insulating film is made flat; A second semiconductor layer is formed on the upper surface of the second interlayer insulating film. The second semiconductor layer includes a semiconductor pattern of the second transistor, and the semiconductor pattern of the second transistor is electrically connected to the first conductive pattern to receive the data signal. A second gate insulating film is formed on the second semiconductor layer; A second conductive layer is formed on the second gate insulating film, the second conductive layer including the gate electrode of the second transistor and a first electrode of a capacitor electrically connected to the gate electrode of the second transistor; A third interlayer insulating film is formed on the second conductive layer; A third conductive layer is formed on the third interlayer insulating film, and the third conductive layer includes the second electrode of the capacitor; A fourth interlayer insulating film is formed on the third conductive layer; A third semiconductor layer is formed on the fourth interlayer insulating film, the third semiconductor layer including the semiconductor pattern of the third transistor; A third gate insulating film is formed on the third semiconductor layer; and A fourth conductive layer is formed on the third gate insulating film, the fourth conductive layer including the gate electrode of the third transistor.

19. The method according to claim 18, wherein, The method further includes: Prior to the formation of the third semiconductor layer, the upper surface of the fourth interlayer insulating film is formed to be flat. The third semiconductor layer is disposed above the upper surface of the fourth interlayer insulating film.

20. The method according to claim 18, wherein, Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer comprises polycrystalline silicon, and Each of the first transistor, the second transistor, and the third transistor is a PMOS transistor.

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