Processing system and method for forming contacts

Abstract

Embodiments disclosed herein include a processing system and method for forming contacts. The processing system includes a plurality of processing chambers configured to deposit, etch, and / or anneal a source / drain region of a substrate. The method includes depositing a doped semiconductor layer over the source / drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method for forming contacts results in reduced contact resistance by using integrated processing that allows various operations for forming a source / drain contact to be performed within the same processing system.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to an apparatus and a method, and more particularly to a processing system and a method for forming contacts. Background Technology

[0002] Transistors are fundamental components of modern digital processors and memory devices, and are used in high-power electronics. Currently, various transistor designs and types are available for different applications. These types include, for example, bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), vertical-channel or trench field-effect transistors, and superjunction transistors or multi-drain transistors. A relatively new type of transistor within the MOSFET family is the FinFET (Fin Field-Effect Transistor).

[0003] FinFETs can be fabricated on a bulk semiconductor substrate, such as a silicon substrate, and include a fin-like structure that extends along the length of the substrate surface and in a height direction orthogonal to the substrate surface. This fin has a narrow width, for example, less than 250 nanometers. This fin can be permeated by an insulating layer. A gate structure comprising a conductive gate material and a gate insulator can be formed above a region of this fin. The upper portion of this fin is doped on either side of the gate structure to form a source / drain region adjacent to the gate.

[0004] FinFETs offer superior electrostatic properties compared to complementary MOSFETs scaled down to smaller sizes. Because the fin is a three-dimensional structure, the transistor channel can be formed on all three surfaces of the fin, allowing FinFETs to exhibit high current switching capability over a given surface area on the substrate. Furthermore, since the channel and device can be raised from the substrate surface, there is reduced electric field coupling between adjacent devices compared to conventional planar MOSFETs.

[0005] One of the key challenges in semiconductor design, manufacturing, and operation is contact resistance. For example, the source and drain regions of a FinFET device are eroded by the etching process that forms source / drain contact trenches, resulting in increased contact resistance. One consequence of increased contact resistance is reduced performance of circuit devices, which include transistors and other device structures formed on a semiconductor substrate.

[0006] Therefore, contacts that reduce contact resistance are needed. Summary of the Invention

[0007] Embodiments of this disclosure generally relate to processing systems and methods for forming contacts. The processing system includes multiple processing chambers configured to deposit, etch, and / or anneal source / drain regions of a substrate. The method includes depositing a doped semiconductor layer over the source / drain regions, forming an anchor layer in a trench, and depositing a conductor in the trench. The contact formation method achieves reduced contact resistance through integrated processing, which allows various operations for source / drain contact formation to be performed within the same processing system.

[0008] In one embodiment, a processing system is provided, including a system controller, a first processing chamber, a second processing chamber, and a fourth processing chamber. The controller is configured such that the first processing chamber deposits a doped semiconductor layer and a metal silicide layer on exposed surfaces of source / drain regions of a substrate. The source / drain regions are exposed via trenches formed in a dielectric material, which is formed above the source / drain regions. The controller is configured such that the second processing chamber forms an anchoring layer above the metal silicide layer and the sidewalls of the trenches. The controller is configured such that a third processing chamber fills the trenches with conductors. The controller is configured such that the fourth processing chamber heats the substrate, causing the conductors to reflow within the trenches. The source / drain regions have a first doping concentration. The doped semiconductor layer has a second doping concentration higher than the first doping concentration.

[0009] In another embodiment, a processing system is provided, including a plurality of processing chambers. The plurality of processing chambers include a first processing chamber configured to remove contaminants from exposed surfaces of source / drain regions of a substrate, wherein the source / drain regions are exposed via trenches formed in a dielectric material above the source / drain regions; a second processing chamber configured to successively deposit a doped semiconductor layer and a metal silicide layer above the source / drain regions; a third processing chamber configured to deposit a barrier layer on the sidewalls of the metal silicide layer and the trench; a fourth processing chamber configured to deposit an anchoring layer above the barrier layer; a fifth processing chamber configured to fill the trenches with conductors; a sixth processing chamber configured to deposit an overburden layer above the conductors; and a seventh processing chamber configured to heat the substrate to reflow the conductors within the trenches. The source / drain regions have a first doping concentration. The doped semiconductor layer has a second doping concentration higher than the first doping concentration.

[0010] In yet another embodiment, a method for forming contacts is provided, comprising depositing a doped semiconductor layer on an exposed surface of a source / drain region of a substrate, wherein the source / drain regions are exposed via trenches formed in a dielectric material above the source / drain regions; depositing a metal silicide layer on the doped semiconductor layer; forming an anchoring layer above the metal silicide layer and the sidewalls of the trench; filling the trench with a conductor; and heating the substrate to cause the conductor to flow back within the trench. The source / drain regions have a first doping concentration. The doped semiconductor layer has a second doping concentration higher than the first doping concentration. Attached Figure Description

[0011] To gain a more detailed understanding of the above features of the invention, a more specific description of the invention, briefly summarized above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it will be noted that the accompanying drawings illustrate only exemplary embodiments and are therefore not intended to limit the scope of the invention, which allows for other equivalent embodiments.

[0012] Figure 1 This is a flowchart of a method for forming contacts according to one embodiment.

[0013] Figures 2A to 2D The illustration depicts a scenario according to one embodiment. Figure 1 Various views of the substrate during different stages of the method.

[0014] Figure 3 A cross-sectional view of a substrate according to one embodiment is shown.

[0015] Figure 4 A top view diagram illustrating a multi-chamber processing system according to one embodiment is provided.

[0016] For ease of understanding, the same reference numerals have been used as much as possible to refer to the same elements shared in the drawings. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further explanation. Detailed Implementation

[0017] The embodiments disclosed herein include processing systems and methods for forming contacts. In various embodiments, this method includes performing subsequent operations in the processing system without breaking the vacuum: performing a pre-cleaning process on exposed surfaces of the source / drain regions of a transistor on a substrate, the source / drain regions being exposed via trenches formed in a dielectric material above the source / drain regions; forming a silicide layer on the exposed source / drain regions by epitaxial deposition; forming a barrier layer / pad layer on the silicide layer by atomic layer deposition; forming an anchoring layer on the barrier layer / pad layer by physical vapor deposition; filling the trenches with a conductor by chemical vapor deposition; and annealing the substrate. This integration process can form cobalt contacts with reduced resistance and porosity, thereby providing high-performance logic transistors. The embodiments disclosed herein can be used, but are not limited to, creating contacts with reduced contact resistance.

[0018] The foregoing provides a broad overview of the techniques described in this invention. It is contemplated that the concepts of this disclosure can be implemented for planar transistor devices or for three-dimensional transistor devices, such as FinFETs, Horizontal Gate All-Around (HGAA) FETs, Vertical Gate All-Around (VGAA) FETs, Nanowire Channel FETs, Strained Semiconductor Devices, and the like.

[0019] When used here, the term "approximately" means a variation of + / - 10% in the indicator value. It should be understood that such variation can be included in any values ​​provided herein.

[0020] Figure 1 This is a flowchart of the operation of a method 100 for forming contacts according to one embodiment. Figures 2A to 2D Various views of the substrate 200 during different stages of method 100 according to one embodiment are illustrated. Although... Figure 1 and Figures 2A to 2D By describing the operation of method 100 in conjunction with this description, those skilled in the art will understand that any system configured to perform this method operation in any order falls within the scope of the embodiments described herein. It should be noted that method 100 can be used to form any other semiconductor structure not presented herein. Those skilled in the art will recognize that the complete process for forming semiconductor devices and related structures is not illustrated in the drawings or described herein. Contacts may be part of transistors or other semiconductor devices.

[0021] Method 100 begins operation 102 by providing substrate 200 into a processing chamber. The processing chamber may be an etching chamber. Substrate 200 may be any substrate used in the art and includes any semiconductor, insulator, or metallic material. Figure 2AAs illustrated, substrate 200 includes a semiconductor layer 202, a plurality of semiconductor structures 204, a first dielectric material 206, source / drain regions 208, a contact etch stop layer (CESL) 210, and a second dielectric material 212. The plurality of semiconductor structures 204 (only two are shown in the diagram) extend from semiconductor layer 202. Semiconductor structures 204 may be semiconductor fins. Semiconductor layer 202 may be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), or group III / V compound semiconductors such as gallium arsenide (GaAs) or indium gallium arsenide (InGaAs). Semiconductor layer 202 may be doped with p-type or n-type dopants. In one embodiment, semiconductor layer 202 is doped with a p-type dopant, such as boron (B). In another embodiment, semiconductor layer 202 is doped with an n-type dopant, such as phosphorus (P) or arsenic (As). Semiconductor structures 204 are made of the same material as semiconductor layer 202. In one embodiment, semiconductor structure 204 is integrated with semiconductor layer 202.

[0022] A first dielectric material 206 is disposed between semiconductor structures 204 on semiconductor layer 202. The first dielectric material 206 may be a shallow trench isolation (STI) region and may be made of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbonitride (SiCN) or other suitable dielectric materials.

[0023] In one instance, source / drain region 208 is either a source region or a drain region. In another instance, source / drain region 208 includes merged source / drain regions, such as... Figure 2A As illustrated. In any example, the source / drain region 208 is fabricated from a semiconductor material epitaxially grown on the semiconductor structure 204. The source / drain region 208 is fabricated from Si, Ge, SiGe, or a III / V compound semiconductor, such as GaAs or InGaAs. The source / drain region 208 may be doped with p-type or n-type dopants. In one example, the source / drain region 208 is doped with a p-type dopant, such as B. Alternatively, the source / drain region 208 is doped with an n-type dopant, such as P or As. The source / drain region 208 may be epitaxially grown on the semiconductor structure 204, and due to different growth rates on different surface planes, multiple facets may be formed, causing the source / drain region 208 to have a diamond shape.

[0024] CESL 210 is formed on the first dielectric material 206 and the source / drain region 208. CESL 210 is made of a dielectric material, such as SiO2, Si3N4, SiCN, or a combination thereof. A second dielectric material 212 is disposed above CESL 210. The second dielectric material 212 may be a dielectric layer and may be made of a dielectric material, such as SiO2, Si3N4, SiCN, or a combination thereof. The substrate 200 may further include a plurality of gates (not shown) disposed above the semiconductor structure 204 and extending perpendicularly to the semiconductor structure 204.

[0025] In operation 104, trenches 214 are formed in the second dielectric material 212 to expose the respective source / drain regions 208, such as Figure 2B As illustrated. Trench 214 is formed by removing a portion of the second dielectric material 212, with CESL 210 disposed above each source / drain region 208 and exposing the surface 216 of each source / drain region 208. Trench 214 can be formed by any suitable removal process. In one example, trench 214 is formed by a plasma etching process.

[0026] A single source / drain region 208 is exposed in each trench 214. Alternatively, combined source / drain regions 208 are exposed in each trench 214, such as... Figure 2B As illustrated. A portion of the source / drain region 208 can be removed during the formation of trench 214. The etched source / drain region 208 has increased contact resistance. Trench 214 is formed in a processing chamber, which may be a reactive ion etching (RIE) chamber or other suitable etching chamber.

[0027] In operation 106, a pre-cleaning process is performed on the exposed surface 216 of the source / drain region 208. The pre-cleaning process removes any contaminants, such as carbon or oxide contaminants, from the surface 216 of the source / drain region 208. The pre-cleaning process can be any suitable etching process, such as dry etching, wet etching, or a combination thereof. In one example, the pre-cleaning process includes a wet etching process followed by a dry etching process. The wet etching process can utilize an ammonia (NH3) or hydrogen nitride (HF) solution. The dry etching process can be a plasma etching process and can utilize nitrogen- or hydrogen-containing etchants. The pre-cleaning process does not substantially remove any portion of the source / drain region 208.

[0028] The pre-cleaning process is performed in the first processing chamber of the processing system, which may be the same as or a different processing chamber than those operating 102 and 104. In one example, the pre-cleaning process is performed in a processing chamber using a remote plasma source. An exemplary processing chamber suitable for performing the pre-cleaning process is the ACTIV Pre-Clean, available from Applied Materials Inc., Santa Clara, California.TM Chamber or SiCoNi TM Cleaning the chamber. Alternatively, the pre-cleaning process can be performed in an etching chamber, such as an etching chamber using an inductively coupled plasma (ICP) source. An exemplary etching chamber is a modified decoupled plasma nitriding (DPN) chamber, available from Applied Materials, Santa Clara, California. However, it is contemplated that other suitable chamber configurations from other manufacturers could also be used to perform the pre-cleaning process.

[0029] In operation 108, a doped semiconductor layer 220 is formed on the surface 216 of the exposed source / drain region 208, such as... Figure 2C As illustrated. The doped semiconductor layer 220 can be formed by selective epitaxial deposition. The doped semiconductor layer 220 is formed on the exposed surface of the source / drain region 208, i.e., on the bottom of the trench 214, and not on the sidewalls 218 of the trench 214 due to selective epitaxial deposition. The doped semiconductor layer 220 can be made of the same material as the source / drain region 208, except that the doping concentration in the doped semiconductor layer 220 is higher than that in the source / drain region 208. In one embodiment, the doped semiconductor layer 220 is formed by a dopant immersion process. During the dopant immersion process, the top portion of the source / drain region 208 (e.g., from surface 216 to a predetermined depth) is converted into the doped semiconductor layer 220. The doped semiconductor layer 220 may have a depth from approximately to approximately The thickness range. In one embodiment, the ratio of doping concentration in the doped semiconductor layer 220 to doping concentration in the source / drain region 208 is in the range of about 1.5:1 to about 10:1, for example, about 2:1 to about 6:1. In one example, the doping concentration in the doped semiconductor layer 220 is about 1 × 10⁻⁶. 19 atoms / cm 3 To approximately 1×10 22 atoms / cm 3 Increasing the doping concentration in the doped semiconductor layer 220 reduces contact resistance.

[0030] Selective epitaxial deposition is performed in a second processing chamber of the processing system. In one embodiment, a doped semiconductor layer 220 is formed in the epitaxial chamber. An example of an epitaxial chamber is a reduced pressure (RP) Epi chamber available from Applied Materials, Inc., Santa Clara, California. However, it is contemplated that other suitable chamber configurations from other manufacturers may also be used to perform selective epitaxial deposition or dopant immersion processes to form the doped semiconductor layer 220.

[0031] In operation 110, a metal silicide layer 222 is formed on the doped semiconductor layer 220 by selective epitaxial deposition, such as... Figure 2C As illustrated, a metal silicide layer 222 is formed on the doped semiconductor layer 220, i.e., at the bottom of trench 214, and is not on the sidewalls 218 of trench 214 due to selective epitaxial deposition. The metal silicide layer 222 may include titanium silicide (TiSi), cobalt silicide (CoSi), ruthenium silicide (RuSi), or other suitable metal silicides. The metal silicide layer 222 may be formed in the same processing chamber as the doped semiconductor layer 220.

[0032] Alternatively, the doped semiconductor layer 220 and the metal silicide layer 222 can be replaced by a silicide layer 209 formed on the surface of the exposed source / drain region 208, such as... Figure 3 As illustrated. In one embodiment, a silicide layer 209 is formed by forming a conformal metal layer on the surface of the exposed source / drain region 208 over the surface 216 of the second dielectric material 212. The conformal metal layer may be a refractory metal layer formed using CVD processing, PECVD processing, high-density CVD processing, PVD processing, electroplating processing, sputtering processing, evaporation processing, or other suitable processing. The metal layer may include cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), tantalum (Ta), tungsten (W), alloys of the foregoing metals, other suitable metal silicides, or any combination of the foregoing. Certain examples of the metal layer include, but are not limited to, TiSi, RuSi, nickel-platinum (NiPt) alloys, nickel-palladium (NiPd), nickel-rhenium (NiRe), titanium-tantalum (TiTa), or titanium-niobium (TiNb).

[0033] Once the metal layer has been formed, the substrate 200 is then heated, such as by annealing, causing the exposed source / drain regions 208 to react with the metal layer and form a silicide layer 209. The annealing process causes the silicide reaction to occur wherever the metal layer contacts the source / drain regions 208. Depending on the metal layer used, the silicide layer 209 may be a silicide of the metal layer. For example, if the metal layer includes Co, then the silicide layer 209 includes CoSi. The annealing process can be performed in a rapid thermal annealing (RTA) chamber. An exemplary chamber is available from Applied Materials Inc., Santa Clara, California. RADOX TM An RTP chamber or other suitable chamber is then used. Unreacted metal layers are then removed by selective etching to leave a silicide layer 209 on the substrate.

[0034] In embodiments utilizing silicide layer 209, an optional cap layer 224 may be formed on silicide layer 209, such as... Figure 3As illustrated. Although not shown, a capping layer 224 may also be formed on the metal silicide layer 222, such that the capping layer 224 is disposed between the metal silicide layer 222 and the barrier layer 225 (or liner layer) and / or the anchoring layer 227 will be subsequently formed on the capping layer 224. The capping layer 224 prevents metal diffusion from the subsequently deposited anchoring layer 227 and / or the contact metal subsequently filled in the trench 214 and reacts with the underlying silicide layer 209 and / or the source / drain region 208. The capping layer 224 may also serve as an adhesion layer to improve the adhesion between the contact metal subsequently filled in the trench 214 and the silicide layer 209.

[0035] The capping layer 224 may be a nitride layer. The nitride layer may include, but is not limited to, TiN, Si3N4, or metallic silicon nitride. The capping layer 224 may include a metallic material containing a transition metal, such as iridium (Ir) or molybdenum (Mo). In one embodiment, the capping layer 224 is a nitride layer formed by a nitriding process. The nitriding process may include exposing the exposed silicide layer 209 to a nitrogen-containing plasma or a nitrogen-containing ambient environment, such that nitrogen (N) atoms chemically react with atoms present at the exposed surface of the silicide layer 209 to form a surface nitride layer (e.g., capping layer 224). In some embodiments, nitride regions are also formed in the upper portion of the source / drain region 208.

[0036] The nitriding process can be performed in a plasma chamber using an inductively coupled plasma (ICP) source, such as a modified decoupled plasma nitriding (DPN) chamber available from Applied Materials, Santa Clara, California, or other suitable chambers. The capping layer 224 can also be formed by any suitable deposition process, such as ALD, CVD, PECVD, HDP-CVD, low-pressure CVD (LPCVD), PVD, or any suitable deposition technique. In the case where the capping layer 224 is formed by an ALD process, the capping layer 224 can be formed on both the sidewall 218 and the silicide layer 209. In this case, the deposition of the capping layer 224 can be performed in an ALD chamber. An example of an ALD chamber is the Olympia, available from Applied Materials, Santa Clara, California. TM ALD chambers are available, but other suitable chambers may also be used.

[0037] In operation 112, an optional barrier layer 225 is formed on the sidewall 218 of the metal silicide layer 222 and the trench 214, such as Figure 2C As illustrated. In an embodiment where the capping layer 224 is disposed on the metal silicide layer 222, a barrier layer 225 is formed on the capping layer 224, resulting in the capping layer 224 being disposed between the metal silicide layer 222 and the barrier layer 225. Figure 3 An example is illustrated in which a barrier layer 225 is formed on the sidewall 218 of the capping layer 224 and the trench 214.

[0038] Barrier layer 225 may be made of the same material as capping layer 224. In one embodiment, barrier layer 225 comprises TiN. Barrier layer 225 may be formed by any suitable deposition process, such as ALD, CVD, PECVD, HDP-CVD, low-pressure CVD (LPCVD), PVD, or any suitable deposition technique. Deposition of barrier layer 225 is performed in a third processing chamber of the processing system. In one embodiment, barrier layer 225 is formed by ALD. An exemplary chamber is an Olympia chamber available from Applied Materials, Santa Clara, California. TM An ALD chamber may be used, or other suitable chambers may be utilized. Alternatively, the barrier layer 225 may be formed in the same processing chamber as the capping layer 224.

[0039] In operation 114, anchoring layer 227 is optionally formed on the exposed surface of barrier layer 225, such as Figure 2C and Figure 3 As shown. In embodiments where the barrier layer 225 is not used, the anchoring layer 227 is formed on the metal silicide layer 222. Figure 2C ) or on the cover layer 224 ( Figure 3 Anchor layer 227 further improves the adhesion between the contact metal subsequently filled in trench 214 and the silicide layer 209 and / or source / drain regions 208. Anchor layer 227 may be made of metal, such as Co, W, Cu, Ru, aluminum (Al), gold (Au), silver (Ag), alloys of the foregoing, the like, or combinations thereof, and may be deposited by CVD, ALD, PVD, ECP, or other suitable deposition techniques.

[0040] The deposition of the anchoring layer 227 is performed in the fourth processing chamber of the processing system. In one embodiment, the anchoring layer 227 is formed in a PVD chamber. An exemplary chamber is a Cirrus product available from Applied Materials, Inc., Santa Clara, California. TM RT PVD chamber. However, it is conceivable that other suitable chamber configurations from other manufacturers could also be used to perform the deposition process to form the anchoring layer 227.

[0041] In operation 116, a conductor 226 is formed in trench 214 to fill trench 214, such as Figure 2D and Figure 3 As illustrated. A seed layer 229 may be disposed between the anchor layer 227 and the conductor 226. The seed layer 229 may be formed on the exposed surface of the anchor layer 227, such as... Figure 2DAs illustrated. Seed layer 229 and conductor 226 may be made of the same or different materials. Suitable materials for conductor 226 and seed layer 229 include, but are not limited to, Co, Cu, W, Al, Ru, Ti, Ag, platinum (Pt), palladium (Pa), alloys of the foregoing, derivatives of the foregoing, or any combination of the foregoing. In one embodiment, conductor 226 is made of Co. Conductor 226 and seed layer 229 may be formed on anchor layer 227 using one or more deposition processes, such as CVD, PECVD, ALD, PEALD, PVD, electroplating, ECP, or other suitable deposition techniques.

[0042] The formation of conductor 226 is performed in the fifth processing chamber of the processing system. In one embodiment, conductor 226 is formed in a CVD chamber. An exemplary chamber is the Volta, available from Applied Materials, Inc., Santa Clara, California. TM CVD chamber. However, it is conceivable that other suitable chamber configurations from other manufacturers could also be used to perform the deposition process to form conductor 226.

[0043] In operation 118, in some embodiments, after the trench 214 is filled with conductor 226, a capping layer 231 is formed on the exposed surfaces of conductor 226 and the second dielectric material 212. The capping layer 231 may include a metal, which may include the same material as conductor 226. In one embodiment, the capping layer 231 includes Co. The capping layer 231 may be formed over the exposed surfaces of conductor 226 and the second dielectric material 212 until a predetermined thickness is reached. After the capping layer is formed, the substrate 200 is heated to a predetermined temperature by the thermal annealing process described above to reflow the metal of the capping layer 231 and conductor 226, thereby eliminating gaps or holes in conductor 226. Alternatively, the thermal annealing process may be performed prior to the formation of the capping layer.

[0044] The capping layer 231 can be formed using any suitable deposition technique, such as PVD processing, ALD processing, CVD processing, PECVD processing, HDP-CVD processing, low-pressure CVD (LPCVD) processing, etc. The deposition of the capping layer 231 can be performed in the sixth processing chamber of the processing system. In one embodiment, the capping layer 231 is formed in a PVD chamber. An exemplary chamber is the Versa, available from Applied Materials Inc., Santa Clara, California. TM XT PVD chamber. Alternatively, the deposition of the capping layer can be performed in the fourth processing chamber of the processing system. However, it is contemplated that other suitable chamber configurations from other manufacturers could also be used to perform the deposition process to form the capping layer.

[0045] In operation 120, the substrate 200 is heated to a predetermined temperature during a thermal annealing process. The thermal annealing process can be performed in a temperature range from about 200°C to about 800°C, for example, from about 300°C to about 600°C. During the thermal annealing process, the metal of the conductor 226 within the trench 214 can be reflowed to eliminate gaps or voids in the conductor 226. If any gaps or voids remain in the conductor 226, the capping layer 231 can also be reflowed to further fill the trench 214. The thermal annealing process can also increase grain size, clean the conductor 226 (e.g., with Co), and / or reduce resistance. Thus, a high-quality, void-free conductor 226 is obtained.

[0046] The thermal annealing process is performed in the seventh processing chamber of the processing system. In one embodiment, the thermal annealing process is performed in an annealing chamber. An exemplary chamber is the Pyra, available from Applied Materials Inc., Santa Clara, California. TM Annealing chamber. Another exemplary chamber is a rapid thermal annealing (RTA) chamber, such as those available from Applied Materials, Inc., Santa Clara, California. RADOX TM RTP chambers. However, it is conceivable that other suitable chamber configurations from other manufacturers could also be used to perform the heat annealing process.

[0047] In operation 122, excess conductor 226 (and capping layer 231 (if used)) can be removed by a planarization process such as chemical mechanical polishing (CMP). The planarization process removes capping layer 231 and excess conductor 226 from the top surface of the second dielectric material 212. Therefore, conductor 226, seed layer 229 (if used), anchoring layer 227, barrier layer 225, and the top surface of the second dielectric material 212 can be coplanar. The resulting conductive features can be referred to as contacts, plugs, etc. The substrate 200 can undergo further processing to complete the transistor.

[0048] In one implementation, the planarization process is performed in a CMP system. An exemplary system is available from Applied Materials Inc., Santa Clara, California. LK Prime TM CMP system. However, it is conceivable that other suitable configurations of CMP systems from other manufacturers could also be used to perform the deposition process to form conductor 226.

[0049] Examples of processing systems that can be appropriately modified based on the teachings provided herein include those commercially available from Applied Materials, Inc., Santa Clara, California. or Integrated processing systems or other suitable processing systems. It is anticipated that other processing systems (including those from other manufacturers) may be adapted to benefit from the aspects described herein.

[0050] Figure 4 A top-view illustration of a multi-chamber processing system 400 according to one embodiment is shown. The multi-chamber processing system 400 is configured to perform various semiconductor processing methods, such as method 100 described above, on one or more substrates. As shown in the figures, the multi-chamber processing system 400 includes a plurality of processing chambers 402, 414, 416, a first transfer chamber 404, pass-through chambers 406, a second transfer chamber 410, a loading locking chamber 412, a factory interface 420, one or more compartments 430, and a system controller 480.

[0051] Each of the processing chambers 402 is coupled to a first transfer chamber 404. The first transfer chamber 404 is also coupled to a first pair of through chambers 406. The first transfer chamber 404 has a centrally located transfer robot (not shown) for transferring substrates between the through chambers 406 and the processing chambers 402. The through chambers 406 are coupled to a second transfer chamber 410, which is coupled to a processing chamber 414 configured to perform a pre-cleaning process (operation 106) and a processing chamber 416 configured to perform a silicide layer (operation 108 / 110). The second transfer chamber 410 has a centrally located transfer robot (not shown) for transferring substrates between the loading locking chamber 412 and the processing chambers 414 and / or 416. A factory interface 420 is connected to the second transfer chamber 410 via the loading locking chamber 412. The factory interface 420 is coupled to one or more compartments 430 on the opposite side of the loading locking chamber 412. Cabin 430 is typically a front-opening standard cabin (FOUP) that can be accessed from the cleanroom.

[0052] In some embodiments, a substrate is provided to an etching chamber to perform a trench forming process (e.g., operation 104). The etching chamber may be part of a multi-chamber processing system 400, or it may be part of a separate processing tool. The substrate is then transferred to a processing chamber 414. According to one embodiment, the substrate is transferred to a chamber 430 before being transferred to the processing chamber 414.

[0053] The substrate is transferred to processing chamber 414, where a pre-cleaning process (e.g., operation 106) is performed to remove contaminants, such as carbon or oxide contaminants from exposed surfaces of the source / drain regions of transistors on the substrate. The substrate is then transferred to processing chamber 416, where a doped semiconductor layer and a metal silicide layer are deposited (e.g., operations 108 and 110) (or, in an alternative embodiment, a silicide layer 209 is deposited). In some embodiments, processing chambers 414 and / or 416 are exchanged with any of one or more processing chambers 402.

[0054] The substrate is then conveyed to one or more processing chambers 402, in which a barrier layer (e.g., operation 112, such as ALD of a TiN barrier layer), an anchoring layer (e.g., operation 114, such as PVD of a Co anchoring layer), trenches are filled with conductors (e.g., operation 116, such as CVD of a Co conductor), a capping layer (e.g., operation 118, such as PVD of a capping layer), and an annealing process is performed on the substrate (e.g., operation 120). Because all these operations 106, 108, 110, 112, 114, 116, 118, and 120 are performed within the same processing system, the vacuum is not broken when the substrate is conveyed to the various chambers, which reduces the probability of contamination and improves the quality of the deposited epitaxial film.

[0055] System controller 480 is coupled to processing system 400. System controller 480 controls processing system 400 or its components. For example, system controller 480 controls the operation of processing system 400 by directly controlling chambers 402, 404, 406, 410, 412, 414, 416 and / or plant interface 420 and / or compartment 430, or by controlling controllers associated with chambers 402, 404, 406, 410, 412, 414, 416 and / or plant interface 420 and / or compartment 430. In operation, system controller 480 is capable of collecting and feeding back data from individual chambers to coordinate the performance of processing system 400.

[0056] As shown in the diagram, system controller 480 includes a central processing unit (CPU) 482, memory 484, and support circuitry 486. CPU 482 may be one of any type of general-purpose processor used in an industrial setting. Memory 484 may include non-transitory computer-readable media and / or machine-readable storage devices. Memory 484 is accessible to CPU 482 and may be one or more types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage device, local or remote. Support circuitry 486 is coupled to CPU 482 and may include cache, clock circuitry, input / output subsystems, power supply, and the like. System controller 480 is configured to execute method 100 stored in memory 484. The various embodiments disclosed in this specification can generally be implemented under the control of CPU 482 by executing computer instruction code (such as a computer program product or software routine) stored in memory 484 (or in memory within a specific processing chamber). In other words, the computer program product is tangibly embodied in memory 484 (or a non-transitory computer-readable medium or machine-readable storage device). When the CPU 482 executes the computer instruction code, the CPU 482 controls the chamber to perform operations according to various implementation methods.

[0057] As described above, this document provides methods and processing systems for forming contacts. The processing system includes multiple processing chambers configured to deposit, etch, and / or anneal source / drain regions of a substrate. The methods include depositing a doped semiconductor layer over the source / drain regions, forming an anchoring layer in a trench, and depositing a conductor in the trench.

[0058] The method of forming contacts reduces contact resistance through integrated processing, allowing various source / drain contact formation operations to be performed within the same processing system. Therefore, the vacuum is not broken when the substrate is transferred between various processing chambers, reducing the chance of contamination and improving the quality of the deposited layer.

[0059] While the foregoing relates to embodiments of the present invention, other and further embodiments of the present invention may be conceived without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A processing system, comprising: System controller; A first processing chamber, wherein the system controller is configured such that the first processing chamber converts a portion of a source / drain region into a doped semiconductor layer to reduce contact resistance, and deposits a metal silicide layer on the doped semiconductor layer, wherein the source / drain region is exposed via trenches formed in a dielectric material above the source / drain region, and the source / drain region has a first doping concentration while the doped semiconductor layer has a second doping concentration higher than the first doping concentration; A second processing chamber, wherein the system controller is configured such that the second processing chamber forms an anchoring layer over the metal silicide layer and over the sidewalls of the trench; A third processing chamber, wherein the system controller is configured such that the third processing chamber fills the trench with a conductor; A fourth processing chamber, wherein the system controller is configured to heat the substrate in the fourth processing chamber to cause the conductor to recirculate within the trench; A first transfer chamber is coupled to one or more of the first to fourth processing chambers, the first transfer chamber being configured to transfer the substrate to one or more of the first to fourth processing chambers coupled to the first transfer chamber and to receive the substrate from one or more of the first to fourth processing chambers coupled to the first transfer chamber. It is coupled to the first transmission chamber via the chamber; A second transfer chamber is coupled to the passage chamber; and A fifth processing chamber, wherein the system controller is configured to deposit a capping layer over the metal silicide layer, wherein the system controller is configured to form a barrier layer on the capping layer, and wherein the anchoring layer is on the exposed surface of the barrier layer. The ratio of the second doping concentration to the first doping concentration is in the range of 1.5:1 to 10:1, and The substrate is transported between various chambers without breaking the vacuum.

2. The processing system of claim 1, further comprising: A sixth processing chamber, wherein the system controller is configured such that the sixth processing chamber deposits a capping layer over the conductor.

3. The processing system of claim 2, wherein the anchoring layer, the conductor, and the capping layer comprise cobalt (Co).

4. The processing system of claim 1, wherein the first processing chamber is an epitaxial chamber, the second processing chamber is a physical vapor deposition (PVD) chamber, the third processing chamber is a chemical vapor deposition (CVD) chamber, and the fourth processing chamber is an annealing chamber.

5. The processing system of claim 2, wherein the sixth processing chamber is a physical vapor deposition (PVD) chamber.

6. A processing system, comprising: Multiple processing chambers, including: A first processing chamber is configured to remove contaminants from the exposed surfaces of source / drain regions of a substrate, wherein the source / drain regions are exposed via trenches formed in a dielectric material above the source / drain regions. A second processing chamber is configured to convert a portion of the source / drain regions into a doped semiconductor layer to reduce contact resistance, and to deposit a metal silicide layer on the doped semiconductor layer, wherein the source / drain regions have a first doping concentration and the doped semiconductor layer has a second doping concentration, the second doping concentration being higher than the first doping concentration; A third processing chamber is configured to deposit a barrier layer on the metal silicide layer and on the sidewalls of the trench; The fourth processing chamber is configured to deposit an anchoring layer over the barrier layer; The fifth processing chamber is configured to fill the trench with a conductor; The sixth processing chamber is configured to deposit a capping layer over the conductor; and A seventh processing chamber is configured to heat the substrate to cause the conductor to recirculate within the trench. A first transfer chamber is coupled to one or more of the plurality of processing chambers, the first transfer chamber being configured to transfer the substrate to one or more of the plurality of processing chambers coupled to the first transfer chamber and to receive the substrate from one or more of the plurality of processing chambers coupled to the first transfer chamber. It is coupled to the first transmission chamber via the chamber; and The second transfer chamber is coupled to the passage chamber. The ratio of the second doping concentration to the first doping concentration is in the range of 1.5:1 to 10:

1. The third processing chamber is configured to form a capping layer between the barrier layer and the metal silicide layer, and The substrate is transported between various chambers without breaking the vacuum.

7. The processing system of claim 6, wherein the second processing chamber is an epitaxial chamber, the third processing chamber is an atomic layer deposition (ALD) chamber, the fourth processing chamber is a physical vapor deposition (PVD) chamber, the fifth processing chamber is a chemical vapor deposition (CVD) chamber, the sixth processing chamber is a PVD chamber, and the seventh processing chamber is an annealing chamber.

8. The processing system of claim 6, wherein the anchoring layer, the conductor, and the capping layer comprise cobalt (Co).

9. The processing system of claim 6, wherein the barrier layer and the capping layer comprise nitrogen (N).

10. A method for forming a contact using the processing system of claim 1, comprising: In a first processing chamber, a portion of the source / drain region of a substrate is converted into a doped semiconductor layer to reduce contact resistance, wherein the source / drain region is exposed via trenches formed in a dielectric material above the source / drain region; A metal silicide layer is deposited over the doped semiconductor layer; An anchoring layer is formed above the metal silicide layer and above the sidewalls of the trench; The trench is filled with a conductor; and Heating the substrate causes the conductor to flow back within the trench; The source / drain regions have a first doping concentration, while the doped semiconductor layer has a second doping concentration, which is higher than the first doping concentration. The ratio of the second doping concentration to the first doping concentration is in the range of 1.5:1 to 10:

1.

11. The method of claim 10, further comprising: A barrier layer is deposited over the metal silicide layer; and A covering layer is formed over the conductor.

12. The method of claim 10, further comprising planarizing the substrate, wherein planarizing the substrate comprises a chemical mechanical polishing (CMP) process.

13. The method of claim 11, wherein The anchoring layer and the conductor contain cobalt (Co), and The barrier layer contains nitrogen (N).

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