Method and system for testing integrated circuits

Abstract

A method of testing an integrated circuit is provided. The method includes operations of generating, by a processing unit, a mapping table associated with a plurality of scan chains and a plurality of shift cycles, the shift cycles corresponding to a plurality of values stored in the scan chains in the integrated circuit; determining, in response to values output from the scan chains, at least one faulty flip-flop in the scan chains based on the mapping table; and identifying at least one fault location corresponding to the at least one faulty flip-flop.

Description

Technical Field

[0001] This case relates to a method for testing integrated circuits, and more particularly to a test method and system for detecting defective flip-flops in a scanning flip-flop. Background Technology

[0002] In semiconductor integrated circuit manufacturing, integrated circuits (ICs) are conventionally tested during manufacturing and before shipment to ensure proper operation. Wafer testing is a commonly used testing technique in the production testing of wafer-mounted semiconductor ICs, in which temporary electrical connections are established between automated test equipment (ATE) and the IC formed on the wafer to verify the proper performance of the IC. Summary of the Invention

[0003] According to one embodiment of this invention, a method for testing an integrated circuit is provided. The method includes several operations: generating a mapping table by a processing unit indicating the output results of a plurality of pins, each of which outputs a plurality of values ​​in a plurality of shift cycles, the values ​​being stored in a corresponding one of a plurality of scan chains of the integrated circuit; determining at least one defective flip-flop in the scan chain based on the mapping table in response to the value output by the self-scan chain; and identifying at least one fault location corresponding to the at least one defective flip-flop.

[0004] According to one embodiment of this application, a method for testing an integrated circuit is provided. The method includes several operations: testing a first scan chain operating at a first voltage level using a tester with a first test pattern; after operating the first scan chain at a second voltage level lower than the first voltage level, retesting the first scan chain operating at the first voltage level with a second test pattern to generate a failure log; and diagnosing at least one first non-compliant flip-flop in the first scan chain by a processor based on the failure log and a mapping table, wherein the mapping table is associated with the first scan chain and a plurality of shift cycles, wherein diagnosing at least one first non-compliant flip-flop includes: determining at least one non-compliant shift cycle; and determining at least one first non-compliant flip-flop in the first scan chain corresponding to at least one non-compliant shift cycle.

[0005] According to one embodiment of this invention, a system for testing integrated circuits is provided. The system includes: one or more processing units; and a storage unit for storing a plurality of instructions, which, when executed by at least one of the processing units, perform a plurality of operations, including: reading a result sample received from a tester, wherein the result sample includes a plurality of bit data; detecting at least one non-conforming result value in the result sample; determining a non-conforming chain and at least one non-conforming shift loop corresponding to the at least one non-conforming result value; and determining at least one non-conforming flip-flop associated with the non-conforming chain and at least one non-conforming shift loop.

[0006] According to one embodiment of this invention, a method for testing an integrated circuit is provided. The method includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one defective chain in the scan chains and determining at least one defective shift cycle corresponding to at least one defective value; mapping the at least one defective chain and the at least one defective shift cycle to the scan chains to identify at least one defective flip-flop; and identifying at least one fault location corresponding to the at least one defective flip-flop.

[0007] According to one embodiment of this invention, a method for testing integrated circuits is provided. The method includes several operations: loading multiple values ​​into a first scan chain and storing the values ​​in the first scan chain at a first voltage level; operating the first scan chain at a second voltage level, which is different from the first voltage level; outputting a clock value at the first voltage level as multiple output values ​​in multiple shift cycles; comparing the output values ​​with values ​​to generate a failure log; and determining whether a failure flip-flop is in the first scan chain based on the failure log and a mapping table.

[0008] According to one embodiment of this invention, a system for testing integrated circuits is provided. The system includes: one or more processing units; and a storage unit for storing a plurality of instructions, which, when executed by at least one of the processing units, perform a plurality of operations, the operations including: at least one non-conforming result value in a self-test result sample; determining at least one non-conforming shift loop corresponding to the at least one non-conforming result value; and determining at least one non-conforming flip-flop associated with the at least one non-conforming shift loop based on a mapping table. Attached Figure Description

[0009] The appearance of one embodiment of this invention is best understood by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1Here is a block diagram of a test system for testing integrated circuits according to some embodiments of this case;

[0011] Figure 2 This is a flowchart of a method for testing integrated circuits according to some embodiments of this case;

[0012] Figure 3 The illustrations, according to some embodiments of this case, include... Figure 1 A simplified schematic diagram of a scan flip-flop circuit in an integrated circuit.

[0013] Figure 4A According to some embodiments of this case, the corresponding Figure 3 A schematic diagram of a mapping table for a scanning flip-flop circuit;

[0014] Figure 4B According to some embodiments of this case Figure 3 A schematic diagram of the scanning flip-flop circuit;

[0015] Figure 5 According to some embodiments of this case, including... Figure 1 A simplified schematic diagram of a scan flip-flop circuit in an integrated circuit.

[0016] Figure 6 According to some embodiments of this case, including... Figure 5 A schematic diagram of a flip-flop in a scanning flip-flop circuit;

[0017] Figure 7 According to some embodiments of this case, including... Figure 6 A schematic diagram of a latch circuit in a flip-flop circuit;

[0018] Figure 8 According to some embodiments of this case, including... Figure 1 A simplified schematic diagram of a scan flip-flop circuit in an integrated circuit.

[0019] Figure 9 The illustrations, according to some embodiments of this case, include... Figure 1 A simplified schematic diagram of a scan flip-flop circuit in an integrated circuit.

[0020] Figure 10A According to some embodiments of this case, the corresponding Figure 9 A schematic diagram of a mapping table for a scanning flip-flop circuit;

[0021] Figure 10B According to some embodiments of this case, the corresponding Figure 9 A schematic diagram of the scanning flip-flop circuit of one of them.

[0022] [Symbol Explanation]

[0023] 100: Test System

[0024] 110: Processing Unit

[0025] 111: Test Sample Generator

[0026] 112: Non-conforming diagnostic unit

[0027] 120: Tester

[0028] 130: Integrated Circuits

[0029] 140: Database

[0030] 150: Storage Unit

[0031] 200: (Methods for testing integrated circuits)

[0032] 210-290: Operation

[0033] 300, 800, 900: Scan flip-flop circuit

[0034] 310, 320, 330, 910, 920, 930: Level

[0035] 311: Decompressor

[0036] 312: Compressor

[0037] 313, 811-815, 821-825, 911: Flip-Flipper

[0038] 314: Mark

[0039] 331-334: Circle

[0040] PIN1-PIN3: Pins

[0041] IN: Input signal

[0042] OUT: Output signal

[0043] 400,1000: Mapping table

[0044] CHAIN1-CHAIN3: Scan Chain

[0045] FF1-FF6: Shifter

[0046] F: Unacceptable result value

[0047] 500: One-bit scanning flip-flop circuit, scanning flip-flop circuit

[0048] 510: Multiplexer

[0049] 520: First D flip-flop, first flip-flop

[0050] 530, 541, 831: Inverters

[0051] 540: Second D flip-flop, second flip-flop

[0052] 542,543,832: AND gate

[0053] 544, 545: NOR gate

[0054] 546: Latch circuit

[0055] 833: OR gate

[0056] CLK: Clock signal

[0057] D,Q,Q': terminal

[0058] D1, D2: Data

[0059] DA: Data Output

[0060] FL: Invalid Log

[0061] N1-N4, P1-P4: Transistors

[0062] Pa1, Pa2: Leakage paths

[0063] ROW1, ROW2: rows

[0064] SE: Scan Enable Signal

[0065] SI: Scan Data Input

[0066] TP: Test Sample Signal Detailed Implementation

[0067] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of the present invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0068] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which they are used. The use of examples in this specification (including examples of any terms discussed herein) is illustrative only and is in no way intended to limit the scope or meaning of any embodiment of this invention or any of the illustrative terms. Similarly, an embodiment of this invention is not limited to the various embodiments given in this specification.

[0069] As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like shall be understood as open-ended, that is, meaning including but not limited to.

[0070] Throughout this specification, the references to "one embodiment," "an embodiment," or "some embodiments" mean that a particular feature, structure, implementation, or characteristic described in connection with that embodiment is included in at least one embodiment of this document. Therefore, the use of the phrases "in one embodiment," "in one embodiment," or "in some embodiments" throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular feature, structure, implementation, or characteristic may be combined in any suitable manner.

[0071] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship between one component or feature as illustrated in the figures and another component or feature. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0072] As used herein, “approximately,” “about,” “roughly,” or “substantially” should generally refer to any approximation of a given value or range, which varies depending on the various techniques to which it pertains, and its scope should be consistent with the broadest interpretation understood by one skilled in the art to which it pertains, so as to encompass all such modifications and similar structures. In some embodiments, it should generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numerical quantities given herein are approximations, meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated, or mean other approximations.

[0073] Integrated circuits, including system-on-a-chip (SoC), integrate various digital and sometimes analog components on a single chip. Integrated circuits can have manufacturing defects, such as physical faults and manufacturing defects that cause them to malfunction. Therefore, it is necessary to test integrated circuits to detect manufacturing defects. Design for Test (DFT) technology adds testability features to integrated circuits, allowing automated test equipment (ATE) to perform various fault tests using test patterns. An integrated circuit undergoing fault testing consists of multiple scan flip-flops forming a scan chain. Instead of removing data, test data is shifted into one end of the scan chain and removed at the other end using start data to detect any faults.

[0074] Scan chain diagnostics focuses on detecting fixed-type faults, where the term "fixed-type fault" implies that the logic state of one or more flip-flops cannot be rewritten or altered. Scan chain diagnostics can diagnose and identify a non-conforming scan flip-flop in a scan chain under normal operating power conditions, for example, a scan chain operating at a first voltage. However, when a non-conforming flip-flop has slight leakage at a relatively low voltage, the current scan chain diagnostics operating at a higher first voltage cannot detect the non-conforming flip-flop.

[0075] One embodiment of this invention provides a method for diagnosing a defective flip-flop with a slight leakage at relatively low voltages compared to normal operation, and for identifying a fault location corresponding to the defective flip-flop for further physical failure analysis (PFA). Therefore, investigating the root cause of the failure is used in a continuous improvement process (CIP) to achieve higher yields and reliability of integrated circuits.

[0076] Now to Figure 1 Please refer to it. Figure 1 This is a block diagram of a test system 100 for testing an integrated circuit 130 according to some embodiments of this case. (See also...) Figure 1The diagram illustrates that the test system 100 includes a processing unit 110, a tester 120, an integrated circuit 130 for testing, a database 140, and a storage unit 150. The processing unit 110 is coupled to the tester 120, the database 140, and the storage unit 150. In operation, in some embodiments, the processing unit 110 outputs a test sample signal TP to the tester 120. The tester 120 transmits an input signal IN to the integrated circuit 130 for testing and receives an output signal OUT including the test result value. The tester 120 further generates a non-conformance log based on the output signal OUT and sends the non-conformance log to the processing unit 110.

[0077] In some embodiments, processing unit 110 is included in a host computer programmed by a test engineer. Processing unit 110 is coupled to tester 120 via a bus (not shown). Processing unit 110 is configured to execute computer program code encoded in storage unit 150 and receive data from database 140, so that test system 100 can be used to perform some or all of the processes and / or methods indicated below. In one or more embodiments, processing unit 110 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0078] As in Figure 1 As shown in the illustration, in some embodiments, the processing unit 110 further includes a test pattern generator and a non-conformance diagnosis unit 112. The test pattern generator 111 receives scan chain test patterns from the database 140 and generates a test pattern signal TP for testing. The non-conformance diagnosis unit 112 analyzes the non-conformance log FL received from the tester 120 based on a mapping table stored in the storage unit 150. The non-conformance diagnosis unit 112 further receives the location (corresponding to the integrated circuit layout) of the tested flip-flops in the integrated circuit 130 and identifies the fault location corresponding to the non-conformance flip-flops based on the analysis.

[0079] In some embodiments, the processing program executed by the processing unit 110 implements the function of a program stored in the storage unit 150 together with data stored in the database 140. In some embodiments, the database 140 and the storage unit 150 are electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor systems (or devices or components). For example, each of the database 140 and the storage unit 150 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, each of the database 140 and the storage unit 150 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD). In some embodiments, each of the database 140 and the storage unit 150 includes a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, the external / removable and / or internal / built-in storage or memory units mentioned above.

[0080] Continue reading Figure 1 Tester 120 implements automated test equipment (ATE). A suitable ATE is a wafer-based or wafer-packaged test system, typically including a main controller (usually a computer) that synchronizes one or more sources with capture devices such as D / A and A / D converters. Integrated circuit 130 is the device under test (DUT), typically connected to the ATE by a robotic handle or probe entity that engages conductors on the wafer and adapts the ATE's output and input sources to temporarily operatively unite the ATE with the integrated circuit 130 during testing. The engaged conductors include input and output lines to the integrated circuit 130, but also conductors that can be accessed on the surface of the integrated circuit 130 to contact the ATE probes. ATE probes are typically custom-designed portions of interface test adapters (ITAs) or "fixtures" tailored to the integrated circuit design and adapting the ATE's resources to the DUT. The ATE applies static or dynamically changing digital or analog levels in sequence or pattern designed to establish an operating environment for the integrated circuit 130.

[0081] Figure 1The configurations shown are for illustrative purposes. Various implementations are within the expected scope of one embodiment of this case. For example, in some embodiments, database 140 is integrated with storage unit 150.

[0082] Now to Figure 2 Please refer to it. Figure 2 This is a flowchart of a method 200 for testing an integrated circuit 130 according to some embodiments of this case. It should be understood that the method can be implemented by... Figure 2 Additional operations are provided before, during, and after the demonstrated process, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable. Similar elements are identified using similar reference numerals throughout the various views and illustrative embodiments. Method 200 includes the following references Figure 1 The test system 100 describes operations 210 to 290.

[0083] In operation 210, the test pattern generator 111 of the processing unit 110 generates a plurality of first and second test patterns included in the test pattern signal TP based on the scan chain test pattern. For example, in some embodiments, the scan chain test pattern includes test data and commands (i.e., downloading test data, sequences, conditions, or timing selections) for the operation of the tester 120 to test the integrated circuit 130. Each scan chain test pattern is programmed for a specific scan (flipper) chain. The first test pattern is associated with shifting test data into the scan chain and storing the value of the test data in the flipper 313 of each scan chain. The second test pattern is associated with removing the stored value from the scan chain and detecting a faulty flipper.

[0084] In operation 220, processing unit 110 generates a mapping table associated with scan chains and shift cycles. For example, in some embodiments, there are three scan chains in a scan flip-flop circuit, and four shift cycles are required to clock out (shift out) all stored values ​​(i.e., four values ​​(bits)) in the scan chains. Therefore, the mapping table includes three rows corresponding to the three scan chains and four columns corresponding to the four shift cycles. In various embodiments, the generated mapping table is stored in storage unit 150.

[0085] In some embodiments, the operation of generating the mapping table further includes obtaining a first test pattern to determine shift cycles and scan chains. For example, the first test pattern includes test data comprising four values ​​for each of three scan chains. Thus, a mapping table similar to the mapping table mentioned above is generated. In some embodiments, a second test pattern includes the same information regarding the number of scan chains and the number of values ​​in the test data. Therefore, alternatively, the operation of generating the mapping table further includes obtaining a second test pattern to determine shift cycles and scan chains.

[0086] In operation 230, by loading a first test sample into the scan chain to store the value associated with the first test sample, tester 120 tests the scan flip-flop circuit, as in... Figure 3 It is displayed in the middle. Figure 3 The illustrations, according to some embodiments of this case, include... Figure 1 A simplified schematic diagram of the scan flip-flop circuit 300 in integrated circuit 130 is shown. For illustration purposes, the scan flip-flop circuit 300 includes a decompressor 311, a compressor 312, and a flip-flop 313 included in three scan chains. Figure 3 The number of scan chains and flip-flops 313 is given for illustrative purposes. Various implementations of the number of scan chains and flip-flops 313 are within the expected scope of one embodiment of this invention. The scan flip-flop circuit 300 operates in three stages 310 to 330. Figure 3 As shown, decompressor 311 receives a first test sample loaded as an input signal IN and decompresses the test data into a scan chain. Test data with a "1100" sequence is clocked in at each stage of the scan chain and stored in the corresponding flip-flop. In some embodiments, the scan chain is operating at a first voltage level at stage 310. In various embodiments, stage 310 is referred to as normal operating mode.

[0087] In some embodiments, method 200 further includes reducing the operating voltage level of the scan flip-flop circuit 300. (As in...) Figure 3 As shown, at stage 320, the scan flip-flop circuit 300 operates at a second voltage level lower than the first voltage level of stage 310. The ratio between the second voltage level and the first voltage level ranges from about 80% to about 20%. In various embodiments, the operating voltage level of the scan flip-flop circuit 300 is maintained at the second voltage level for a certain duration. The duration is determined by experimental results indicating a sufficient duration for detecting minute leaks in defective flip-flops, and the duration is related to IC design and / or technology. In various embodiments, the duration is greater than about 100 milliseconds (ms).

[0088] In operation 240, tester 120 retests the flip-flop circuit 300 using a second test pattern to output values ​​stored in flip-flop 313, and records these values ​​(i.e., the result pattern) in the failure log FL. In some embodiments, the output values ​​are recorded in the second test pattern. For illustration purposes, as shown in Figure 3As shown in the diagram, at stage 330, the operating voltage of the scan flip-flop circuit 300 is changed to a first voltage, and the scan flip-flop circuit 300 operates in normal operating mode. The scan flip-flop circuit 300 outputs these values ​​in a predetermined number of shift cycles, and records the output values ​​in the defect log FL via the output signal OUT. The output signal OUT is generated by compressor 312 compressing values ​​at pins PIN1 to PIN3. For example, since four values ​​are stored in the scan chain, at least four shift cycles are executed. Furthermore, the output in the same shift cycle is generated by... Figure 3 The values ​​circled in circles 331 to 334. For example, in shift loop 1 (circle 331), the first value "0" at pin 1 corresponding to the top scan chain, the first value "0" at pin 2 corresponding to the middle scan chain, and the first value "0" at pin 3 corresponding to the bottom scan chain are output together, and so on. In some embodiments, such as in Figure 3 As shown, when the flip-flop malfunctions (labeled 314) after the flip-flop circuit 300 swings between the first and second voltage levels, the stored value changes from the desired "1" to "0". Therefore, the output data at pin PIN2 has a "1000" sequence, where the faulty value is the first "0" from the left and... Figure 3 The Chinese characters are marked in bold and underlined.

[0089] In some embodiments, the retest further includes generating a non-conforming result value by comparing the input value with the output value. For example, as mentioned above, by comparing the output sequence "1000" with the input sequence "1100", the third value output at pin PIN2 in loop 3 (cycle 333) is identified as a non-conforming value. To indicate a non-conforming third value, the tester 120 correspondingly generates a non-conforming result value "F" in the non-conforming log. In some embodiments, for example, corresponding to Figure 3 In the example shown, the non-conformance log FL is represented as follows: 1100

[0091] 1F00 1100

[0093] The values ​​in the top row correspond to the top scan chain coupled to pin PIN1. The values ​​in the middle row correspond to the middle scan chain coupled to pin PIN2. The values ​​in the bottom row correspond to the bottom scan chain coupled to pin PIN3. Alternatively, the non-conforming log is associated with the sequence of scan chains, values, and shift cycles. The configuration of the non-conforming result values ​​is given for illustrative purposes. Various implementations are within the expected scope of one embodiment of this invention. For example, in some embodiments, the non-conforming result value is given as "X".

[0094] Continue reading Figure 2 The non-conformance diagnosis unit 112 is used to diagnose non-conformance flip-flops in the scan chain based on the non-conformance log FL and the mapping table. The following description includes detailed operations of 250 to 290.

[0095] In operation 250, the non-compliance diagnosis unit 112 of the processing unit 110 maps the non-compliance log FL to, as in Figure 4A The mapping table shown in the image is used to analyze non-compliant logs (FL). Figure 4A According to some embodiments of this case, the corresponding Figure 3 A schematic diagram of a mapping table 400 for a scanning flip-flop circuit 300. (As shown in...) Figure 4A The diagram illustrates, for example, that the values ​​in the top row of the defective log FL are recorded in the top row of the mapping table, and the first value "0" output in shift loop 1 is stored in the rightmost column corresponding to shift loop 1. The configuration of other values ​​recorded in mapping table 400 is similar to that of the values ​​in the top row of the defective log FL. Therefore, repeated descriptions are omitted. The configuration of mapping table 400 is given for illustrative purposes. Various implementations are within the expected scope of one embodiment of this case. For example, in some embodiments, the sequence of shift loops in mapping table 400 is reversed, and therefore, the values ​​in the defective log FL are recorded in mapping table 400 in a reversed sequence.

[0096] In operation 260, the non-conformance diagnostic unit 112 detects non-conformance result values ​​in the mapping table 400. For example, in Figure 4A In the embodiment shown, the non-compliant result value "F" is detected in the second row and the third column from the right.

[0097] In operation 270, after detecting a non-conforming result value, the corresponding non-conforming chain and the corresponding non-conforming shift cycle are determined. For example, in... Figure 4A As shown, the aforementioned non-conforming result value "F" corresponds to pin PIN2 and shift cycle 3. Because pin PIN2 corresponds to the intermediate scan chain in the flip-flop circuit 300, the intermediate scan chain is determined to be a non-conforming chain.

[0098] In operation 280, the non-converters corresponding to the non-conforming chain and non-conforming shift cycle are identified, such as in... Figure 4B It is displayed in the middle. Figure 4B According to some embodiments of this case Figure 3A schematic diagram of the scan flip-flop circuit 300 is shown. For illustration purposes, pins PIN1 to PIN3 correspond to scan chains CHAIN1 to CHAIN3. Flip-flops FF1 to FF4 sequentially correspond to flip-flops 313 arranged sequentially from self-decompressors 311 to compressors 312. In some embodiments, the defect diagnosis unit 112 maps defect chains and defect shift cycles to scan chains. For example, as mentioned above in operation 270, the defect intermediate chain is mapped to scan chain CHAIN2. Shift cycle 3 is mapped to flip-flop FF2. Therefore, in... Figure 4B The flip-flop marked in black is deemed a defective flip-flop.

[0099] In operation 290, the fault location corresponding to the defective flip-flop is identified. For example, the defect diagnostic unit 112 retrieves the location corresponding to scan chains CHAIN1 to CHAIN3 from the database 140. On the layout of integrated circuit 130, these locations are referred to as the coordinates of the flip-flop in scan chains CHAIN1 to CHAIN3. Therefore, when a defective flip-flop is determined, the defect diagnostic unit 112 identifies the fault location corresponding to the defective flip-flop.

[0100] In some embodiments, the fault location is obtained for test engineers to perform physical fault analysis on the non-conforming flip-flop. For example, in some embodiments, the physical fault analysis methods include transmission electron microscopy (TEM), atomic force microscopy (AFM), or any other suitable method. Physical faults are investigated, including, for example, minute current leakage between the terminals of a transistor. See also Figures 5 to 7 Provide an example of a physical failure.

[0101] Now to Figure 5 Please refer to it. Figure 5 According to some embodiments of this case, including... Figure 1 A schematic diagram of a one-bit scanning flip-flop circuit 500 in an integrated circuit. For illustration purposes, the scanning flip-flop circuit 500 includes a multiplexer 510, a first D flip-flop 520, an inverter 530, and a second D flip-flop 540. Grouped signals are input to the scanning flip-flop circuit 500 to control and observe the scanning mechanism. The multiplexer 510 receives the scan data input SI, the data output DA, and the scan enable signal SE, and outputs either the scan data input SI or the data output DA according to the scan enable signal SE. The first flip-flop 520 and the second flip-flop 540 receive the clock signal CLK to be cross-coupled and the inverted clock signal to store the data state. The inverted clock signal is generated by the inverter 530, which inverts the clock signal CLK.

[0102] Now to Figure 6 Please refer to it. Figure 6 According to some embodiments of this case, including... Figure 5 A schematic diagram of the second D flip-flop 540 in the scan flip-flop circuit 500. For illustration purposes, the second D flip-flop 540 includes an inverter 541, AND gates 542 to 543, and NOR gates 544 to 545. The inverter 541 is coupled to AND gates 542 to 543 and terminal D. AND gates 542 to 543 are coupled to a clock signal CLK. NOR gates 544 to 545 are coupled to the output terminals of AND gates 542 to 543 to receive data D1 to D2. NOR gates 544 to 545 are formed in a latch circuit 546 coupled to terminals Q and Q'. In some embodiments, as mentioned above, test data is shifted into and stored in the scan flip-flop circuit 500 operating at a first voltage level. The logic state at terminal Q represents the logic state stored in the latch circuit 546, such as "1" or "0".

[0103] Now to Figure 7 Please refer to it. Figure 7 According to some embodiments of this case, including... Figure 6 A schematic diagram of the latch circuit 546 in the flip-flop circuit. For illustration purposes, transistors P1 to P2 and N1 to N2 are included to form NOR gate 544. Transistors P3 to P4 and N3 to N4 are included to form NOR gate 545. The gates of transistors P1 and N1, which operate as input terminals of the latch circuit 546, receive data D1. The gates of transistors P3 and N4, which operate as other input terminals of the latch circuit 546, receive data D2. The gates of transistors P2 and N2 and the drains of transistors N3 to N4 and P4 are coupled to terminal Q'. The gates of transistors P4 and N3 and the drains of transistors N1 to N2 and P2 are coupled to terminal Q.

[0104] In some embodiments, see Figure 6 When the logic state at terminal D is "1" and the clock signal CLK is "0", data D1 to D2 have a logic state of "0". Therefore, as in Figure 7 As shown in the diagram, the logic states at terminals Q and Q' are "1" and "0" respectively.

[0105] In some embodiments, when the latch circuit 546 operates at a second voltage lower than the first voltage level (as mentioned above), the logic states of terminals Q and Q' are affected by physical faults. For example, in some embodiments, such as in Figure 7As shown, a charge with logic "1" at terminal Q flows through a leakage path Pa1 between the gate of transistor N1 and terminal Q to the gate of transistor N1 (which has logic "0"). Therefore, the logic state at terminal Q changes from "1" to "0". Similarly, in various embodiments, a leakage path Pa2 exists between the gate of transistor P3 and terminal Q, as shown in... Figure 7 As shown in the diagram, a charge with logic "1" at terminal Q flows to the gate of transistor P3 (which has logic "0"), and the logic state at terminal Q changes from "1" to "0".

[0106] As discussed above, the defective value stored in the latch circuit 546 is shifted out at the first voltage level, and by Figure 1 The test system 100 analyzes the flip-flop 540. The flip-flop 540 is determined to be a defective flip-flop. Alternatively, the defective flip-flop is identified and its coordinates are obtained using the test system 100 mentioned above. The test engineer further utilizes physical failure analysis to understand the root cause of the defective flip-flop. For example, by cutting the integrated circuit 130 at the fault location given by the test system 100, a cross-sectional view of the flip-flop 540 is obtained, and leakage paths Pa1 and / or Pa2 are found.

[0107] Figures 2 to 7 The configuration is given for illustrative purposes. Various implementations are within the expected scope of one embodiment of this case. For example, in some embodiments, instead of recording the exact stored value in the failure log FL, the value recorded in the failure log FL corresponding to the normal flip-flop is replaced by the normal result value (e.g., "P"). Specifically, in Figure 4A In the mapping table 400, the value in the top row is “PPPP” and the value in the middle row is “PFPP”.

[0108] Now to Figure 8 Please refer to it. Figure 8 According to some embodiments of this case, including... Figure 1 A simplified schematic diagram of a scan flip-flop circuit 800 in integrated circuit 130 is shown. For illustration, scan chains CHAIN1 to CHAIN2 are arranged in two adjacent rows ROW1 and ROW2. Scan chain CHAIN1 includes flip-flops 811 to 815, and scan chain CHAIN2 includes flip-flops 821 to 825. Flip-flops 811 to 812 are coupled to flip-flops 822 to 823 via inverter 831 and AND gate 832. Flip-flops 812 to 814 are coupled to flip-flops 822 to 823 via OR gate 833 and AND gate 832.

[0109] In some embodiments, the configuration of the test scan flip-flop circuit 800 is similar to that of the test scan flip-flop circuit 300. Specifically, the scan chains CHAIN1 to CHAIN2 are tested using the first test pattern and the second test pattern mentioned above. Test data including the value "11001" is shifted in at a first voltage level and stored in the scan chains CHAIN1 to CHAIN2. After shifting in, the operating voltage level drops to a second voltage level for a duration and then increases back to the first voltage level. (As in...) Figure 8 The diagram illustrates the removal of the stored value "11011" from scan chain CHAIN1, where the defective value is the second "1" from the right. Similarly, the removal of the stored value "11000" from scan chain CHAIN2, where the defective value is the first "0" from the right. Figure 8 Non-conforming values ​​will be marked in bold and underlined. This is achieved through methods such as... Figures 1 to 7 The configuration of the test system 100 shown in the figure, based on the output value and the corresponding mapping table, determines the flip-flops 814 and 825 in the scan chain 1 as unqualified flip-flops.

[0110] In some methods, the scan flip-flop circuit operates at a constant voltage level (e.g., the first voltage level mentioned above). When a flip-flop malfunctions and cannot flip in the scan chain (i.e., holds the logic state "1"), during the shift-out operation, each bit of the malfunctioning flip-flop is "fixed" and retains the logic state of the malfunctioning flip-flop. For example, as in... Figure 8 As shown, if flip-flop 814 is a faulty flip-flop and its logic state is "1", then the shift-in test data "11000" is shifted out of scan chain CHAIN1 as "11111". In this configuration, because each bit is affected by the faulty flip-flop, it is impossible to determine the faulty flip-flop based on comparing the shift-out data and the shift-in data. In some methods, to determine the faulty flip-flop, the test data is shifted to scan chain CHAIN2 via inverter 831, AND gate 832, and OR gate 833. Because scan chain CHAIN2 does not have faulty flip-flops, the test data is shifted out accurately. The faulty flip-flop is determined by comparing the shift-out data from scan chains CHAIN1 and CHAIN2 in each shift cycle. However, when there are one or more faulty flip-flops in scan chain CHAIN2, the shift-out data is affected by the faulty flip-flops in scan chain CHAIN2. It is impossible to identify the faulty flip-flops in scan chain CHAIN1 or scan chain CHAIN2.

[0111] With as in Figure 8Compared to some methods shown in the example, through the configuration of one embodiment of this case, when the scanning flip-flop circuit is operating at the second voltage level, the logic state of the faulty flip-flop is disturbed, and the faulty flip-flop can still flip at the first voltage level during the shift-out period. Therefore, each bit of the test data is not affected by the faulty flip-flop and, after shifting out, retains its original logic state. As described above. Figure 8 The description states that defective flippers in each scan chain are identified separately without transferring test data into adjacent scan chains. Therefore, multiple defective flippers in two adjacent scan chains can be diagnosed. This provides greater flexibility in diagnosing defective flippers compared to some other methods.

[0112] Figure 8 The configurations shown are provided for illustrative purposes. Various implementations are within the expected scope of one embodiment of this invention. For example, in some embodiments, inverter 831, AND gate 832, and OR gate 833 are eliminated.

[0113] Now to Figure 9 Please refer to it. Figure 9 The illustrations, according to some embodiments of this case, include... Figure 1 A simplified schematic diagram of a scan flip-flop circuit 900 in an integrated circuit. In some embodiments, regarding, for example... Figure 3 The scanning flip-flop circuit 300 is used to configure the scanning flip-flop circuit 900. Figure 1 The test system 100 further executes method 200 to test the scan flip-flop circuit 900. Operation stages 910 to 930 are, for example, related to... Figure 3 The configuration ranges from level 310 to 330. The input signal IN is about, for example... Figure 3 The input signal IN is configured. For illustration, the scan flip-flop circuit 900 includes a flip-flop 911. In some embodiments, the flip-flop 911 is related to, for example... Figure 3 The flip-flop 313 configuration. For the sake of brevity, components including, for example, the corresponding decompressor and compressor are omitted here.

[0114] In some embodiments, there are different numbers of flip-flops included in the three scan chains. For example, in Figure 9 As shown, six flip-flops 911, three flip-flops 911, and four flip-flops 911 are individually included in the top, middle, and bottom scan chains, respectively. In various embodiments, the test data (i.e., samples) used for different scan chains are different from each other. For example, as in... Figure 9 As shown, test data "101010", test data "101", and test data "1100" are shifted into and stored in three different scan chains via the input signal IN at stage 910. The scan flip-flop circuit 900 operates at the first voltage level.

[0115] After operating at stage 920 for a duration at a second voltage level lower than the first voltage level, the scan flip-flop circuit 900 operates at the first voltage level at stage 930. Stored values ​​are shifted out at pins PIN1 to PIN3. For illustration, the value "100000" is shifted out at pin PIN1, the value "100" is shifted out at pin PIN2, and the value "1100" is shifted out at pin PIN3. For the output of pin PIN1, the non-conforming values ​​are the second and fourth "0"s from the right. For the output of pin PIN2, the non-conforming value is the first "0" from the right. Figure 9 Non-conforming values ​​are marked in bold and underlined. The removed values ​​are recorded in the non-conforming log FL. In some embodiments, for example, corresponding to... Figure 9 In the example shown, the non-conformance log FL is represented as follows:

[0116] 10F0F0

[0117] 10F 1100

[0119] The values ​​in the top row correspond to the top scan chain coupled to pin PIN1. The values ​​in the middle row correspond to the middle scan chain coupled to pin PIN2. The values ​​in the bottom row correspond to the bottom scan chain coupled to pin PIN3.

[0120] Now to Figure 10A Please refer to it. Figure 10A According to some embodiments of this case, the corresponding Figure 9 A schematic diagram of the mapping table 1000 for the scanning flip-flop circuit 900. For illustration purposes, the values ​​in the non-conforming log FL are recorded in the mapping table 1000, as shown in... Figure 10A It is displayed in the middle.

[0121] Figure 1 The non-conformance diagnosis unit 112 detects non-conformance result values ​​in the mapping table 1000. For example, in Figure 10A In the embodiment shown, two non-compliant result values ​​"F" are detected in the first row and the second and fourth columns from the right, and another is detected in the second row and the first column from the right.

[0122] After detecting a non-compliant result value, the corresponding non-compliant chain and the corresponding non-compliant shift cycle are determined. For example, in... Figure 10A As shown, one non-compliant result value corresponds to pin PIN1 (top scan chain) and shift loop 2, another corresponds to pin PIN1 and shift loop 4, and yet another corresponds to pin PIN2 (middle scan chain) and shift loop 1.

[0123] Now to Figure 10B Please refer to it. Figure 10B According to some embodiments of this case, the corresponding Figure 9 A schematic diagram of the scan flip-flop circuit 900 is shown. For illustration, pins PIN1 to PIN3 correspond to scan chains CHAIN1 to CHAIN3. Flip-flops FF1 to FF6 sequentially correspond to flip-flops 911 arranged sequentially from the input terminal to the pin. In some embodiments, the failure diagnosis unit 112 maps the failure chain and failure shift cycle to the scan chain. For example, pin PIN1 and shift cycle 2 correspond to flip-flop FF5 in scan chain CHAIN1. Pin PIN1 and shift cycle 4 correspond to flip-flop FF3 in scan chain CHAIN1. Pin PIN2 and shift cycle 1 correspond to flip-flop FF6 in scan chain CHAIN2.

[0124] In some embodiments, after identifying a defective flip-flop, the corresponding fault location is obtained for further physical fault analysis.

[0125] Figure 9 The configurations shown are for illustrative purposes. Various implementations are within the expected scope of one embodiment of this case. For example, in some embodiments, scan chains CHAIN2 to CHAIN3 include the same number of flip-flops as scan chain CHAIN1.

[0126] As described above, a method for testing a scanning flip-flop circuit is provided. The scanning flip-flop circuit oscillates between high and low voltages to detect fault-induced leakage. By analyzing a non-conformance log provided by a tester using a mapping table, one or more corresponding non-conforming flip-flops are identified for further physical fault analysis. Therefore, integrated circuits can be tested before shipment to ensure proper operation, enhancing the detectability of minute leaks, and in one embodiment of this invention, detecting a low defect parts per million (DPPM).

[0127] In some embodiments, a method is provided herein. The method includes several operations: generating a mapping table associated with a plurality of scan chains and a plurality of shift cycles, the shift cycles corresponding to a plurality of values ​​stored in the scan chains within an integrated circuit; determining at least one defective flip-flop in the scan chains based on the mapping table in response to a value output from a scan chain; and identifying at least one fault location corresponding to the at least one defective flip-flop. In some embodiments, generating the mapping table includes acquiring a plurality of first test patterns to determine the shift cycles and scan chains. In some embodiments, the method includes generating a plurality of first test patterns and a plurality of second test patterns based on the plurality of scan chain test patterns; loading the first test patterns into the scan chains to store values ​​associated with the first test patterns; and outputting values ​​to be included in the second test patterns for determining at least one defective flip-flop. In some embodiments, the method includes operating the integrated circuit by a tester for a predetermined number of shift cycles to generate a defect log; and mapping the defect log to the mapping table to determine at least one defective flip-flop. The defect log is associated with the scan chains and values. In some embodiments, determining at least one defective flip-flop includes determining at least one defective chain and at least one defective shift loop corresponding to at least one defective value in the values ​​output by the self-scanning chain; and mapping the at least one defective chain and at least one defective shift loop to the scan chain to identify at least one defective flip-flop. In some embodiments, when at least one defective flip-flop includes first and second defective flip-flops in a first and a second chain respectively in the scan chain, determining at least one defective flip-flop includes identifying a first defective value in the output values ​​from the first chain and identifying a second defective value in the output values ​​from the second chain; and determining the first defective flip-flop and the second defective flip-flop based on a mapping table. The first chain is adjacent to the second chain, and at least one flip-flop in the first chain is coupled to the second chain. In some embodiments, the method includes obtaining, by a processing unit, multiple positions corresponding to the scan chain from a database, including at least one fault location.

[0128] Also disclosed is a method comprising the steps of: testing a first scan chain operating at a first voltage level by a tester using a first test pattern; after operating the first scan chain at a second voltage level lower than the first voltage level, retesting the first scan chain operating at the first voltage level using a second test pattern to generate a failure log; and diagnosing at least one first failure flip-flop in the first scan chain by a processor based on the failure log and a mapping table. The mapping table is associated with the first scan chain and a plurality of shift cycles. In some embodiments, testing the first scan chain using the first test pattern includes loading a plurality of values ​​into the first scan chain and storing the values ​​in the first scan chain. Retesting the first scan chain includes clock output stored values ​​as values ​​of a plurality of outputs in the shift cycle; and generating at least one failure result value by comparing the output values ​​with values. In some embodiments, the failure log is associated with the order of the plurality of shift cycles and the plurality of output values ​​corresponding to the shift cycles. In some embodiments, diagnosing at least one first non-conforming flip-flop includes mapping a non-conforming log to a mapping table; and detecting at least one non-conforming result value in the mapping table to determine at least one first non-conforming flip-flop. In some embodiments, diagnosing at least one first non-conforming flip-flop includes mapping the non-conforming log to determine at least one non-conforming cycle in a shift loop; determining at least one first non-conforming flip-flop in a first scan chain corresponding to at least one non-conforming cycle; and obtaining at least one fault location corresponding to at least one first non-conforming flip-flop from a database by a processing unit to perform a physical fault analysis. In some embodiments, the method includes testing a second scan chain operating at a first voltage level using a third test pattern; after operating the second scan chain at a second voltage, retesting the second scan chain operating at the first voltage level using a fourth test pattern to update the non-conforming log; and diagnosing at least one second non-conforming flip-flop in the second scan chain based on the non-conforming log and the mapping table. The first scan chain includes at least one flip-flop coupled between two adjacent flip-flops in the second scan chain. In some embodiments, the first test pattern is different from the third test pattern. In some embodiments, diagnosing at least one second faulty flip-flop in the second scan chain includes determining whether an input terminal of a latching circuit used to store a value in at least one second faulty flip-flop is short-circuited.

[0129] Also disclosed is a system including one or more processing units; and a memory unit for storing instructions that, when executed by at least one of the processing units, perform operations including: reading a result sample received from a tester, wherein the result sample includes multiple bit data; detecting at least one non-conforming result value in the result sample; determining a non-conforming chain and at least one non-conforming shift loop corresponding to the at least one non-conforming result value; and determining at least one non-conforming flip-flop associated with the non-conforming chain and at least one non-conforming shift loop. In some embodiments, the operation further includes obtaining at least one fault location corresponding to the at least one non-conforming flip-flop from a database. In some embodiments, the operation further includes generating a test sample to the tester based on a scan chain sample to operate an integrated circuit that oscillates between a first voltage level and a second voltage level below the first voltage level; and generating a mapping table associated with the test sample, wherein the mapping table is associated with multiple shift loops. In some embodiments, the operation further includes mapping the result sample to multiple shift loops and multiple chains to determine a non-conforming chain and at least one non-conforming shift loop. In some embodiments, the operation further includes mapping at least one defective shift loop to a plurality of flippers in a defective chain to determine at least one defective flipper.

[0130] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this application. Those skilled in the art should understand that this application can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and adjustments can be made without departing from the spirit and scope of this application.

Claims

1. A method for testing integrated circuits, characterized in that, Includes the following steps: A processing unit generates a mapping table indicating an output result of multiple pins, each of which outputs multiple values ​​in multiple shift cycles, the multiple values ​​being stored in a corresponding one of multiple scan chains of an integrated circuit; In response to the plurality of values ​​output from the plurality of scan chains, at least one of the plurality of scan chains is determined to be a non-compliant flip-flop based on the mapping table; as well as Identify at least one fault location corresponding to the at least one non-conforming flip-flop.

2. The method as described in claim 1, characterized in that, The steps involved in generating this mapping table include: Multiple first test samples are obtained to determine the multiple shift cycles and the multiple scan chains.

3. The method as described in claim 1, characterized in that, Further steps include: Multiple first test patterns and multiple second test patterns are generated based on multiple scan chain test patterns; The plurality of first test patterns are loaded into the plurality of scan chains to store the plurality of values ​​associated with the plurality of first test patterns; as well as The multiple values ​​are output to be included in the multiple second test samples for determining the at least one non-converter.

4. The method as described in claim 1, characterized in that, Further steps include: A tester operates the integrated circuit for a predetermined number of the plurality of shift cycles to generate a defect log, wherein the defect log is associated with the plurality of scan chains and the plurality of values; as well as Map the non-compliant log to the mapping table to determine the at least one non-compliant flip-flop.

5. The method as described in claim 1, characterized in that, The step of determining the at least one defective flip-flop includes the following steps: Determine at least one non-compliant chain and at least one non-compliant shift loop corresponding to at least one non-compliant value among the multiple values ​​output from the multiple scan chains; as well as The at least one defective chain and the at least one defective shift cycle are mapped to the plurality of scan chains to identify the at least one defective flip-flop.

6. The method as described in claim 1, characterized in that, The step of determining the at least one defective flip-flop includes the following steps: When the at least one defective flip-flop includes a first defective flip-flop in a first chain and a second defective flip-flop in a second chain, respectively, among the plurality of scan chains. Identify a first non-compliant value among a plurality of output values ​​from the first chain and identify a second non-compliant value among a plurality of output values ​​from the second chain; as well as Based on the mapping table, the first defective flip-flop and the second defective flip-flop are determined; The first chain is adjacent to the second chain, and at least one flip-flop in the first chain is coupled to the second chain.

7. The method as described in claim 6, characterized in that, Further steps include: The processing unit retrieves multiple positions corresponding to the multiple scan chains from a database, the multiple positions including the at least one fault location.

8. A method for testing integrated circuits, characterized in that, Includes the following steps: A tester tests a first scan chain operating at a first voltage level using a first test pattern. After operating the first scan chain at a second voltage level lower than the first voltage level, the first scan chain operating at the first voltage level is retested with a second test pattern to generate a failure log. as well as A processor diagnoses at least one first faulty flip-flop in the first scan chain based on the fault log and a mapping table, wherein the mapping table is associated with the first scan chain and a plurality of shift loops, wherein diagnosing the at least one first faulty flip-flop includes: Determine at least one invalid cycle among the plurality of shift cycles; and Determine the at least one first non-conforming flip-flop in the first scan chain corresponding to the at least one non-conforming cycle.

9. The method as described in claim 8, characterized in that, The step of testing the first scan chain using the first test pattern includes the following steps: Loading multiple values ​​into the first scan chain and storing the multiple values ​​in the first scan chain; The step of retesting the first scan chain includes the following steps: The clock outputs multiple stored values ​​as multiple output values ​​in the multiple shift cycles; as well as At least one unqualified result value is generated by comparing the plurality of output values ​​with the plurality of values.

10. The method as described in claim 8, characterized in that, The defective log is associated with a sequence of multiple shift cycles and multiple output values ​​corresponding to the multiple shift cycles.

11. The method as described in claim 10, characterized in that, The step of diagnosing the at least one first defective flip-flop further includes the following steps: Map the invalid log to this mapping table; and Detect at least one non-compliant result value in the mapping table to determine the at least one first non-compliant flip-flop.

12. The method as described in claim 8, characterized in that, The step of diagnosing the at least one first defective flip-flop further includes the following steps: Map the invalid log to this mapping table; and The processing unit retrieves at least one fault location corresponding to the at least one first non-conforming flip-flop from a database for performing a physical fault analysis.

13. The method as described in claim 8, characterized in that, Further steps include: A second scan chain operating at the first voltage level is tested using a third test sample; After operating the second scan chain at the second voltage, the second scan chain operating at the first voltage level is retested using a fourth test sample to update the failure log; and Diagnose at least one second defective flip-flop in the second scan chain based on the defect log and the mapping table; The first scan chain includes at least one flip-flop coupled between two adjacent flip-flops in the second scan chain.

14. The method as described in claim 13, characterized in that, The first test sample is different from the third test sample.

15. The method as described in claim 13, characterized in that, The step of diagnosing the at least one second defective flip-flop in the second scan chain includes the following steps: Determine whether an input terminal of a latching circuit used to store a value in the at least one second defective flip-flop is short-circuited.

16. A system for testing integrated circuits, characterized in that, Include: One or more processing units; and A storage unit for storing a plurality of instructions, which, when executed by at least one of the one or more processing units, perform a plurality of operations, the plurality of operations including: A result sample is read from a tester, wherein the result sample contains multiple bits of metadata; Detect at least one non-compliant result value in the result sample; Determine a non-conforming chain and at least one non-conforming shift cycle corresponding to the at least one non-conforming result value; and Determine at least one defective flip-flop associated with the defective chain and the at least one defective shift cycle.

17. The system as claimed in claim 16, characterized in that, The plurality of operations further include: Retrieve from a database at least one fault location corresponding to the at least one non-conforming flip-flop.

18. The system as claimed in claim 16, characterized in that, The plurality of operations further include: A test pattern is generated based on a scan chain pattern to the tester to operate an integrated circuit that swings between a first voltage level and a second voltage level below the first voltage level; as well as Generate a mapping table associated with the test pattern, wherein the mapping table is associated with multiple shift cycles.

19. The system as claimed in claim 16, characterized in that, The plurality of operations further include: The result pattern is mapped to multiple shift cycles and multiple chains to determine the non-compliant chain and the at least one non-compliant shift cycle.

20. The system as claimed in claim 16, characterized in that, The plurality of operations further include: The at least one defective shift loop is mapped to multiple flip-flops in the defective chain to determine the at least one defective flip-flop.

21. A method for testing integrated circuits, characterized in that, Includes the following steps: Test multiple scan chains in multiple shift loops to obtain multiple values; Determine at least one non-compliant chain among the plurality of scan chains and determine at least one non-compliant shift loop corresponding to at least one non-compliant value among the plurality of values; A mapping table is generated, which includes the plurality of shift cycles, the plurality of values, and a plurality of pins for outputting the plurality of values; The at least one defective chain and the at least one defective shift loop are mapped to the plurality of scan chains via the mapping table to identify at least one defective flip-flop; as well as Identify at least one fault location corresponding to the at least one non-conforming flip-flop.

22. The method as described in claim 21, characterized in that, The steps involved in generating this mapping table include: Multiple first test samples are obtained to determine the multiple shift cycles and the multiple scan chains.

23. The method as described in claim 21, characterized in that, The number of the plurality of pins is equal to the number of the plurality of scan chains.

24. The method as described in claim 21, characterized in that, Further steps include: Multiple first test patterns and multiple second test patterns are generated based on multiple scan chain test patterns; The plurality of first test patterns are loaded into the plurality of scan chains to store the plurality of values ​​associated with the plurality of first test patterns; as well as The multiple values ​​are output to be included in the multiple second test samples for determining the at least one non-converter.

25. The method as described in claim 21, characterized in that, The at least one non-conforming chain includes a first non-conforming chain and a second non-conforming chain. The step of determining the at least one non-conforming chain includes the following steps: A first pin is identified to determine the first non-conforming chain by identifying a first non-conforming value among the plurality of output values. as well as A second pin is identified to determine the second non-conforming chain by identifying a second non-conforming value among the plurality of output values, the second pin being different from the first pin.

26. The method as described in claim 25, characterized in that, The step of determining the at least one non-compliant shift cycle includes the following steps: Identify a first non-conforming shift cycle corresponding to the first non-conforming value and a second non-conforming shift cycle corresponding to the second non-conforming value.

27. The method as described in claim 21, characterized in that, The step of testing the multiple scan chains includes the following steps: A first scan chain of the plurality of scan chains is tested with a first test sample to operate at a first voltage level; and After operating the first scan chain at a second voltage level lower than the first voltage level, the first scan chain operating at the first voltage level is retested with a second test pattern to obtain corresponding multiple values.

28. The method as described in claim 27, characterized in that, The step of retesting the first scan chain includes the following steps: The clock outputs multiple stored values ​​as multiple output values ​​in the multiple shift cycles; as well as At least one unqualified result value is generated by comparing the plurality of output values ​​with the plurality of test values ​​of the second test pattern.

29. The method as described in claim 27, characterized in that, A second scan chain of the plurality of scan chains is adjacent to the first scan chain, and The at least one defective flip-flop in the first scan chain is coupled to the second scan chain.

30. The method as described in claim 21, characterized in that, Further steps include: A processing unit retrieves multiple positions corresponding to the plurality of scan chains from a database, the plurality of positions including the at least one fault location.

31. A method for testing integrated circuits, characterized in that, Includes the following steps: Loading multiple values ​​into a first scan chain and storing the multiple values ​​in the first scan chain at a first voltage level; The first scan chain is operated at a second voltage level, which is different from the first voltage level. At the first voltage level, the clock outputs the plurality of values ​​as the plurality of output values ​​in a plurality of shift cycles; Compare the plurality of output values ​​with the plurality of values ​​to generate an invalid log; as well as Based on the non-compliance log and a mapping table, it is determined whether a non-compliance flip-flop is in the first scan chain.

32. The method as described in claim 31, characterized in that, The second voltage level is lower than the first voltage level.

33. The method as described in claim 31, characterized in that, The mapping table is associated with the first scan chain and the plurality of shift cycles.

34. The method as described in claim 31, characterized in that, One of the second scan chains is adjacent to the first scan chain, and the defective flip-flop in the first scan chain is coupled to the second scan chain.

35. A system for testing integrated circuits, characterized in that, Include: One or more processing units; and A storage unit for storing a plurality of instructions, which, when executed by at least one of the one or more processing units, perform a plurality of operations, the plurality of operations including: A tester detects at least one non-conforming result value in a result sample; Determine at least one non-conforming shift cycle corresponding to the at least one non-conforming result value; and Based on a mapping table, at least one defective flip-flop is identified as being associated with the at least one defective shift cycle. The at least one defective flip-flop is included in one of a plurality of scan chains. The plurality of scan chains have different numbers of positive and negative converters.

36. The system as described in claim 35, characterized in that, The plurality of operations further include: Determine a nonconforming chain corresponding to the at least one nonconforming result value.

37. The system as described in claim 35, characterized in that, The plurality of operations further include: A test pattern is generated based on a scan chain pattern to the tester to operate an integrated circuit that swings between a first voltage level and a second voltage level below the first voltage level to generate the result pattern.

38. The system as described in claim 37, characterized in that, The plurality of operations further include: Generate a mapping table associated with the test sample, wherein the mapping table is associated with a plurality of shift cycles including the at least one non-conforming shift cycle.

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