Semiconductor structure and image sensor and method for forming the same

Abstract

Semiconductor structures and image sensors and methods for forming the same include photodetectors, transistors, and metal interconnects that can be formed on the front side of a semiconductor substrate. A trench is formed through a backside surface toward the front side of the semiconductor substrate by an anisotropic etching process, the anisotropic etching process providing a vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nanometers. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process on the vertical or tapered surface of the trench at a growth temperature below 500 degrees Celsius. The physically exposed side surface of the single crystalline semiconductor liner may have a second root mean square surface roughness less than 0.5 nanometers. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film that can be advantageously used to reduce dark current and white pixels.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and an image sensor and a method for forming the same, and more particularly to a semiconductor structure and an image sensor of an epitaxial semiconductor liner for enhancing the uniformity of a charged layer in a deep trench and a method for forming the same. Background Art

[0002] Semiconductor image sensors are used to sense electromagnetic radiation, such as light in the visible range, infrared radiation, and / or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital cameras or embedded cameras in mobile devices. These devices use the photogeneration of electron-hole pairs to detect radiation using a pixel array (which may include photodiodes and transistors). Backside illuminated (BSI) image sensors are image sensors configured to detect light impinging on the back side of a semiconductor substrate. CMOS circuitry for detecting and processing photogenerated signals may be formed on the front side of the semiconductor substrate. Summary of the invention

[0003] In some embodiments, a semiconductor structure includes a semiconductor substrate, a single crystal semiconductor liner, and at least one dielectric metal oxide liner. The semiconductor substrate includes a substrate semiconductor layer, the substrate semiconductor layer having a first flat surface and a second flat surface parallel to the first flat surface and containing a groove extending from the second flat surface toward the first flat surface, wherein the first single crystal semiconductor material of the substrate semiconductor layer has a surface with a first root mean square surface roughness at the sidewall of the groove, and the first root mean square surface roughness is greater than 0.5 nm. The single crystal semiconductor liner includes a second single crystal semiconductor material, the second single crystal semiconductor material contains a vertical extension portion, the vertical extension portion has a first side surface in contact with a vertical or tapered surface on a first side and has a second side surface, the second side surface has a second root mean square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner is located on the second side surface of the single crystal semiconductor liner.

[0004] In some embodiments, an image sensor includes a pixel array, a plurality of grooves, a single crystal semiconductor liner, and at least one dielectric metal oxide liner. The pixel array is located on a semiconductor substrate including a substrate semiconductor layer, wherein each pixel in the pixel array includes at least one sub-pixel, and each of the at least one sub-pixel includes a corresponding photodetector and a corresponding sensing circuit located on the front surface of the semiconductor substrate. A plurality of grooves extend from the back surface of the semiconductor substrate toward the front surface at the boundaries between adjacent pairs of sub-pixels in the sub-pixels, wherein the first single crystal semiconductor material of the substrate semiconductor layer has a vertical or tapered surface at the sidewall of the grooves in the plurality of grooves, and the vertical or tapered surface has a first root mean square surface roughness greater than 0.5 nm. The single crystal semiconductor liner includes a second single crystal semiconductor material, the second single crystal semiconductor material contains a vertical extension portion, the vertical extension portion has a first side surface in contact with the vertical or tapered surface on the first side and has a second side surface, and the second side surface has a second root mean square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner is located on the second side surface of the single crystal semiconductor liner.

[0005] In some embodiments, a method of forming a semiconductor structure includes forming a trench in a substrate semiconductor layer of a semiconductor substrate, wherein a sidewall of the trench includes a vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nm. Forming a single crystal semiconductor liner comprising a second single crystal semiconductor material by performing an epitaxial growth process on the vertical or tapered surface of the trench at a growth temperature below 500 degrees Celsius, wherein the single crystal semiconductor liner includes a vertical extension portion having a first side surface on a first side in contact with the vertical or tapered surface and having a second side surface having a second root mean square surface roughness less than 0.5 nm. Forming at least one dielectric metal oxide liner on the second side surface of the single crystal semiconductor liner. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a plan view of a first configuration of a pixel array of an image sensor according to an embodiment of the present disclosure.

[0008] Figure 1B is a plan view of a second configuration of a pixel array of an image sensor according to an embodiment of the present disclosure.

[0009] Figure 2A is a plan view of a front-side sensor component located within a sub-pixel region in an exemplary structure according to an embodiment of the present disclosure.

[0010] Figure 2B It is along Figure 2A A vertical cross-sectional view of an exemplary structure taken along vertical plane BB' is shown.

[0011] Figure 3 is a vertical cross-sectional view of an exemplary structure after metal interconnect structures are formed in an interconnect-level dielectric layer and a carrier substrate is bonded according to an embodiment of the present disclosure.

[0012] Figure 4 is a vertical cross-sectional view of an exemplary structure after thinning of a semiconductor substrate according to an embodiment of the present disclosure.

[0013] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming a deep trench on the backside of a semiconductor substrate according to an embodiment of the present disclosure.

[0014] Fig. 6A is a vertical cross-sectional view of an exemplary structure after removing a hard mask layer and a pad dielectric layer according to an embodiment of the present disclosure.

[0015] Figure 6B yes Fig. 6A Magnified view of area B in FIG.

[0016] Figure 7 is an enlarged view of a portion of a deep trench after forming a single crystal semiconductor liner according to an embodiment of the present disclosure.

[0017] Fig. 8A is a vertical cross-sectional view of an exemplary structure after forming at least one dielectric metal oxide liner and a dielectric isolation layer according to an embodiment of the present disclosure.

[0018] Figure 8B yes Fig. 8A Magnified view of area B in FIG.

[0019] Fig. 9A is a vertical cross-sectional view of an exemplary structure after forming a grid structure according to an embodiment of the present disclosure.

[0020] Fig. 9B yes Fig. 9A A plan view of the exemplary structure shown, with the hinged vertical plane A-A' corresponding to Fig. 8A The plane of the vertical section view is shown.

[0021] Fig.10is a vertical cross-sectional view of an exemplary structure after forming a planarization dielectric layer, a color filter, and a lens according to an embodiment of the present disclosure.

[0022] Fig.11 is a vertical cross-sectional view of an exemplary structure after removal of a carrier substrate according to an embodiment of the present disclosure.

[0023] Fig.12 is a flow chart of an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure.

[0024] Fig.13A is a schematic vertical cross-sectional view of a comparative exemplary test sample including a trench formed in a semiconductor substrate and two dielectric metal oxide liners formed on sidewalls of the trench.

[0025] Fig. 13B is a schematic vertical cross-sectional view of a test sample according to an embodiment of the present disclosure, the test sample including a trench formed in a semiconductor substrate, a single crystal semiconductor liner formed using a low temperature epitaxial process, and two dielectric metal oxide liners formed on sidewalls of the trench. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed in itself.

[0027] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0028] The present disclosure relates to a semiconductor device, and more particularly to a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the same.

[0029] In general, the structures and methods disclosed herein can be used to provide image sensors with low dark current and reduce the formation of white pixels in image sensors. An epitaxial process can be performed after forming deep trenches to form a single crystalline semiconductor liner, which is epitaxially aligned to the single crystalline material of the semiconductor substrate. A dielectric metal oxide liner can be used in the deep trenches, which surround each semiconductor material portion extending between the front surface and the backside surface of the semiconductor substrate. The dielectric metal oxide liner can trap negative charges to provide a depletion region around the deep trenches. The single crystalline semiconductor liner can solidify defects on the sidewalls of the deep trenches to provide a semiconductor surface with a smaller root-mean-square surface roughness and a lower surface defect density. The dielectric metal oxide liner can be formed to have a smaller defect density and a smaller thickness, which can be advantageously used to provide a more uniform negatively charged film that is more effective in providing a surface depletion region and suppressing dark current and preventing the formation of white pixels.

[0030] Specifically, photodetectors, transistors, and metal interconnect structures can be formed on the front side of a semiconductor substrate. A deep trench can be formed from the back side of the semiconductor substrate toward the front side using an anisotropic etching process. The anisotropic etching process forms a deep trench having a depth ranging from 1.5 microns to 10 microns. Significant surface damage may occur on the sidewalls of the deep trench. Forming a dielectric metal oxide liner on such a damaged sidewall typically results in significant variations in the local thickness of the dielectric metal oxide liner. In addition, a major portion of the sidewalls of the deep trenches formed by the anisotropic etching process include non-facet surfaces (i.e., surfaces that are not located in a crystal plane). Such surfaces increase the average thickness of the dielectric metal oxide liner that can be formed on the surface. A thick dielectric metal oxide liner is less effective as a charge-containing layer that can provide a negative surface charge. In addition, local variations in the thickness of the dielectric metal oxide liner can result in uneven distribution of negative charge and make the device characteristics of the photodetector unpredictable.

[0031] The epitaxial semiconductor deposition process is used to form a single crystal semiconductor liner, which covers the non-faceted surface of the sidewall of the deep trench and provides a surface made mainly of the faceted surface. In addition, surface defects on the sidewall of the deep trench can be partially or completely cured by the single crystal semiconductor liner. In addition, the surface of the single crystal semiconductor liner that is physically exposed has a surface roughness that is smaller than the sidewall of the deep trench formed by the anisotropic etching process. The dielectric metal oxide liner formed on the physically exposed surface of the single crystal semiconductor liner can have a smaller thickness and a smaller thickness variation than the dielectric metal oxide liner formed directly on the damaged sidewall of the deep trench. The dielectric metal oxide liner can be formed of a non-stoichiometric composition with excess oxygen atoms, which provide negative charges. By forming the single crystal semiconductor liner before forming the dielectric metal oxide liner, the dielectric metal oxide liner can be formed to have a smaller average thickness and a smaller thickness variation, thereby more effectively providing a more uniform and thicker depletion region around the deep trench. The dielectric metal oxide liner acts as a uniform negatively charged film, which can be advantageously used to reduce dark current and white pixels of the image sensor.

[0032] Reference Figure 1A and Figure 1B , a first configuration of an array 1000 of pixels 900 of an image sensor and a second configuration of an array 1000 of pixels 900 of an image sensor are shown in plan view, respectively. The image sensor may be a backside illuminated (BIS) image sensor device. However, it should be understood that embodiments of the present disclosure may be used in a frontside illuminated (FSI) image sensor.

[0033] To generate an image from an image sensor, each pixel 900 represents a minimum unit area. Herein, a region of the array 1000 including pixels 900 is referred to as a pixel array region. The pixels 900 in the pixel array region may be arranged in rows and columns. For example, the pixel array region may include M rows and N columns, where M and N are between 1 and 2. 16 In the range (e.g. from 2 8 To 2 14 ). The rows of pixels 900 may be numbered consecutively using integers ranging from 1 to M and the columns of pixels 900 may be numbered consecutively using integers ranging from 1 to N. Pixel Pij refers to the pixel 900 in the i-th row and the j-th column.

[0034] Each pixel 900 includes at least one photodetector that can be configured to detect radiation of a given wavelength range. Each pixel 900 may include multiple photodetectors configured to detect radiation of corresponding wavelength ranges, and the wavelength ranges may be different among the multiple photodetectors. In one embodiment, each pixel 900 may include multiple sub-pixels, each of which includes a corresponding combination of a photodetector and an electronic circuit, and the electronic circuit is configured to detect radiation irradiated into the photodetector. For example, the pixel 900 may include a sub-pixel configured to detect radiation in a red wavelength range (e.g., a range from 635nm to 700nm), a sub-pixel configured to detect radiation in a green wavelength range (e.g., a range from 520nm to 560nm), and a sub-pixel configured to detect radiation in a blue wavelength range (e.g., a range from 450nm to 490nm). Such seed pixels are respectively referred to as red sub-pixels, green sub-pixels, and blue sub-pixels.

[0035] In general, the pixel 900 generates information in the illumination radiation per unit detection area. The sub-pixel generates information about the intensity of the illumination radiation within a specific wavelength range detected within the area of ​​the unit detection area. A monochrome pixel 900 may include only a single sub-pixel. A pixel 900 configured to detect a spectral distribution of the illumination radiation includes a plurality of sub-pixels having at least two different detection wavelength ranges. The photodetector in the pixel array area may include a photodiode, a complementary metal oxide semiconductor (CMOS) image sensor, a charge coupled device (CCD) sensor, an active sensor, a passive sensor, other applicable sensors, or a combination thereof.

[0036] Reference Figure 2A and Figure 2B , Figure 2A and Figure 2B The front side sensor assembly 600 is shown in the image sensor in the region of a sub-pixel. Figure 2A The interconnect level dielectric layer 670 is omitted. The semiconductor substrate 500 includes a substrate semiconductor layer 601. The front side sensor assembly 600 includes all components of the image sensor that may be formed on the front surface 609 of the semiconductor substrate 500 or may be formed in the substrate semiconductor layer 601. Each sub-pixel includes a photodetector and a sensing circuit for the photodetector. A group of sub-pixels may be used for a pixel and the array 1000 of pixels may be as shown. Figure 1A or Figure 1B The array may be arranged as shown in FIG. 1 or in any other suitable array configuration to provide an image sensor.

[0037] Each sub-pixel may be formed on or in a substrate semiconductor layer 601 having a front surface 609 and a back surface. The substrate semiconductor layer 601 includes a semiconductor material such as silicon, germanium, a silicon-germanium alloy, a compound semiconductor material, or any other semiconductor material having a band gap that does not exceed the energy of the photons to be detected. The material within the substrate semiconductor layer 601 may be selected based on the energy range of the photons to be detected by the sub-pixels. In one embodiment, the substrate semiconductor layer 601 may include single crystal silicon. A commercial single crystal semiconductor substrate may be used for the semiconductor substrate 500. The semiconductor substrate 500 provided in this processing step may have a sufficiently high thickness that can withstand standard complementary metal oxide semiconductor (CMOS) processing steps. For example, the thickness of the semiconductor substrate 500 may be in the range of 200 microns to 1 millimeter, but smaller thicknesses and larger thicknesses may also be used.

[0038] The top portion of the substrate semiconductor layer 601 may be appropriately doped to have a first conductivity type, which may be a p-type or an n-type. For example, an epitaxial semiconductor deposition process may be performed to form a single crystal epitaxial semiconductor material layer at the upper portion of the substrate semiconductor layer so that the atomic concentration of the dopant of the first conductivity type is between 1.0×10 13 / cm 3 to 1.0×10 16 / cm 3 The thickness of the single crystal epitaxial semiconductor material layer may be in the range of 1 micron to 10 microns, but smaller atomic concentrations and larger atomic concentrations may also be used.

[0039] The first conductivity type well 607 may be formed by ion implantation around a region where a shallow trench isolation structure 620 is subsequently formed. The atomic concentration of the first conductivity type dopant in the first conductivity type well 607 may be between 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 The range of , but smaller atomic concentrations and larger atomic concentrations may also be used. The shallow trench isolation structure 620 may be formed to provide electrical isolation between various components within a sub-pixel.

[0040] The gate structure (614, 605, 615) can be formed above the front surface 609 of the semiconductor substrate 500 by depositing a layer stack including a gate dielectric layer and a gate electrode layer and patterning the layer stack. Each patterned portion of the layer stack constitutes a gate structure (614, 605, 615), and the gate structure (614, 605, 615) includes a transfer gate structure (transfer gate structure; 614, 605) and a control gate structure (control gate structure; 614, 615). The transfer gate structure (614, 605) is the gate structure of the transfer transistor 630 and includes a stack of a gate dielectric 614 and a transfer gate electrode 605. Each of the control gate structures (614, 615) includes a respective layer stack of a gate dielectric 614 and gate electrodes 615 of other transistors in the sensing circuit, which may include a reset transistor 640, a source-follower transistor 650, a select transistor 660, and other suitable transistors that may be used to amplify the signal generated by the photodetector of the sub-pixel.

[0041] At least one masked ion implantation process may be used to implant a dopant of a second conductivity type through the front surface 609 of the semiconductor substrate 500. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, or vice versa. Various doped regions having doping of the second conductivity type may be formed by the at least one masked ion implantation process. A fixed photodiode layer 602 of the second conductivity type may be formed below the front surface 609 of the semiconductor substrate 500, such that the periphery of the fixed photodiode layer 602 of the second conductivity type overlaps the edge of the transfer gate electrode 605 in a plan view. Various active regions (608, 612) having doping of the second conductivity type may be formed, the active regions (608, 612) including a floating diffusion region 608 used as a drain region of the transfer transistor 630. The fixed photodiode layer 602 of the second conductivity type accumulates charge (e.g., electrons in the case where the second conductivity type is n-type) during sensing (i.e., when the subpixel is actively detecting photons impinging on the subpixel for purposes such as capturing a frame or photograph) to serve as the source region of the transfer transistor 630. The active region 612 includes the source and drain regions of the various transistors (640, 650, 660) in the sensing circuit.

[0042] The first conductivity type fixed layer 603 may be formed by ion implantation of a first conductivity type dopant directly on top of the second conductivity type fixed photodiode layer 602. The first conductivity type fixed layer 603 may suppress depletion of an interface between the second conductivity type fixed photodiode layer 602 and the first conductivity type fixed layer 603 and electrically stabilize the second conductivity type fixed photodiode layer 602.

[0043] An interconnect level dielectric layer 670 may be formed over the front surface 609 of the semiconductor substrate 500 and metal interconnect structures 680 may be formed within each sub-pixel to connect various nodes of the transistors (630, 640, 650, 660). The interconnect level dielectric layer 670 may include a corresponding dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, porous dielectric material, or a combination thereof. Dielectric liners including various dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxycarbide, and / or dielectric metal oxides, may be optionally used in the interconnect level dielectric layer 670. The metal interconnect structures 680 may include various metal via structures 682 and various metal line structures 684. For example, the floating diffusion region 608 may be connected to the gate electrode 615 of the source follower transistor 650 through a subset of the metal interconnect structures 680. The photodetector may be implemented as a transfer transistor 630 and may be connected to a sensing circuit including additional transistors ( 640 , 650 , 660 ).

[0044] Reference Figure 3 , additional interconnect-level dielectric layers 670 and additional metal interconnect structures 680 may be formed on the front side of the semiconductor substrate 500. The front side of the assembly of the semiconductor substrate 500, the interconnect-level dielectric layer 670, and the structures formed therein may be bonded to a carrier substrate 690. The carrier substrate 690 may be temporarily attached to the assembly of the semiconductor substrate 500 and the interconnect-level dielectric layer 670 to provide for subsequent thinning of the semiconductor substrate 500 and for subsequent processing of the assembly of the thinned semiconductor substrate 500 and the interconnect-level dielectric layer 670. The carrier substrate 690 may include a semiconductor material, an insulating material, or a metal material and may have a thickness in the range of 300 microns to 1 mm, although lesser thicknesses and greater thicknesses may also be used.

[0045] Generally speaking, an array of front side sensor components 600 may be formed on a semiconductor substrate 500. The front side sensor components 600 include Figure 1A and Figure 1B1000 of the array of pixels shown in FIG. Each sub-pixel region of the front-side assembly 600 may include a corresponding photodetector including a transfer transistor and a corresponding sensing circuit located on the front surface of the semiconductor substrate 500. Each sensing circuit includes a transistor. An interconnect level dielectric layer 670 and a metal interconnect structure 680 may be formed on the front side of the semiconductor substrate 500.

[0046] The carrier substrate 690 may be bonded to the front side of the interconnect level dielectric layer 670 using any suitable bonding method. Exemplary bonding methods that may be used to bond the carrier substrate 690 to the interconnect level dielectric layer 670 include, but are not limited to, oxide-to-oxide bonding, oxide-to-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding processes, and / or combinations thereof. Other suitable bonding methods are also within the intended scope of the present disclosure. Optionally, a bonding buffer layer 689 comprising an intermediate bonding material (e.g., silicon oxide, silicon nitride, or a semiconductor material) may be used to provide bonding between the interconnect level dielectric layer 670 and the carrier substrate 690. The carrier substrate 690 may be directly bonded to the interconnect level dielectric layer 670 or may be bonded to the interconnect level dielectric layer 670 through a bonding buffer layer 689.

[0047] Reference Figure 4 , the back side of the semiconductor substrate 500 may be thinned, for example, by grinding, polishing, an isotropic etching process, and / or an anisotropic etching process. During the thinning process, the carrier substrate 690 may provide mechanical support for the semiconductor substrate 500. In one embodiment, the semiconductor substrate 500 may be thinned to have a thickness in the range of 1 micron to 12 microns (e.g., from 1.5 microns to 8 microns). In this document, the thinned semiconductor substrate 500 after the thinning process is referred to as a thinned semiconductor substrate 510 or semiconductor substrate 500. The thickness of the thinned semiconductor substrate 510 may be determined by the maximum depth of the deep trenches subsequently formed on the back side of the thinned semiconductor substrate 510. In one embodiment, the thickness of the thinned semiconductor substrate 510 may be selected so that the deep trenches subsequently formed on the back side of the semiconductor substrate 510 reach the proximal surface of the shallow trench isolation structure 620. The backside surface 709 of the thinned semiconductor substrate 510 may be polished to provide a flat horizontal surface parallel to the front surface 609 of the thinned semiconductor substrate 510. The exemplary structure may then be turned upside down for further processing.

[0048] Reference Figure 5 , an optional pad dielectric layer 711 and a hard mask layer 712 may be formed over the backside surface 709 of the semiconductor substrate 510. The optional pad dielectric layer 711, if present, may include a silicon oxide layer and may have a thickness in a range of 5 nm to 50 nm. The hard mask layer 712 includes an etch mask material that may subsequently be selectively removed relative to the pad dielectric layer 711 and / or relative to the semiconductor substrate 510. For example, the hard mask layer 712 may include silicon nitride, borosilicate glass, or a metal material. The hard mask layer 712 may have a thickness in a range of 50 nm to 800 nm, although lesser thicknesses and greater thicknesses may also be used.

[0049] A photoresist layer (not shown) may be applied over the hard mask layer 712 and the photoresist layer may be photolithographically patterned to form openings that generally replicate the pattern of the shallow trench isolation structure 620 located below the openings. A first etching process may be performed to transfer the pattern in the photoresist layer through the hard mask layer 712 and the optional pad dielectric layer 711. The unmasked portion of the semiconductor substrate 510 may be etched by performing a second anisotropic etching process that transfers the pattern of the openings in the photoresist layer and the hard mask layer 712 through the semiconductor substrate 510 to the top surface of a corresponding one of the shallow trench isolation structures 620. The depth of the deep trench 719 may be in the range of 1 micron to 10 microns (e.g., from 1.5 microns to 8 microns). During the second anisotropic etching process, the photoresist layer may be completely consumed. The deep trench 719 may be formed through the semiconductor substrate 510.

[0050] In general, the substrate semiconductor layer 601 may have a first planar surface (e.g., front surface 609) and a second planar surface (e.g., backside surface 709) parallel to the first planar surface. A deep trench 719 may be included in the substrate semiconductor layer 601. The deep trench 719 may be formed through the second planar surface (e.g., backside surface 709) and extend from the second planar surface toward the first planar surface (i.e., toward the front side of the semiconductor substrate 510). In one embodiment, a shallow trench isolation structure 620 may be located in the semiconductor substrate 510 on the front side 609 of the semiconductor substrate 510 between transistors. Each of the deep trenches 719 may extend vertically through the semiconductor substrate 510 to a corresponding one of the shallow trench isolation structures 620. The horizontal surface of the shallow trench isolation structure 620 may be physically exposed at the bottom of each deep trench 719. In one embodiment, all bottom surfaces of the deep trenches 719 may be surfaces of the shallow trench isolation structure 620.

[0051] The deep trench 719 may define the area of ​​the sub-pixel 800. Each sub-pixel 800 may be located in a corresponding sub-pixel area, and the sub-pixel area is located in the area of ​​the pixel (i.e., in the pixel area). For example, the area of ​​the pixel may include the area of ​​the first sub-pixel 801, the area of ​​the second sub-pixel 802, and the area of ​​the third sub-pixel 803. In an exemplary embodiment, the first sub-pixel 801 may be formed in an area including a photodetector configured to detect green light, the second sub-pixel 802 may be formed in an area including a photodetector configured to detect red light, and the third sub-pixel 803 may be formed in an area including a photodetector configured to detect blue light. Each sub-pixel 800 may include a volume containing a patterned columnar portion of the semiconductor substrate 510, which is surrounded by a set of continuously connected deep trenches 719 in the lateral direction. The pixel area of ​​the pixel includes all sub-pixel areas of the set of sub-pixels 800 contained in the pixel.

[0052] Reference Fig. 6A and Figure 6B , the hard mask layer 712 may be selectively removed relative to the semiconductor substrate 510, the pad dielectric layer 711, and the shallow trench isolation structure 620. In an illustrative example, if the hard mask layer 712 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the hard mask layer 712. Subsequently, the pad dielectric layer 711 may be selectively removed relative to the semiconductor substrate 510.

[0053] A plurality of deep trenches 719 may extend vertically from the backside surface 709 toward the front surface of the semiconductor substrate 510 at the boundaries between adjacent pairs of sub-pixels. Each deep trench 719 may have a depth ranging from 1.5 microns to 10 microns, but smaller depths and greater depths may also be used. Each deep trench 719 may have a sidewall including a vertical or tapered surface.

[0054] In one embodiment, the deep trench 719 may have a bowed vertical cross-sectional profile (i.e., a profile in which the width at the middle portion is greater than the width at the top portion and the bottom portion). The taper angle within the deep trench may be in the range of -10 degrees to +10 degrees. In one embodiment, the sidewall of the deep trench 719 may have a retro-tapered portion and a normal-tapered portion, the retro-tapered portion providing a trench width that increases with increasing vertical distance from the backside surface 709 of the semiconductor substrate 510, and the normal-tapered portion providing a trench width that decreases with increasing vertical distance from the backside surface 709 of the semiconductor substrate 510.

[0055] In one embodiment, the substrate semiconductor layer 601 may include a first single crystal semiconductor material. The anisotropic etching process that etches through the semiconductor material of the substrate semiconductor layer 601 may produce significant surface damage on the sidewalls of the deep trench 719. The sidewalls of the deep trench may be the physically exposed surface of the first single crystal semiconductor material and include structural damage and surface changes caused by ion damage during the anisotropic etching process of forming the deep trench 719. The surface damage may include depressions, protrusions, mini-pockets that are recessed downward toward the front surface 609 in a needle shape, local amorphization or disoriented regions, or various other types of surface damage. The root mean square roughness of the sidewalls of the deep trench 719 is greater than 0.5 nm and is typically in the range of 1 nm to 5 nm. In this article, the root mean square roughness of the physically exposed sidewalls of the substrate semiconductor layer 601 around each deep trench 719 is referred to as the first root mean square surface roughness. In other words, the first single crystalline semiconductor material of the substrate semiconductor layer 601 may have a vertical or tapered surface at the sidewall of the trench, the vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nm.

[0056] Reference Figure 7 , the physically exposed surface of the substrate semiconductor layer 601 at the periphery of the deep trench 719 and on the backside surface 709 of the semiconductor substrate 510 may be cleaned to remove surface oxide (e.g., native oxide of non-stoichiometric composition including silicon oxide). For example, the surface oxide may be removed from the physically exposed surface of the first single crystal semiconductor material of the substrate semiconductor layer 601 by a wet etching process using dilute hydrofluoric acid or a HF vapor clean process using gaseous hydrofluoric acid (HF).

[0057] A single crystal semiconductor liner 661 including a second single crystal semiconductor material can be formed by performing an epitaxial growth process on the physically exposed surface of the first single crystal semiconductor material of the substrate semiconductor layer 601, and the single crystal semiconductor liner 661 includes a vertical or tapered surface of the deep trench 719. Due to the presence of a metal interconnect structure 680 on the front side of the semiconductor substrate 510, the process temperature of the epitaxial growth process is limited to a temperature below 500 degrees Celsius. Therefore, the growth temperature of the epitaxial growth process is limited to a temperature range below 500 degrees Celsius. The growth temperature of the epitaxial growth process of the embodiment of the present disclosure may be in the range of 400 degrees Celsius to 500 degrees Celsius and may be in the range of 420 degrees Celsius to 480 degrees Celsius.

[0058] The semiconductor precursor gas that can be used in the epitaxial growth process can be a silane-based semiconductor precursor gas (e.g., silane or disilane). A carrier gas (e.g., hydrogen, nitrogen, or argon) can be used during the epitaxial growth process. During the epitaxial growth process, the partial pressure of the silane-based semiconductor precursor gas can be in the range of 200 mTorr to 10 Torr. The total pressure in the processing chamber performing the epitaxial growth process can be in the range of 5 Torr to 300 Torr.

[0059] Generally speaking, for a silane-based silicon deposition process, the deposition rate decreases by 50% or more for every approximately 25 degrees Celsius decrease in deposition temperature. Thus, an epitaxial growth process performed at a deposition temperature below 500 degrees Celsius provides a low deposition rate (e.g., a deposition rate of less than 100 nm per hour), which is impractical for the deposition of thick semiconductor films. According to an embodiment, the thickness of the single crystalline semiconductor liner 661 may be less than 20 nm (e.g., from 1.5 nm to 10 nm), so that the deposition of the single crystalline semiconductor liner 661 may be completed within a reasonable processing time of a semiconductor deposition tool (e.g., less than 3 hours and / or less than 1 hour). The silane-based silicon deposition process has been successfully tested to have a growth rate of approximately 10 nm per hour at 450 degrees Celsius.

[0060] The second single crystal semiconductor material may be epitaxially aligned to the first single crystal semiconductor material. In one embodiment, the single crystal semiconductor liner 661 contains a vertical extension portion having a first side surface in contact with a vertical or tapered surface of the first single crystal semiconductor material of the substrate semiconductor layer 601 on a first side. As described above, each vertical or tapered surface of the first single crystal semiconductor material of the substrate semiconductor layer 601 around the deep trench 719 has a first root mean square surface roughness greater than 0.5 nm, and the first root mean square surface roughness is generally in the range of 1 nm to 5 nm. The vertical extension portion of the single crystal semiconductor liner 661 has a second side surface (which is a surface that is physically exposed) having a root mean square surface roughness less than 0.5 nm, which is referred to herein as the second root mean square surface roughness. In one embodiment, the single crystal semiconductor liner 661 has an average thickness in the range of 1.5 nm to 10 nm, and the first root mean square surface roughness is at least three times the second root mean square surface roughness. In other words, the second root mean square surface roughness may be less than one third of the first root mean square surface roughness.

[0061] When the formation of a faceted surface is energetically superior to that of an irregular surface, the single crystal semiconductor liner 661 generally forms such a faceted surface. In general, an irregular surface with defects or large surface height variations is not energetically superior to a faceted crystalline surface (i.e., a surface located within a crystallographic plane having a corresponding Miller index). In one embodiment, more than 50% of the entire surface area of ​​the vertical or conical surface of each deep trench 719 includes a surface segment of the faceted surface that does not contain the first single crystal semiconductor material. In this case, the single crystal semiconductor liner 661 can form a sufficient number of crystallographic planes as growth planes so that more than 50% of the entire surface area of ​​the second side surface of the second single crystal semiconductor material of the single crystal semiconductor liner 661 includes a surface segment of the faceted surface (i.e., a crystallographic surface having a corresponding Miller index and contained within a Euclidean two-dimensional plane with a resolution of atomic thickness) of the second single crystal semiconductor material.

[0062] In one embodiment, by adjusting the dopant concentration in the single crystal semiconductor liner 661, the width of the depletion region subsequently formed in the single crystal semiconductor liner 661 and in the adjacent portion of the substrate semiconductor layer 601 can be advantageously increased. In one embodiment, the first single crystal semiconductor material of the substrate semiconductor layer 601 and the second single crystal semiconductor material of the single crystal semiconductor liner 661 have p-type doping, and the second single crystal semiconductor material has a lower atomic concentration of the p-type dopant than the portion of the first single crystal semiconductor material in contact with the second single crystal semiconductor material. For example, the portion of the first single crystal semiconductor material in contact with the second single crystal semiconductor material can be between 1.0×10 13 / cm 3 to 1.0×10 15 / cm 3 The second single crystal semiconductor material may contain a p-type dopant in an atomic concentration range of 1.0×10 12 / cm 3 to 1.0×10 14 / cm 3 The atomic concentration in the range of includes p-type dopants.

[0063] The surface roughness of the single crystal semiconductor liner 661 may be smaller than the surface roughness of the sidewall of the substrate semiconductor layer 601 around the deep trench 719. In this way, the lateral thickness of the single crystal semiconductor liner 661 may have a range equivalent to the surface height variation of the sidewall of the substrate semiconductor layer 601 around the deep trench 719. The difference between the maximum thickness t_max and the minimum thickness t_min of the single crystal semiconductor liner 661 may be in the range of 1.5 nm to 6 nm and may be in the range of 40% to 100% of the average thickness of the single crystal semiconductor liner 661.

[0064] Reference Fig. 8A and Figure 8B, at least one dielectric metal oxide liner 721 may be formed on the second side surface of the single crystal semiconductor liner 661. In one embodiment, the at least one dielectric metal oxide liner 721 includes a dielectric metal oxide material that can trap negative charges in the at least one dielectric metal oxide liner 721. For example, at least one layer within the at least one dielectric metal oxide liner 721 includes a non-stoichiometric oxygen-rich dielectric metal oxide that traps negative charges in the at least one layer. The at least one dielectric metal oxide liner 721 may include a single layer formed of a negative charge trapping dielectric metal oxide material or a plurality of layers formed of different negative charge trapping dielectric metal oxide materials. In general, a uniform film composition and a uniform film thickness of each layer within the at least one dielectric metal oxide liner 721 promote uniform distribution of negative charges. However, surface defects or surface roughness may result in non-uniform distribution of negative charges in the at least one dielectric metal oxide liner 721. Therefore, reducing the surface roughness by using the single crystalline semiconductor liner 661 promotes uniformity of the at least one dielectric metal oxide liner 721 and uniformity of negative charges trapped in the at least one dielectric metal oxide liner 721 .

[0065] In one embodiment, the at least one dielectric metal oxide liner 721 includes a layer stack of a first dielectric metal oxide liner 721A and a second dielectric metal oxide liner 721B. The first dielectric metal oxide liner 721A may be deposited first, and the first dielectric metal oxide liner 721A is referred to herein as the outer dielectric metal oxide liner. Later, the second dielectric metal oxide liner 721B may be deposited on the sidewalls of the first dielectric metal oxide liner 721A, and the second dielectric metal oxide liner 721B is referred to herein as the inner dielectric metal oxide liner.

[0066] In one embodiment, the first dielectric metal oxide liner 721A may include an aluminum oxide layer contacting the single crystal semiconductor liner 661 and having a thickness in a range of 0.8 nm to 1.6 nm and having a root mean square thickness variation of less than 0.1 nm. Since the surface roughness of the single crystal semiconductor liner 661 is reduced compared to the surface roughness of the sidewall of the substrate semiconductor layer 601 formed around the deep trench 719 by the anisotropic etching process, the interface silicon oxide layer formed between the aluminum oxide layer and the single crystal semiconductor liner 661 can be significantly reduced.

[0067] In one embodiment, the second dielectric metal oxide liner 721B (i.e., dielectric metal oxide liner) includes a dielectric metal oxide material having a dielectric constant greater than 7.9 and having a material composition different from that of aluminum oxide (e.g., hafnium oxide). The second dielectric metal oxide liner 721B may contact the first dielectric metal oxide liner 721A (e.g., aluminum oxide layer).

[0068] In general, each layer within the at least one dielectric metal oxide liner 721 may include a dielectric metal oxide material having a dielectric constant greater than 7.9 (i.e., a "high-k" dielectric material). Exemplary dielectric metal oxide materials that can be used for the at least one dielectric metal oxide liner 721 include hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, titanium oxide, lanthanum oxide, barium oxide, or a combination thereof. Other suitable materials may be used within the intended scope of the present disclosure. Each layer within the at least one dielectric metal oxide liner 721 may be deposited using a chemical vapor deposition process or atomic layer deposition (ALD). The thickness of the at least one dielectric metal oxide liner 721 may be in the range of 4 nm to 12 nm, although lesser thicknesses and greater thicknesses may also be used. In one embodiment, the at least one dielectric metal oxide liner 721 includes a first dielectric metal oxide liner 721A having a thickness in the range of 3 nm to 6 nm and a second dielectric metal oxide liner 721B having a thickness in the range of 3 nm to 6 nm.

[0069] The at least one dielectric metal oxide liner 721 may be formed to provide negative charge trapping. For example, the at least one dielectric metal oxide liner 721 may be deposited using a non-stoichiometric oxygen-rich composition or the at least one dielectric metal oxide liner 721 may be surface treated, for example, using a plasma, to have a non-stoichiometric oxygen-rich surface composition. In this case, the at least one dielectric metal oxide liner 721 may include an oxygen-rich dielectric metal oxide material having negatively charged interstitial oxygen atoms and / or dangling or broken metal oxide bonds, thereby providing an accumulation of negative charges within the at least one dielectric metal oxide liner 721. In an exemplary embodiment, the areal density of the negative charges accumulated within the at least one dielectric metal oxide liner 721 may be between 5.0×10 9 electrons to 1.0×10 per square centimeter 14 electrons per square centimeter (e.g., from 1.0×10 10 electrons per square centimeter to 2.0×10 13 electrons). The dielectric metal oxide material used in the at least one dielectric metal oxide liner 721 can accumulate more negative charges than other dielectric materials (e.g., silicon nitride or silicon oxide). The negative charges in the at least one dielectric metal oxide liner 721 increase the hole accumulation in the interface portion of the first conductivity type well 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510. A depletion region can be formed in the first conductivity type well 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510 near the at least one dielectric metal oxide liner 721. The depletion region reduces the dark current and / or white pixels of the image sensor.

[0070] In some embodiments, minimizing the average thickness of the first dielectric metal oxide liner 721A can be advantageous for achieving the purpose of providing a uniform negative charge in the at least one dielectric metal oxide liner 721 without increasing the surface roughness of the first dielectric metal oxide liner 721A. In such a case, using a single crystalline semiconductor liner 661 provides such a reduction in the thickness of the first dielectric metal oxide liner 721A (e.g., an aluminum oxide layer).

[0071] In one embodiment, the substrate semiconductor layer 601 has a p-type doping, and each photodetector includes an n-doped fixed photodiode layer as a fixed photodiode layer 602 of the second conductivity type. The at least one dielectric metal oxide liner 721 may include at least one oxygen-rich dielectric metal oxide material and / or may consist essentially of at least one oxygen-rich dielectric metal oxide material and have a net negative charge. In one embodiment, the net negative charge may have a value ranging from 5.0×10 9 electrons per square centimeter to 1.0×10 14 The surface density of electrons.

[0072] The dielectric isolation layer 722 may be formed by conformally depositing a dielectric material on the at least one dielectric metal oxide liner 721 in the remaining volume of the deep trench 719. The dielectric isolation layer 722 includes a dielectric material (e.g., silicon oxide). The silicon oxide may include undoped silicate glass, doped silicate glass (e.g., borosilicate glass), or a combination thereof. The combination of the dielectric metal oxide liner 721 and the dielectric isolation layer 722 may fill the deep trench 719 (with or without a seam and / or an encapsulated cavity). Herein, the vertically extending portion of the combination of the dielectric metal oxide liner 721 and the dielectric isolation layer 722 that fills the deep trench 719 is referred to as a deep trench isolation structure 720. The horizontally extending portions of the dielectric metal oxide liner 721 and the dielectric isolation layer 722 may overlie the backside surface of the semiconductor substrate 510. In the case where the dielectric isolation layer 722 includes silicon oxide, the silicon oxide material portion (i.e., the vertically extending portion of the dielectric isolation layer 722) may be located within each deep trench 719 and may contact the surface of the inner dielectric metal oxide liner (i.e., the second dielectric metal oxide liner 721B).

[0073] Reference Fig. 9A and Fig. 9B , a grid structure 740 may be formed on the horizontally extending portion of the dielectric isolation layer 722. For example, a layer stack including a dielectric grid material layer and a metal reflective material layer may be sequentially formed on the horizontally extending portion of the dielectric isolation layer 722. The dielectric grid material layer may include a dielectric material, such as silicon oxide, a porous dielectric material, polyimide, or another dielectric material. The thickness of the dielectric grid material layer may be in the range of 50nm to 500nm, but smaller thicknesses and larger thicknesses may also be used. The metal reflective material layer may include a metal material that can provide high reflectivity. For example, the metal reflective material layer may include silver, aluminum, copper, gold, or any other highly reflective metal material. The thickness of the metal reflective material layer may be in the range of 50nm to 500nm, but smaller thicknesses and larger thicknesses may also be used.

[0074] A photoresist layer (not shown) may be coated over the metal reflective material layer and may be photolithographically patterned to form an opening in the region of the second conductivity type fixed photodiode layer 602 (i.e., in the region of the photodetector including the corresponding pn junction between the second conductivity type fixed photodiode layer 602 and the first conductivity type well 607). The region of the transistors of the sensing circuit (e.g., the reset transistor 640, the source follower transistor 650, and the select transistor 660) may or may not be covered by the photoresist layer.

[0075] Portions of the dielectric grid material layer and the metal reflective material layer that are not masked by the patterned portion of the photoresist layer may be etched to form openings through the dielectric grid material layer and the metal reflective material layer. The remaining portion of the dielectric grid material layer forms a dielectric grid structure 742, and the remaining portion of the metal reflective material layer forms a metal grid structure 744. The stack of the dielectric grid structure 742 and the metal grid structure 744 constitutes a grid structure 740.

[0076] The grid structure 740 may overlie the periphery of the fixed photodiode layer 602 of the second conductivity type and define a light collection area for each photodetector located within the corresponding sub-pixel 800. The pixel 900 may include a group of sub-pixels configured to detect light of different wavelengths. Each pixel 900 may be located within a corresponding pixel region including a group of sub-pixels 800. For example, the pixel 900 may include at least one instance of a first sub-pixel 801, at least one instance of a second sub-pixel 802, and at least one instance of a third sub-pixel 803. In the example shown, the pixel may include a first sub-pixel 801 (e.g., a green sub-pixel) located in a first sub-pixel region, two second sub-pixels 802 (e.g., two red sub-pixels) located in two second sub-pixel regions, and a third sub-pixel 803 (e.g., a blue sub-pixel) located in a third sub-pixel region. In general, the pixel 900 may include various combinations of at least two types of sub-pixels 800 configured to detect light of different wavelength ranges. Alternatively, the image sensor may be a monochrome image sensor including a single type of sub-pixel 800. In this case, each pixel 900 may include only a single sub-pixel 800 .

[0077] The grid structure 740 may divide each sub-pixel 800 into a detector region and a sensing circuit region. For example, the first sub-pixel 801 may include a first detector region 801D overlying the second conductivity type fixed photodiode layer 602 of the first sub-pixel 801 and a first sensing circuit region 801S overlying the sensing circuit (640, 650, 660) of the first sub-pixel 801. The second sub-pixel 802 may include a second detector region 802D overlying the second conductivity type fixed photodiode layer 602 of the second sub-pixel 802 and a second sensing circuit region 802S overlying the sensing circuit (640, 650, 660) of the second sub-pixel 802. The third sub-pixel 803 may include a third detector region 803D overlying the second conductivity type fixed photodiode layer 602 of the third sub-pixel 803 and a third sensing circuit region 803S overlying the sensing circuit (640, 650, 660) of the third sub-pixel 803. In general, all sub-pixels 800 of the set of sub-pixels 800 within a pixel 900 may benefit from any pattern arrangement of the pixel 900 that periodically repeats within the array 1000 of pixels 900 .

[0078] Reference Fig.10 , a planarization dielectric layer 770 having a planar top surface may be formed over the grid structure. The planarization dielectric layer 770 may be formed by depositing a self-planarizing dielectric material (e.g., flowable oxide (FOX)). Alternatively, a transparent dielectric material may be deposited and planarized, for example, by chemical mechanical planarization, to provide the planarization dielectric layer 770.

[0079] Various color filter materials may be coated over the planarization dielectric layer 770 and may be patterned to form various color filters 780. The color filters 780 may include a first type color filter 781 formed in the region of the first sub-pixel 801, a second type color filter 782 formed in the region of the second sub-pixel 802, and a third type color filter 783 formed in the region of the third sub-pixel 803. The composition of each color filter material may be selected so that light within a target wavelength range passes through the color filter material and light outside the target wavelength range is absorbed by the color filter material.

[0080] An optical lens 790 may be formed over the color filter 780 by coating an optically transparent material over the color filter 780 and by patterning the optically transparent material into a material portion having a convex surface, the optical lens 790 being centrally located within the grid structure 740 over a corresponding one of the underlying openings.

[0081] In general, the grid structure 740 may overlie the backside surface 709 of the semiconductor substrate 510 and may have an array of openings within the region of a corresponding one of the sub-pixels, i.e., within the corresponding sub-pixel region 800. An array of color filters 780 may overlie the grid structure 740 and an array of lenses 790 may overlie the array of color filters 780.

[0082] Reference Fig.11 , the carrier substrate 690 and the bonding buffer layer 689 (if present) may be detached from the interconnect level dielectric layer 670. Before or after the carrier substrate 690 is detached from the semiconductor substrate 510, the semiconductor substrate 510 and the device structures on the semiconductor substrate 510 may be singulated into discrete image sensors.

[0083] Reference Fig.12 and the aforementioned figures of the present disclosure, a general method of forming a semiconductor structure is provided according to an embodiment of the present disclosure. Referring to step 1210, a front side sensor component may be formed on a front side surface of a substrate semiconductor layer 601 of a semiconductor substrate 510. Referring to step 1220, a trench 719 may be formed in the substrate semiconductor layer 601 of the semiconductor substrate 510. The sidewall of each trench 719 includes a vertical or tapered surface, and the vertical or tapered surface has a first root mean square surface roughness greater than 0.5 nm. Referring to step 1230, a single crystal semiconductor liner 661 including a second single crystal semiconductor material may be formed by performing an epitaxial growth process on the vertical or tapered surface of the trench 719 at a growth temperature lower than 500 degrees Celsius. The single crystal semiconductor liner 661 contains a vertical extension portion, the vertical extension portion having a first side surface in contact with the vertical or tapered surface on a first side and having a second side surface, the second side surface having a second root mean square surface roughness less than 0.5 nm. Referring to step 1240, at least one dielectric metal oxide liner 721 and a dielectric isolation layer 722 may be formed on the second side surface of the single crystalline semiconductor liner 661 in each of the trenches 719. The at least one dielectric metal oxide liner 721 may have a uniform thickness and may have a non-stoichiometric oxygen-rich composition that traps negative charges in the at least one dielectric metal oxide liner 721. The single crystalline semiconductor liner 661 may enhance the uniformity of negative charges in the at least one dielectric metal oxide liner 721 by reducing composition variation and thickness variation in the at least one dielectric metal oxide liner 721. Referring to step 1250, a planarization dielectric layer 770, a color filter 780, and a lens 790 may be formed over the filled trenches 719.

[0084] Reference Fig.13A, a schematic vertical cross-sectional view of a comparative exemplary test sample shows a deep trench formed in a semiconductor substrate. Due to reactive ion etching damage, the interface between the substrate semiconductor layer 601 and the two dielectric metal oxide liners (721A, 721B) shows a root mean square surface roughness greater than 1 nm. A chromium layer 910 and a silicon oxide layer 920 are subsequently deposited to Fig.13A A comparison between the various layers is provided in the schematic vertical cross-sectional views shown.

[0085] Reference Fig. 13B , Fig. 13B A schematic vertical cross-sectional view of a test sample according to an embodiment of the present disclosure is shown. A deep trench 719 is formed in a semiconductor substrate including a substrate semiconductor layer 601. As described above, a single crystal semiconductor liner 661 is formed using a low temperature epitaxial process. Subsequently, two dielectric metal oxide liners (721A, 721B) are formed on the sidewalls of the deep trench. Subsequently, a dielectric isolation layer 722 containing silicon oxide is deposited on the two dielectric metal oxide liners (721A, 721B). The two dielectric metal oxide liners (721A, 721B) show a flat interface with the single crystal semiconductor liner 661, and the single crystal semiconductor liner 661 has a root mean square surface roughness of less than 0.5 nm (for example, less than 0.3 nm). In addition, Fig.13A Compared with the side wall surface of the substrate semiconductor layer 601, Fig. 13B The sidewall surface of the single crystal semiconductor liner 661 in the embodiment shows much fewer defects and surface morphology features. In addition, Fig. 13B The surface of the single crystal semiconductor liner 661 in the single crystal semiconductor liner 661 is along a straight line along the crystal plane of the single crystal material of the single crystal semiconductor liner 661. Fig. 13B The surface quality of the side wall of the single crystal semiconductor liner 661 is better than Fig.13A The surface quality of the side wall of the substrate semiconductor layer 601 is therefore related to Fig.13A Compared with the first dielectric metal oxide liner 721A, Fig. 13B The first dielectric metal oxide liner 721A in the embodiment of the present invention shows a more uniform film thickness distribution and significantly reduced surface roughness. Compared with the comparative exemplary image sensor not including the single crystal semiconductor liner 661 of the present invention, the image sensor including Fig. 13B The image sensor with the structure shown has excellent dark current and white pixel performance.

[0086] With reference to all the drawings and according to various embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a semiconductor substrate 510, the semiconductor substrate 510 comprising a substrate semiconductor layer 601, the substrate semiconductor layer 601 having a first flat surface (e.g., a front surface 609) and a second flat surface (e.g., a backside surface 709) parallel to the first flat surface and containing a trench 719 extending from the second flat surface toward the first flat surface, wherein the first single crystal semiconductor material of the substrate semiconductor layer 601 has a vertical or tapered surface at the sidewall of the trench, the vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nm. The semiconductor structure comprises a single crystal semiconductor liner 661, the single crystal semiconductor liner 661 comprises a second single crystal semiconductor material, the second single crystal semiconductor material having a vertical extension portion, the vertical extension portion having a first side surface in contact with the vertical or tapered surface on a first side and having a second side surface, the second side surface having a second root mean square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner 721 may be located on the second side surface of the single crystal semiconductor liner 661.

[0087] In some embodiments, a surface segment of greater than 50% of the total surface area of ​​the vertical or conical surface comprises a faceted surface that does not contain the first single crystalline semiconductor material, and a surface segment of greater than 50% of the total surface area of ​​the second side surface of the second single crystalline semiconductor material comprises a faceted surface that is the second single crystalline semiconductor material. In some embodiments, the at least one dielectric metal oxide liner comprises an aluminum oxide layer, the aluminum oxide layer contacts the single crystalline semiconductor liner and has a thickness in the range of 0.8 nm to 1.6 nm and has a root mean square thickness variation of less than 0.1 nm. In some embodiments, the at least one dielectric metal oxide liner comprises at least one oxygen-rich dielectric metal oxide material and has a net negative charge, and a silicon oxide material is partially located in the trench and contacts the surface of the at least one dielectric metal oxide liner. In some embodiments, the single crystalline semiconductor liner has an average thickness in the range of 1.5 nm to 10 nm, and the first root mean square surface roughness is at least three times the second root mean square surface roughness.

[0088] According to another aspect of the present disclosure, an image sensor is provided, the image sensor comprising: an array 1000 of pixels (900) located on a semiconductor substrate 510 including a substrate semiconductor layer (601), wherein each pixel 900 in the array 1000 of pixels comprises at least one sub-pixel 800, each sub-pixel 800 comprises a corresponding photodetector 630 and a corresponding sensing circuit (640, 650, 660) located on a front surface of the semiconductor substrate 510; a plurality of grooves 719 extending from a back surface 709 of the semiconductor substrate 510 toward a front surface 609 at boundaries between adjacent pairs of sub-pixels in the sub-pixels, wherein the plurality of grooves 719 extend from a back surface 709 of the semiconductor substrate 510 toward a front surface 609 of the semiconductor substrate 510. The first single crystal semiconductor material of the middle substrate semiconductor layer 601 has a vertical or conical surface at the side wall of the groove in the plurality of grooves, and the vertical or conical surface has a first root mean square surface roughness greater than 0.5 nm; the single crystal semiconductor liner 661 comprises a second single crystal semiconductor material, and the second single crystal semiconductor material contains a vertical extension portion, and the vertical extension portion has a first side surface on the first side that contacts the vertical or conical surface and has a second side surface, and the second side surface has a second root mean square surface roughness less than 0.5 nm; and at least one dielectric metal oxide liner 721, which is located on the second side surface of the single crystal semiconductor liner 661.

[0089] In some embodiments, the substrate semiconductor layer has a p-type doping, each of the photodetectors includes an n-doped fixed photodiode layer, and the at least one dielectric metal oxide liner layer includes at least one oxygen-rich dielectric metal oxide material and has a net negative charge. In some embodiments, the net negative charge has a value ranging from 5.0×10 9 electrons to 1.0×10 per square centimeter 14In some embodiments, the second single crystal semiconductor material is epitaxially aligned to the first single crystal semiconductor material, the first single crystal semiconductor material and the second single crystal semiconductor material have p-type doping, and the second single crystal semiconductor material has a lower p-type dopant atomic concentration than a portion of the first single crystal semiconductor material in contact with the second single crystal semiconductor material. In some embodiments, the at least one dielectric metal oxide liner includes an aluminum oxide layer, the aluminum oxide layer contacts the single crystal semiconductor liner and has a thickness in the range of 0.8 nm to 1.6 nm and has a root mean square thickness variation of less than 0.1 nm, the at least one dielectric metal oxide liner includes an inner dielectric metal oxide liner, the inner dielectric metal oxide liner includes a dielectric metal oxide material with a dielectric constant greater than 7.9, has a material composition different from aluminum oxide and contacts the aluminum oxide layer, and a silicon oxide material is partially located in the trench and contacts the surface of the inner dielectric metal oxide liner. In some embodiments, the single crystal semiconductor liner has an average thickness in the range of 1.5 nm to 10 nm, and the first root mean square surface roughness is at least three times the second root mean square surface roughness. In some embodiments, more than 50% of the surface segment of the entire surface area of ​​the vertical or conical surface includes a faceted surface that does not contain the first single crystal semiconductor material, and more than 50% of the surface segment of the entire surface area of ​​the second side surface of the second single crystal semiconductor material includes a faceted surface that is the second single crystal semiconductor material. In some embodiments, the image sensor also includes a grid structure, a color filter array, and a lens array, the grid structure overlying the back side surface of the semiconductor substrate and having an opening array in the area of ​​a corresponding one of the sub-pixels, the color filter array overlying the grid structure, and the lens array overlying the color filter array.

[0090] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, wherein the semiconductor structure may be formed in the following manner: a trench 719 is formed in a substrate semiconductor layer 601 of a semiconductor substrate 510, wherein a sidewall of the trench 719 includes a vertical or conical surface having a first root mean square surface roughness greater than 0.5 nm. A single crystal semiconductor liner 661 including a second single crystal semiconductor material may be formed by performing an epitaxial growth process on the vertical or conical surface of the trench 719 at a growth temperature lower than 500 degrees Celsius, wherein the single crystal semiconductor liner contains a vertical extension portion having a first side surface in contact with the vertical or conical surface on a first side and having a second side surface having a second root mean square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner 721 may be formed on the second side surface of the single crystal semiconductor liner 661.

[0091] In some embodiments, the epitaxial growth process uses a silicon-containing precursor gas selected from silane and disilane, the single crystal semiconductor liner has an average thickness ranging from 1.5 nm to 10 nm, and the first root mean square surface roughness is at least three times the second root mean square surface roughness. In some embodiments, the method includes forming a transistor, an interconnection level dielectric layer, and a metal interconnection structure on the front side of the semiconductor substrate, and the trench is formed through the back side surface of the semiconductor substrate toward the front side of the semiconductor substrate. In some embodiments, the method also includes bonding a carrier substrate to the interconnection level dielectric layer, thinning the semiconductor substrate after bonding the carrier substrate, and forming the trench after forming the metal interconnection structure. In some embodiments, the method also includes forming a photodetector and a sensing circuit for the photodetector on the front side of the semiconductor substrate, forming a grid structure overlying the back side surface of the semiconductor substrate, forming a color filter array on the grid structure, and forming a lens array on the color filter array. In some embodiments, the method further comprises forming a shallow trench isolation structure in the semiconductor substrate on the front side directly between the transistors, wherein the trench comprises a deep trench extending through the semiconductor substrate into one of the shallow trench isolation structures and having a depth in the range of 1.5 microns to 10 microns, depositing a dielectric isolation layer in the remaining volume of the deep trench on the at least one dielectric metal oxide liner, wherein the at least one dielectric metal oxide liner comprises at least one oxygen-rich dielectric metal oxide material and has a net negative charge, and the at least one dielectric metal oxide liner and the portion of the dielectric isolation layer located in the deep trench constitute the dielectric isolation structure. In some embodiments, a surface segment of greater than 50% of the entire surface area of ​​the vertical or tapered surface comprises a faceted surface that does not contain the first single crystalline semiconductor material, and a surface segment of greater than 50% of the entire surface area of ​​the second side surface of the second single crystalline semiconductor material comprises a faceted surface that is the second single crystalline semiconductor material.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

[0093] [Explanation of Symbols]

[0094] 500: Semiconductor substrate

[0095] 510: Thinned semiconductor substrate / semiconductor substrate

[0096] 600: Front sensor assembly / front assembly

[0097] 601: Substrate semiconductor layer

[0098] 602: Fixed photodiode layer

[0099] 603: Fixed layer

[0100] 605: Gate structure / transfer gate structure / transfer gate electrode / gate electrode

[0101] 607: Trap

[0102] 608: Active area / floating diffusion area

[0103] 609: Front surface / front side

[0104] 612: Active area

[0105] 614: Gate structure / transfer gate structure / control gate structure / gate dielectric

[0106] 615: Gate structure / control gate structure / gate electrode

[0107] 620: Shallow Trench Isolation Structure

[0108] 630: Transfer transistor / transistor

[0109] 640: Reset transistor / transistor / sensing circuit

[0110] 650: Source follower transistor / transistor / sensing circuit

[0111] 660: Select transistor / transistor / sensing circuit

[0112] 661: Single crystal semiconductor liner

[0113] 670: Interconnect level dielectric layer

[0114] 680: Metal interconnect structure

[0115] 682: Metal Via Structure

[0116] 684: Metal Wire Structure

[0117] 689: Combined buffer layer

[0118] 690: Carrier substrate

[0119] 709: Dorsal surface

[0120] 711: Pad dielectric layer

[0121] 712: Hard mask layer

[0122] 719: Deep Groove / Groove

[0123] 720: Deep Trench Isolation Structure

[0124] 721: Dielectric Metal Oxide Liner

[0125] 721A: First dielectric metal oxide liner / dielectric metal oxide liner

[0126] 721B: Second dielectric metal oxide liner / dielectric metal oxide liner

[0127] 722: Dielectric isolation layer

[0128] 740: Grid structure

[0129] 742: Dielectric Grid Structure

[0130] 744: Metal Grid Structure

[0131] 770: Planarizing dielectric layer

[0132] 780: Color filter

[0133] 781: Type 1 color filter

[0134] 782: Second type of color filter

[0135] 783: The third type of filter

[0136] 790: Optical lens

[0137] 800: Sub-pixel / sub-pixel area

[0138] 801: First sub-pixel

[0139] 801D: First detector area

[0140] 801S: First sensing circuit area

[0141] 802: Second sub-pixel

[0142] 802D: Second detector area

[0143] 802S: Second sensing circuit area

[0144] 803: The third sub-pixel

[0145] 803D: Third detector area

[0146] 803S: The third sensing circuit area

[0147] 900, Pij: pixels

[0148] 910: Chrome layer

[0149] 920: Silicon oxide layer

[0150] 1000: Array

[0151] 1210, 1220, 1230, 1240, 1250: Steps

[0152] B: Area

[0153] A-A', B-B': vertical plane

[0154] t_max: maximum thickness

[0155] t_min: minimum thickness

Claims

1. A semiconductor structure comprising: A semiconductor substrate, comprising a substrate semiconductor layer, the substrate semiconductor layer having a first flat surface and a second flat surface parallel to the first flat surface and containing a trench extending from the second flat surface toward the first flat surface, wherein a first single crystal semiconductor material of the substrate semiconductor layer has a vertical or tapered surface at a sidewall of the trench, the vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nanometers; a single crystal semiconductor liner comprising a second single crystal semiconductor material, the second single crystal semiconductor material having a vertical extension portion having a first side surface in contact with the vertical or tapered surface on a first side and having a second side surface having a second root mean square surface roughness of less than 0.5 nanometers; and At least one dielectric metal oxide liner is located on the second side surface of the single crystal semiconductor liner.

2. The semiconductor structure according to claim 1, wherein: a surface segment of greater than 50% of the total surface area of ​​the vertical or tapered surface comprising a faceted surface that is free of the first single crystalline semiconductor material; as well as A surface segment of more than 50% of the entire surface area of ​​the second side surface of the second single-crystalline semiconductor material comprises a faceted surface as the second single-crystalline semiconductor material.

3. The semiconductor structure of claim 1 , wherein the at least one dielectric metal oxide liner comprises an aluminum oxide layer contacting the single crystalline semiconductor liner and having a thickness ranging from 0.8 nm to 1.6 nm and having a root mean square thickness variation of less than 0.1 nm.

4. The semiconductor structure of claim 1, wherein: The at least one dielectric metal oxide liner comprises at least one oxygen-rich dielectric metal oxide material and has a net negative charge; and The silicon oxide material is partially located in the trench and contacts the surface of the at least one dielectric metal oxide liner.

5. The semiconductor structure of claim 1, wherein: The single crystal semiconductor liner has an average thickness ranging from 1.5 nanometers to 10 nanometers; and The first root mean square surface roughness is at least three times the second root mean square surface roughness.

6. An image sensor, comprising: A pixel array located on a semiconductor substrate including a substrate semiconductor layer, wherein each pixel in the pixel array includes at least one sub-pixel, and each of the at least one sub-pixel includes a corresponding photodetector and a corresponding sensing circuit located on a front surface of the semiconductor substrate; a plurality of grooves extending from the backside surface of the semiconductor substrate toward the front surface at boundaries between adjacent pairs of sub-pixels in the sub-pixels, wherein the first single-crystalline semiconductor material of the substrate semiconductor layer has a vertical or tapered surface at a sidewall of a groove in the plurality of grooves, the vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nanometers; a single crystal semiconductor liner comprising a second single crystal semiconductor material, the second single crystal semiconductor material having a vertical extension portion having a first side surface in contact with the vertical or tapered surface on a first side and having a second side surface having a second root mean square surface roughness of less than 0.5 nanometers; and At least one dielectric metal oxide liner is located on the second side surface of the single crystal semiconductor liner.

7. The image sensor according to claim 6, wherein: The substrate semiconductor layer has p-type doping; Each of the photodetectors includes an n-doped fixed photodiode layer; and The at least one dielectric metal oxide liner includes at least one oxygen-rich dielectric metal oxide material and has a net negative charge.

8. The image sensor according to claim 7, wherein the net negative charge has a value from 5.0×10 9 electrons per square centimeter to 1.0×10 14 The surface density of electrons.

9. The image sensor according to claim 6, wherein: the second single crystalline semiconductor material is epitaxially aligned to the first single crystalline semiconductor material; The first single crystal semiconductor material and the second single crystal semiconductor material have p-type doping; as well as The second single crystalline semiconductor material has a lower p-type dopant atomic concentration than a portion of the first single crystalline semiconductor material that is in contact with the second single crystalline semiconductor material.

10. The image sensor according to claim 6, wherein: The at least one dielectric metal oxide liner includes an aluminum oxide layer, the aluminum oxide layer contacts the single crystal semiconductor liner and has a thickness ranging from 0.8 nanometers to 1.6 nanometers and has a root mean square thickness variation of less than 0.1 nanometers; The at least one dielectric metal oxide liner includes an inner dielectric metal oxide liner, the inner dielectric metal oxide liner comprising a dielectric metal oxide material having a dielectric constant greater than 7.9, having a different material composition than aluminum oxide, and contacting the aluminum oxide layer; and The silicon oxide material is partially located in the trench and contacts the surface of the inner dielectric metal oxide liner.

11. The image sensor according to claim 6, wherein: The single crystal semiconductor liner has an average thickness ranging from 1.5 nanometers to 10 nanometers; and The first root mean square surface roughness is at least three times the second root mean square surface roughness.

12. The image sensor according to claim 6, wherein: a surface segment of greater than 50% of the total surface area of ​​the vertical or tapered surface comprising a faceted surface that is free of the first single crystalline semiconductor material; as well as A surface segment of more than 50% of the entire surface area of ​​the second side surface of the second single-crystalline semiconductor material comprises a faceted surface as the second single-crystalline semiconductor material.

13. The image sensor according to claim 6, further comprising: a grid structure overlying the backside surface of the semiconductor substrate and having an array of openings in the region of a corresponding one of the sub-pixels; A color filter array overlying the grid structure; as well as A lens array is disposed on the color filter array.

14. A method of forming a semiconductor structure, comprising: forming a trench in a substrate semiconductor layer of a semiconductor substrate, wherein a sidewall of the trench comprises a vertical or tapered surface having a first root mean square surface roughness greater than 0.5 nanometers; forming a single crystal semiconductor liner comprising a second single crystal semiconductor material by performing an epitaxial growth process on the vertical or tapered surface of the trench at a growth temperature lower than 500 degrees Celsius, wherein the single crystal semiconductor liner comprises a vertical extension portion having a first side surface on a first side in contact with the vertical or tapered surface and having a second side surface having a second root mean square surface roughness of less than 0.5 nanometers; as well as At least one dielectric metal oxide liner is formed on the second side surface of the single crystal semiconductor liner.

15. The method for forming a semiconductor structure according to claim 14, wherein: The epitaxial growth process uses a silicon-containing precursor gas selected from silane and disilane; The single crystal semiconductor liner has an average thickness ranging from 1.5 nanometers to 10 nanometers; and The first root mean square surface roughness is at least three times the second root mean square surface roughness.

16. The method for forming a semiconductor structure according to claim 14, wherein: The method includes forming transistors, interconnect-level dielectric layers, and metal interconnect structures on a front side of the semiconductor substrate; and The trench is formed through a backside surface of the semiconductor substrate toward the front side of the semiconductor substrate.

17. The method for forming a semiconductor structure according to claim 16, further comprising: bonding a carrier substrate to the interconnect level dielectric layer; After laminating the carrier substrate, thinning the semiconductor substrate; as well as After forming the metal interconnect structure, the trench is formed.

18. The method for forming a semiconductor structure according to claim 16, further comprising: forming a photodetector and a sensing circuit for the photodetector on the front side of the semiconductor substrate; forming a grid structure overlying the backside surface of the semiconductor substrate; forming a color filter array on the grid structure; as well as A lens array is formed on the color filter array.

19. The method for forming a semiconductor structure according to claim 16, further comprising: forming a shallow trench isolation structure in the semiconductor substrate on the front side directly between the transistors, wherein the trench comprises a deep trench extending through the semiconductor substrate to one of the shallow trench isolation structures and having a depth in a range of 1.5 microns to 10 microns; as well as depositing a dielectric isolation layer on the at least one dielectric metal oxide liner in a remaining volume of the deep trench, wherein: The at least one dielectric metal oxide liner comprises at least one oxygen-rich dielectric metal oxide material and has a net negative charge; and The at least one dielectric metal oxide liner and a portion of the dielectric isolation layer located in the deep trench form a dielectric isolation structure.

20. The method for forming a semiconductor structure according to claim 14, wherein: a surface segment of greater than 50% of the total surface area of ​​the vertical or tapered surface comprises a faceted surface that is free of first single crystalline semiconductor material; and A surface segment of more than 50% of the entire surface area of ​​the second side surface of the second single-crystalline semiconductor material comprises a faceted surface as the second single-crystalline semiconductor material.

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