Display device and method of manufacturing the same

Abstract

The present application relates to a display device and a method of manufacturing a display device. The display device includes a substrate; first and second electrodes spaced apart from each other by a first distance along a first direction on the substrate; third and fourth electrodes respectively on the first and second electrodes and spaced apart from each other by a second distance along the first direction; a first insulating layer on the third and fourth electrodes; and a light emitting element positioned on the first insulating layer and between the third and fourth electrodes in a plan view, and the second distance is greater than the first distance.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0011177, filed on January 30, 2020, and Korean Patent Application No. 10-2020-0155637, filed on November 19, 2020, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to display devices and methods of manufacturing them. Background Technology

[0004] Recently, with the increase in interest in information display, research and development of display devices has been ongoing. Summary of the Invention

[0005] This disclosure provides a display device and a method of manufacturing the same, in which reliability can be improved by arranging light-emitting elements in precise positions.

[0006] Another aspect of this disclosure provides a display device that can improve the reliability of electrical signals.

[0007] The aspects of this disclosure are not limited to those described above, and other aspects not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to some embodiments of this disclosure, a display device includes: a substrate; a first electrode and a second electrode, disposed on the substrate and spaced apart from each other by a first distance along a first direction; a third electrode and a fourth electrode, respectively disposed on the first electrode and the second electrode and spaced apart from each other by a second distance along the first direction; and a light-emitting element, located between the third electrode and the fourth electrode in a plan view. The second distance may be greater than the first distance.

[0009] In some embodiments, the length of the light-emitting element in the first direction may be greater than the first distance and less than the second distance, and at least a portion of the first electrode and at least a portion of the second electrode may overlap with the light-emitting element.

[0010] In some implementations, the first and second electrodes may comprise the same material, and the third and fourth electrodes may comprise materials different from those of the first and second electrodes.

[0011] In some embodiments, the first electrode and the second electrode may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO).

[0012] In some embodiments, the third and fourth electrodes may include at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, and Cu.

[0013] In some implementations, the third electrode may contact the first electrode, and the fourth electrode may contact the second electrode.

[0014] In some embodiments, the display device further includes a first insulating layer on the third and fourth electrodes. The light-emitting element may be located on the first insulating layer.

[0015] In some embodiments, the display device further includes a first insulating pattern and a second insulating pattern spaced apart from each other on a first insulating layer and along a first direction. A light-emitting element may be positioned between the first insulating pattern and the second insulating pattern.

[0016] In some embodiments, the display device further includes a fifth electrode that contacts the first electrode and the first end of the light-emitting element, and a sixth electrode that contacts the second electrode and the second end of the light-emitting element.

[0017] In some embodiments, the fifth and sixth electrodes may be on the first insulating layer, the first insulating layer and the third electrode may include a first opening that exposes at least a portion of the first electrode, the first insulating layer and the fourth electrode may include a second opening that exposes at least a portion of the second electrode, the fifth electrode may be connected to the first electrode through the first opening, and the sixth electrode may be connected to the second electrode through the second opening.

[0018] In some embodiments, the display device further includes an anchoring layer on the light-emitting element. The anchoring layer may contact at least a portion of the outer peripheral surface of the light-emitting element and expose a first end and a second end of the light-emitting element.

[0019] In some embodiments, the display device further includes: a first dam between the first electrode and the substrate, and overlapping the first electrode and the third electrode; and a second dam between the second electrode and the substrate, and overlapping the second electrode and the fourth electrode.

[0020] In some embodiments, the display device further includes a first dike and a second dike, each having a shape protruding in the display direction of the light-emitting element on the first insulating layer. A first opening may be located between the first dike and the light-emitting element, and a second opening may be located between the second dike and the light-emitting element.

[0021] According to another embodiment of this disclosure, a method for manufacturing a display device includes: sequentially forming a first conductive layer and a second conductive layer on a substrate; etching the first conductive layer to form a first electrode and a second electrode spaced apart from each other by a first distance along a first direction, and etching the second conductive layer to form a third electrode and a fourth electrode spaced apart from each other by a second distance along the first direction; forming an insulating layer on the third electrode and the fourth electrode; and aligning a light-emitting element on the insulating layer. The second distance may be greater than the first distance, and the light-emitting element may be aligned between the third electrode and the fourth electrode in a planar view.

[0022] In some embodiments, the length of the light-emitting element in the first direction may be greater than the first distance and less than the second distance, and at least a portion of the first electrode and at least a portion of the second electrode may overlap with the light-emitting element.

[0023] In some embodiments, forming the first to fourth electrodes includes: etching a first conductive layer and a second conductive layer; crystallizing the first and second electrodes by performing a baking process for heating the substrate; and forming the third and fourth electrodes by further etching the etched second conductive layer.

[0024] The method further includes: forming a first opening in the third electrode and the insulating layer; and forming a second opening in the fourth electrode and the insulating layer.

[0025] The method further includes forming a fifth electrode and a sixth electrode on an insulating layer. Forming the fifth electrode and the sixth electrode may include contacting the fifth electrode with the first electrode through a first opening; and contacting the sixth electrode with the second electrode through a second opening.

[0026] The method further includes forming a first dike and a second dike, each having a shape protruding in the display direction of the light-emitting element, on the insulating layer. A first opening may be located between the first dike and the light-emitting element, and a second opening may be located between the second dike and the light-emitting element.

[0027] In some embodiments, forming the insulating layer further includes forming a first insulating pattern and a second insulating pattern spaced apart from each other along a first direction on the insulating layer. The light-emitting element may be located between the first insulating pattern and the second insulating pattern.

[0028] According to another embodiment, the display device includes: a substrate; a first electrode and a second electrode on the substrate; a third electrode on the first electrode and having a first opening exposing at least a portion of the first electrode; a fourth electrode on the second electrode and having a second opening exposing at least a portion of the second electrode; a light-emitting element located between the third and fourth electrodes when viewed in a planar plane and capable of emitting light in a display direction; a fifth electrode having at least a portion electrically connected to one end of the light-emitting element and being on the third electrode; and a sixth electrode having at least a portion electrically connected to the other end of the light-emitting element and being on the fourth electrode. The fifth electrode can be connected to the first electrode through the first opening, and the sixth electrode can be connected to the second electrode through the second opening.

[0029] In some embodiments, the first and fifth electrodes comprise a first material, and the second and sixth electrodes comprise a second material.

[0030] In some embodiments, the first and second materials include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO).

[0031] The display device also includes: an emitting region through which light can be emitted; a non-emitting region, which is a region different from the emitting region; and a partition wall having a shape that protrudes in the display direction and defines the emitting region. A first opening and a second opening may be located in the non-emitting region.

[0032] The display device includes a first opening and a second opening that overlap with the partition wall.

[0033] In some implementations, the non-emission region includes the area where at least a portion of the first electrode or the second electrode is cut off.

[0034] The display device also includes a dam arranged in the emission area and having a shape that protrudes in the display direction. At least a portion of each of the first electrode and the second electrode may be located on the dam, and the first opening and the second opening may not overlap with the dam.

[0035] The means for solving the problems of this disclosure are not limited to the solutions described above. Based on this disclosure and the accompanying drawings, those skilled in the art will clearly understand solutions not mentioned. Attached Figure Description

[0036] The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the specification, serve to explain the principles of the inventive concept. The drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification.

[0037] Figure 1 and Figure 2 This is a perspective view of a partial cutaway of a light-emitting element according to one or more embodiments of the present disclosure.

[0038] Figure 3 This is a plan view illustrating a display device according to one or more embodiments of the present disclosure.

[0039] Figures 4 to 6 This is a circuit diagram illustrating a pixel according to one or more embodiments of the present disclosure.

[0040] Figure 7 This is a circuit diagram illustrating a pixel according to another embodiment of the present disclosure.

[0041] Figure 8 This is a plan view schematically illustrating pixels according to one or more embodiments of the present disclosure.

[0042] Figure 9 It is along Figure 8 A sectional view taken by line I-I'.

[0043] Figure 10 This is a schematic plan view of pixels according to another embodiment of the present disclosure.

[0044] Figure 11 It is along Figure 10 The sectional view taken from line II-II'.

[0045] Figure 12 This is a schematic plan view of pixels according to yet another embodiment of the present disclosure.

[0046] Figure 13 It is along Figure 12 The sectional view taken from line III-III'.

[0047] Figure 14 This is a schematic plan view of pixels according to yet another embodiment of the present disclosure.

[0048] Figure 15 It is along Figure 14 A sectional view taken from line IV-IV'.

[0049] Figure 16 This is a schematic plan view of pixels according to yet another embodiment of the present disclosure.

[0050] Figure 17 and Figure 18 It is along Figure 16 A sectional view taken by line V-V'.

[0051] Figures 19 to 31This is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure. Detailed Implementation

[0052] The aspects and features of this disclosure, as well as methods for implementing this disclosure, will become clearer from the exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments described below, but can be implemented in various different forms. The exemplary embodiments are provided only to improve the content of this disclosure and to fully inform those skilled in the art to which this disclosure pertains. This disclosure is limited only by the scope of the appended claims.

[0053] The phrase "an element or layer located on another element or another layer" can mean that an element can be located directly on another element and / or that an element can be located indirectly on another element via another element or another layer. Throughout this disclosure, the same reference numerals generally refer to the same elements. The shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings for describing embodiments are examples, and therefore, this disclosure is not limited thereto.

[0054] Although the terms first, second, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the first component discussed below may be the second component. Singular expressions may include plural expressions unless the context clearly indicates otherwise.

[0055] Features of each of the exemplary embodiments of this disclosure may be paired or combined with each other in part or in whole, and may be interlocked and driven differently in a technical manner. Each of the exemplary embodiments may be implemented independently of each other, or may be implemented together in association.

[0056] Throughout this disclosure, the same reference numerals denote the same parts in the various figures and embodiments of this disclosure.

[0057] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. It should be understood that, in addition to the orientation depicted in the figures, these spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as “between” two layers, it can be the only layer between the two layers, or there may be one or more intervening layers.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than as terms of degree and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those skilled in the art.

[0059] As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the elements of the entire list without modifying individual elements within the list when following an element of a list. Furthermore, when describing embodiments of the inventive concept, the use of “may” means “one or more embodiments of the invention.” Additionally, the term “exemplary” is intended to indicate an example or illustration. As used herein, the terms “use,” “using,” and “used” are to be understood as synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0060] It should be understood that when an element or layer is referred to as being "on" another element or layer, "connected to", "linked to", or "adjacent to" another element or layer, it can be directly on, directly connected to, directly linked to, or directly adjacent to the other element or layer, or one or more intervening elements or layers may exist. Conversely, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to", "directly linked to", or "directly adjacent to" another element or layer, there are no intervening elements or layers.

[0061] In the following, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0062] This disclosure relates to display devices and methods for manufacturing display devices.

[0063] Figure 1 and Figure 2 This is a perspective view of a partially cut-off light-emitting element according to one or more embodiments of the present disclosure.

[0064] refer to Figure 1 and Figure 2 The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element (LD) may be implemented as a stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked sequentially.

[0065] The light-emitting element (LD) can be configured as a rod shape extending in one direction. When the extension direction of the light-emitting element (LD) is longitudinal, the light-emitting element (LD) can have one end and the other end along the longitudinal direction.

[0066] One of the first semiconductor layer 11 and the second semiconductor layer 13 can be positioned adjacent to one end of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be positioned adjacent to the other end of the light-emitting element LD.

[0067] In one or more embodiments of this disclosure, the light-emitting element (LD) may be configured in a rod shape. Here, the term "rod shape" can include rod-like or bar-like shapes that are long in the longitudinal direction (e.g., having an aspect ratio greater than 1), such as cylinders or polygonal pillars. For example, the length of the light-emitting element LD may be greater than its diameter. However, this disclosure is not limited thereto. Furthermore, the light-emitting element LD may be a light-emitting element with a core-shell structure.

[0068] For example, light-emitting diodes (LDs) can be manufactured with diameters and / or lengths in the micrometer or nanometer range. For instance, the diameter of an LD can be approximately 600 nm or less, and the length can be approximately 4 μm or less. However, the size of an LD is not limited to these dimensions, and the size can be varied to meet the requirements of display devices employing LDs.

[0069] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For instance, the first semiconductor layer 11 may include any semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. In another embodiment, the first semiconductor layer 11 may include a semiconductor layer doped with a first dopant (such as Si, Ge, Sn, etc.). However, the materials constituting the first semiconductor layer 11 are not limited thereto.

[0070] The active layer 12 can be formed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. In one or more embodiments, when the active layer 12 includes a material having a multi-quantum well structure, multiple quantum layers and multiple well layers can be stacked alternately.

[0071] In one or more embodiments, when an electric field exceeding a certain voltage (e.g., a set or predetermined voltage) is applied between the two ends of the light-emitting element LD, the light-emitting element LD can emit light while electron-hole pairs recombine in the active layer 12. When the light emission of the light-emitting element LD is controlled using this principle, the light-emitting element LD can be used as a light source for various light-emitting devices, including pixels of a display device.

[0072] The active layer 12 can emit light with wavelengths from about 400 nm to about 900 nm. For example, when the active layer 12 emits light with a blue wavelength band, it can include materials such as AlGaN or AlGaInN. For example, when the active layer 12 has a multi-quantum-well structure in which quantum layers and well layers are stacked alternately, the quantum layers can include materials such as AlGaN or AlGaInN, and the well layers can include materials such as GaN or AlInN. In one or more embodiments, the active layer 12 can include AlGaInN as a quantum layer and AlInN as a well layer. In this case, the active layer 12 can emit blue light with a center wavelength band in the range of about 450 nm to about 495 nm.

[0073] However, this disclosure is not limited thereto. The active layer 12 may have a structure in which semiconductor materials with large bandgap energies and semiconductor materials with small bandgap energies are stacked alternately, and the active layer 12 may include other semiconductor materials from group III to group V, depending on the wavelength range of the emitted light. The light emitted from the active layer 12 is not limited to light in the blue wavelength band, and in some cases the light emitted from the active layer 12 may be light in the red and green wavelength bands.

[0074] On the other hand, in one or more embodiments, light emitted from the active layer 12 can be emitted from the outer surface and both sides of the light-emitting element LD in the longitudinal direction. The direction of light emitted from the active layer 12 is not limited to one direction.

[0075] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. The second semiconductor layer 13 may include, for example, at least one p-type semiconductor layer. For instance, the second semiconductor layer 13 may include at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. In another embodiment, the second semiconductor layer 13 may include a semiconductor layer doped with a second dopant (such as Mg, Zn, Ca, Se, Ba, etc.). The materials constituting the second semiconductor layer 13 are not limited thereto.

[0076] In one or more embodiments, Figure 1 and Figure 2 In the diagram, the first semiconductor layer 11 and the second semiconductor layer 13 are each shown as a single layer. However, this disclosure is not limited thereto. For example, depending on the material of the active layer 12, the first semiconductor layer 11 and the second semiconductor layer 13 may include a greater number of layers. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may also include a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0077] According to one or more embodiments of this disclosure, the light-emitting element LD may further include other phosphor layers, active layers, semiconductor layers and / or electrode layers located above and / or below each of the first semiconductor layer 11, the active layer 12 and the second semiconductor layer 13.

[0078] In one or more embodiments, the light-emitting element (LD) may further include at least one electrode layer located at one end of the second semiconductor layer 13 (e.g., the upper surface of the light-emitting element LD) or one end of the first semiconductor layer 11 (e.g., the lower surface of the light-emitting element LD). For example, as Figure 2As shown, the light-emitting element LD may further include an electrode layer 15 located at one end of the second semiconductor layer 13. In one or more embodiments, the electrode layer 15 may be located at one end of the first semiconductor layer 11. The electrode layer 15 may be an ohmic contact electrode, but this disclosure is not limited thereto. For example, the electrode layer 15 may be a Schottky contact electrode. The electrode layer 15 may include a metal or a metal oxide. For example, the electrode layer 15 may include chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO) or oxides, alloys, or mixtures thereof. However, this disclosure is not limited thereto. In another embodiment, the electrode layer 15 may be substantially transparent or translucent. Therefore, light generated in the light-emitting element LD can pass through the electrode layer 15 and can be emitted to the outside of the light-emitting element LD.

[0079] In one or more embodiments, the light-emitting element LD may further include an insulating film 14. However, according to one or more embodiments of this disclosure, the insulating film 14 may be omitted, or the insulating film 14 may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the insulating film 14 may be disposed in portions other than the two ends of the light-emitting element LD, thereby exposing the two ends of the light-emitting element LD.

[0080] For ease of description, Figure 1 and Figure 2 A state is shown in which a portion of the insulating film 14 is removed, but the general side surface of the light-emitting element LD can be surrounded by the insulating film 14.

[0081] According to one or more embodiments, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ) and titanium dioxide (TiO) x The insulating film 14 may contain at least one insulating material. However, this disclosure is not limited thereto, and the insulating film 14 may include a variety of other materials having insulating properties.

[0082] The insulating film 14 can prevent (or provide protection against) electrical short circuits that may occur when the active layer 12 comes into contact with conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In one or more embodiments, by forming the insulating film 14, surface defects of the light-emitting element LD are minimized or reduced, thereby improving lifetime and efficiency. In one or more embodiments, when multiple light-emitting elements LD are positioned adjacent to each other, the insulating film 14 can prevent unwanted short circuits that may occur between the light-emitting elements LD. For example, the insulating film 14 can provide protection against unwanted short circuits between adjacent light-emitting elements LD.

[0083] The type, structure, and shape of the light-emitting element (LD) according to embodiments of this disclosure can be varied.

[0084] Figure 3 This is a plan view illustrating a display device according to one or more embodiments of the present disclosure.

[0085] refer to Figure 1 , Figure 2 and Figure 3 The display device 1000 may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. The display device 1000 (or the substrate SUB) may include a display area DA and a non-display area NDA other than the display area DA, in which the plurality of pixels PXL are arranged to display an image.

[0086] The display area DA can be the area in which the pixel PXL is disposed. The non-display area NDA can be the area in which driving units for driving the pixel PXL are disposed (e.g., scan driving voltage unit or scan driver SDV, data driving voltage unit or data driver DDV and transmit driving voltage unit or transmit control driver EDV) and various wiring for connecting the pixel PXL and the driving units SDV, DDV and EDV are disposed.

[0087] The display area DA can have various shapes. For example, the display area DA can have various shapes such as a closed polygon with straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges.

[0088] In one or more embodiments, when the display area DA comprises multiple areas, each area may also have various shapes such as a closed polygon including straight edges, a circle including curved edges, or an ellipse. In one or more embodiments, the areas of the multiple areas may be the same or different. In one or more embodiments of this disclosure, the case where the display area DA is set as a single area having a rectangular shape including straight edges will be described as an example.

[0089] The non-display area NDA may be disposed on at least one side of the display area DA. In one or more embodiments of this disclosure, the non-display area NDA may surround the display area DA.

[0090] Pixels PXL can be disposed on the substrate SUB in the display area DA. Each of the pixels PXL may include at least one light-emitting element LD, which is connected to the scan line and the data line and is driven by the corresponding scan signal and data signal.

[0091] Each of the pixels PXL can emit light of any one of red, green, and blue, but this disclosure is not limited thereto. For example, each of the pixels PXL can emit light of one of cyan, magenta, yellow, and white.

[0092] In one or more embodiments, a pixel PXL may include a first pixel PXL1 (or a first sub-pixel) that emits light of a first color, a second pixel PXL2 (or a second sub-pixel) that emits light of a second color different from the first color, and a third pixel PXL3 (or a third sub-pixel) that emits light of a third color different from the first and second colors. At least one first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 positioned adjacent to each other can constitute a pixel unit PXU capable of emitting light of various colors.

[0093] In one or more embodiments, the first pixel PXL1 may be a red pixel that emits red light, the second pixel PXL2 may be a green pixel that emits green light, and the third pixel PXL3 may be a blue pixel that emits blue light.

[0094] In one or more embodiments, pixel PXL may have a light-emitting element LD that emits light of the same color. However, in one or more embodiments, when pixel PXL includes a light conversion layer of a different color located on the light-emitting element LD, pixel PXL may emit light of different colors. In another embodiment, pixel PXL may include light-emitting elements LD that emit light of different colors. However, the color, type, and / or number of pixels PXL are not particularly limited.

[0095] Multiple pixels PXL can be provided and arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the arrangement of pixels PXL is not particularly limited and can be arranged in various forms.

[0096] The drive units SDV, DDV, and EDV can provide signals to each pixel PXL through each wiring unit, and therefore can control the driving of each pixel PXL. Figure 3 For ease of description, wiring units are omitted.

[0097] The driving units SDV, DDV, and EDV may include a scan driver SDV that provides scan signals to pixel PXL via scan lines, a data driver DDV that provides data signals to pixel PXL via data lines, a transmit control driver EDV that provides transmit control signals to pixel PXL via transmit control lines, and a timing controller. The timing controller can control the scan driver SDV, the data driver DDV, and the transmit control driver EDV. In one or more embodiments, the transmit control driver EDV may be omitted; however, the embodiments of this disclosure are not limited thereto.

[0098] The scan driver SDV can be located on one side of the substrate SUB and can be arranged along one direction (e.g., a second direction DR2). The scan driver SDV can be mounted on the substrate SUB as a separate component, but this disclosure is not limited thereto. For example, the scan driver SDV can be formed directly on the substrate SUB. In one or more embodiments, the scan driver SDV can be located outside the substrate SUB and can be connected to the pixel PXL via a separate connecting member.

[0099] The data driver DDV can be located on one side of the substrate SUB and can be arranged along a direction intersecting the aforementioned scan driver SDV (e.g., a first direction DR1). The data driver DDV can be mounted on the substrate SUB as a separate component, or it can be located outside the substrate SUB and connected to the pixel PXL via a separate connecting member.

[0100] The emitter control driver (EDV) can be located on one side of the substrate (SUB) and can be arranged along one direction (e.g., a second direction DR2). Figure 3 As shown, the emission control driver EDV may be located on the same side of the substrate SUB and the same side of the display area DA as the scan driver SDV, but this disclosure is not limited thereto. For example, the emission control driver EDV may be located on a different side from the scan driver SDV (e.g., with the display area DA between them). The emission control driver EDV may be mounted on the substrate SUB as a separate component, but this disclosure is not limited thereto. For example, the emission control driver EDV may be formed directly on the substrate SUB. In one or more embodiments, the emission control driver EDV may be located outside the substrate SUB and may be connected to the pixel PXL via a separate connecting member.

[0101] In one or more embodiments, each of the pixels PXL can be configured as an active pixel. However, the type, structure, and / or driving method of the pixels PXL applicable to this disclosure are not particularly limited.

[0102] Figures 4 to 6 This is a circuit diagram illustrating pixels according to one or more embodiments of the present disclosure. In one or more embodiments, Figures 4 to 6 An example of pixels that make up an active light-emitting display panel is shown.

[0103] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 The pixel PXL may include at least one light-emitting element LD and a driving circuit DC connected to the light-emitting element LD to drive the light-emitting element LD.

[0104] The first electrode of the light-emitting element LD (e.g., Figure 8 The 'RFE1' shown can be connected to the first drive power supply VDD via the drive circuit DC, and can also be connected via the second electrode (e.g., Figure 8 The 'RFE2' shown is connected to the second drive power supply VSS. According to the example, the first electrode RFE1 can be the anode electrode, and the second electrode RFE2 can be the cathode electrode, but this disclosure is not limited thereto. The light-emitting element LD can emit light with a brightness corresponding to the amount of drive current controlled by the drive circuit DC.

[0105] First electrode RFE1 to fourth electrode RFE4 (see...) Figure 8 At least one of the first electrodes RFE1 to the fourth electrodes RFE4 can be a pixel electrode of pixel PXL. After at least one of the first electrodes RFE1 to the fourth electrodes RFE4 is formed as an alignment line, a portion of at least one of the first electrodes RFE1 to the fourth electrodes RFE4 can be in the emission region of adjacent pixel PXL and / or each pixel PXL (refer to...). Figure 8 The 'EMA' shown is cut off between the pixels to divide them into corresponding pixel electrodes. In this case, the emission region EMA can refer to the area where light is emitted from pixel PXL. According to the example, the emission region EMA can be divided by a partition wall (e.g., Figure 8 The 'OBNK' shown is the definition.

[0106] Figure 4 Only one light-emitting element (LD) is shown; however, this disclosure is not limited thereto. For example, a pixel PXL may include multiple light-emitting elements (LDs). Multiple light-emitting elements (LDs) may be connected in parallel and / or in series with each other.

[0107] The first driving power supply VDD and the second driving power supply VSS can have different potentials. For example, the potential of the first driving power supply VDD can be higher than the threshold voltage of the light-emitting element (LD) than the potential of the second driving power supply VSS. For example, the voltage applied from the first driving power supply VDD can be greater than the voltage applied from the second driving power supply VSS.

[0108] According to one or more embodiments, the driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0109] One electrode of the first transistor M1 (e.g., a driver transistor) can be electrically connected to a first drive power supply VDD, and the other electrode of the first transistor M1 can be electrically connected to a first electrode RFE1 of the light-emitting element LD. The gate electrode of the first transistor M1 can be connected to a first node N1. The first transistor M1 can control the amount of drive current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0110] One electrode of the second transistor M2 (e.g., a switching transistor) can be connected to the data line DL, and the other electrode of the second transistor M2 can be connected to the first node N1. Here, one electrode and the other electrode of the second transistor M2 can be different electrodes. For example, when one electrode of the second transistor M2 is the source electrode, the other electrode of the second transistor M2 can be the drain electrode. The gate electrode of the second transistor M2 can be connected to the scan line SL.

[0111] When a scan signal is provided from the scan line SL, allowing the second transistor M2 to conduct (e.g., gate turn-on voltage), the second transistor M2 can conduct to electrically connect the data line DL and the first node N1. In this case, the data signal for the corresponding frame can be provided to the data line DL, and therefore, the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0112] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the other electrode of the storage capacitor Cst can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1, and can maintain the charged voltage until the next frame of data signal is provided.

[0113] For ease of description, Figure 4 A driving circuit DC with a relatively simple structure is shown, which includes a second transistor M2 for transmitting data signals to the interior of the pixel PXL, a storage capacitor Cst for storing data signals, and a first transistor M1 for providing a driving current corresponding to the data signals to the light-emitting element LD.

[0114] However, this disclosure is not limited thereto, and the structure of the driving circuit DC can be varied. For example, the driving circuit DC may also include various transistors, such as a compensation transistor for compensating the threshold voltage of the first transistor M1, an initialization transistor for initializing the first node N1, and / or an emission control transistor for controlling the emission time of the light-emitting element LD, as well as other circuit elements such as a boost capacitor for increasing the voltage of the first node N1.

[0115] exist Figure 4 In this embodiment, transistors (e.g., first transistor M1 and second transistor M2) included in the drive circuit DC are shown as P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor M1 and second transistor M2 included in the drive circuit DC may be changed to an N-type transistor.

[0116] For example, such as Figure 5 As shown, the first transistor M1 and the second transistor M2 in the drive circuit DC can be implemented as N-type transistors. Aside from the change in the connection positions of some components due to the change in transistor type, Figure 5 The DC drive circuit shown can be similar in structure or operation to Figure 4 The DC drive circuit. Therefore, it is not necessary to repeat the detailed description of its same or similar components.

[0117] As another implementation method, refer to Figure 6 The pixel PXL may also include a third transistor M3 (e.g., a sensing transistor).

[0118] The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. One electrode of the third transistor M3 can be connected to the sensing line SENL, and the other electrode of the third transistor M3 can be connected to the anode electrode of the light-emitting element LD. During the sensing cycle, the third transistor M3 can transmit the voltage value of the anode electrode of the light-emitting element LD to the sensing line SENL according to the sensing signal provided to the sensing signal line SSL. The voltage value transmitted through the sensing line SENL can be provided to external circuitry (e.g., a timing controller). The external circuitry can extract characteristic information of pixel PXL (e.g., the threshold voltage of the first transistor M1) based on the provided voltage value. The extracted characteristic information can be used to convert image data to compensate for characteristic deviations of pixel PXL.

[0119] Figure 7 This is a circuit diagram illustrating a pixel according to another embodiment of the present disclosure.

[0120] Reference Figure 7According to another embodiment of the present disclosure, the pixel PXL may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and a storage capacitor Cst.

[0121] The first electrode RFE1 (e.g., the anode electrode) of the light-emitting element LD can be connected to the first transistor T1 via the sixth transistor T6, and the second electrode RFE2 (e.g., the cathode electrode) of the light-emitting element LD can be connected to the second driving power supply VSS. The light-emitting element LD can emit light with a brightness (e.g., a set or predetermined brightness) corresponding to the amount of driving current supplied from the first transistor T1.

[0122] One electrode of the first transistor T1 (e.g., a driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and the other electrode of the first transistor T1 can be connected to the first electrode RFE1 of the light-emitting element LD via the sixth transistor T6. The first transistor T1 can control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1 connected to the gate electrode of the first transistor T1.

[0123] A second transistor T2 (e.g., a switching transistor) may be connected between a data line DL and an electrode of the first transistor T1. In one or more embodiments, the gate electrode of the second transistor T2 may be connected to a first scan line SL. When a scan signal with a gate-on voltage is provided to the first scan line SL, the second transistor T2 may be turned on to electrically connect the data line DL and an electrode of the first transistor T1.

[0124] A third transistor T3 may be connected between the other electrode of the first transistor T1 and the first node N1. In one or more embodiments, the gate electrode of the third transistor T3 may be connected to the first scan line SL. When a scan signal of the gate on-state voltage is provided to the first scan line SL, the third transistor T3 may be turned on to electrically connect the other electrode of the first transistor T1 and the first node N1.

[0125] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. In one or more embodiments, the gate electrode of the fourth transistor T4 can be connected to the second scan line SL-1. When a scan signal with a gate-on voltage is provided to the second scan line SL-1, the fourth transistor T4 can be turned on to provide the voltage of the initialization power supply Vint to the first node N1. Here, the initialization power supply Vint can be set to a voltage lower than the data signal voltage. The scan signal provided to the second scan line SL-1 can have the same waveform as the scan signal provided to the first scan line of the previous stage pixel.

[0126] The fifth transistor T5 can be connected between the first drive power supply VDD and one electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the emitter control line EL. When the emitter control signal with gate on-voltage is provided to the emitter control line EL, the fifth transistor T5 can be turned on, and when the emitter control signal with gate on-voltage is not provided to the emitter control line EL, the fifth transistor T5 can be turned off.

[0127] The sixth transistor T6 can be connected between the other electrode of the first transistor T1 and the first electrode RFE1 of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the emitter control line EL. When the emitter control signal of the gate on-voltage is provided to the emitter control line EL, the sixth transistor T6 can be turned on, and when the emitter control signal of the gate on-voltage is not provided to the emitter control line EL, the sixth transistor T6 can be turned off.

[0128] A seventh transistor T7 can be connected between the initialization power supply Vint and the first electrode RFE1 of the light-emitting element LD. In one or more embodiments, the gate electrode of the seventh transistor T7 can be connected to the third scan line SL+1. When a scan signal with a gate-on voltage is provided to the third scan line SL+1, the seventh transistor T7 can be turned on to provide the voltage of the initialization power supply Vint to the first electrode RFE1 of the light-emitting element LD. The scan signal provided to the third scan line SL+1 can have the same waveform as the scan signal provided to the first scan line of the next pixel.

[0129] Figure 7 An embodiment of this disclosure is shown in which the gate electrode of the seventh transistor T7 is connected to the third scan line SL+1. However, the spirit of this disclosure is not limited thereto. For example, in another embodiment of this disclosure, the gate electrode of the seventh transistor T7 may be connected to the first scan line SL or the second scan line SL-1. In this case, when a scan signal of the gate on-state voltage is provided to the first scan line SL or the second scan line SL-1, the voltage of the initialization power supply Vint may be provided to the anode electrode of the light-emitting element LD via the seventh transistor T7.

[0130] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The voltage corresponding to the data signal and the threshold voltage of the first transistor T1 can be stored in the storage capacitor Cst.

[0131] exist Figure 7In this embodiment, transistors included in the DC drive circuit (e.g., first transistor T1 to seventh transistor T7) are shown as P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to seventh transistor T7 may be changed to an N-type transistor.

[0132] In the following text, reference will be made to Figures 8 to 18 To describe the structure of the pixels according to the implementation method.

[0133] For ease of description, each electrode is simplified and shown as a single electrode layer in the following description. However, this disclosure is not limited thereto, and each electrode may consist of multiple electrode layers. In one or more embodiments of this disclosure, the phrase "formed and / or located in the same layer (or at the same layer)" may mean that they are formed in the same process and are formed of the same material.

[0134] exist Figures 8 to 18 For ease of description, the transistors connected to the light-emitting elements and the signal lines connected to the transistors are omitted.

[0135] In addition, Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 In this illustration, the light-emitting element LD is shown aligned such that its longitudinal direction corresponds to the first direction DR1, but this disclosure is not limited thereto. For example, the light-emitting element LD may be aligned diagonally relative to the first direction DR1.

[0136] Reference Figure 8 and Figure 9 Describes a pixel PXL according to one or more embodiments. Figure 8 and Figure 9 It may be a diagram showing a pixel PXL according to one or more embodiments. Figure 8 It is a schematic plan view of pixels according to one or more embodiments. Figure 9 It is along Figure 8 A sectional view taken by line I-I'.

[0137] Reference Figure 8 and Figure 9 A pixel PXL according to one or more embodiments of the present disclosure may include a substrate SUB, a first electrode RFE1, a second electrode RFE2, a third electrode RFE3, a fourth electrode RFE4, a first insulating layer INS1, and a light-emitting element LD. The pixel PXL may also include a first dam BNK1, a second dam BNK2, an anchoring layer INSA, a fifth electrode CTE1, a sixth electrode CTE2, a second insulating layer INS2, a third insulating layer INS3, and a partition wall OBNK.

[0138] Figure 8 The pixel PXL shown can be the above reference. Figure 3 The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 are described.

[0139] In the first electrode RFE1 to the fourth electrode RFE4, a pair of electrodes constituting each series stage can be positioned adjacent to the region in which the light-emitting element LD is disposed. For example, the first electrode RFE1 and the second electrode RFE2 can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The third electrode RFE3 and the fourth electrode RFE4 can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1.

[0140] The light-emitting element (LD) can be located between the first electrode RFE1 and the second electrode RFE2. The light-emitting element (LD) can also be located between the third electrode RFE3 and the fourth electrode RFE4. When viewed in a plane, the light-emitting element (LD) can be located within a sub-emission region SEA. The sub-emission region SEA can be a region within the emission region EMA that includes the area where the light-emitting element (LD) is arranged.

[0141] At least one of the first electrodes RFE1 to the fourth electrodes RFE4 can be a pixel electrode for each pixel PXL. After any one of the first electrodes RFE1 to the fourth electrodes RFE4 is formed as an alignment line, a portion of any one of the first electrodes RFE1 to the fourth electrodes RFE4 can be cut between adjacent pixels PXL and / or the sub-emission regions SEA of each pixel PXL to divide it into corresponding pixel electrodes.

[0142] The first electrode RFE1 to the fourth electrode RFE4 can be electrically connected to the light-emitting element LD through their respective contact electrodes (e.g., the fifth electrode CTE1 and / or the sixth electrode CTE2).

[0143] At least a portion of the fifth electrode CTE1 can be connected to the first end EP1 of the light-emitting element LD to connect the first electrode RFE1 and the light-emitting element LD. At least a portion of the sixth electrode CTE2 can be connected to the second end EP2 of the light-emitting element LD to connect the second electrode RFE2 and the light-emitting element LD.

[0144] The fifth electrode CTE1 can be connected to the first electrode RFE1 through the first opening OP1. The sixth electrode CTE2 can be connected to the second electrode RFE2 through the second opening OP2.

[0145] The first opening OP1 can be formed in the third electrode RFE3 and the first insulating layer INS1. The second opening OP2 can be formed in the fourth electrode RFE4 and the first insulating layer INS1. The first opening OP1 and the second opening OP2 can have a hole shape.

[0146] Here, the first opening OP1 and the second opening OP2 can be located in the non-emission region NEA. Therefore, the fifth electrode CTE1 can be electrically connected to the first electrode RFE1 in the non-emission region NEA, and the sixth electrode CTE2 can be connected to the second electrode RFE2 in the non-emission region NEA.

[0147] The non-emitting region (NEA) can refer to a region that does not emit light. The NEA can be a region different from the emitting region (EMA). According to an example, the NEA can be a region where no light-emitting element (LD) is disposed, and it can also refer to a region where a partition wall (OBNK) is disposed. Alternatively, the NEA can be a region where neither the LD nor the OBNK is located, and it can include a region from which at least a portion is removed (e.g., opening region 110), such that any one of the first electrodes RFE1 to the fourth electrode RFE4 is configured as a pixel electrode. According to an example, the first opening OP1 can not overlap with the LD along the first direction DR1. The second opening OP2 can not overlap with the LD along the first direction DR1.

[0148] According to some embodiments, the first opening OP1 and the second opening OP2 may be located in a region where the light-emitting element LD and the partition wall OBNK are not located, or may be located in the opening region 110, although not shown in the figures.

[0149] Reference Figure 9 The substrate SUB can be a rigid substrate or a flexible substrate. The material and physical properties of the substrate SUB are not particularly limited. For example, the substrate SUB can be a rigid substrate made of glass or tempered glass, or a flexible substrate composed of a thin film made of plastic or metal. In one or more embodiments, the substrate SUB can be a transparent substrate, but this disclosure is not limited thereto. For example, the substrate SUB can be a translucent substrate, an opaque substrate, or a reflective substrate.

[0150] The first dam BNK1 and the second dam BNK2 can be located on the substrate SUB. The space for the light-emitting element LD to be positioned can be disposed between the first dam BNK1 and the second dam BNK2. In one or more embodiments, the first dam BNK1 and the second dam BNK2 can be spaced apart from each other on the substrate SUB along a first direction DR1 by a distance greater than the length WLD of the light-emitting element LD. The first dam BNK1 and the second dam BNK2 can be located on the same layer and can have the same height. However, this disclosure is not limited thereto. Furthermore, the first dam BNK1 and the second dam BNK2 can extend along a second direction DR2 intersecting the first direction DR1.

[0151] The first barrier BNK1 and the second barrier BNK2 can be insulating materials comprising organic or inorganic materials, but this disclosure is not limited thereto. Furthermore, the first barrier BNK1 and the second barrier BNK2 can be formed from a single layer, but this disclosure is not limited thereto. The first barrier BNK1 and the second barrier BNK2 can be formed from multiple layers. In this case, the first barrier BNK1 and the second barrier BNK2 can have a structure in which at least one organic insulating layer and at least one inorganic insulating layer are stacked.

[0152] In one or more embodiments, each of the first dam BNK1 and the second dam BNK2 may have a shape that protrudes in the display direction of the light-emitting element LD. The cross-section of the first dam BNK1 and the second dam BNK2 may have a trapezoidal shape having side surfaces inclined at a certain angle (e.g., a set angle or a predetermined angle). However, the shape of the cross-section of the first dam BNK1 and the second dam BNK2 is not limited to this, and may have various shapes such as a semi-elliptical shape, a circular shape, and a square shape.

[0153] The first electrode RFE1 and the second electrode RFE2 can be located on one of the corresponding sections of the first dam BNK1 and the second dam BNK2, respectively. For example, the first electrode RFE1 can be located on the first dam BNK1, and the second electrode RFE2 can be located on the second dam BNK2.

[0154] In one or more embodiments, the first electrode RFE1 and the second electrode RFE2 may be spaced apart from each other. The first electrode RFE1 and the second electrode RFE2 may be spaced apart from each other by a first distance W1 along a first direction DR1. Here, the first distance W1 may be less than the length WLD of the light-emitting element LD, which will be described later. Therefore, when the light-emitting element LD is located in the central portion between the first electrode RFE1 and the second electrode RFE2, at least a portion of the first electrode RFE1 and at least a portion of the second electrode RFE2 may overlap with the light-emitting element LD respectively along a third direction DR3.

[0155] In one or more embodiments, the first electrode RFE1 and the second electrode RFE2 may extend in a plane along a second direction DR2.

[0156] The first electrode RFE1 and the second electrode RFE2 may have substantially uniform thicknesses along the surfaces of the first embankment BNK1 and the second embankment BNK2. The first electrode RFE1 and the second electrode RFE2 may be configured to correspond to the shapes of the first embankment BNK1 and the second embankment BNK2. For example, the first electrode RFE1 may have a shape corresponding to the inclination of the first embankment BNK1, and the second electrode RFE2 may have a shape corresponding to the inclination of the second embankment BNK2.

[0157] The first electrode RFE1 and the second electrode RFE2 can be located in the same plane and can have substantially the same thickness. Furthermore, the first electrode RFE1 and the second electrode RFE2 can be formed in parallel (e.g., simultaneously) in the same process.

[0158] The first electrode RFE1 and the second electrode RFE2 may comprise conductive materials. For example, the first electrode RFE1 and the second electrode RFE2 may comprise transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). However, this disclosure is not limited thereto.

[0159] For ease of description, although the first electrode RFE1 and the second electrode RFE2 are shown as being directly disposed on the substrate SUB, this disclosure is not limited thereto. For example, a component for driving the display device as a passive or active matrix may also be disposed between the first electrode RFE1 and the second electrode RFE2 and the substrate SUB. This component may be a reference... Figures 4 to 7 The described circuit elements of the pixel PXL. For example, a transistor connected to at least one of the first electrode RFE1 and the second electrode RFE2 may be located between the first electrode RFE1 and the second electrode RFE2 and the substrate SUB.

[0160] The third electrode RFE3 and the fourth electrode RFE4 can be located on the first electrode RFE1 and the second electrode RFE2, respectively. For example, the third electrode RFE3 can be located on the first electrode RFE1, and the fourth electrode RFE4 can be located on the second electrode RFE2. The third electrode RFE3 and the fourth electrode RFE4 can be spaced apart from each other.

[0161] In some embodiments, the third electrode RFE3 can be formed directly on the first electrode RFE1 to contact the first electrode RFE1. Similarly, the fourth electrode RFE4 can be formed directly on the second electrode RFE2 to contact the second electrode RFE2.

[0162] The third electrode RFE3 and the fourth electrode RFE4 can be spaced apart from each other by a second distance W2 along the first direction DR1. Here, the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4 can be greater than the first distance W1 between the first electrode RFE1 and the second electrode RFE2. In one or more embodiments, the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4 can be greater than the length WLD of the light-emitting element LD, which will be described later.

[0163] Because the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4 is greater than the length WLD of the light-emitting element LD, the light-emitting element LD does not need to overlap with the third electrode RFE3 and the fourth electrode RFE4. For example, by adjusting the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4, the space occupied by the light-emitting element LD can be controlled (or restricted). Therefore, the light-emitting element LD can be located at a desired position.

[0164] In one or more embodiments, the third electrode RFE3 and the fourth electrode RFE4 may extend in the second direction DR2 in a plane.

[0165] The third electrode RFE3 and the fourth electrode RFE4 may have substantially uniform thickness along the surfaces of the first electrode RFE1 and the second electrode RFE2. The third electrode RFE3 and the fourth electrode RFE4 may be configured to correspond to the shapes of the first electrode RFE1 and the second electrode RFE2. For example, the third electrode RFE3 may have a shape corresponding to the tilt angle of the first electrode RFE1, and the fourth electrode RFE4 may have a shape corresponding to the tilt angle of the second electrode RFE2.

[0166] The third electrode RFE3 and the fourth electrode RFE4 can be located in the same plane and can have substantially the same thickness. Furthermore, the third electrode RFE3 and the fourth electrode RFE4 can be formed in parallel (e.g., simultaneously) in the same process.

[0167] The third electrode RFE3 and the fourth electrode RFE4 can be made of conductive materials. For example, the third electrode RFE3 and the fourth electrode RFE4 can include metals such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, Li, Ca, LiF / Ca, LiF / Al, Mo, Cu or alloys thereof.

[0168] However, the third electrode RFE3 and the fourth electrode RFE4 can be made of different materials than the first electrode RFE1 and the second electrode RFE2 described above. For example, compared to the first electrode RFE1 and the second electrode RFE2, the third electrode RFE3 and the fourth electrode RFE4 can be made of conductive materials that have a fast side etching rate in wet etching processes. (See below for further details.) Figures 19 to 31 Provide a description related to this.

[0169] In one or more embodiments, the third electrode RFE3 and the fourth electrode RFE4 may be made of a material having a higher conductivity than the first electrode RFE1 and the second electrode RFE2 (e.g., a material with low resistivity).

[0170] Here, the materials of the third electrode RFE3 and the fourth electrode RFE4 are not limited to those described above. For example, the third electrode RFE3 and the fourth electrode RFE4 may include conductive materials with constant reflectivity. When the third electrode RFE3 and the fourth electrode RFE4 are made of conductive materials with constant reflectivity, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD can be reflected by the third electrode RFE3 and the fourth electrode RFE4 and travel in the display direction (e.g., the third direction DR3).

[0171] In one or more embodiments, the third electrode RFE3 and the fourth electrode RFE4 may have shapes corresponding to the shapes of the first electrode RFE1 and the second electrode RFE2 (or the first embankment BNK1 and the second embankment BNK2), and may have a constant angle relative to the substrate SUB. Light emitted from the first end EP1 and the second end EP2 of each light-emitting element LD can be reflected by the third electrode RFE3 and the fourth electrode RFE4 and further traveled on the third direction DR3. Therefore, the light output efficiency of the display device can be improved.

[0172] The third electrode RFE3 may include a first opening OP1, and the fourth electrode RFE4 may include a second opening OP2. The first opening OP1 of the third electrode RFE3 can expose the first electrode RFE1. The second opening OP2 of the fourth electrode RFE4 can expose the second electrode RFE2.

[0173] Reference Figure 9 The first opening OP1 may not overlap with the first dam BNK1, and the second opening OP2 may not overlap with the second dam BNK2. For example, each of the first opening OP1 and the second opening OP2 may overlap with the partition wall OBNK. The first opening OP1 may be located between the partition wall OBNK and the substrate SUB, and the second opening OP2 may be located between the partition wall OBNK and the substrate SUB.

[0174] The first electrode RFE1 and the third electrode RFE3 described above can contact each other to form a first pixel electrode, and the second electrode RFE2 and the fourth electrode RFE4 can contact each other to form a second pixel electrode. Here, one of the first pixel electrode and the second pixel electrode can be an anode electrode, and the other of the first pixel electrode and the second pixel electrode can be a cathode electrode. For example, the first pixel electrode can be a cathode electrode, and the second pixel electrode can be an anode electrode. However, this disclosure is not limited to this and may include the opposite situation.

[0175] The first pixel electrode and the second pixel electrode can provide a driving signal to the light-emitting element LD, and the light-emitting element LD can emit light corresponding to the provided driving signal.

[0176] Further reference Figure 4 The first pixel electrode and the second pixel electrode can be electrically connected to either the driving circuit DC or the second driving power supply VSS via separate connection wiring or connection components. For example, the first pixel electrode can be electrically connected to the second driving power supply VSS, and the second pixel electrode can be electrically connected to the driving circuit DC. For example, at least one of the first electrode RFE1 and the third electrode RFE3 can be connected to the second driving power supply VSS, and at least one of the second electrode RFE2 and the fourth electrode RFE4 can be connected to the driving circuit DC. However, the connection relationship between the first pixel electrode and the second pixel electrode is not limited to the above and can include the opposite situation.

[0177] The first pixel electrode and the second pixel electrode can be connected to the first terminal EP1 and the second terminal EP2 of the light-emitting element LD, respectively, to provide a driving signal to the light-emitting element LD. The light-emitting element LD can emit light with a certain brightness (e.g., set brightness or predetermined brightness) in response to the driving current provided from the driving circuit DC.

[0178] A first insulating layer INS1 may be disposed on the third electrode RFE3 and the fourth electrode RFE4. The first insulating layer INS1 may be disposed on the entire surface of the substrate SUB to cover the first dam BNK1 and the second dam BNK2, as well as the first electrode RFE1, the second electrode RFE2, the third electrode RFE3, and the fourth electrode RFE4. In one or more embodiments, the first insulating layer INS1 may be positioned along a surface of the substrate SUB where the first dam BNK1 and the second dam BNK2, as well as the first electrode RFE1, the second electrode RFE2, the third electrode RFE3, and the fourth electrode RFE4 are not positioned. The first insulating layer INS1 may comprise an inorganic material or an organic material. According to an example, the inorganic material may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) xN y ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ) and hafnium oxide (HfO) x Any one of the following: . Organic materials may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and dinaphthalene-containing resin.

[0179] In one or more embodiments, the first insulating layer INS1 may include a first opening OP1 and a second opening OP2. The first opening OP1 may expose at least a portion of the first electrode RFE1. The second opening OP2 may expose at least a portion of the second electrode RFE2.

[0180] The first opening OP1 may have a thickness and / or depth corresponding to the sum of the thickness of the first insulating layer INS1 and the thickness of the third electrode RFE3. For example, the first opening OP1 may penetrate the first insulating layer INS1 and the third electrode RFE3 in the corresponding region.

[0181] The second opening OP2 may have a thickness and / or depth corresponding to the sum of the thickness of the first insulating layer INS1 and the thickness of the fourth electrode RFE4. For example, the second opening OP2 may penetrate the first insulating layer INS1 and the fourth electrode RFE4 in the corresponding region.

[0182] Therefore, at least a portion of each of the first electrode RFE1 and the second electrode RFE2 can be exposed to the outside and can contact the fifth electrode CTE1 and the sixth electrode CTE2, which will be described later.

[0183] The light-emitting element LD can be located on the first insulating layer INS1. The light-emitting element LD can be located in the space provided by the first dike BNK1 and the second dike BNK2. In one or more embodiments, in a plan view, the light-emitting element LD can be located between the third electrode RFE3 and the fourth electrode RFE4. For example, the light-emitting element LD may not overlap with the third electrode RFE3 and the fourth electrode RFE4.

[0184] The first distance W1 between the first electrode RFE1 and the second electrode RFE2, and the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4, can be different from each other. Therefore, steps can be generated between the first electrode RFE1 and the second electrode RFE2, and between the third electrode RFE3 and the fourth electrode RFE4, respectively. The light-emitting element LD can be located in the groove (or light-emitting element region LDA) formed by the steps.

[0185] For example, the first insulating layer INS1 may have steps (e.g., set steps or predetermined steps) along the surfaces of the first electrode RFE1, the second electrode RFE2, the third electrode RFE3 and the fourth electrode RFE4.

[0186] For example, the first insulating layer INS1 located in a region where the first electrode RFE1 and the second electrode RFE2 are not disposed may have a first height 102 from the substrate SUB. In one or more embodiments, the first insulating layer INS1 located in a region where the third electrode RFE3 and the fourth electrode RFE4 are not disposed but the first electrode RFE1 and the second electrode RFE2 are disposed may have a second height 104 from the substrate SUB, the second height 104 being greater than the first height 102.

[0187] The first electrode RFE1 may include a first region 112 not covered by the third electrode RFE3, and the second electrode RFE2 may include a second region 114 not covered by the fourth electrode RFE4. Here, the first end EP1 of the light-emitting element LD may be positioned on the first insulating layer INS1 located in the first region 112, and the second end EP2 of the light-emitting element LD may be positioned on the first insulating layer INS1 located in the second region 114.

[0188] Therefore, the light-emitting element region LDA can be disposed on the first insulating layer INS1, wherein the first electrode RFE1 and the second electrode RFE2 overlap with the portions exposed from the third electrode RFE3 and the fourth electrode RFE4.

[0189] For example, at least a portion of the upper surface of the first electrode RFE1 may be exposed and not covered by the third electrode RFE3, and at least a portion of the upper surface of the second electrode RFE2 may be exposed and not covered by the fourth electrode RFE4. The light-emitting element LD may be located in the area where the first electrode RFE1 and the second electrode RFE2 are exposed (e.g., the light-emitting element region LDA).

[0190] The length WLD of the light-emitting element LD can be greater than the first distance W1 between the first electrode RFE1 and the second electrode RFE2, and can be less than the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4. For example, at least a portion of the first electrode RFE1 and at least a portion of the second electrode RFE2 can overlap with the light-emitting element LD on the third direction DR3, and the third electrode RFE3 and the fourth electrode RFE4 can not overlap with the light-emitting element LD on the third direction DR3.

[0191] An anchoring layer INSA for stably supporting and fixing the light-emitting element LD can be located on the light-emitting element LD. The anchoring layer INSA can be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. The anchoring layer INSA can cover at least a portion of the outer peripheral surface of each light-emitting element LD and can be formed to expose a first end EP1 and a second end EP2 of the light-emitting element LD. Therefore, because the anchoring layer INSA stably supports and fixes the light-emitting element LD, the light-emitting element LD does not need to separate from the substrate SUB. According to one or more embodiments, the anchoring layer INSA can be positioned to fill the space between the light-emitting element LD and the first insulating layer INS1. Depending on the process conditions of the display device, the anchoring layer INSA can be omitted.

[0192] The fifth electrode CTE1 (or the first contact electrode) and the sixth electrode CTE2 (or the second contact electrode) can be located on the first insulating layer INS1, the light-emitting element LD, and the anchoring layer INSA. In addition, the second insulating layer INS2 can be disposed between the fifth electrode CTE1 and the sixth electrode CTE2.

[0193] The fifth electrode CTE1 and the sixth electrode CTE2 can contact one of the two ends EP1 and EP2 of each light-emitting element (LD). For example, the fifth electrode CTE1 can contact the first end EP1 of each LD, and the sixth electrode CTE2 can contact the second end EP2 of each LD. The fifth electrode CTE1 can be electrically connected to the first end EP1 of the LD, and the sixth electrode CTE2 can be electrically connected to the second end EP2 of the LD.

[0194] When viewed in a plane (e.g., in a planar view), the fifth electrode CTE1 may overlap with at least a portion of each of the first electrode RFE1 and the third electrode RFE3.

[0195] The fifth electrode CTE1 can be connected to the first electrode RFE1 through the first opening OP1 formed in the first insulating layer INS1 and the third electrode RFE3. The fifth electrode CTE1 can contact the first electrode RFE1 on the first embankment BNK1. The fifth electrode CTE1 can be in physical contact with at least a portion of the first electrode RFE1.

[0196] The fifth electrode CTE1 can directly receive electrical signals from the first electrode RFE1. At least a portion of the fifth electrode CTE1 can be in physical contact with the first electrode RFE1 and can be directly electrically connected to the first electrode RFE1.

[0197] The sixth electrode CTE2 can be connected to the second electrode RFE2 through the second opening OP2 formed in the first insulating layer INS1 and the fourth electrode RFE4. The sixth electrode CTE2 can contact the second electrode RFE2 on the second embankment BNK2. The sixth electrode CTE2 can be in physical contact with at least a portion of the second electrode RFE2.

[0198] The sixth electrode CTE2 can directly receive electrical signals from the second electrode RFE2. At least a portion of the sixth electrode CTE2 can be in physical contact with the second electrode RFE2 and can be directly electrically connected to the second electrode RFE2.

[0199] According to the example, in the plan view, the area where the fifth electrode CTE1 and the first electrode RFE1 are connected may not overlap with the first embankment BNK1, and the area where the sixth electrode CTE2 and the second electrode RFE2 are connected may not overlap with the second embankment BNK2.

[0200] The region where the fifth electrode CTE1 and the first electrode RFE1 are connected, as well as the region where the sixth electrode CTE2 and the second electrode RFE2 are connected, can be located in the non-emission region NEA.

[0201] The area where the fifth electrode CTE1 and the first electrode RFE1 are connected can be located under the partition wall OBNK arranged in the non-emission region NEA, and the area where the sixth electrode CTE2 and the second electrode RFE2 are connected can be located under the partition wall OBNK arranged in the non-emission region NEA.

[0202] As described above, the fifth electrode CTE1 and the sixth electrode CTE2, configured as contact electrodes for the light-emitting element (LD), can be directly connected to the first electrode RFE1 and the second electrode RFE2, respectively, and can directly receive electrical signals from the first electrode RFE1 and the second electrode RFE2. Therefore, signal loss during its movement along the electrodes can be prevented, and signal distortion can be prevented. This improves the reliability of the display device.

[0203] Each of the fifth electrode CTE1 and the sixth electrode CTE2 can be made of a transparent conductive material. For example, transparent conductive materials may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), and ITZO (indium tin zinc oxide). When the fifth electrode CTE1 and the sixth electrode CTE2 are made of a transparent conductive material, light loss can be reduced as light emitted from the light-emitting element LD travels along the third direction DR3. The materials of the fifth electrode CTE1 and the sixth electrode CTE2 are not limited to the materials described above.

[0204] The second insulating layer INS2 may be located between the fifth electrode CTE1 and the sixth electrode CTE2. For example, the second insulating layer INS2 may comprise an inorganic insulating layer made of an inorganic material. The second insulating layer INS2 may be positioned to cover one of the fifth electrode CTE1 and the sixth electrode CTE2, and the other electrode may be located on the second insulating layer INS2. For example, the second insulating layer INS2 may be located on the fifth electrode CTE1 to cover it. The sixth electrode CTE2 may be located on the second insulating layer INS2. For example, the fifth electrode CTE1 and the sixth electrode CTE2 may be electrically isolated by the second insulating layer INS2.

[0205] However, the arrangement of the fifth electrode CTE1 and the sixth electrode CTE2 is not limited to this. For example, the fifth electrode CTE1 and the sixth electrode CTE2 can be located in the same layer. In this case, the fifth electrode CTE1 and the sixth electrode CTE2 can be formed substantially in parallel (e.g., simultaneously). Therefore, the manufacturing process of the display device can be simplified and the manufacturing cost of the display device can be reduced.

[0206] The third insulating layer INS3 can be located on the fifth electrode CTE1, the sixth electrode CTE2, and the second insulating layer INS2. The third insulating layer INS3 can prevent damage to the first electrode RFE1, the second electrode RFE2, the third electrode RFE3, the fourth electrode RFE4, the fifth electrode CTE1, the sixth electrode CTE2, and the light-emitting element LD during the manufacturing process of the display device, and also serves as a sealing layer to prevent the penetration of oxygen and moisture.

[0207] The third insulating layer INS3 may be formed of an inorganic insulating layer comprising inorganic materials. The third insulating layer INS3 may be formed as a single layer. However, this disclosure is not limited thereto, and the third insulating layer INS3 may include a multilayer structure. When the third insulating layer INS3 includes a multilayer structure, the third insulating layer INS3 may also include an organic insulating layer containing organic materials, and may include a multilayer structure in which organic insulating layers and inorganic insulating layers are alternately positioned.

[0208] The partition wall OBNK may have a structure surrounding at least a portion of the pixel PXL. The partition wall OBNK may have a shape protruding in the display direction of the light-emitting element LD. The partition wall OBNK may define the emission region EMA of the pixel PXL. A region in which the partition wall OBNK is disposed may be included in the non-emission region NEA. The partition wall OBNK may include light-blocking and / or reflective materials to prevent light leakage defects between adjacent pixels PXL. Depending on the manufacturing process of the display device, the partition wall OBNK may be omitted.

[0209] Although not shown in the accompanying drawings, in some embodiments, a planarization layer may also be provided on the third insulating layer INS3. The planarization layer reduces steps created by various configurations located beneath it. The upper surface of the planarization layer is typically flat. The planarization layer may include an organic insulating layer. However, this disclosure is not limited thereto, and the planarization layer may also include an inorganic insulating layer.

[0210] During the alignment of the light-emitting element (LD), an off-center defect may occur when the LD is positioned too close to the first electrode RFE1 or the third electrode RFE3. For example, an off-center defect can be defined as a defect indicating that the center point of the LD deviates from the center between the first electrode RFE1 and the second electrode RFE2. When an off-center defect occurs, the LD may fail to make proper contact with the pixel electrode in subsequent processes, and therefore, may not emit light because a drive signal cannot be provided.

[0211] As described above, a pixel PXL according to one or more embodiments may include a first electrode RFE1 and a second electrode RFE2 spaced apart by a first distance W1, and a third electrode RFE3 and a fourth electrode RFE4 spaced apart by a second distance W2 greater than the first distance W1, and a light-emitting element LD may be located between the steps generated by the first electrode RFE1, the second electrode RFE2, the third electrode RFE3, and the fourth electrode RFE4.

[0212] In this way, the light-emitting element (LD) can be positioned precisely (e.g., between the third electrode RFE3 and the fourth electrode RFE4), and the off-center defect of the LD being positioned too close to the first electrode RFE1 (or the third electrode RFE3) or the second electrode RFE2 (or the fourth electrode RFE4) can be prevented. For example, the reliability of the display device can be improved.

[0213] In the following description, another embodiment of the pixel will be described. In the following embodiment, the same reference numerals are given to the same components as in the foregoing embodiment, and their description will be omitted or simplified, with the differences being described primarily.

[0214] Figure 10 and Figure 11 It could be a diagram showing pixel PXL according to another embodiment. Figure 10 This is a schematic plan view of pixels according to another embodiment of the present disclosure. Figure 11 It is along Figure 10 The sectional view taken from line II-II'.

[0215] According to this embodiment, the position of the first opening OP1 and the position of the second opening OP2 are the same as the positions of each of the openings according to the above embodiment (for example, see...). Figure 9 )different.

[0216] Reference Figure 10 and Figure 11 The first opening OP1 and the second opening OP2 can be located within the launch area EMA. The first opening OP1 and the second opening OP2 may not overlap with the partition wall OBNK. The first opening OP1 may not overlap with the first embankment BNK1, and the second opening OP2 may not overlap with the second embankment BNK2.

[0217] Therefore, the fifth electrode CTE1 can be connected to the first electrode RFE1 in the region where the first dam BNK1 is not located. The sixth electrode CTE2 can be connected to the second electrode RFE2 in the region where the second dam BNK2 is not located.

[0218] Figure 12 This is a schematic plan view of pixels according to yet another embodiment of the present disclosure. Figure 13 It is along Figure 12 A sectional view taken from line III-III'. Figure 12 For ease of description, the structure of pixel PXL is shown schematically.

[0219] According to this embodiment, the position of the first opening OP1 and the position of the second opening OP2 are the same as the positions of each of the openings according to the above embodiment (for example, see...). Figure 9 and Figure 11 )different.

[0220] Reference Figure 12 and Figure 13 The first opening OP1 can overlap with the first dike BNK1, and the second opening OP2 can overlap with the second dike BNK2. The first opening OP1 can be located on the first dike BNK1. The second opening OP2 can be located on the second dike BNK2.

[0221] For example, according to this embodiment, the fifth electrode CTE1 can be connected to the first electrode RFE1 on the first dike BNK1. The sixth electrode CTE2 can be connected to the second electrode RFE2 on the second dike BNK2.

[0222] Figure 14 and Figure 15 It could be a diagram showing the pixel PXL according to yet another embodiment. Figure 14 This is a schematic plan view of pixels according to yet another embodiment of the present disclosure. Figure 15 It is along Figure 14 A sectional view taken along line IV-IV'. Figure 14 For ease of description, the structure of pixel PXL is shown schematically.

[0223] Reference Figure 14 and Figure 15 The first insulating pattern INSP1 and the second insulating pattern INSP2 can be located on the first insulating layer INS1.

[0224] The first insulating pattern INSP1 and the second insulating pattern INSP2 may be spaced apart from each other on the first insulating layer INS1 along the first direction DR1, and may cover at least a portion of the first insulating layer INS1.

[0225] The first insulating pattern INSP1 and the second insulating pattern INSP2 may be positioned to extend to a step formed in the first insulating layer INS1, but this disclosure is not limited thereto. In another embodiment, the first insulating pattern INSP1 and the second insulating pattern INSP2 may be spaced apart from each other along a first direction DR1 at a distance equal to the second distance W2. In another embodiment, the first insulating pattern INSP1 and the second insulating pattern INSP2 may be spaced apart from each other by a distance greater than the second distance W2.

[0226] In one or more embodiments, the first insulating pattern INSP1 and the second insulating pattern INSP2 may extend along the second direction DR2 on a plane.

[0227] Even when the first insulating pattern INSP1 and the second insulating pattern INSP2 are located on the first insulating layer INS1, the first insulating layer INS1 and the third electrode RFE3 may include a first opening OP1 and expose at least a portion of the first electrode RFE1. In one or more embodiments, the first insulating layer INS1 and the fourth electrode RFE4 may include a second opening OP2 and expose at least a portion of the second electrode RFE2.

[0228] The first insulating pattern INSP1 and the second insulating pattern INSP2 can be organic insulating layers comprising organic materials or inorganic insulating layers comprising inorganic materials. When the first insulating pattern INSP1 and the second insulating pattern INSP2 are made of organic insulating layers, the manufacturing process can be simplified.

[0229] According to this embodiment, the height of the step generated in the first insulating layer INS1 can be further increased by using the first insulating pattern INSP1 and the second insulating pattern INSP2. For example, the height of the recess (or light-emitting element region LDA) where the light-emitting element LD is located can be increased, and the region where the light-emitting element LD is located can be further confined between the first insulating pattern INSP1 and the second insulating pattern INSP2. Therefore, it is possible to more effectively prevent the eccentricity defect in which the light-emitting element LD is positioned too close to either side, and the reliability of the display device can be improved.

[0230] Figures 16 to 18It could be a diagram showing the pixel PXL according to yet another embodiment. Figure 16 This is a schematic plan view of pixels according to yet another embodiment of the present disclosure. Figure 17 and Figure 18 It is along Figure 16 A sectional view taken by line V-V'. Figure 16 For ease of description, the structure of pixel PXL is shown schematically.

[0231] In accordance with Figures 16 to 18 In the pixel PXL of the structure, the first dam BNK1 and the second dam BNK2 may not overlap with the first opening OP1 and the second opening OP2, respectively.

[0232] First, refer to Figure 16 and Figure 17 The first opening OP1 may not be located on the first dike BNK1. The first opening OP1 may not overlap with the first dike BNK1. The second opening OP2 may not be located on the second dike BNK2. The second opening OP2 may not overlap with the second dike BNK2.

[0233] When viewed in a plane, the first opening OP1 can be located between the area where the light-emitting element LD is located and the area where the first dam BNK1 is located. When viewed in a plane, the second opening OP2 can be located between the area where the light-emitting element LD is located and the area where the second dam BNK2 is located.

[0234] Therefore, the area where the fifth electrode CTE1 and the first electrode RFE1 contact can be located between the first dam BNK1 and the light-emitting element LD, and similarly, the area where the sixth electrode CTE2 and the second electrode RFE2 contact can be located between the second dam BNK2 and the light-emitting element LD. However, the area where the first electrode RFE1 and the fifth electrode CTE1 contact is not limited to the above example.

[0235] Figure 18 Implementation methods and Figure 17 The difference in the implementation method may be that the first dike BNK1 and the second dike BNK2 are located on the first insulating layer INS1. For example, according to Figure 18 In the structure of the pixel PXL of the embodiment shown, the first barrier BNK1 and the second barrier BNK2 can be formed after the first insulating layer INS1 is formed. In this case, since the first electrode RFE1 to the fourth electrode RFE4 are not located on the first barrier BNK1 or the second barrier BNK2, the electrical reliability can be further improved.

[0236] In the following text, reference will be made to Figures 19 to 31 A method for manufacturing a display device according to one or more embodiments is described.

[0237] Figures 19 to 31 This is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure. Figures 19 to 26 Each of the figures shown can be along Figure 12 A sectional view taken by line III-III', and can be used to describe Figure 12 and Figure 13 The structure shown. Figure 27 The diagram shown is along Figure 14 A sectional view taken by line IV-IV', and can be used to describe Figure 14 and Figure 15 The structure shown. Figures 28 to 31 The diagram shown can be along Figure 16 A cross-sectional view taken by line V-V'. In this case... Figure 28 and Figure 29 It can be used to describe Figure 16 and Figure 17 The diagram shows the structure shown, and Figure 30 and Figure 31 It can be used to describe Figure 16 and Figure 18 The diagram shows the structure.

[0238] refer to Figure 19 A first conductive layer BMT1 and a second conductive layer BMT2 can be sequentially formed on the substrate SUB. The first conductive layer BMT1 and the second conductive layer BMT2 can be formed on the entire surface of the substrate SUB.

[0239] The first conductive layer BMT1 may be a base material for forming the first electrode RFE1 and the second electrode RFE2, and includes transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO).

[0240] The second conductive layer BMT2 can be directly formed on the first conductive layer BMT1. The second conductive layer BMT2 can be the base material for forming the third electrode RFE3 and the fourth electrode RFE4, and includes metals such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, Li, Ca, LiF / Ca, LiF / Al, Mo, Cu or alloys thereof.

[0241] The materials constituting the first conductive layer BMT1 and the second conductive layer BMT2 are not limited to the materials described above. The first conductive layer BMT1 and the second conductive layer BMT2 may include different materials. For example, compared with the first conductive layer BMT1, the second conductive layer BMT2 may be made of a material that has a fast side etching rate in a wet etching process.

[0242] In some embodiments, a first dam BNK1 and a second dam BNK2 may be formed on the substrate SUB before forming the first conductive layer BMT1. The first dam BNK1 and the second dam BNK2 may be spaced apart from each other along a first direction DR1. The space for the light-emitting element LD to be positioned may be disposed between the first dam BNK1 and the second dam BNK2. (Reference) Figure 20 The first conductive layer BMT1 can be etched to form the first electrode RFE1 and the second electrode RFE2, and the second conductive layer BMT2 can be etched to form the first base electrode RFE3a and the second base electrode RFE4a.

[0243] The first conductive layer BMT1 and the second conductive layer BMT2 can be etched using the same etching process (e.g., the first etching process). The first conductive layer BMT1 can be etched to form a first electrode RFE1 and a second electrode RFE2 spaced apart from each other along the first direction DR1 by a first distance W1, and the second conductive layer BMT2 can be etched to form a first base electrode RFE3a and a second base electrode RFE4a spaced apart from each other along the first direction DR1.

[0244] Although not shown in the figure, the photoresist layer used to perform the etching process may be located on the first conductive layer BMT1 and the second conductive layer BMT2. At least a portion of the second conductive layer BMT2 may be exposed through the photoresist layer.

[0245] Figure 20 A structure in which the first conductive layer BMT1 and the second conductive layer BMT2 are etched at the same interval is shown. For example, the first base electrode RFE3a and the second base electrode RFE4a formed by etching the second conductive layer BMT2 can also be separated from each other by a first distance W1, but this disclosure is not limited thereto. As described above, because the side etching rate of the second conductive layer BMT2 can be greater than the side etching rate of the first conductive layer BMT1, the distance between the first base electrode RFE3a and the second base electrode RFE4a can be greater than the first distance W1.

[0246] In one or more embodiments, when the first conductive layer BMT1 includes a transparent electrode material, the first electrode RFE1 and the second electrode RFE2 formed by the etching process can be in an amorphous state.

[0247] Reference Figure 21 The first electrode RFE1 and the second electrode RFE2 can be crystallized by performing a baking process for heating the substrate SUB, and the first base electrode RFE3a and the second base electrode RFE4a can be additionally etched to form the third electrode RFE3 and the fourth electrode RFE4.

[0248] The first conductive layer BMT1 can be etched to form the first electrode RFE1 and the second electrode RFE2, and the second conductive layer BMT2 can be etched to form the first base electrode RFE3a and the second base electrode RFE4a. Afterwards, a baking process for heating the substrate SUB can be performed. The baking process can be performed by heating the substrate SUB at a temperature of 200°C or higher, but the heating temperature is not limited to this, and the heating temperature can be 300°C or higher.

[0249] In this way, the amorphous first electrode RFE1 and second electrode RFE2 can be crystallized. Compared with amorphous electrodes, the crystalline first electrode RFE1 and second electrode RFE2 have improved electronic conduction properties, thus improving electron mobility. Furthermore, the crystalline first electrode RFE1 and second electrode RFE2 do not need to be etched in the etching process described later.

[0250] The first electrode RFE1 and the second electrode RFE2 can be crystallized by a baking process, and the first base electrode RFE3a and the second base electrode RFE4a can be further etched by an additional etching process (e.g., a second etching process). In this case, the photoresist layer on the first base electrode RFE3a and the second base electrode RFE4a can be the same as the photoresist layer used in the first etching process. For example, after the first etching process, the photoresist layer is not removed, and the second etching process can be performed.

[0251] As described above, the first electrode RFE1 and the second electrode RFE2 are not etched, and only the first base electrode RFE3a and the second base electrode RFE4a are etched, so that the third electrode RFE3 and the fourth electrode RFE4 can be formed. The third electrode RFE3 and the fourth electrode RFE4 can be spaced apart from each other along the first direction DR1 by a second distance W2. The second distance W2 can be greater than the first distance W1 between the first electrode RFE1 and the second electrode RFE2.

[0252] The first electrode RFE1 and the second electrode RFE2 can be separated from each other by a first distance W1, and the third electrode RFE3 and the fourth electrode RFE4 can be separated from each other by a second distance W2. Therefore, steps can be created between the first electrode RFE1 and the second electrode RFE2 and between the third electrode RFE3 and the fourth electrode RFE4. These steps can limit the space in which the light-emitting element LD, described later, can be positioned.

[0253] Reference Figure 22A first insulating layer INS1 can be formed. The first insulating layer INS1 can be formed on the entire surface of the substrate SUB. The first insulating layer INS1 can completely cover the components located on the substrate SUB. For example, the first insulating layer INS1 can cover the first electrode RFE1 to the fourth electrode RFE4. As described above, the first insulating layer INS1 can comprise inorganic or organic materials.

[0254] The first insulating layer INS1 can be formed in the shape of a step corresponding to the first electrode RFE1 and the second electrode RFE2 and the third electrode RFE3 and the fourth electrode RFE4, and the light-emitting element region LDA can be disposed between the first step between the first electrode RFE1 and the third electrode RFE3 and the second step between the second electrode RFE2 and the fourth electrode RFE4.

[0255] Reference Figure 23 At least a portion of the first insulating layer INS1 can be removed. At least a portion of the first insulating layer INS1 can be removed by a dry etching process, so that a first opening OP1 and a second opening OP2 can be formed in the first insulating layer INS1.

[0256] The area from which at least a portion of the first insulating layer INS1 is removed may overlap with the area where the fifth electrode CTE1, to be subsequently disposed, contacts the first electrode RFE1. For example, a process for etching the first insulating layer INS1 located in the area where the fifth electrode CTE1 is to be connected to the first electrode RFE1 may be performed. In some embodiments, the area from which at least a portion of the first insulating layer INS1 is removed may overlap with the area where the sixth electrode CTE2, to be subsequently disposed, contacts the second electrode RFE2. For example, a process for etching the first insulating layer INS1 located in the area where the sixth electrode CTE2 is to be connected to the second electrode RFE2 may be performed.

[0257] Reference Figure 24 It is possible to remove at least a portion of each of the third electrode RFE3 and the fourth electrode RFE4. At least a portion of the third electrode RFE3 can be removed such that the first opening OP1 can be included in the third electrode RFE3. At least a portion of the fourth electrode RFE4 can be removed such that the second opening OP2 can be included in the fourth electrode RFE4.

[0258] The process of removing at least a portion of each of the third electrode RFE3 and the fourth electrode RFE4 can be performed simultaneously with the dicing process used to form the pixel electrode.

[0259] In this step, the area from which the third electrode RFE3 is removed may overlap with the location of the first opening OP1 formed in the first insulating layer INS1. In this step, the area from which the fourth electrode RFE4 is removed may overlap with the location of the second opening OP2 formed in the first insulating layer INS1.

[0260] For example, in this step, a process for etching the third electrode RFE3 and the fourth electrode RFE4 can be performed. In this case, the layer located in the region where the first opening OP1 and the second opening OP2 are not formed (e.g., the third electrode RFE3 where the first opening OP1 is not formed) can be covered by the first insulating layer INS1 and can be removed without the etching process.

[0261] According to this procedure, a first opening OP1 can be formed in the first insulating layer INS1 and the third electrode RFE3, and a second opening OP2 can be formed in the first insulating layer INS1 and the fourth electrode RFE4. (Refer to...) Figure 25 The light-emitting element LD can be aligned on the first insulating layer INS1. Before alignment, the light-emitting element LD can be provided in a solution-mixed state. The solution including the light-emitting element LD can be dispensed onto the first insulating layer INS1 using an inkjet printing method.

[0262] In this configuration, a first alignment voltage can be applied to the first electrode RFE1 and the third electrode RFE3, and a second alignment voltage can be applied to the second electrode RFE2 and the fourth electrode RFE4. For example, one of the first and second alignment voltages can be an AC voltage, and the other can be a DC voltage (or ground voltage). Based on the potential difference between the first and second alignment voltages, the light-emitting element (LD) in the solution can be aligned between the first electrode RFE1 and the second electrode RFE2 (or between the third electrode RFE3 and the fourth electrode RFE4).

[0263] In the alignment process, the position of the light-emitting element (LD) can be limited to the light-emitting element region LDA located between the first step of the first electrode RFE1 and the third electrode RFE3 and the second step of the second electrode RFE2 and the fourth electrode RFE4. In this way, a display device with the light-emitting element LD aligned at a precise position can be manufactured.

[0264] In one or more embodiments, the length WLD of the light-emitting element LD can be greater than the first distance W1 between the first electrode RFE1 and the second electrode RFE2, and can be less than the second distance W2 between the third electrode RFE3 and the fourth electrode RFE4. Therefore, at least a portion of the first electrode RFE1 and at least a portion of the second electrode RFE2 can overlap with the light-emitting element LD on the third-direction DR3, respectively, and the third electrode RFE3 and the fourth electrode RFE4 can not overlap with the light-emitting element LD on the third-direction DR3.

[0265] Subsequently, refer to Figure 26 A fifth electrode CTE1 and a sixth electrode CTE2 can be arranged. In this case, the fifth electrode CTE1 can be connected to the first electrode RFE1 through a first opening OP1 formed in the first insulating layer INS1 and the third electrode RFE3. The sixth electrode CTE2 can be connected to the second electrode RFE2 through a second opening OP2 formed in the first insulating layer INS1 and the fourth electrode RFE4. Furthermore, after the fifth electrode CTE1 is arranged and before the sixth electrode CTE2 is arranged, the second insulating layer INS2 can be positioned to cover the fifth electrode CTE1. Thereafter, although not shown in the figure, the third insulating layer INS3 can be located on the entire surface of the second insulating layer INS2 and the sixth electrode CTE2. Therefore, it is possible to manufacture according to Figure 12 and Figure 13 The implementation of the pixel PXL and the display device including the pixel PXL.

[0266] Next, along with Figure 14 and Figure 15 The implementation methods described herein shall be referred together with those described herein. Figure 27 To describe another embodiment of the present disclosure, a method for manufacturing a display device is described.

[0267] like Figure 27 As shown, pixel PXL can be manufactured by further forming a first insulating pattern INSP1 and a second insulating pattern INSP2 on the first insulating layer INS1.

[0268] For example, after forming the first insulating layer INS1 on the first electrode RFE1, the second electrode RFE2, the third electrode RFE3, and the fourth electrode RFE4, the first insulating pattern INSP1 and the second insulating pattern INSP2 can be formed before aligning the light-emitting element LD.

[0269] The first insulating pattern INSP1 and the second insulating pattern INSP2 may be spaced apart from each other on the first insulating layer INS1 along the first direction DR1, and may cover at least a portion of the first insulating layer INS1.

[0270] According to this embodiment, the height of the step generated in the first insulating layer INS1 can be further increased by the first insulating pattern INSP1 and the second insulating pattern INSP2. For example, the height of the groove (or the light-emitting element region LDA) where the light-emitting element LD is located can be increased, and the region where the light-emitting element LD is located can be further confined between the first insulating pattern INSP1 and the second insulating pattern INSP2. Therefore, it is possible to more effectively prevent the eccentricity defect in which the light-emitting element LD is positioned too close to either side, and the reliability of the display device can be improved.

[0271] The first insulating pattern INSP1 and the second insulating pattern INSP2 can be organic insulating layers comprising organic materials or inorganic insulating layers comprising inorganic materials. When the first insulating pattern INSP1 and the second insulating pattern INSP2 are made of organic insulating layers, the manufacturing process of the display device can be simplified.

[0272] Before aligning the light-emitting element (LD), additional steps can be performed to form... Figure 8 The first insulating layer INS1 shown is formed using a dry etching process with first opening OP1 and second opening OP2. The first insulating pattern INSP1 and the second insulating pattern INSP2 can be formed in parallel (e.g., simultaneously) during the process of forming the first opening OP1 and the second opening OP2. For example, when the first insulating pattern INSP1 and the second insulating pattern INSP2 include an organic insulating layer, separate photolithography or etching processes for forming the first insulating pattern INSP1 and the second insulating pattern INSP2 are not required. Therefore, the manufacturing process of the display device can be simplified, and the manufacturing cost of the display device can be reduced.

[0273] Subsequently, although not shown in the figure, processes for positioning the fifth electrode CTE1, the sixth electrode CTE2, the second insulating layer INS2, and the third insulating layer INS3 can be performed separately. Therefore, it is possible to manufacture according to... Figure 14 and Figure 15 The implementation of the pixel PXL and the display device including the pixel PXL.

[0274] Next, along with references Figure 16 and Figure 17 The described implementation methods are referred to together. Figure 28 and Figure 29 To describe a method of manufacturing a display device according to yet another embodiment of the present disclosure.

[0275] refer to Figure 28 A first dam BNK1, a second dam BNK2, first electrodes RFE1 to fourth electrodes RFE4, and a first insulating layer INS1 can be formed on the substrate SUB.

[0276] Subsequently, a dry etching process can be performed to form a first opening OP1 in the first insulating layer INS1 and the third electrode RFE3, and a second opening OP2 in the first insulating layer INS1 and the fourth electrode RFE4. Therefore, the first electrode RFE1 can be exposed through the first opening OP1, and the second electrode RFE2 can be exposed through the second opening OP2.

[0277] In this case, according to this embodiment (for example, see...), Figure 28 The first opening OP1 can be formed so as not to overlap with the first dam BNK1, and the second opening OP2 can be formed so as not to overlap with the second dam BNK2. For example, the first opening OP1 can be located between the first dam BNK1 and the light-emitting element LD, and the second opening OP2 can be located between the second dam BNK2 and the light-emitting element LD.

[0278] Reference Figure 29 A fifth electrode CTE1 and a sixth electrode CTE2 can be formed. In this case, the region where the fifth electrode CTE1 and the first electrode RFE1 are connected can overlap with the first opening OP1. Furthermore, the region where the sixth electrode CTE2 and the second electrode RFE2 are connected can overlap with the second opening OP2. The fifth electrode CTE1 can be connected to the first electrode RFE1 through the first opening OP1, which does not overlap with the first embankment BNK1, and the sixth electrode CTE2 can be connected to the second electrode RFE2 through the second opening OP2, which does not overlap with the second embankment BNK2.

[0279] Subsequently, the second insulating layer INS2 and the third insulating layer INS3 can be positioned. Therefore, it is possible to manufacture according to... Figure 16 and Figure 17 The implementation of the pixel PXL and the display device including the pixel PXL.

[0280] Next, along with references Figure 16 and Figure 18 The described implementation methods are referred to together. Figure 30 and Figure 31 To describe a method of manufacturing a display device according to yet another embodiment of the present disclosure.

[0281] Reference Figure 30 First electrodes RFE1 to fourth electrodes RFE4 and a first insulating layer INS1 can be formed on the substrate SUB. Subsequently, a first dam BNK1 and a second dam BNK2 can be positioned on the first insulating layer INS1. Figure 28 and Figure 29 The implementation methods shown are different, according to Figure 30 and Figure 31 In the embodiment shown, the first dike BNK1 and the second dike BNK2 can be located on the first insulating layer INS1.

[0282] After positioning the first dike BNK1 and the second dike BNK2, a first opening OP1 can be formed in the first insulating layer INS1 and the third electrode RFE3, and a second opening OP2 can be formed in the first insulating layer INS1 and the fourth electrode RFE4.

[0283] However, this disclosure is not limited thereto. According to some embodiments, after forming a first opening OP1 and a second opening OP2 in each of the first insulating layer INS1, the third electrode RFE3, and the fourth electrode RFE4, a first dam BNK1 and a second dam BNK2 can be arranged. In this case, the first opening OP1 can be located between the first dam BNK1 and the light-emitting element LD, and the second opening OP2 can be located between the second dam BNK2 and the light-emitting element LD. For example, according to this embodiment (see, for example, see...), Figures 30 to 31 The first dam BNK1 and the second dam BNK2 can be located on the first insulating layer INS1, but the first opening OP1 can be located between the light-emitting element LD and the first dam BNK1, and the second opening OP2 can be located between the light-emitting element LD and the second dam BNK2.

[0284] Subsequently, refer to Figure 31 The fifth electrode CTE1 can contact the first electrode RFE1 through the first opening OP1, and the sixth electrode CTE2 can contact the second electrode RFE2 through the second opening OP2. In one or more embodiments, by providing a second insulating layer INS2 and a third insulating layer INS3, it is possible to manufacture according to Figure 16 and Figure 18 The implementation of the pixel PXL and the display device including the pixel PXL.

[0285] According to one or more embodiments of the present disclosure, by arranging the light-emitting elements in precise positions, a display device with improved reliability and a method of manufacturing the same can be provided.

[0286] According to another embodiment of this disclosure, a display device with improved reliability of electrical signals and a method of manufacturing the same can be provided.

[0287] The aspects of this disclosure are not limited to the embodiments described above, and those skilled in the art will clearly understand from this disclosure and the accompanying drawings aspects that are not mentioned.

[0288] The above description is merely an illustration of the technical spirit of this disclosure, and those skilled in the art will be able to make various modifications and changes without departing from the basic characteristics of this disclosure. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0289] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to illustrate it. The scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and all technical spirit within the scope of the appended claims should be interpreted as included within the scope of this disclosure.

Claims

1. A display device, including: Substrate; The first electrode and the second electrode are on the substrate and spaced apart from each other by a first distance along a first direction; The third and fourth electrodes are respectively located on the first and second electrodes and are separated from each other by a second distance along the first direction; as well as The light-emitting element is located between the third electrode and the fourth electrode in the plan view. Wherein, the second distance is greater than the first distance, and the length of the light-emitting element in the first direction is greater than the first distance and less than the second distance.

2. The display device according to claim 1, wherein, At least a portion of the first electrode and at least a portion of the second electrode overlap with the light-emitting element.

3. The display device according to claim 1, wherein, The first electrode and the second electrode comprise the same material. The third and fourth electrodes are made of materials different from those of the first and second electrodes. Wherein, the first electrode and the second electrode comprise at least one of indium tin oxide, indium zinc oxide, zinc oxide, and indium tin zinc oxide, and The third electrode and the fourth electrode include at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti and Cu.

4. The display device according to claim 1, wherein, The third electrode is in contact with the first electrode, and the fourth electrode is in contact with the second electrode.

5. The display device according to claim 1, further comprising: A first insulating layer is formed on the third electrode and the fourth electrode; as well as A first insulating pattern and a second insulating pattern are on the first insulating layer and spaced apart from each other along the first direction. The light-emitting element is located on the first insulating layer and between the first insulating pattern and the second insulating pattern.

6. The display device according to claim 5, further comprising: The fifth electrode contacts the first end of the light-emitting element and the first electrode; as well as The sixth electrode contacts the second end of the light-emitting element and the second electrode. The fifth electrode and the sixth electrode are located on the first insulating layer. Wherein, the first insulating layer and the third electrode include a first opening that exposes at least a portion of the first electrode. The first insulating layer and the fourth electrode include a second opening that exposes at least a portion of the second electrode. The fifth electrode is connected to the first electrode through the first opening, and The sixth electrode is connected to the second electrode through the second opening.

7. The display device according to claim 6, further comprising: An anchoring layer on the light-emitting element, The anchoring layer contacts at least a portion of the outer peripheral surface of the light-emitting element and exposes the first end and the second end of the light-emitting element.

8. The display device according to claim 1, further comprising: A first dam is located between the first electrode and the substrate, and overlaps with both the first electrode and the third electrode; as well as The second dam is located between the second electrode and the substrate, and overlaps with both the second electrode and the fourth electrode.

9. The display device according to claim 6, further comprising: The first and second dikes are on the first insulating layer and each has a shape that protrudes in the display direction of the light-emitting element. Wherein, the first opening is located between the first dam and the light-emitting element, and The second opening is located between the second embankment and the light-emitting element.

10. The display device according to claim 1, wherein, At least a portion of the first electrode and at least a portion of the second electrode, located between the substrate and the light-emitting element in the thickness direction of the substrate, are spaced apart from the light-emitting element in the thickness direction of the substrate and overlap with the light-emitting element in the thickness direction of the substrate.

11. A method for manufacturing a display device, the method comprising: A first conductive layer and a second conductive layer are sequentially formed on the substrate; The first conductive layer is etched to form a first electrode and a second electrode spaced apart from each other by a first distance along a first direction, and the second conductive layer is etched to form a third electrode and a fourth electrode spaced apart from each other by a second distance along the first direction; An insulating layer is formed on the third electrode and the fourth electrode; as well as Align the light-emitting element on the insulating layer. Wherein, the second distance is greater than the first distance, and In the plan view, the light-emitting element is aligned between the third electrode and the fourth electrode.

12. The method according to claim 11, wherein, The length of the light-emitting element in the first direction is greater than the first distance and less than the second distance, and Wherein, at least a portion of the first electrode and at least a portion of the second electrode overlap with the light-emitting element.

13. The method according to claim 12, wherein, Forming the first electrode to the fourth electrode includes: Etch the first conductive layer and the second conductive layer; The first and second electrodes are crystallized by performing a baking process for heating the substrate; and The third and fourth electrodes are formed by further etching the already etched second conductive layer.

14. The method of claim 11, further comprising: A first opening is formed in the third electrode and the insulating layer; A second opening is formed in the fourth electrode and the insulating layer; as well as A fifth electrode and a sixth electrode are formed on the insulating layer. The formation of the fifth electrode and the sixth electrode includes: The fifth electrode is brought into contact with the first electrode through the first opening; and The sixth electrode is brought into contact with the second electrode through the second opening.

15. The method of claim 14, further comprising: A first dike and a second dike, each having a shape protruding in the display direction of the light-emitting element, are formed on the insulating layer. Wherein, the first opening is located between the first dam and the light-emitting element, and The second opening is located between the second embankment and the light-emitting element.

16. The method according to claim 11, wherein, The formation of the insulating layer further includes: A first insulating pattern and a second insulating pattern spaced apart from each other along the first direction are formed on the insulating layer, and The light-emitting element is located between the first insulating pattern and the second insulating pattern.

17. A display device, including: Substrate; The first electrode and the second electrode are on the substrate; A third electrode is placed on the first electrode and has a first opening that exposes at least a portion of the first electrode. A fourth electrode, on the second electrode, and having a second opening that exposes at least a portion of the second electrode; The light-emitting element is located between the third electrode and the fourth electrode when viewed on a plane, and is capable of emitting light in the display direction; The fifth electrode has at least a portion electrically connected to one end of the light-emitting element, and the fifth electrode is on the third electrode; as well as A sixth electrode, having at least a portion electrically connected to the other end of the light-emitting element, is located on the fourth electrode. The fifth electrode is connected to the first electrode through the first opening, and The sixth electrode is connected to the second electrode through the second opening.

18. The display device according to claim 17, wherein, The first electrode and the fifth electrode comprise a first material, and Wherein, the second electrode and the sixth electrode comprise a second material, and The first material and the second material include at least one of indium tin oxide, indium zinc oxide, zinc oxide and indium tin zinc oxide.

19. The display device according to claim 17, further comprising: The emission region through which light is emitted; Non-emission region, which is a region different from the emission region; as well as A partition wall, having a shape that protrudes in the display direction and defines the emission area. Wherein, the first opening and the second opening are in the non-emission area, and The first opening and the second opening overlap with the partition wall.

20. The display device according to claim 17, further comprising: The emission region through which light is emitted; Non-emission region, which is a region different from the emission region; as well as A partition wall, having a shape that protrudes in the display direction and defines the emission area. Wherein, the first opening and the second opening are in the non-emission area, and The non-emission region includes the area where at least a portion of the first electrode or the second electrode is cut off.

21. The display device according to claim 17, further comprising: The emission region through which light is emitted; Non-emission region, which is a region different from the emission region; A partition wall having a shape that protrudes in the display direction and defines the emission area; as well as A dam, arranged in the launch area and having a shape that protrudes in the display direction, is provided. Wherein, the first opening and the second opening are in the non-emission area, Wherein, at least a portion of each of the first electrode and the second electrode is located on the embankment, and The first opening and the second opening do not overlap with the dike.

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