Semiconductor device including guard ring

Abstract

A semiconductor device includes a substrate, a guard ring disposed on the substrate and adjacent an edge of the substrate, an integrated circuit structure surrounded by the guard ring and disposed on the substrate, and an insulative material structure disposed on a side surface of the guard ring, wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnect structure disposed on a pair of the plurality of guard contact structures adjacent each other, wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0019003, filed on February 17, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices including a guard ring. Background Technology

[0004] As the demand for high performance, high speed, and / or versatility in semiconductor devices increases, the integration density of semiconductor devices has also increased. When manufacturing semiconductor devices with fine patterns that result in high integration density, it is necessary to achieve patterns with fine widths or fine separation distances. To overcome the limitations of operating characteristics caused by the small size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs), various efforts have been made to develop semiconductor devices, including fin field-effect transistors (FinFETs) with three-dimensional channels. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor device may include: a substrate having a first region, a second region, and a third region, the second region at least partially surrounding the first region, and the third region at least partially surrounding the second region; an integrated circuit structure on the substrate in the first region; a first guard ring disposed on the substrate in the second region and at least partially surrounding the integrated circuit structure; a second guard ring disposed on the substrate in the third region and at least partially surrounding the first guard ring; and an insulating material structure on the side surfaces of the first guard ring and the second guard ring. The integrated circuit structure may include: an active circuit fin disposed on the substrate in the first region, a gate structure intersecting the active circuit fin, a source or drain region disposed adjacent to the side surface of the gate structure on the active circuit fin, a circuit contact structure disposed on the source or drain region, and a circuit interconnect structure disposed on the circuit contact structure. The first protective ring may include: a first protective active structure disposed on the substrate in the second region, a plurality of first protective contact structures disposed on each of the first protective active structures, and a first protective interconnect structure disposed on the plurality of first protective contact structures. The second protective ring may include: a second protective active structure disposed on the substrate in the third region, a second protective contact structure disposed on the second protective active structure, and at least one second protective interconnect structure disposed on the second protective contact structure. The source or drain region may be located between the circuit contact structure and the circuit active fin. Each of the first protective active structures may include first external active fins spaced apart from each other, and first internal active fins spaced apart from each other and disposed between the first external active fins. In each of the first protective active structures, the upper surfaces of a first set of first external active fins and first internal active fins may at least partially overlap with the insulating material structure in the vertical direction, and the upper surfaces of a second set of first external active fins and first internal active fins may contact the plurality of first protective contact structures. In the plan view, the vertical direction can be perpendicular to the upper surface of the substrate.

[0006] According to an exemplary embodiment of the present invention, each of the second protective active structures in the second protective active structure may include: a second external active fin, and a second internal active fin spaced apart from and disposed between the second external active fins. The second protective active structure includes a pair of second protective active structures that are adjacent to and parallel to each other.

[0007] According to an exemplary embodiment of the present invention, a first set of second protective contact structures may contact the second internal active fin, and the first set of second protective contact structures may be spaced apart from the second external active fin adjacent to the second internal active fin. A second set of second protective contact structures may contact both the second internal active fin and the second external active fin.

[0008] According to an exemplary embodiment of the present invention, the upper surface of the active fin that at least partially overlaps with the insulating material structure in the vertical direction among the first external active fin and the first internal active fin can be positioned at a higher level than the upper surface of the active fin that contacts the plurality of first protective contact structures.

[0009] According to an exemplary embodiment of the present invention, the height difference between the lower and upper surfaces of each of the plurality of first protective contact structures may be greater than the height difference between the lower and upper surfaces of the circuit contact structure. The upper surface of each of the plurality of first protective contact structures and the upper surface of the circuit contact structure may be disposed at the same level.

[0010] According to an exemplary embodiment of the present invention, the distance between one of the first internal active fins that are adjacent to each other and one of the first external active fins may be less than the distance between the first internal active fins that are adjacent to each other.

[0011] According to an exemplary embodiment of the present invention, in one of the first protective active structures, the upper surface of the first inner active fin can contact the plurality of first protective contact structures respectively, and the upper surface of the first outer active fin can at least partially overlap the insulating material structure in the vertical direction.

[0012] According to an exemplary embodiment of the present invention, the first protective interconnect structure may contact the upper surface of each of the plurality of first protective contact structures. The first protective interconnect structure may at least partially overlap with the insulating material structure disposed between the plurality of first protective contact structures in the vertical direction.

[0013] According to an exemplary embodiment of the present invention, each of the plurality of first protective contact structures may include: an upper region having a maximum width in the range of about 50 nm to about 60 nm and configured to be adjacent to the first protective interconnect structure; and a lower region having a maximum width in the range of about 30 nm to about 40 nm and configured to be adjacent to the first protective active structure.

[0014] According to an exemplary embodiment of the present invention, the insulating material structure may include: an isolation region disposed on the side surfaces of the first protective active structure and the second protective active structure; a first protective layer disposed on the isolation region and covering the first protective active structure and the second protective active structure; and a second protective layer covering the first protective layer. Each of the first protective contact structure and the second protective contact structure may contact the first protective layer and the second protective layer.

[0015] According to an exemplary embodiment of the present invention, the semiconductor device may further include: a wire that overlaps with the first protective ring, the second protective ring, and the insulating material structure in the vertical direction; and a plurality of vias that are respectively connected to the first protective interconnect structure and the second protective interconnect structure and disposed below the wire.

[0016] According to an exemplary embodiment of the present invention, the first protective ring may have a shape in which rectangular regions are repeatedly arranged adjacent to each other in a plan view, and the second protective ring may have an uneven shape in a plan view.

[0017] According to an exemplary embodiment of the present invention, the first protective ring having a bent shape may surround the corner portion of the first region, and the second protective ring having a bent shape may surround the corner portion of the second region.

[0018] According to an exemplary embodiment of the present invention, at least a portion of the first protective active structure and the second protective active structure may include a semiconductor stack structure in which silicon layers and silicon-germanium layers are repeatedly stacked.

[0019] According to an exemplary embodiment of the present invention, a semiconductor device may include: a substrate; a protective ring disposed on the substrate and adjacent to an edge of the substrate; an integrated circuit structure surrounded by the protective ring and disposed on the substrate; and an insulating material structure disposed on a side surface of the protective ring. The integrated circuit structure may include: active circuit fins disposed on the substrate, a gate structure intersecting the active circuit fins, a source or drain region on the active circuit fins and adjacent to a side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnect structure disposed on the circuit contact structure. The protective ring may include: a plurality of protective active structures on the substrate, a plurality of protective contact structures disposed on each of the plurality of protective active structures, and a protective interconnect structure disposed on a pair of adjacent protective contact structures among the plurality of protective contact structures. The source or drain region may be disposed between the circuit contact structure and the active circuit fins. Each of the plurality of protective active structures may include a plurality of protective active fins spaced apart from each other. In each of the plurality of active protective structures, the upper surface of the first group of the plurality of active protective fins may at least partially overlap with the insulating material structure in the vertical direction, and the upper surface of the second group of the plurality of active protective fins may contact the plurality of protective contact structures. The vertical direction may be perpendicular to the upper surface of the substrate.

[0020] According to an exemplary embodiment of the present invention, the protective interconnect structure may at least partially overlap with the pair of protective contact structures and the insulating material structure. The insulating material structure may be disposed between the pair of protective contact structures in the vertical direction.

[0021] According to an exemplary embodiment of the present invention, the width of each of the plurality of protective contact structures may be greater than the width of each of the circuit active fins. Each of the plurality of protective contact structures may contact one of the protective active fins in a pair of adjacent protective active fins, and may be spaced apart from the other protective active fin in the pair of protective active fins.

[0022] According to an exemplary embodiment of the present invention, a semiconductor device may include: a substrate; an integrated circuit structure disposed on the substrate; a guard ring disposed on the substrate and at least partially surrounding the integrated circuit structure; and an insulating material structure on a side surface of the guard ring. The integrated circuit structure may include: active circuit fins disposed on the substrate, a gate structure intersecting the active circuit fins, a source or drain region disposed on the active circuit fins adjacent to a side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnect structure disposed on the circuit contact structure. The guard ring may include: a guard active structure comprising a plurality of spaced-apart guard active fins disposed on the substrate, spaced-apart guard contact structures, and guard interconnect structures disposed on the guard contact structures. The source or drain region may be disposed between the circuit contact structure and the active circuit fins. The guard interconnect structure may contact the guard contact structure. The guard active structure may contact the guard contact structure. The plurality of protective active fins may include a pair of protective active fins adjacent to each other, wherein one of the protective active fins in the pair is in contact with one of the protective contact structures, and the other of the protective active fins in the pair is not in contact with the protective contact structure.

[0023] According to an exemplary embodiment of the present invention, the insulating material structure may include: an isolation region disposed on the side surface of the plurality of protective active fins; a protective layer disposed on the isolation region; and an interlayer insulating layer disposed on the protective layer. The protective layer may cover the upper surface of the protective active fins that are not in contact with the protective contact structure.

[0024] According to an exemplary embodiment of the present invention, the two opposing side surfaces of the protective interconnect structure may at least partially overlap with the upper surface of the adjacent protective contact structure in the vertical direction. The region between the two side surfaces of the protective interconnect structure may at least partially overlap with the insulating material structure in the vertical direction. The vertical direction is perpendicular to the upper surface of the substrate. Attached Figure Description

[0025] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0027] Figure 2AThis is a partially enlarged view of the protective ring of a semiconductor device according to an exemplary embodiment of the present invention.

[0028] Figure 2B This is a partially enlarged view of the protective ring of a semiconductor device according to an exemplary embodiment of the present invention.

[0029] Figure 3A This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention.

[0030] Figure 3B This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention.

[0031] Figure 4 This is a partial enlarged view of a semiconductor device according to an exemplary embodiment of the present invention.

[0032] Figures 5A to 5D This is a cross-sectional view of a semiconductor device according to some exemplary embodiments conceived in accordance with the present invention.

[0033] Figures 6A to 6F This is a cross-sectional view illustrating a protective ring of a semiconductor device according to some exemplary embodiments conceived in accordance with the present invention.

[0034] Figures 7A to 7C This is a partially enlarged view illustrating a protective ring of a semiconductor device according to some exemplary embodiments conceived in accordance with the present invention.

[0035] Figures 8A to 8C This is a partially enlarged view showing the edge portion of the protective ring of a semiconductor device according to some exemplary embodiments of the present invention.

[0036] Figures 9A to 15B This is a process flow diagram illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention. Detailed Implementation

[0037] Here it will be understood that when a layer element is referred to as being “on”, “connected to”, or “coupled to” another element, the element may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be an intermediate element or layer.

[0038] Throughout the specification, the same reference numerals may refer to the same elements. In the drawings, the thickness of layers, films, or regions may be exaggerated for clarity.

[0039] The term "and / or" includes any and all combinations of one or more of the related listed items.

[0040] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements are not necessarily limited to these terms. These terms are used only to distinguish one component from others. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0041] Additionally, terms such as "below," "under," "above," and "over" are used to explain the relationships between components or elements shown in the accompanying drawings. These terms are intended as relative concepts and are described based on the directions shown in the drawings.

[0042] In the following description, exemplary embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0043] Reference Figures 1 to 3B Describe a semiconductor device. Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 2A yes Figure 1 A magnified view of region 'A' in the image. Figure 2B yes Figure 1 A magnified view of region 'B' in the image. Figure 3A It is along Figure 2A The cross-sectional view taken from line I-I' in the diagram. Figure 3B It is along Figure 2B The cross-sectional view taken from line II-II' in the diagram.

[0044] Reference Figures 1 to 3B The semiconductor device 10 may include a substrate 101 having a first region R1, a second region R2, and a third region R3, and an integrated circuit structure 100 on the substrate 101 in the first region R1 (see [link to documentation]). Figure 4 The semiconductor device 10 includes a first protective ring 200 on the substrate 101 in the second region R2 and a second protective ring 300 on the substrate 101 in the third region R3. The first region R1 may be the central region of the substrate 101, the second region R2 may surround the first region R1, and the third region R3 may surround the second region R2. The semiconductor device 10 may include insulating material structures 110, 112, 114, 181, 182, 183, and 184 on the side surfaces of the first protective ring 200 and the second protective ring 300. The insulating material structures 110, 112, 114, 181, 182, 183, and 184 include an isolation region 110, a first protective layer 112 and a second protective layer 114, and first to fourth interlayer insulating layers 181, 182, 183, and 184.

[0045] The substrate 101 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate 101 may be configured as a bulk wafer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0046] According to an embodiment of the present invention, the first protective ring 200 may have a rectangular shape. However, the shape of the first protective ring 200 is not limited to this, and the first protective ring 200 may have any shape, as long as the first protective ring 200 can surround the integrated circuit structure 100 of the first region R1. The first protective ring 200 may include a plurality of first protective rings 200 arranged side by side on the outside of the first region R1 away from the center of the first region R1. However, the present disclosure is not limited thereto, and as... Figure 7A As shown, the first protective ring 200 has a repeating pattern and can be configured to surround the first region R1. The first protective ring 200 can be adjacent to the edge of the substrate 101.

[0047] The first protective ring 200 may include a first protective active fin 205 surrounding a first region R1 and extending over a second region R2, a first protective contact structure CA1 on the first protective active fin 205, and a first protective interconnect structure CM1 on the first protective contact structure CA1.

[0048] The first protective active fin 205 may have a fin structure and may be defined by an isolation region 110 in the substrate 101. The first protective active fin 205 may have a structure that protrudes from the substrate 101. The upper end of the first protective active fin 205 may protrude from the upper surface of the isolation region 110 to a predetermined height. The first protective active fin 205 may be formed as part of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The first protective active fin 205 may have a circuit active fin 105 (see reference) of the integrated circuit structure 100. Figures 4 to 5C The width, height, and spacing of the fins may be different or the same. For example, the first protective active fin 205 may have a larger width than the circuit active fin 105 of the integrated circuit structure 100.

[0049] In the first protective active fin 205, a pair of adjacent first protective active fins 205 may include one first protective active fin 205 that can contact one of the first protective contact structures CA1, and another first protective active fin 205 that can not contact the first protective contact structure CA1.

[0050] In the first protective active fin 205, multiple first protective active fins 205 can be arranged side by side. The multiple first protective active fins 205 arranged side by side can, together with the first protective active region 202, form a first protective active structure RX1. Multiple first protective active structures RX1 can be arranged side by side. The first protective active structure can be designated as RX1' in the accompanying drawings (see figure). Figure 7A ).

[0051] In one of the multiple first protective active structures RX1, the upper surface of the first internal active fin 205a and the first protective contact structure CA1 can be in contact with each other, and the upper surface of the first external active fin 205b can at least partially overlap with the insulating material structures 110, 112, 114, 181, 182, 183 and 184 in the vertical direction. The vertical direction can be a direction perpendicular to the upper surface of the substrate 101, for example, the Z direction.

[0052] The first protective active structure RX1 may include first external active fins 205b spaced apart from each other, and first internal active fins 205a spaced apart from each other between the first external active fins 205b. In each first protective active structure RX1, the upper surfaces of some of the first external active fins 205b and the first internal active fins 205a may at least partially overlap with insulating material structures 110, 112, 114, 181, 182, 183, and 184 in the vertical direction (Z direction). The upper surfaces of the remaining protective active fins in the first external active fins 205b and the first internal active fins 205a may contact the first protective contact structure CA1.

[0053] According to an embodiment of the present invention, in the first external fin 205b and the first internal active fin 205a, the upper surface of the protective active fin that overlaps with the insulating material structures 110, 112, 114, 181, 182, 183 and 184 in the vertical direction (Z direction) can be positioned at a higher level than the upper surface of the protective active fin that contacts the contact structure CA1.

[0054] The distance between the first internal active fin 205a and the adjacent first external active fin 205b can be smaller than the distance between adjacent first internal active fins 205a.

[0055] According to an exemplary embodiment of the present invention, the first protective active structure RX1 may include a single protective active fin or multiple protective active fins, and the number, arrangement, width and spacing of the active fins are not limited to those shown in the figures.

[0056] The isolation region 110 can be configured to have first protective active fins 205 disposed on the substrate 101. The isolation region 110 can be formed by, for example, a shallow trench isolation (STI) process. The isolation region 110 can expose the upper sidewalls of the first protective active fins 205. According to an exemplary embodiment, the isolation region 110 can include a deep isolation region 111 extending deeper between the first protective active fins 205 into the lower portion of the substrate 101. The isolation region 110 can have a curved upper surface with a higher level in the direction toward the first protective active fins 205. However, the shape of the upper surface of the isolation region 110 is not limited thereto. The isolation region 110 can be formed of an insulating material. The isolation region 110 can include, for example, oxides, nitrides, or combinations thereof.

[0057] The first protective contact structure CA1 can be configured to include a plurality of first protective contact structures CA1. The plurality of first protective contact structures CA1 can be disposed on each of the first protective active structures RX1. Each first protective contact structure CA1 can penetrate the first interlayer insulation layer 181 to contact at least two of the first inner active fin 205a and the first outer active fin 205b. The first protective contact structures CA1 can be spaced apart from each other in the X direction to contact the first inner active fin 205a respectively. The first protective contact structure CA1 can contact the first protective active fin 205 by recessing the upper portion of the first protective active fin 205. The lower end of the first protective contact structure CA1 can be disposed below the uppermost end of the first protective fin 205. The first protective contact structure CA1 can have inclined side surfaces, wherein the width of the lower portion is narrower than the width of the upper portion according to the aspect ratio, but this disclosure is not limited thereto.

[0058] The height difference between the lower and upper surfaces of the first protective contact structure CA1 can be greater than that of the circuit contact structure CA (refer to...). Figure 4 The height difference between the lower and upper surfaces of the first protective contact structure CA1 and the upper surface of the circuit contact structure CA can be set at the same level.

[0059] The first protective contact structure CA1 can be configured to overlap at least a portion of the first protective active fin 205 in a direction perpendicular to the upper surface of the substrate 101. In a plan view, the first protective contact structure CA1 can have a shape corresponding to the first protective active fin 205. For example, when the first protective active fin 205 has the shape of a line extending in one direction (e.g., the Y direction), the first protective contact structure CA1 can also overlap at least a portion of the first protective active fin 205 and can have the shape of a line extending in the Y direction.

[0060] A pair of first protective contact structures CA1 can be formed on a first protective active structure RX1. For example, a single first protective active structure RX1 may include at least two active fins, and a pair of first protective contact structures CA1 may be respectively connected to adjacent first protective active fins 205. Each of the first protective contact structures CA1 may contact one of the adjacent pair of first protective active fins 205, and may be spaced apart from the other active fin.

[0061] Reference Figure 3A The first protective active structure RX1 may include, for example, four active fins. The four active fins may be a first active fin, a second active fin, a third active fin, and a fourth active fin arranged sequentially from left to right in the X direction. However, this disclosure is not limited thereto. According to exemplary embodiments of the present invention, the first protective active structure RX1 may include a single active fin or multiple active fins, and the number of active fins may vary. In an exemplary embodiment, a pair of first protective contact structures CA1 may be connected to the second and third active fins, respectively. According to an embodiment, a first interlayer insulating layer 181 may be disposed between the pair of first protective contact structures CA1 and between the second and third active fins below the first protective interconnect structure CM1.

[0062] The distance in the X-direction between the center of the first active fin and the center of the second active fin is referred to as the first spacing P1. The first spacing P1 can be the same as the distance in the X-direction between the center of the third active fin and the center of the fourth active fin. The distance in the X-direction between the center of the second active fin and the center of the third active fin can be referred to as the second spacing P2. According to an embodiment of the present invention, the second spacing P2 can be greater than the first spacing P1.

[0063] The width of the lower end of the first protective contact structure CA1 in the X direction can be referred to as the first width W1. The width of the upper end of the first protective contact structure CA1 in the X direction can be referred to as the second width W2. The second width W2 can be greater than the first width W1. According to an embodiment of the present invention, the first width W1 can be greater than the width of each first protective active fin 205. The first width W1 of the first protective contact structure CA1 can be less than the first spacing P1 and the second spacing P2. However, the present disclosure is not limited thereto, and the first width W1 of the first protective contact structure CA1 can be greater than the first spacing P1 and less than the second spacing P2. According to an embodiment of the present invention, the width of each first protective contact structure CA1 can be greater than the width of each circuit active fin 105.

[0064] In an exemplary embodiment of the present invention, the first protective contact structure CA1 may have an upper region configured to be adjacent to the first protective interconnect structure CM1 and a lower region configured to be adjacent to the first protective active structure RX1, wherein the maximum width of the upper region is in the range of approximately 50 nm to approximately 60 nm and the maximum width of the lower region is in the range of approximately 30 nm to approximately 40 nm.

[0065] The size of the first protective contact structure CA1 can be the same as that of the circuit contact structure CA of the integrated circuit structure 100 (refer to...). Figures 4 to 5C The dimensions of the first protective contact structure CA1 and the circuit contact structure CA can differ. For example, the size of the first protective contact structure CA1 can be larger than the size of the circuit contact structure CA. In an exemplary embodiment, reference is made to... Figure 5B The circuit contact structure CA may have an upper region that is configured to be adjacent to the circuit interconnect structure CM1a and a lower region that is configured to be adjacent to the circuit active fin 105. The maximum width of the upper region is in the range of about 10 nm to about 30 nm, and the maximum width of the lower region is in the range of about 10 nm to about 15 nm.

[0066] When a pair of first protective contact structures CA1 are formed on a first protective active structure RX1, the first protective contact hole GH1 used to form the first protective contact structure CA1 (see...) Figure 13A The size of ) can be reduced. Therefore, it is possible to prevent ) Figure 13A The insulating residue generated during the etching process is deposited in the first protective contact hole GH1 and can prevent poor contact between the first protective contact structure CA1 and the first protective active fin 205.

[0067] The first protective contact structure CA1 may include a first protective barrier layer 254 and a first protective contact plug 255. The first protective barrier layer 254 may surround the first protective contact plug 255. The first protective barrier layer 254 may cover the side surface and the lower surface of the first protective contact plug 255. The first protective barrier layer 254 may be disposed between the first protective active fin 205 and the first protective contact plug 255.

[0068] The first protective barrier layer 254 may be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first protective contact plug 255 may be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0069] Protective layers 112 and 114 may be disposed on the side surface of the first protective ring 200. Protective layers 112 and 114 may conformally cover the first protective active fin 205 and the isolation region 110. Protective layers 112 and 114 may include a first protective layer 112 covering the first protective active fin 205 and the isolation region 110, and a second protective layer 114 covering the first protective layer 112. According to an exemplary embodiment of the present invention, protective layers 112 and 114 may be disposed on the side surfaces of the first protective active structure RX1 and the second protective active structure RX2. During the fabrication of the integrated circuit structure 100 in the first region R1, protective layers 112 and 114 may be used to protect the first protective active fin 205 and the second protective active fin 305 in the second region R2 and the third region R3. In one embodiment of the present invention, the first protective layer 112 may be disposed on the isolation region 110 and may cover the first protective active structure RX1 and the second protective active structure RX2.

[0070] Each of the first protective contact structure CA1 and the second protective contact structure CA2 may contact protective layers 112 and 114. At least a portion of protective layers 112 and 114 may contact the lower end of the first protective contact structure CA1. The first interlayer insulation layer 181 may at least partially cover protective layers 112 and 114. Protective layers 112 and 114 may cover the upper surface of the first protective active fin 205 that is not in contact with the first protective contact structure CA1.

[0071] Protective layers 112 and 114 may be formed of oxides, nitrides, or oxide oxynitrides. For example, protective layers 112 and 14 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. In an exemplary embodiment, the first protective layer 112 may include silicon oxide, and the second protective layer 114 may include silicon nitride. The second protective layer 114 may include an etch stop layer 135 (see [link to documentation]) of the integrated circuit structure 100. Figure 5B The same material.

[0072] In embodiments of the present invention, the gate structure extending across the first protective active fin 205 and the second protective active fin 305 may not be disposed on the second region R2 and the third region R3. Gate structure 140 (see reference) Figures 4 to 5C It can be set to extend across the active fin 105 only in the first region R1.

[0073] The first protective interconnect structure CM1 can electrically connect a pair of first protective contact structures CA1 via the second interlayer insulation layer 182. The first protective interconnect structure CM1 may have inclined side surfaces, wherein the width of the lower portion is narrower than the width of the upper portion according to the aspect ratio. However, this disclosure is not limited thereto. The first protective interconnect structure CM1 may contact the upper surface of the first protective contact structure CA1. The first protective interconnect structure CM1 may at least partially overlap with the insulating material structures 110, 112, 114, and 181 disposed between the first protective contact structures CA1 in the Z direction.

[0074] The first interlayer insulation layer 181 may be disposed between a pair of first protective contact structures CA1 below the first protective interconnect structure CM1. At least a portion of the lower end of the first protective interconnect structure CM1 may contact the upper surface of the first interlayer insulation layer 181.

[0075] The two opposing side surfaces of the first protective interconnect structure CM1 may at least partially overlap with the upper surface of the adjacent first protective contact structure CA1 in the vertical direction (Z direction). The area between the two side surfaces of the first protective interconnect structure CM1 may overlap with the insulating material structures 110, 112, 114 and 181 in the vertical direction (Z direction).

[0076] The first protective interconnect structure CM1 may include a first conductive barrier layer 264 and a first protective interconnect layer 265. The first conductive barrier layer 264 may surround the first protective interconnect layer 265. According to an embodiment of the present invention, the first conductive barrier layer 264 may surround the side surface and the bottom surface of the first protective interconnect layer 265.

[0077] The first conductive barrier layer 264 may be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first protective interconnect layer 265 may be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0078] In embodiments of the present invention, a first via 271 on the first protective interconnect structure CM1 of the first protective ring 200 and a first conductor 281 on the first via 271 may also be provided. The first conductor 281 may overlap with the first protective ring 200 and the second protective ring 300, as well as the insulating material structures 110, 112, 114, 181, 182, and 183 in the vertical direction (Z direction). The first via 271 may be connected below the first conductor 281 to each of the first protective interconnect structure CM1 and the second protective interconnect structure CM2.

[0079] The first conductor 281 and other upper interconnects connected to the first conductor 281 may not be electrically connected to other upper interconnects on the integrated circuit structure 100. Current flowing to the first conductor 281 and other upper interconnects connected to the first conductor 281 can be grounded to the substrate 101 through a first protective ring 200 including a first protective active fin 205, a first protective contact structure CA1, and a first protective interconnect structure CM1. Therefore, electrostatic current that may flow into the integrated circuit structure 100 from the outside can be significantly reduced, and damage to the integrated circuit structure 100 can be prevented.

[0080] According to an embodiment of the present invention, the second protective ring 300 may be rectangular. However, the shape of the second protective ring 300 is not limited to this, and the second protective ring 300 may have any shape, as long as it can surround the first protective ring 200 of the second region R2.

[0081] The second protective ring 300 can be configured to have multiple second protective rings. The second protective rings 300 can be arranged with more lines than the first protective ring 200, and can be arranged more densely than the first protective ring 200. The second protective rings 300 can be arranged side-by-side outside the first region R1, away from the center of the first region R1. However, this disclosure is not limited thereto, and as... Figure 7B or Figure 7C As shown, the second protective ring 300 can be formed with a repeating uneven shape. The second protective ring 300 can be adjacent to the edge of the substrate 101.

[0082] In an exemplary embodiment of the present invention, 'n' first protective rings 200 may be arranged side-by-side on the second region R2, and 'm' second protective rings 300 may be arranged side-by-side on the third region R3. According to the embodiment, 'm' may be greater than 'n'. In the present invention, 'n' represents the number of first protective rings 200, and 'm' represents the number of second protective rings 300.

[0083] The second protective ring 300 may include a second protective active fin 305 extending on the third region R3, a second protective contact structure CA2 on the second protective active fin 305, and a second protective interconnect structure CM2 on the second protective contact structure CA2. The second protective contact structure CA2 may be connected to the second protective active fin 305 via a first interlayer insulating layer 181. The second protective interconnect structure CM2 may be connected to the second protective contact structure CA2 via a second interlayer insulating layer 182.

[0084] Reference Figure 3B Some of the second protective rings 300a may have the same (or similar) structure as the first protective ring 200.

[0085] For example, multiple second protective active fins 305 may together with the second protective active region 302 constitute a second protective active structure RX2. The second protective active structure RX2 may include a second outer active fin 305b and a second inner active fin 305a between the second outer active fins 305b. Each of the second protective contact structures CA2 may be spaced apart from each other to contact the second inner active fin 305a respectively. The second protective active structure RX2 may include a pair of second protective active structures RX2 that are adjacent to and parallel to each other. In some places throughout the specification, the second protective active structure may be designated as RX2' (see reference). Figure 7B , Figure 7C ).

[0086] According to an embodiment of the present invention, the second protective contact structure CA2 may include a second protective barrier layer 354 and a second protective contact plug 355, and the second protective interconnect structure CM2 may include a second conductive barrier layer 364 and a second protective interconnect layer 365.

[0087] According to an embodiment of the present invention, a single second protective interconnect structure CM2 or multiple second protective interconnect structures CM2 may be disposed on the second protective contact structure CA2.

[0088] In the second protective active fin 305, the second protective contact structure CA2, and the second protective interconnect structure CM2 of the second protective ring 300, the elements corresponding to the first protective active fin 205, the first protective contact structure CA1, and the first protective interconnect structure CM1 will be indicated by the same or similar reference numerals as those in the first protective ring 200, or if the description of the element has been omitted, it can be assumed that the description is at least similar to the description of the corresponding element that has been described elsewhere in this specification.

[0089] However, the second protective ring 300 may include a greater number of active protective fins than the first protective ring 200. For example, the number of second active protective structures RX2 may be greater than the number of first active protective structures RX1. The number of second protective contact structures CA2 may be greater than the number of first protective contact structures CA1.

[0090] Reference Figure 3B The remaining second protective rings 300b in the second protective ring 300 may have a structure different from that of the first protective ring 200. The remaining second protective rings 300b in the second protective ring 300 may include a third protective contact structure CA3 and a third protective interconnection structure CM3.

[0091] Unlike the second protective contact structure CA2, the third protective contact structure CA3 can be connected to all the second protective active fins 305 constituting a single second protective active structure RX2. For example, the second protective contact structure CA2 can contact the second inner active fin 305a and can be spaced apart from the second outer active fin 305b adjacent to the second inner active fin 305a, while the third protective contact structure CA3 can contact both the second inner active fin 305a and the second outer active fin 305b.

[0092] Unlike the second protective interconnect structure CM2, the third protective interconnect structure CM3 can be connected to the third protective contact structure CA3.

[0093] The third protective contact structure CA3 may include a third protective barrier layer 454 and a third protective contact plug 455, and will be indicated by the same or similar reference numerals as the second protective barrier layer 354 and the second protective contact plug 355, or if a description of an element has been omitted, it may be assumed that the description is at least similar to the description of the corresponding element that has been described elsewhere in this specification.

[0094] The third protective interconnect structure CM3 may include a third conductive barrier layer 464 and a third protective interconnect layer 465, and will be indicated by the same or similar reference numerals as the second conductive barrier layer 364 and the second protective interconnect layer 365, respectively. Alternatively, if a description of an element has been omitted, it may be assumed that the description is at least similar to the description of the corresponding element that has been described elsewhere in this specification.

[0095] In embodiments of the present invention, a second via 272 and a second conductor 282 on the second protective interconnect structure CM2 of the second protective ring 300 may also be provided. The second via 272 may be disposed on the second protective interconnect structure CM2. The second conductor 282 and other upper interconnects connected to the second conductor 282 may not be electrically connected to other upper interconnects on the integrated circuit structure 100.

[0096] In an embodiment of the present invention, the third via 273 may be disposed on the third protective interconnect structure CM3 of the second protective ring 300. The second conductor 282 may be disposed on the third via 273. The second conductor 282 and other upper interconnects connected to the second conductor 282 may not be electrically connected to other upper interconnects on the integrated circuit structure 100.

[0097] After multiple semiconductor devices are fabricated on a wafer using a second protective ring 300 including a second protective active fin 305, a second protective contact structure CA2, and a second protective interconnect structure CM2, an integrated circuit including multiple transistors can be protected to prevent moisture from penetrating into the integrated circuit or to prevent cracking in the integrated circuit.

[0098] In an embodiment of the present invention, Figure 2B and Figure 3B The number of each of the second protective rings 300a and 300b arranged in the middle can be varied. The second protective ring 300a including the second protective contact structure CA2 and the second protective ring 300b including the third protective contact structure CA3 can each include multiple second protective rings, or only one of the second protective rings 300a and 300b can include multiple second protective rings.

[0099] Reference Figures 4 to 5C Describe the integrated circuit structure of a semiconductor device. Figure 4 yes Figure 1 A magnified view of region 'C' in the image. Figure 5A It is along Figure 4 The cross-sectional view taken from line III-III' in the diagram. Figure 5B It is along Figure 4 The cross-sectional view taken from line IV-IV' in the diagram. Figure 5C It is along Figure 4 The cross-sectional view taken from line V-V' in the diagram.

[0100] Reference Figures 4 to 5C The integrated circuit structure 100 of the semiconductor device 10 may include an active circuit fin 105 on a substrate 101 in the first region R1, an isolation region 110 defining the active circuit fin 105, a gate structure 140 extending across the active circuit fin 105, and a source / drain region 130 on the active circuit fin 105 adjacent to the side surface of the gate structure 140.

[0101] In the integrated circuit structure 100, the active circuit fin 105 may be a FinFET, wherein the channel region of the transistor is formed in the active circuit fin 105 intersecting with the gate structure 140. The active circuit fin 105 may be disposed on the active region 102 in the integrated circuit structure 100. The active region 102 may be defined by a deep isolation region 111. The active region 102 may extend in the X direction. The active circuit fin 105 may protrude from the active region 102 in the Z direction. In the structure of the active circuit fin 105, portions identical in structure to the first protective active fin 205 will be indicated by the same or similar reference numerals, or if a description of an element has been omitted, it may be assumed that the description is at least similar to the description of the corresponding element described elsewhere in this specification. However, a portion of the active circuit fin 105 on the substrate 101 may be recessed on both sides of the gate structure 140, and source / drain regions 130 may be disposed on the recessed active circuit fin 105. According to an exemplary embodiment, the active fin 105 of the circuit may include impurities, and at least a portion of the active fin 105 of the circuit may include impurities that have different conductivity types from each other, but this disclosure is not limited thereto.

[0102] The isolation region 110 may define the active circuit fin 105 on the substrate 101. In the isolation region 110 and the active circuit fin 105, portions that are the same as those in the isolation region 110 and the first protective active fin 205 will be indicated by the same or similar reference numerals, or if a description of an element has been omitted, it may be assumed that the description is at least similar to the description of the corresponding element that has been described elsewhere in this specification.

[0103] The source / drain region 130 may be located between the active fin 105 and the circuit contact structure CA. The source / drain region 130 may be configured as the source or drain region of a transistor. The source / drain region 130 may be implemented on a region after a portion of the upper part of the active fin 105 is recessed. However, the operation of recessing this portion may or may not be performed, and the depth of the recess may vary. The source / drain region 130 may be a semiconductor layer comprising silicon (Si) and may include an epitaxial layer. The source / drain region 130 may include impurities of different conductivity types and / or different concentrations. For example, the source / drain region 130 may include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). In exemplary embodiments of the inventive concept, the source / drain region 130 may include multiple regions comprising elements and / or dopants of different concentrations.

[0104] The gate structure 140 may be configured to extend in one direction (e.g., the Y direction) over the active circuit fin 105. A channel region of the transistor may be formed in the active circuit fin 105 intersecting the gate structure 140. The gate structure 140 includes a gate electrode 145, a gate dielectric layer 142 between the gate electrode 145 and the active circuit fin 105, a gate spacer layer 144 on a side surface of the gate electrode 145, and a gate capping layer 146 on the gate electrode 145.

[0105] A gate dielectric layer 142 may be disposed between the active fin 105 and the gate electrode 145. The gate dielectric layer 142 may be configured to surround one or more surfaces of the gate electrode 145. In one embodiment, the gate dielectric layer 142 may not surround the uppermost surface of the gate electrode 145. The gate dielectric layer 142 may comprise an oxide, nitride, or high-k dielectric material.

[0106] The gate electrode 145 may be configured to extend across the active circuit fin 105. The gate electrode 145 may comprise a conductive material, such as a metal nitride like titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metallic material like aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material like doped polycrystalline silicon. The gate electrode 145 may have a multilayer structure comprising two or more layers.

[0107] The gate spacer layer 144 may be disposed on both side surfaces of the gate electrode 145 and may extend in the Z direction perpendicular to the upper surface of the substrate 101. According to an exemplary embodiment of the present invention, the gate spacer layer 144 may have a multilayer structure. The gate spacer layer 144 may be formed of oxides, nitrides, and oxynitrides, particularly low-k dielectric materials.

[0108] A gate capping layer 146 may be disposed on the gate electrode 145. The gate capping layer 146 may be configured to extend along the upper surface of the gate electrode 145 in a second direction (e.g., the Y direction). The gate capping layer 146 may be formed of oxides, nitrides, and oxide oxynitrides.

[0109] The integrated circuit structure 100 of the semiconductor device 10 may include a first interlayer insulating layer 181 on a substrate 101, a circuit contact structure CA that penetrates the first interlayer insulating layer 181 and is disposed on the source / drain region 130, a gate contact structure CB that is electrically connected to the gate electrode 145 through the first interlayer insulating layer 181, a second interlayer insulating layer 182 on the first interlayer insulating layer 181, a circuit interconnect structure CM1a that is connected to the circuit contact structure CA through the second interlayer insulating layer 182, and a gate interconnect structure CM1b that penetrates the second interlayer insulating layer 182 and is disposed on the gate contact structure CB.

[0110] The circuit contact structure CA can be electrically connected to the source / drain region 130 through the first interlayer insulating layer 181, and can apply an electrical signal to the source / drain region 130. The circuit contact structure CA can be disposed on the source / drain region 130, such as... Figure 4 As shown in the exemplary embodiment, the circuit contact structure CA may be configured to have a length in the Y direction longer than the source / drain region 130. The circuit contact structure CA may have sloping side surfaces, wherein the width of the lower portion is narrower than the width of the upper portion according to the aspect ratio, but the present disclosure is not limited thereto. In the exemplary embodiment, the circuit contact structure CA may cause the upper portion of the source / drain region 130 to be recessed. The circuit contact structure CA may be configured to contact the source / drain region 130 along the upper surface of the source / drain region 130 without causing the source / drain region 130 to be recessed.

[0111] The circuit contact structure CA may include a metal-semiconductor compound layer 152a, a barrier layer 154a, and a contact plug 155a. The barrier layer 154a may surround the contact plug 155a. The barrier layer 154a may cover the side surface and the bottom surface of the contact plug 155a. The metal-semiconductor compound layer 152a may be disposed between the barrier layer 154a and the source / drain region 130.

[0112] The metal-semiconductor compound layer 152a may include a metal silicide, a metal germanide, or a metal silicide-germanide. The metal may be Ti, Ni, Ta, Co, or W, and the semiconductor may be Si, Ge, or SiGe. The barrier layer 154a may be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The contact plug 155a may be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0113] The gate contact structure CB can be electrically connected to the gate electrode 145 through the second interlayer insulating layer 182 and the gate capping layer 146, and can apply an electrical signal to the gate electrode 145. The gate contact structure CB can be disposed on the gate electrode 145, such as... Figure 5C As shown in the diagram. The gate contact structure CB may have sloping side surfaces, wherein the width of the lower portion is narrower than the width of the upper portion depending on the aspect ratio, but this disclosure is not limited thereto. In an exemplary embodiment, the gate contact structure CB may cause the upper portion of the gate electrode 145 to be recessed.

[0114] The gate contact structure CB may include a gate barrier layer 154b and a gate contact plug 155b. The gate barrier layer 154b may surround the gate contact plug 155b. The gate barrier layer 154b may cover the side surface and the bottom surface of the gate contact plug 155b.

[0115] The gate barrier layer 154b can be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The gate contact plug 155b can be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0116] In an exemplary embodiment of the present invention, the lower surface of the gate contact plug 155b may be higher than the lower surface of the contact plug 155a. The upper surface of the gate contact plug 155b may be substantially coplanar with the upper surface of the first interlayer insulating layer 181 and / or the upper surface of the contact plug 155a.

[0117] The circuit interconnect structure CM1a can be connected to the circuit contact structure CA via the second interlayer insulating layer 182. The circuit interconnect structure CM1a may have sloping side surfaces, wherein the width of the lower part is narrower than the width of the upper part according to the aspect ratio, but this disclosure is not limited thereto.

[0118] The circuit interconnect structure CM1a may include a metal barrier layer 164a and a metal interconnect layer 165a. The metal barrier layer 164a may surround the metal interconnect layer 165a. The metal barrier layer 164a may cover the side surface and the bottom surface of the metal interconnect layer 165a.

[0119] The metal barrier layer 164a can be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The metal interconnect layer 165a can be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0120] The gate interconnect structure CM1b can be connected to the gate contact structure CB via the second interlayer insulating layer 182. The gate interconnect structure CM1b may have sloping side surfaces, wherein the width of the lower part is narrower than the width of the upper part according to the aspect ratio, but this disclosure is not limited thereto.

[0121] The gate interconnect structure CM1b may include a gate conductive barrier layer 164b and a gate conductive interconnect layer 165b. The gate conductive barrier layer 164b may surround the gate conductive interconnect layer 165b. The gate conductive barrier layer 164b may cover the side surface and the bottom surface of the gate conductive interconnect layer 165b.

[0122] The gate conductive barrier layer 164b can be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The gate conductive interconnect layer 165b can be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0123] The integrated circuit structure 100 of the semiconductor device 10 may further include a body contact structure for applying a body bias to a substrate 101 in a first region R1. The body contact structure may be in direct contact with at least a portion of the active circuit fins 105.

[0124] The integrated circuit structure 100 of the semiconductor device 10 may include a third interlayer insulating layer 183 on the second interlayer insulating layer 182, a first circuit region via 171 and a second circuit region via 172 connected to the circuit contact structure CA and the gate contact structure CB respectively through the third interlayer insulating layer 183, and a first circuit region conductor 191 and a second circuit region conductor 192 connected to the first circuit region via 171 and the second circuit region via 172 respectively.

[0125] The first to fourth interlayer insulating layers 181, 182, 183, and 184 may be sequentially stacked on the substrate 101. At least one of the first to fourth interlayer insulating layers 181, 182, 183, and 184 comprises, for example, tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-coated glass (SOG), tonnen silazene (TOSZ), or combinations thereof.

[0126] The first circuit region via 171 and the second circuit region via 172 can contact the upper portion of the metal interconnect layer 165a and the upper portion of the gate conductive interconnect layer 165b through the third interlayer insulating layer 183. The first circuit region via 171 and the second circuit region via 172 may include copper or an alloy containing copper.

[0127] The first circuit region conductor 191 and the second circuit region conductor 192 can contact the upper part of the first circuit region via 171 and the upper part of the second circuit region via 172 through the fourth interlayer insulation layer 184. The first circuit region conductor 191 and the second circuit region conductor 192 may include copper or an alloy containing copper.

[0128] Figure 5D This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 5D It is along Figure 4 The cross-sectional view of the semiconductor device taken by line III-III' in the figure.

[0129] Reference Figure 5DThe integrated circuit structure 100a of the semiconductor device 10 may further include a channel structure 120, which includes a plurality of channel layers 121, 122, and 123 disposed on the active circuit fin 105 and vertically spaced apart from each other. A gate electrode 145a may be disposed between the active circuit fin 105 and the channel structure 120, between the plurality of channel layers 121, 122, and 123 of the channel structure 120, and on the channel structure 120. Therefore, the semiconductor device 10 may include the channel structure 120, the source / drain region 130, and a multi-bridge channel FET (MBCFET) formed by the gate structure 140a. TM ).

[0130] The gate structure 140a includes a gate electrode 145a, a gate dielectric layer 142a, a gate spacer layer 144 on the side surface of the gate electrode 145a, and a gate capping layer 146 on the gate electrode 145a.

[0131] A gate dielectric layer 142a may be disposed between the active fin 105 and the gate electrode 145a. The gate dielectric layer 142a may be configured to surround one or more surfaces of the gate electrode 145a. In one embodiment, the gate dielectric layer 142a may not surround the uppermost surface of the gate electrode 145a. The gate dielectric layer 142a may comprise an oxide, nitride, or high-k dielectric material.

[0132] In the integrated circuit structure 100a of the semiconductor device 10, the gate structure 140a may further include an internal spacer layer 141. The internal spacer layer 141 may be configured as a gate electrode 145a parallel to the channel structures 120. The internal spacer layer 141 may be disposed on both sides of the gate structure 140a in the X direction on the lower surface of each of the first to third channel layers 121, 122, and 123. The internal spacer layer 141 may have an outer surface substantially coplanar with the outer surfaces of the first to third channel layers 121, 122, and 123. The gate electrode 145a may be spaced apart from the source / drain region 130 by the internal spacer layer 141 below the third channel layer 123 for electrical isolation from the source / drain region 130. The internal spacer layer 141 may be formed of oxides, nitrides, and oxynitrides, particularly low-k dielectric materials.

[0133] Figure 6A This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6A It shows along Figure 2A The line I-I' in the middle intercepts the line with Figure 2A The area corresponding to the cross-section of the protective ring of the semiconductor device in the middle.

[0134] Reference Figure 6A The pair of first protective contact structures CA1a of the first protective ring 200-1 can contact all the first protective active fins 205 of the first protective active structure RX1. For example, the pair of first protective contact structures CA1a can be spaced apart from each other in the X direction, and each of the pair of first protective contact structures CA1a can contact two adjacent first protective active fins 205 and two other adjacent first protective active fins 205 in the first protective active structure RX1, respectively.

[0135] The width of the lower end of the first protective contact structure CA1a in the X direction can be referred to as the first width W1a. The width of the upper end of the first protective contact structure CA1a in the X direction can be referred to as the second width W2a. The second width W2a can be greater than the first width W1a. According to an embodiment of the present invention, the first width W1a can be greater than the width of each first protective active fin 205. According to an embodiment of the present invention, the width of each first protective contact structure CA1a can be greater than the width of each circuit active fin 105.

[0136] In an embodiment of the present invention, the width of the lower end of the first protective contact structure CA1a in the X direction (i.e., the first width W1a) can be greater than the reference width. Figure 3A The first spacing P1 and the second spacing P2 are described.

[0137] In an embodiment of the present invention, the first protective contact structure CA1a may include a first protective barrier layer 254a and a first protective contact plug 255a. The first protective barrier layer 254a may surround the first protective contact plug 255a. The first protective barrier layer 254a may cover the side surface and the lower surface of the first protective contact plug 255a. The first protective barrier layer 254a may be disposed between the first protective active fin 205 and the first protective contact plug 255a.

[0138] The first protective barrier layer 254a may be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first protective contact plug 255a may be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0139] Figure 6B This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6B It shows along Figure 2A The line I-I' in the middle intercepts the line with Figure 2A The area corresponding to the cross-section of the protective ring of the semiconductor device in the middle.

[0140] Reference Figure 6BThe pair of first protective contact structures CA1b of the first protective ring 200-2 can be spaced apart from each other, and each of the pair of first protective contact structures CA1b can respectively contact the first external active fin 205b of the first protective active structure RX1. In this embodiment of the present invention, each of the pair of first protective contact structures CA1b may not contact the first internal active fin 205a, but the present disclosure is not limited thereto. In another embodiment, each of the pair of first protective contact structures CA1b can contact at least a portion of the first internal active fin 205a.

[0141] In an embodiment of the present invention, the first protective contact structure CA1b may include a first protective barrier layer 254b and a first protective contact plug 255b. The first protective barrier layer 254b may surround the first protective contact plug 255b. The first protective barrier layer 254b may cover the side surface and the lower surface of the first protective contact plug 255b. The first protective barrier layer 254b may be disposed between the first protective active fin 205 and the first protective contact plug 255b.

[0142] The first protective barrier layer 254b may be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first protective contact plug 255b may be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0143] Figure 6C This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6C It shows along Figure 2A The line I-I' in the middle intercepts the line with Figure 2A The area corresponding to the cross-section of the protective ring of the semiconductor device in the middle.

[0144] Reference Figure 6C The first active protective structure RX1 of the first protective ring 200-3 may include two first active protective fins 205. A pair of first protective contact structures CA1 may be spaced apart from each other in the X direction, and the pair of first protective contact structures CA1 may contact the two first active protective fins 205 respectively.

[0145] Figure 6D This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6D It shows along Figure 2A The line I-I' in the middle intercepts the line with Figure 2A The area corresponding to the cross-section of the protective ring of the semiconductor device in the middle.

[0146] Reference Figure 6DThe first protective active fin 205 of the first protective ring 200-4 may include a semiconductor stack structure in which a first semiconductor layer 206 and a second semiconductor layer 207 are repeatedly stacked. The first protective contact structure CA1 can contact the semiconductor stack structure by recessing a portion of the upper part of the semiconductor stack structure. For example, the first semiconductor layer 206 may include silicon germanium (SiGe), and the second semiconductor layer 207 may include silicon (Si).

[0147] This embodiment of the present invention can be used in conjunction with the reference. Figure 5D MBCFET description TM This is achieved during the manufacturing process of the corresponding semiconductor device 10. For example, it can be implemented with... Figure 5D The second semiconductor layer 207 is formed using the same process as the respective channel layers 121, 122, and 123 in the previous layer. It can be formed using the same process as the layer constructed by... Figure 5D The gate electrode 145a between the channel layers 121, 122 and 123 is replaced by the same or substantially similar process to form the first semiconductor layer 206.

[0148] Figure 6E This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6E It shows along Figure 2A The line I-I' in the middle intercepts the line with Figure 2A The area corresponding to the cross-section of the protective ring of the semiconductor device in the middle.

[0149] Reference Figure 6E A pair of first protective interconnect structures CM1c of the first protective ring 200-5 can each contact a pair of first protective contact structures CA1. The pair of first protective interconnect structures CM1c can be spaced apart from each other in the X direction to connect to the pair of first protective contact structures CA1. The pair of first protective contact structures CA1 and the pair of first protective interconnect structures CM1c can be connected through the first via 271.

[0150] The first protective interconnect structure CM1c may include a first conductive barrier layer 264a and a first protective interconnect layer 265a. The first conductive barrier layer 264a may surround the first protective interconnect layer 265a. According to an embodiment of the present invention, the first conductive barrier layer 264a may surround the side surface and the bottom surface of the first protective interconnect layer 265a.

[0151] The first conductive barrier layer 264a may be formed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first protective interconnect layer 265a may be formed of, for example, tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

[0152] Figure 6F This is a cross-sectional view showing a protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6F It shows along Figure 2A The line I-I' in the middle intercepts the line with Figure 2A The area corresponding to the cross-section of the protective ring of the semiconductor device in the middle.

[0153] Reference Figure 6F The first protective interconnect structure CM1 can be excluded in the second region R2. A first via 271a can connect a pair of first protective contact structures CA1 to each other via a second interlayer insulating layer 182. A first interlayer insulating layer 181 can be disposed between the pair of first protective contact structures CA1 below the first via 271a. In this case, at least a portion of the first interlayer insulating layer 181 can directly contact the lower part of the first via 271a.

[0154] Unless otherwise stated, the above refers to Figures 6A to 6F The provided description can be equivalently applied to the second protective ring 300 in the third region R3. The components of the second protective ring 300 will be respectively made of and Figures 6A to 6F The same or similar reference numerals shown in the figures indicate, or if the description of an element has been omitted, that description may be assumed to be at least similar to the description of the corresponding element that has been described elsewhere in this specification.

[0155] Figure 7A This is an enlarged view of the protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 7A It shows the relationship with Figure 1 The region corresponding to region 'A' in the diagram.

[0156] Reference Figure 7A In the planar view, the first protective ring 200a may have a shape in which rectangular regions are repeatedly arranged adjacent to each other. The first protective ring 200a may include a first protective ring outer pattern 200aa extending from both sides of the second region R2 in the Y direction and having an uneven shape, and a first protective ring inner pattern 200ab surrounded by the first protective ring outer pattern 200aa and having a rectangular shape. The first interlayer insulation layer 181 may be disposed in the rectangular region formed by the first protective ring inner pattern 200ab. The first protective active structure RX1' and the first protective contact structure CA1' constituting the first protective ring 200a may also have the same planar shape as described above.

[0157] Figure 7A An exemplary shape of the first protective ring 200a is shown. The shape of the first protective ring 200a can vary depending on the area in which the first protective ring 200a is disposed, the number of first protective active structures RX1', etc.

[0158] Figure 7B This is a partially enlarged view of the protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 7B It shows the relationship with Figure 1 The region corresponding to region 'B' in the text.

[0159] Reference Figure 7B In a planar view, the second protective ring 300aa and the second protective ring 300ab may each have an irregular shape. In a planar view, each of the second protective rings 300aa and 300ab may include a recessed portion and a protruding portion. The second protective rings 300aa and 300ab may extend at regular intervals in the Y direction, bend from at least one point in the X direction, and bend again in the Y direction. The second protective active fin 305', the second protective contact structure CA2', and the third protective contact structure CA3' included in the second protective rings 300aa and 300ab may also have the same planar shape as described above. The second protective ring 300aa may include multiple second protective rings, and based on the same direction, the recessed and protruding portions formed in one second protective ring 300aa may be configured to be opposite to the protruding and recessed portions of another second protective ring 300ab adjacent to that second protective ring 300aa, respectively.

[0160] A portion of the second protective ring 300aa and the second protective ring 300ab may include a second protective contact structure CA2', and other portions of the second protective ring 300aa and the second protective ring 300ab may include a third protective contact structure CA3'.

[0161] Figure 7C This is a partially enlarged view of the protective ring of a semiconductor device according to an exemplary embodiment of the present invention. Figure 7C It shows the relationship with Figure 1 The region corresponding to region 'B' in the text.

[0162] Reference Figure 7C ,and Figure 7B The second protective ring 300aa and the second protective ring 300ab are different. The second protective ring 300aa and the second protective ring 300ab may each include multiple second protective rings, and based on the same direction, the recessed portion and the protruding portion formed in one second protective ring 300aa may be configured to be opposite to the recessed portion and the protruding portion formed in another second protective ring 300ab adjacent to the second protective ring 300aa.

[0163] Due to the uneven shape of the second protective ring 300aa and the second protective ring 300ab, the total length of the second protective ring 300aa and the second protective ring 300ab can be increased, and moisture can be prevented from penetrating into the semiconductor device during the cutting process.

[0164] In the following, some exemplary embodiments of the present invention will be described with reference to Figures 8A to 8C Describes the corner portion of the protective ring of a semiconductor device. Figure 8A Is with Figure 1 A magnified view of the area corresponding to region 'D' in the image. Figure 8B Is with Figure 8A A magnified view of the area corresponding to region 'D-1' in the image. Figure 8C Is with Figure 8A A magnified view of the area corresponding to region 'D-1' in the image.

[0165] exist Figure 1 In the diagram, the corner portion of the protective ring of the semiconductor device 10 is shown excluding any bent or curved portions. However, referring to... Figures 8A to 8C The second region R2 and the third region R3 may each include a bent portion or a curved portion in the corner region of the semiconductor device 10.

[0166] In the plan view, the first region R1 may have an octagonal shape. The second region R2 may have a structure that bends or curves around the first region R1 while also being bent or curved in the corner region of the semiconductor device 10. The third region R3 may also have a structure that bends or curves around the second region R2 while also being bent in the corner region of the semiconductor device 10. The first protective ring 200a may have a portion extending in a repeating pattern on the second region R2 and extending linearly in the corner region of the semiconductor device 10. The first protective ring 200a may be bent around the corner portion of the first region R1. The second protective ring 300aa and the second protective ring 300ab may be bent around the corner portion of the second region R2. The second protective ring 300aa and the second protective ring 300ab may also include a portion extending in a repeating pattern on the third region R3 and bending in a Z-shape in the corner region of the semiconductor device 10.

[0167] The second protective rings 300aa and 300ab in the third region R3 may have a triangular shape in the corner region of the semiconductor device 10. The second edge protective rings 300e1 and 300e2 may also be triangular in shape. The second edge protective rings 300e1 and 300e2 may be spaced apart from the first protective ring 200a in the second region R2 and the second protective rings 300aa and 300ab in the third region R3. The second edge protective rings 300e1 and 300e2 may have the same vertical cross-section as the second protective rings 300aa and 300ab. Each of the second edge protective rings 300e1 and 300e2 may have a line extending in at least one direction within the triangular shape, and may also have an uneven shape. The second edge protective rings 300e1 and 300e2 may be provided to protect an integrated circuit structure in the edge region of the semiconductor device, which is susceptible to moisture penetration or cracking during the semiconductor device dicing process.

[0168] Figures 9A to 15B This is a process flow diagram illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention. Figures 9A to 15B The manufacturing process will be described here (refer to...). Figures 2A to 3B Methods for semiconductor devices.

[0169] Reference Figure 9A and Figure 9B Multiple active fins can be formed on the substrate 101.

[0170] An active fin 105 can be disposed in a first region R1 of the substrate 101 via an isolation region 110. A first protective active fin 205 can be disposed in a second region R2 of the substrate 101 via an isolation region 110. The active fin 105 can be formed on an active region 102. The active region 102 can be defined by a deep isolation region 111. A second protective active fin 305 can be disposed in a third region R3 of the substrate 101 via an isolation region 110. The active fin 105, the first protective active fin 205, and the second protective active fin 305 can have a structure that protrudes from the substrate 101.

[0171] In another exemplary embodiment of the present invention, a plurality of sacrificial layers and a plurality of channel layers 121, 122, and 123 may be alternately stacked on substrate 101. The sacrificial layers may be replaced by a gate dielectric layer 142 and a gate electrode 145 by subsequent processes. The sacrificial layers may be formed of a material having etch selectivity relative to the channel layers 121, 122, and 123. For example, the sacrificial layers may comprise silicon germanium (SiGe), and the channel layers 121, 122, and 123 may comprise silicon (Si).

[0172] Reference Figure 10A and Figure 10B It can form a first protective layer 112 to cover the active fin 105, the first protective active fin 205, the second protective active fin 305, and the isolation area 110.

[0173] The first protective layer 112 may conformally cover the active fin 105, the first protective active fin 205, and the second protective active fin 305. The first protective layer 112 may be formed over the entire area of ​​the first region R1, the second region R2, and the third region R3 of the substrate 101, or only in a portion of regions R1, R2, and R3 (e.g., the second region R2 and the third region R3). The first protective layer 112 formed in the first region R1 may be patterned using a gate electrode mask patterning layer 146' during the process described below, to retain the gate dielectric layer 142' as a sacrificial gate dielectric layer. The first protective layer 112 may include, for example, oxides, nitrides, or combinations thereof.

[0174] During the process of forming the source / drain region 130 and the gate structure 140 (described later), the first protective layer 112 can protect the first protective active fin 205 and the second protective active fin 305 of the second region R2 and the third region R3.

[0175] Reference Figure 11A and Figure 11B A sacrificial gate structure 140' can be formed across the active fin 105. A source / drain region 130 can be formed on the active fin 105 by removing a portion of the active fin 105 and performing a selective epitaxial growth (SEG) process. An etch stop layer 135 can be formed to cover the source / drain region 130. A first interlayer insulating layer 181 can be formed between the sacrificial gate structures 140' and on the source / drain region 130.

[0176] In the first region Rl, the sacrificial gate structure 140' may be formed to extend across the active fin 105 in one direction. The sacrificial gate structure 140' may include a sacrificial gate dielectric layer 142', a sacrificial gate electrode 145', and a gate electrode mask patterning layer 146'. The sacrificial gate dielectric layer 142' and the sacrificial gate electrode 145' may be patterned using the gate electrode mask patterning layer 146'. The sacrificial gate dielectric layer 142' may include silicon oxide, and the sacrificial gate electrode 145' may include polysilicon. The gate electrode mask patterning layer 146' may include silicon oxide and / or silicon nitride. The sacrificial gate structure 140' may have a line shape; for example, the sacrificial gate structure 140' may be formed to extend in the Y direction and be spaced apart from each other in the X direction.

[0177] Gate spacer layer 144 (reference) Figure 5A The gate spacer layer 144 can be formed on the two sidewalls of the sacrificial gate structure 140'. The gate spacer layer 144 can be formed by forming a layer of uniform thickness along the upper surface and side surface of the sacrificial gate structure 140' and anisotropically etching the layer.

[0178] The source / drain region 130 can be formed by removing a portion of the active fin 105 from both sides of the sacrificial gate structure 140' and performing a selective epitaxial growth (SEG) process on the removed active fin 105. A recess can be formed by removing a portion of the active fin 105. A recess can be formed by forming an additional mask layer or by etching a portion of the active fin 105 using a gate electrode mask pattern layer 146' and a gate spacer layer 144 as a mask. A recess can be formed by sequentially applying, for example, dry etching and wet etching processes. The source / drain region 130 can be formed on the etched active fin 105. The source / drain region 130 can include impurities implanted through in-situ doping and can also include multiple layers with different doping elements and / or doping concentrations.

[0179] After forming the etch stop layer 135 to cover the source / drain region 130, a first interlayer insulating layer 181 can be formed.

[0180] The etch stop layer 135 may cover the source / drain region 130 and the isolation region 110 in the first region R1. The etch stop layer 135 may also cover the side surface of the gate spacer layer 144. The etch stop layer 135 may also be formed in the second region R2 and the third region R3, and may be substantially the same as the second protective layer 114. The second protective layer 114 may cover the first protective layer 112 on the second region R2 and the third region R3.

[0181] The first interlayer insulating layer 181 can be formed as an etch stop layer 135 covering the sacrificial gate structure 140' between the first region R1. The first interlayer insulating layer 181 can also be formed as a second protective layer 114 covering the second region R2. The first interlayer insulating layer 181 can be formed by forming an insulating layer to cover the sacrificial gate structure 140' and the source / drain region 130 and performing a planarization process.

[0182] Reference Figure 12A and Figure 12B The sacrificial gate structure 140' can be removed to form a gap region, and a gate dielectric layer 142, a gate electrode 145, and a gate capping layer 146 can be formed in the gap region.

[0183] The sacrificial gate structure 140' can be selectively removed relative to the gate spacer layer 144, the first interlayer insulating layer 181, and the active fin 105. A gap region can be formed by removing the sacrificial gate structure 140'.

[0184] After forming the gate dielectric layer 142 and the gate electrode 145 to fill the gap region, they can be removed from the top of the gap region to a predetermined depth. A gate capping layer 146 can be formed in the region where the gate electrode 145 is removed from the gap region. Therefore, a gate structure 140 including the gate dielectric layer 142, the gate electrode 145, the gate spacer layer 144, and the gate capping layer 146 can be formed.

[0185] Reference Figure 13A and Figure 13B The first interlayer insulation layer 181 can be patterned to form a first protective contact hole GH1, a second protective contact hole GH2, and a contact hole CH1.

[0186] Contact holes CH1 can be formed by removing a portion of the first interlayer insulating layer 181 on both sides of the gate structure 140 using an additional mask layer such as a photoresist pattern. The lower surface of the contact hole CH1 can be recessed into the source / drain region 130, or it can have curvature along the upper surface of the source / drain region 130. In exemplary embodiments of the inventive concept, the shape and arrangement of the contact hole CH1 can be varied.

[0187] The first protective contact hole GH1 and the second protective contact hole GH2 can be formed by removing a portion of the first interlayer insulating layer 181 using an additional mask layer, such as a photoresist pattern. The first protective contact hole GH1 and the second protective contact hole GH2 can recess a portion of the first protective active fin 205 and the second protective active fin 305 to expose them. The first protective contact hole GH1 and the second protective contact hole GH2 can also expose a portion of the first protective layer 112 and the second protective layer 114. Each first protective active structure RX1 can form at least two first protective contact holes GH1, and each second protective active structure RX2 can form at least two second protective contact holes GH2.

[0188] The first protective contact hole GH1 and the second protective contact hole GH2 can be formed in pairs, and can prevent insulation residues generated during the process of patterning the first interlayer insulation layer 181 to remove a portion of it from being deposited in the first protective contact hole GH1 and the second protective contact hole GH2.

[0189] Reference Figure 14A and Figure 14B The circuit contact structure CA, the first protective contact structure CA1, and the second protective contact structure CA2 can be formed. The first interlayer insulating layer 181 can be patterned to form the gate contact hole CH2 and the third protective contact hole GH3.

[0190] A circuit contact structure CA can be formed in the contact hole CH1. A metal-semiconductor compound layer 152a can be formed on the surface of the source / drain region 130 exposed by the contact hole CH1. A barrier layer 154a and a contact plug 155a can be sequentially formed in the contact hole CH1.

[0191] The first protective contact structure CA1 and the second protective contact structure CA2 can be formed in the first protective contact hole GH1 and the second protective contact hole GH2, respectively. The first protective barrier layer 254 and the second protective barrier layer 354, as well as the first protective contact plug 255 and the second protective contact plug 355, can be formed sequentially in the first protective contact hole GH1 and the second protective contact hole GH2, respectively.

[0192] A planarization process can be performed during the formation of the first protective contact structure CA1, the second protective contact structure CA2, and the circuit contact structure CA.

[0193] The third protective contact hole GH3 can expose all the second protective active fins 305 formed on the second protective active structure RX2. The third protective contact hole GH3 can be formed in a region where no second protective contact structure CA2 is formed on the second protective active structure RX2 in the third region R3. Therefore, the second protective ring 300 can include at least one second protective contact structure CA2 and at least one third protective contact structure CA3. However, according to an exemplary embodiment, the second protective ring 300 can include only the second protective contact structure CA2 or only the third protective contact structure CA3.

[0194] Reference Figure 15A and Figure 15B The gate contact structure CB and the third protective contact structure CA3 can be formed in the gate contact hole CH2 and the third protective contact hole GH3, respectively. The interconnect trench can be formed by forming a second interlayer insulating layer 182 on the first interlayer insulating layer 181 and removing a portion of the second interlayer insulating layer 182.

[0195] Reference Figures 3A to 5C An interconnect layer can be formed in the interconnect trench, a third interlayer insulating layer 183 and a plurality of vias 171, 172, 271 and 272 can be formed, and conductors 191, 192, 281 and 282 can be formed on the third interlayer insulating layer 183.

[0196] As described above, the semiconductor device includes a guard ring, wherein a pair of contact structures are formed on a single active fin structure within the guard ring to protect the operating characteristics of the semiconductor device and improve performance against harmful external environments, thereby reducing interface defects between the active fin structure and the contact structure due to insulating residues during highly selective etching processes.

[0197] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor device, comprising: A substrate having a first region, a second region, and a third region, wherein the second region at least partially surrounds the first region, and the third region at least partially surrounds the second region; An integrated circuit structure on the substrate in the first region; A first protective ring is disposed on the substrate in the second region and at least partially surrounds the integrated circuit structure; A second protective ring is disposed on the substrate in the third region and at least partially surrounds the first protective ring; as well as An insulating material structure is present on the side surfaces of the first protective ring and the second protective ring. The integrated circuit structure includes: an active circuit fin disposed on the substrate in the first region; a gate structure intersecting the active circuit fin; a source or drain region disposed on the active circuit fin adjacent to the side surface of the gate structure; a circuit contact structure disposed on the source or drain region; and a circuit interconnect structure disposed on the circuit contact structure. The first protective ring includes: a first protective active structure disposed on the substrate in the second region, a plurality of first protective contact structures disposed on each of the first protective active structures, and a first protective interconnect structure disposed on the plurality of first protective contact structures. The second protective ring includes: a second protective active structure disposed on the substrate in the third region, a second protective contact structure disposed on the second protective active structure, and at least one second protective interconnect structure disposed on the second protective contact structure. The source or drain region is located between the circuit contact structure and the circuit active fin. Each of the first protective active structures includes first external active fins spaced apart from each other, and first internal active fins spaced apart from each other and disposed between the first external active fins. In each of the first active protective structures, the upper surface of one of the first outer active fin and the first inner active fin at least partially overlaps with the insulating material structure in the vertical direction, and the upper surface of the other of the first outer active fin and the first inner active fin contacts the plurality of first protective contact structures. In the plan view, the vertical direction is perpendicular to the upper surface of the substrate. Wherein, the upper surface of the active fin that at least partially overlaps with the insulating material structure in the vertical direction among the first external active fin and the first internal active fin is positioned at a higher level than the upper surface of the active fin that contacts the plurality of first protective contact structures.

2. The semiconductor device according to claim 1, wherein, Each of the second protective active structures in the second protective active structure includes: a second external active fin, and second internal active fins spaced apart from each other and disposed between the second external active fins, and The second active protective structure includes a pair of second active protective structures that are adjacent to and parallel to each other.

3. The semiconductor device according to claim 2, wherein, The first group of the second protective contact structures contacts the second internal active fin, and the first group of the second protective contact structures is spaced apart from the second external active fin adjacent to the second internal active fin. The second protective contact structure of the second group contacts the second internal active fin and the second external active fin.

4. The semiconductor device according to claim 1, wherein, The height difference between the lower and upper surfaces of each of the plurality of first protective contact structures is greater than the height difference between the lower and upper surfaces of the circuit contact structure, and The upper surface of each of the plurality of first protective contact structures and the upper surface of the circuit contact structure are arranged at the same level.

5. The semiconductor device according to claim 1, wherein, The distance between one of the first internal active fins that is adjacent to each other and one of the first external active fins is less than the distance between the first internal active fins that are adjacent to each other.

6. The semiconductor device according to claim 1, wherein, In one of the first protective active structures, the upper surface of the first inner active fin contacts the plurality of first protective contact structures respectively, and the upper surface of the first outer active fin at least partially overlaps the insulating material structure in the vertical direction.

7. The semiconductor device according to claim 1, wherein, The first protective interconnect structure contacts the upper surface of each of the plurality of first protective contact structures, and Wherein, the first protective interconnect structure at least partially overlaps with the insulating material structure disposed between the plurality of first protective contact structures in the vertical direction.

8. The semiconductor device according to claim 1, wherein, Each of the plurality of first protective contact structures includes: The upper region, with a maximum width in the range of 50nm to 60nm, is configured to be adjacent to the first protective interconnect structure; and The lower region has a maximum width in the range of 30nm to 40nm and is configured to be adjacent to the first protective active structure.

9. The semiconductor device according to claim 1, wherein, The insulating material structure includes: An isolation area is disposed on the side surfaces of the first protective active structure and the second protective active structure; A first protective layer is disposed on the isolated area and covers the first protective active structure and the second protective active structure; and A second protective layer covers the first protective layer, and Each of the first protective contact structure and the second protective contact structure is in contact with the first protective layer and the second protective layer.

10. The semiconductor device of claim 1, further comprising: A conductor that overlaps with the first protective ring, the second protective ring, and the insulating material structure in the vertical direction; as well as Multiple vias are respectively connected to the first protective interconnect structure and the second protective interconnect structure and are disposed below the conductor.

11. The semiconductor device according to claim 1, wherein, The first protective ring has a shape in which rectangular areas are repeatedly arranged adjacent to each other in a plan view, and In the plan view, the second protective ring has an uneven shape.

12. The semiconductor device according to claim 1, wherein, The first protective ring, having a bent shape, surrounds the corner portion of the first area, and The second protective ring, which has a bent shape, surrounds the corner portion of the second region.

13. The semiconductor device according to claim 1, wherein, At least a portion of the first and second protective active structures include a semiconductor stack structure in which silicon and silicon-germanium layers are repeatedly stacked.

14. A semiconductor device, comprising: substrate; A protective ring is disposed on the substrate and adjacent to the edge of the substrate; An integrated circuit structure, which is surrounded by the protective ring and disposed on the substrate; as well as An insulating material structure is disposed on the side surface of the protective ring. The integrated circuit structure includes: an active circuit fin disposed on the substrate, a gate structure intersecting the active circuit fin, a source or drain region on the active circuit fin and adjacent to the side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnect structure disposed on the circuit contact structure. The protective ring includes: a plurality of protective active structures on the substrate, a plurality of protective contact structures disposed on each of the plurality of protective active structures, and a protective interconnection structure disposed on a pair of adjacent protective contact structures among the plurality of protective contact structures. The source or drain region is disposed between the circuit contact structure and the active fin of the circuit. Each of the plurality of active protective structures includes a plurality of active protective fins spaced apart from each other. In each of the plurality of active protective structures, the upper surface of one of the plurality of active protective fins at least partially overlaps with the insulating material structure in the vertical direction, and the upper surface of another of the plurality of active protective fins contacts the plurality of protective contact structures. Wherein, the vertical direction is perpendicular to the upper surface of the substrate. The upper surface of one of the protective active fins is positioned at a higher level than the upper surface of the other protective active fin.

15. The semiconductor device according to claim 14, wherein, The protective interconnect structure at least partially overlaps with the pair of protective contact structures and the insulating material structure, wherein the insulating material structure is disposed between the pair of protective contact structures in the vertical direction.

16. The semiconductor device according to claim 14, wherein, The width of each of the plurality of protective contact structures is greater than the width of each of the circuit active fins, and Each of the plurality of protective contact structures is in contact with one of the protective active fins in a pair of adjacent protective active fins, and is spaced apart from the other of the pair of protective active fins.

17. A semiconductor device, comprising: substrate; An integrated circuit structure disposed on the substrate; A protective ring is disposed on the substrate and at least partially surrounds the integrated circuit structure; as well as An insulating material structure is present on the side surface of the protective ring. The integrated circuit structure includes: an active circuit fin disposed on the substrate, a gate structure intersecting the active circuit fin, a source or drain region disposed on the active circuit fin adjacent to the side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnect structure disposed on the circuit contact structure. The protective ring includes: a protective active structure comprising a plurality of protective active fins spaced apart from each other and disposed on the substrate; a protective contact structure spaced apart from each other; and a protective interconnect structure disposed on the protective contact structure. The source or drain region is disposed between the circuit contact structure and the active fin of the circuit. The protective interconnect structure is in contact with the protective contact structure; Wherein, the active protective structure is in contact with the protective contact structure, and The plurality of protective active fins include a pair of protective active fins that are adjacent to each other, wherein one of the protective active fins in the pair is in contact with one of the protective contact structures, and the other protective active fin in the pair is not in contact with the protective contact structure. The upper surface of the other protective active fin is positioned at a higher level than the upper surface of the first protective active fin.

18. The semiconductor device according to claim 17, wherein, The insulating material structure includes: An isolation zone is provided on the side surface of the plurality of protective active fins; A protective layer is disposed on the isolated area; and An interlayer insulating layer is disposed on the protective layer. The protective layer covers the upper surface of the active protective fins that do not contact the protective contact structure.

19. The semiconductor device according to claim 17, wherein, The two opposing side surfaces of the protective interconnect structure at least partially overlap with the upper surface of the adjacent protective contact structure in the vertical direction. Wherein, the region between the two side surfaces of the protective interconnect structure at least partially overlaps with the insulating material structure in the vertical direction, and The vertical direction is perpendicular to the upper surface of the substrate.

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