Electrostatic discharge (ESD) protection for CMOS circuits

Abstract

A voltage clamp is disclosed. The voltage clamp may include multiple transistors to limit the voltage between a power supply and ground. Furthermore, the voltage clamp may include a positive feedback signal to reduce the on-time of the multiple transistors.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of co-pending and co-owned U.S. Provisional Patent Application No. 62 / 976,635, filed February 14, 2020, entitled “ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR CMOS CIRCUITS”, the entire of which is incorporated herein by reference. Technical Field

[0003] This embodiment generally relates to complementary metal-oxide-semiconductor (CMOS) circuits, and more specifically to electrostatic discharge (ESD) protection for CMOS circuits. Background Technology

[0004] Electronic circuits can include N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS) transistors, which operate within and / or are exposed to a limited voltage range. For example, some electronic circuit designs can send, receive, and process electrical signals in the 1.8-volt range, while others can operate using electrical signals in the 3.3-volt range. The design of NMOS and PMOS transistors (collectively referred to as complementary metal-oxide-semiconductor (CMOS) transistors can have design characteristics (oxide thickness, gate size, doping concentration, etc.) that determine their operating voltages.

[0005] In some cases, electronic circuits may be exposed to high voltages that can damage some of the circuit components. For example, electrostatic discharge (ESD) can expose electronic circuits to very high voltages (sometimes thousands of volts) for a relatively short period of time (typically in the nanosecond range). Because circuit components may be designed to operate over lower voltage ranges, they can be damaged by ESD. In some cases, ESD voltages can cause PN junction failure or oxide failure in CMOS transistors. Furthermore, as transistor device geometries shrink, transistors become more susceptible to damage from lower ESD voltages. For example, the breakdown voltage associated with CMOS transistors (e.g., the voltage required to damage a PN junction) may decrease as device geometries become smaller.

[0006] ESD protection circuits prevent ESD damage by limiting or "clamping" the voltage applied to electronic circuits. In some cases, implementations of ESD protection circuits may require a considerable area and / or dedicated equipment. Area requirements and dedicated equipment can increase the cost and complexity of the associated integrated circuits. Therefore, there is a need for simple and low-cost ESD protection circuits for use with electronic circuits. Summary of the Invention

[0007] This summary is provided to introduce, in a simplified form, the selection of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0008] A voltage clamp is disclosed. The voltage clamp may include a first transistor, a second transistor, a third transistor, and a first inverter. The first transistor may have a drain coupled to a power supply. The second transistor may have a drain coupled to the source of the first transistor and a source coupled to ground. The third transistor may be configured to generate a positive feedback signal based on a first voltage at the gate of the second transistor. The first inverter may be configured to control the operation of the first transistor at least partially based on the positive feedback signal, such that the first and second transistors provide a discharge path between the power supply and ground.

[0009] An integrated circuit is disclosed. The integrated circuit may include electronic circuitry and a voltage clamp. The voltage clamp may include a first transistor, a second transistor, a third transistor, and a first inverter. The first transistor may have a drain coupled to a power supply. The second transistor may have a drain coupled to the source of the first transistor and a source coupled to ground. The third transistor may be configured to generate a positive feedback signal based on a first voltage at the gate of the second transistor. The first inverter may be configured to control the operation of the first transistor at least partially based on the positive feedback signal, such that the first and second transistors provide a discharge path between the power supply and ground. Attached Figure Description

[0010] Exemplary embodiments are illustrated by way of example and are not intended to be limited to the figures in the accompanying drawings. The same numerical references are used for the same elements throughout the drawings and description.

[0011] Figure 1 A block diagram of a complementary metal-oxide-semiconductor (CMOS) device according to some embodiments is shown.

[0012] Figure 2A A simplified schematic diagram of a voltage clamp according to some embodiments is shown.

[0013] Figure 2B A simplified schematic diagram of another voltage clamp according to some embodiments is shown. Detailed Implementation

[0014] In the following description, numerous specific details, such as examples of specific components, circuits, and processes, are set forth to provide a thorough understanding of this disclosure. As used herein, the term “coupled” means directly coupled to or through one or more intermediary components or circuits. Furthermore, specific terms and / or details are set forth in the following description and for illustrative purposes to provide a thorough understanding of exemplary embodiments. However, it will be apparent to those skilled in the art that these specific details may not be necessary for practicing exemplary embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring this disclosure. Any signals provided via various buses described herein may be time-division multiplexed with other signals and provided via one or more common buses. Additionally, interconnections between circuit elements or software blocks may be shown as buses or single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be a bus, and a single line or bus may represent any one or more of a large number of physical or logical mechanisms for communication between components. Exemplary embodiments are not intended to be limited to the specific examples described herein, but are intended to include all embodiments as defined by the appended claims within their scope.

[0015] Electronic circuits are at risk of damage when exposed to high voltages, such as those associated with electrostatic discharge (ESD). ESD voltages can have potentials of thousands of volts and can permanently damage circuit components. Traditional ESD protection devices are larger than other circuit components, increasing the cost and complexity of electronic circuits.

[0016] Embodiments of the subject matter described in this disclosure may include voltage clamps that provide protection to electronic circuits from exposure to high voltages, such as voltages associated with ESD phenomena. Voltage clamps may include stacked transistors to limit the voltage between the power supply and ground of the electronic circuit. Additionally, voltage clamps may include positive feedback loops to reduce the on-time of one or more stacked transistors.

[0017] Figure 1A block diagram of a complementary metal-oxide-semiconductor (CMOS) device 100 according to some embodiments is shown. Device 100 may include electronic circuitry 110 and a voltage clamp 120. In some embodiments, device 100 may be an integrated circuit, a system-on-a-chip (SoC), a processor, memory, or any other feasible electronic device or circuit. Electronic circuitry 110 and voltage clamp 120 (sometimes referred to as a power clamp) may include multiple components, including N-type metal-oxide-semiconductor (NMOS) transistors, P-type metal-oxide-semiconductor (PMOS) transistors, bipolar junction transistors (BJTs), capacitors, resistors, diodes, inductors, etc.

[0018] In some embodiments, electronic circuitry 110 may include components arranged to perform any feasible analog and / or digital processing functions (such as numerical and / or program processing functions) to implement memory such as dynamic and / or static memory and / or to transmit and receive communication signals including single-ended, differential, and / or wireless communication signals. Electronic circuitry 110 may be powered by and coupled to a power source (shown as VDD), and may also be coupled to ground.

[0019] Voltage clamp 120 can be coupled between a power source and ground. In some embodiments, voltage clamp 120 can prevent damage to device 100 caused by transient overvoltage phenomena, including, for example, electrostatic discharge (ESD). Voltage clamp 120 can limit or "clamp" the amplitude of the voltage that can be transmitted to electronic circuit 110. In this way, transistors and other components within electronic circuit 110 can be protected from overvoltage phenomena.

[0020] Figure 2A A simplified schematic diagram of a voltage clamp 200 according to some embodiments is shown. The voltage clamp 200 can be... Figure 1 Implementation of voltage clamp 120. Voltage clamp 200 may include resistors R1-R4, capacitors C1-C2, and transistors Q1-Q7. In some implementations, transistors Q1 and Q4 may be PMOS transistors, and transistors Q2-Q3 and Q5-Q7 may be NMOS transistors. However, in some other implementations, transistors Q1-Q7 may be any feasible type of transistor.

[0021] Transistors Q1 and Q2 can form a first inverter 220. For example, the source of transistor Q1 can be coupled to a power supply (described as VDD), and the drains of Q1 and Q2 can be coupled together at junction V4. The gate of transistor Q1 can be coupled to the gate of transistor Q2 at junction V1. The source of transistor Q2 can be coupled to junction V2. In some aspects, the first inverter 220 can extract power from the power supply via transistor Q1 and return power via transistor Q2 through junction V2.

[0022] Transistors Q4 and Q5 can be arranged to form a second inverter 221. For example, the source of transistor Q4 can be coupled to node V4 (e.g., the output of the first inverter 220). The drains of transistor Q4 and Q5 can be coupled together at node V5. The source of transistor Q5 can be coupled to ground. The gates of transistor Q4 and Q5 can be coupled together at node V3. In some aspects, the second inverter 221 can extract power from the output of the first inverter 220 via transistor Q4 and return the power to ground via transistor Q5.

[0023] Resistors R1 and R2 can form a voltage divider. The first terminal of resistor R1 can be coupled to a power supply, and the second terminal of resistor R1 can be coupled to the first terminal of resistor R2 at junction V3. The second terminal of resistor R2 can be coupled to ground. In this way, the output of the voltage divider is coupled to the input of the second inverter 221.

[0024] Resistor R3 and capacitor C1 can form a first resistor-capacitor (RC) network 210. A first terminal of resistor R3 can be coupled to a power supply, and a second terminal of resistor R3 can be coupled to a first terminal of capacitor C1 at node V1 (e.g., the input of the first inverter 220). The second terminal of capacitor C1 can be coupled to node V2. In some embodiments, the first RC network 210 can provide a filtered input signal to the first inverter 220 based on the power supply voltage and the voltage at node V2.

[0025] Resistor R4 and capacitor C2 can form a second RC network 211. The first terminal of resistor R4 can be coupled to node V2, and the second terminal of resistor R4 can be coupled to the first terminal of capacitor C2 at node V3 (e.g., the input of the second inverter 221). The second terminal of capacitor C2 can be coupled to ground. Furthermore, the second terminal of resistor R4 can be coupled to the first terminal of resistor R2. In some embodiments, the second RC network 211 can provide a filtered input signal to the second inverter 221 based on the voltage divider output of resistors R1 and R2. Therefore, the second RC network 211 can filter the output of the voltage divider based on the voltage at node V2 and ground.

[0026] Transistors Q6 and Q7 can be "stacked" and operate as clamping transistors. That is, transistors Q6 and Q7 can form a discharge path to dissipate energy from the power supply VDD to ground. The drain of transistor Q6 can be coupled to the power supply, and the source of transistor Q6 can be coupled to the drain of transistor Q7. The source of transistor Q7 can be coupled to ground. The gate of transistor Q6 can be coupled to the output of the first inverter 220 (e.g., node V4). The gate of transistor Q7 can be coupled to the output of the second inverter INV2 (e.g., node V5). Therefore, the first inverter INV1 can generate a gate signal for transistor Q6, and the second inverter INV2 can generate a gate signal for transistor Q7.

[0027] Transistor Q3 can at least partially provide a feedback path from transistor Q7 to the first inverter INV1. The gate of transistor Q3 can be coupled to the output of the second inverter INV2 and the gate of transistor Q7 (e.g., node V5). The source of transistor Q3 can be coupled to ground, and the drain of transistor Q3 can be coupled to node V2. Therefore, in some respects, transistor Q3 can provide a path to ground for the first inverter 220.

[0028] As described above, transistors Q6 and Q7 operate as clamping transistors to limit the voltage difference between the power supply and ground. In one operating mode, the power supply and ground can be floating and at a common voltage, such as near ground potential. For example, device 100 may be de-energized or unloaded on the printed circuit board. High-voltage ESD phenomena may cause an increase in voltage on the power supply. Capacitor C2 initially keeps the voltage at junction V3 close to ground. Additionally, the voltage at junction V3 can be provided at least partially by a voltage divider formed by resistors R1 and R2 and / or a second RC network RC2. The voltage at junction V3 is inverted by the second inverter 221, causing transistor Q7 to conduct and conduct current between its drain and source.

[0029] Furthermore, the first RC network RC1 and the second RC network RC2 ensure that the voltage at node V2 is at a low level, for example, between 1 and 3 volts. When ESD causes an increase in the power supply voltage, node V2 can operate as a virtual ground for the first inverter INV1. The voltage at node V2 ensures that the voltage at node V4 (through the first inverter INV1) is within the power supply threshold voltage (Vt), allowing transistor Q6 to conduct current between its drain and source. Therefore, transistors Q6 and Q7 form a current dissipation path between the power supply and ground to protect any electronic circuitry that might be coupled to voltage clamp 200.

[0030] In some implementations, transistor Q3 can provide a positive feedback signal (e.g., assert the positive feedback signal) from the second inverter 221 to the first inverter 220. For example, when the gate voltage of transistor Q7 increases in magnitude (as driven by the second inverter 221), transistor Q7 conducts and provides a current path between its drain and source to limit the voltage between the power supply and ground. The gate voltage of transistor Q7 also causes transistor Q3 to increase the current flow between its drain and source. Transistor Q3 thus drives the input to the first inverter 220 (at node V1) towards ground through the first RC network 210. In turn, the first inverter 220 drives its output high, thereby increasing the current flow in transistor Q6, which in turn enhances the operation of transistor Q7. Thus, when current flows through transistor Q7, more current is directed to flow through transistor Q6. In some implementations, the positive feedback signal can reduce the operating time (on-time) of transistors Q6 and Q7, thereby allowing the voltage clamp 200 to respond for a short duration associated with ESD phenomena.

[0031] Transistors Q1-Q7 can have the same characteristics as in Figure 1 The transistors used in electronic circuit 110 share the same features and characteristics. That is, transistors Q1-Q7 can share similar characteristic sizes, breakdown voltages, threshold voltages, etc., with other transistors in device 100. Therefore, special "high-voltage" transistors are not required in voltage clamp 200. Using the same transistors as those used in electronic circuit 110 and / or limiting the transistors used in voltage clamp 200 to the same transistors used in electronic circuit 110 can reduce manufacturing costs.

[0032] Furthermore, the voltage clamp 200 is self-biased through the arrangement of resistors R1-R4, capacitors C1-C2, and transistors Q1-Q7. No additional bias power supply or bias circuitry is required, thus simplifying circuit design and area requirements.

[0033] Among other advantages, the voltage clamp 200 can respond quickly to ESD phenomena. In some aspects, the tuning time constants of the first RC network 210 and the second RC network 211 can allow the designer to control the response time of the voltage clamp 200. In some embodiments, the voltage clamp 200 can operate within a typical ESD period of one or two nanoseconds.

[0034] Figure 2B A simplified schematic diagram of a voltage clamp 250 according to some embodiments is shown. The voltage clamp 250 can be... Figure 1 Another embodiment of the voltage clamp 120, and similar to Figure 2A The voltage clamp 200. For example, the voltage clamp 250 may include transistors Q1-Q4 and Q6-Q7 as described with respect to the voltage clamp 200. The voltage clamp 250 may also include impedance components P1-P6 replacing capacitors C1-C2 and resistors R1-R4 in place of the voltage clamp 200, and resistor R5 replacing transistor Q5. Transistors Q1 and Q2 may form a first inverter 270 similar to the first inverter 220 of the voltage clamp 200. Furthermore, a first RC network 260 may include impedance components P3 and P4, and a second RC network 261 may include impedance components P5 and P6. The second inverter 271 may include transistor Q4 and resistor R5. In this way, the voltage clamp 250 may be a more general implementation of the voltage clamp 200.

[0035] Resistor R5 can be configured to enable the second inverter 271 to function similarly to the second inverter 221 of voltage clamp 200. That is, the resistance of resistor R5 allows the second inverter 271 to drive the gate of transistor Q7 based on the output signal from the second RC network 261. In some embodiments, the resistive voltage divider formed by resistors R1 and R2 of voltage clamp 200 can be replaced by components P1 and P2 in voltage clamp 250, respectively. Components P1 and P2 can be any feasible components (transistors, inductors, diodes, etc.) configured to provide the functionality of resistors R1 and R2. Similarly, the components used to implement the first RC network 260 and the second RC network 261 can be implemented using components other than those described with respect to voltage clamp 200. For example, Figure 2A The resistor R3 and capacitor C1 of the first RC network 210 can be replaced by components P3 and P4 in the first RC network 260, respectively. Components P3 and P4 can be any feasible components configured to provide the functionality of the resistor R3 and capacitor C1 for voltage clamp 200. Figure 2AThe resistor R4 and capacitor C2 in the second RC network 211 can be replaced by components P5 and P6 in the second RC network 261, respectively. Components P5 and P6 can be any feasible components configured to provide the functionality of resistor R4 and capacitor C2 in voltage clamp 200. The universal components P1-P6 in voltage clamp 250 can provide implementation flexibility by allowing the designer to select any feasible components to provide the functionality of resistors R1-R4 and capacitors C1-C2 in voltage clamp 200.

[0036] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0037] In the foregoing specification, exemplary embodiments have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A voltage clamp, comprising: The first transistor has a drain coupled to the power supply; The second transistor has a drain coupled to the source of the first transistor and a source coupled to ground; The third transistor is configured to generate a positive feedback signal based on a first voltage at the gate of the second transistor; A first inverter is configured to control the operation of the first transistor at least in part based on the positive feedback signal, such that the first transistor and the second transistor provide a discharge path between the power supply and ground; A second inverter is configured to generate the first voltage at the gate of the second transistor; A voltage divider, coupled between the power supply and ground, is configured to provide a voltage divider output signal to the input of the second inverter; as well as A second resistor-capacitor network is coupled between the voltage divider and the second inverter, and the second resistor-capacitor network is configured to filter the voltage divider output signal provided to the input of the second inverter.

2. The voltage clamp of claim 1, wherein the output of the first inverter is coupled to the gate of the first transistor.

3. The voltage clamp of claim 1, wherein the first inverter is configured to increase the current through the source and drain of the first transistor based on the amplitude of the positive feedback signal.

4. The voltage clamp of claim 1, wherein the gate of the third transistor is coupled to the gate of the second transistor, and the drain of the third transistor is coupled to the input of the first inverter, and the positive feedback signal is provided to the input of the first inverter via the drain of the third transistor.

5. The voltage clamp of claim 1, further comprising a first resistor-capacitor network configured to provide a filtered input signal to the input of the first inverter based on the voltage difference between the power supply and the positive feedback signal.

6. The voltage clamp of claim 1, wherein the second resistor-capacitor network is configured to filter the voltage divider output signal based on the positive feedback signal.

7. The voltage clamp according to claim 1, wherein the first transistor, the second transistor and the third transistor are NMOS transistors, and the first inverter is a CMOS inverter.

8. An integrated circuit, comprising: Electronic circuits; as well as Voltage clamp, comprising: The first transistor has a drain coupled to the power supply; The second transistor has a drain coupled to the source of the first transistor and a source coupled to ground; The third transistor is configured to generate a positive feedback signal based on a first voltage at the gate of the second transistor; A first inverter is configured to control the operation of the first transistor at least in part based on the positive feedback signal, such that the first transistor and the second transistor provide a discharge path between the power supply and ground; A second inverter is configured to generate the first voltage at the gate of the second transistor; A voltage divider, coupled between the power supply and ground, and configured to provide a voltage divider output signal to the input of the second inverter; and A second resistor-capacitor network is coupled between the voltage divider and the second inverter, and the second resistor-capacitor network is configured to filter the voltage divider output signal provided to the input of the second inverter.

9. The integrated circuit of claim 8, wherein the first inverter is configured to increase the current through the source and drain of the first transistor in response to the amplitude of the positive feedback signal.

10. The integrated circuit of claim 8, wherein the gate of the third transistor is coupled to the gate of the second transistor, and the drain of the third transistor is coupled to the input of the first inverter, and the positive feedback signal is provided to the input of the first inverter via the drain of the third transistor.

11. The integrated circuit of claim 8, wherein the voltage clamp further comprises a first resistor-capacitor network configured to provide a filtered input signal to the input of the first inverter based on the voltage difference between the power supply and the positive feedback signal.

12. The integrated circuit of claim 8, wherein the second resistor-capacitor network is configured to filter the voltage divider output signal based on the positive feedback signal.

13. The integrated circuit of claim 8, wherein the first transistor, the second transistor and the third transistor are NMOS transistors, and the first inverter is a CMOS inverter.

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