Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row selection lines connected to the word driver, and a row decoder for outputting a row selection signal to the plurality of row selection lines based on input row address information. According to an embodiment, the semiconductor device can detect a failure of an address decoder in a simple method.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-016356, filed on February 3, 2020, the contents of which (including the specification, drawings and abstract) are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure specifically relates to fault detection in address decoders. Background Technology

[0004] Recently, there have been issues such as word lines not being activated or multiple word lines being selected at once due to address decoder malfunctions. In such cases, since some abnormal data is read, it is known to detect the fault using ECC (Error Correction Code) circuitry.

[0005] However, although ECC circuits can perform fault detection for 1-bit detection, 2-bit detection, etc., they suffer from the following problem: their detection capability for completely unknown data is very low. In this regard, a method has been proposed to improve detection accuracy by reading data multiple times. However, this involves the complex task of requiring multiple data reads.

[0006] In this regard, the following publicly available technologies exist.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2016-184189. Summary of the Invention

[0008] This disclosure provides a semiconductor device capable of detecting address decoder faults in a simple manner. Other issues and novel features will become apparent from the description in the specification and accompanying drawings.

[0009] According to one embodiment, a semiconductor device includes: a memory array arranged in a matrix; a plurality of word lines corresponding to rows of memory cells; a word driver for driving one of the word lines; a plurality of row select lines connected to the word driver; and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. The semiconductor device includes: a first row encoder connected to the plurality of word lines and generating first row address information based on the signal levels of the plurality of word lines; and a second row encoder connected to the plurality of word lines and generating second row address information complementary to the first row address information based on the signal levels of the plurality of word lines. The semiconductor device includes: a first row determination circuit for outputting a first row determination signal based on a comparison result between the first row address information and the second row address information.

[0010] According to one embodiment, a semiconductor device can detect address decoder faults in a simple way. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating a schematic of the semiconductor device 1 according to the first embodiment;

[0012] Figure 2 This is a diagram illustrating the memory array 2 and its peripheral circuitry according to the first embodiment;

[0013] Figure 3 This is a diagram illustrating the circuit configuration of the detection circuit 5, the row encoder 6, and the column encoder 9 in the first embodiment;

[0014] Figure 4 This is a diagram illustrating the configuration of the dummy unit DMC according to the first embodiment;

[0015] Figure 5 This is a diagram illustrating the relationship between the selection of word line WL and the first line of address information RT and the second line of address information RB to be encoded.

[0016] Figure 6 This is a diagram illustrating the relationship between the first column address information CT and the second column address information CB to be encoded and the selection of the column selection line Y;

[0017] Figure 7 This is a diagram illustrating anomalies in the row decoder 4 and column decoder 10 according to the first embodiment;

[0018] Figure 8 This is a first part of a timing diagram illustrating the operation of the semiconductor device 1 according to the first embodiment;

[0019] Figure 9 This is the second part of a timing diagram used to illustrate the operation of the semiconductor device 1 according to the first embodiment;

[0020] Figure 10 This is the third part of a timing diagram illustrating the operation of the semiconductor device 1 according to the first embodiment;

[0021] Figure 11 This is the fourth part of a timing diagram used to illustrate the operation of the semiconductor device 1 according to the first embodiment;

[0022] Figure 12 This is the fifth part of a timing diagram illustrating the operation of the semiconductor device 1 according to the first embodiment;

[0023] Figure 13 This is the sixth part of a timing diagram illustrating the operation of the semiconductor device 1 according to the first embodiment;

[0024] Figure 14 This is the seventh part of a timing diagram used to illustrate the operation of the semiconductor device 1 according to the first embodiment;

[0025] Figure 15 This is a diagram illustrating the outline of the semiconductor device 1# according to the second embodiment;

[0026] Figure 16 This is a diagram illustrating the circuit configuration of the detection circuit 5P, the row encoder 6, and the column encoder 9 according to the second embodiment;

[0027] Figure 17 This is a diagram illustrating anomalies in the row decoder 4 and column decoder 10 according to the second embodiment;

[0028] Figure 18 This is the first part of a timing diagram illustrating the operation of the semiconductor device 1# according to the second embodiment;

[0029] Figure 19 This is the second part of a timing diagram used to illustrate the operation of the semiconductor device 1# according to the second embodiment;

[0030] Figure 20 This is the third part of a timing diagram used to illustrate the operation of the semiconductor device 1# according to the second embodiment;

[0031] Figure 21 This is the fourth part of a timing diagram used to illustrate the operation of the semiconductor device 1# according to the second embodiment;

[0032] Figure 22 This is the fifth part of a timing diagram illustrating the operation of the semiconductor device 1# according to the second embodiment;

[0033] Figure 23 This is the sixth part of a timing diagram illustrating the operation of the semiconductor device 1# according to the second embodiment;

[0034] Figure 24 This is the seventh part of a timing diagram illustrating the operation of semiconductor device 1# according to the second embodiment;

[0035] Figure 25 This is a diagram illustrating the outline of the semiconductor device 1#A in the third embodiment;

[0036] Figure 26 This is a diagram illustrating the circuit configuration of the detection circuit 5Q, the row encoder 6, and the column encoder 9 according to the third embodiment;

[0037] Figure 27 This is a diagram illustrating anomalies in the row decoder 4 and column decoder 10 according to the third embodiment;

[0038] Figure 28This is the first part of a timing diagram illustrating the operation of the semiconductor device 1#A according to the third embodiment;

[0039] Figure 29 This is the second part of a timing diagram used to illustrate the operation of the semiconductor device 1#A according to the third embodiment;

[0040] Figure 30 This is the third part of a timing diagram used to illustrate the operation of the semiconductor device 1#A according to the third embodiment;

[0041] Figure 31 This is the fourth part of a timing diagram used to illustrate the operation of the semiconductor device 1#A according to the third embodiment;

[0042] Figure 32 This is the fifth part of a timing diagram illustrating the operation of the semiconductor device 1#A according to the third embodiment;

[0043] Figure 33 This is the sixth part of a timing diagram used to illustrate the operation of the semiconductor device 1#A according to the third embodiment;

[0044] Figure 34 This is the seventh part of a timing diagram used to illustrate the operation of the semiconductor device 1#A according to the third embodiment;

[0045] Figure 35 This is a diagram illustrating the outline of the semiconductor device 100 according to the fourth embodiment;

[0046] Figure 36 This is a diagram illustrating a decoder fault detection circuit 200 on the row side according to the fourth embodiment;

[0047] Figure 37 This is a diagram illustrating the detection results of the decoder fault detection circuit 110 according to the fourth embodiment;

[0048] Figure 38 This is a circuit configuration diagram of the determination circuit 120 according to the fourth embodiment;

[0049] Figure 39 This is a diagram illustrating an anomaly of the row decoder 4 and column decoder 10 according to the fourth embodiment;

[0050] Figure 40 This is the first part of a timing diagram illustrating the operation of the semiconductor device 100 according to the fourth embodiment;

[0051] Figure 41 This is the second part of a timing diagram illustrating the operation of the semiconductor device 100 according to the fourth embodiment;

[0052] Figure 42This is the third part of a timing diagram illustrating the operation of the semiconductor device 100 according to the fourth embodiment;

[0053] Figure 43 This is a diagram illustrating the circuit configuration of the decoder fault detection circuit 110# and the determination circuit 120# according to the fourth embodiment.

[0054] Figure 44 This is a diagram illustrating an anomaly of the modified row decoder 4 and column decoder 10 according to the fourth embodiment;

[0055] Figure 45 This is the first part of a timing diagram illustrating the operation of a semiconductor device 100 according to a variant of the fourth embodiment;

[0056] Figure 46 This is the second part of a timing diagram illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment;

[0057] Figure 47 This is the third part of a timing diagram illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment;

[0058] Figure 48 This is the fourth part of a timing diagram illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment;

[0059] Figure 49 This is the fifth part of a timing diagram illustrating the operation of the semiconductor device 100 according to a variant of the fourth embodiment;

[0060] Figure 50 This is a diagram illustrating the general outline of the semiconductor device 1P according to the fifth embodiment;

[0061] Figure 51 This is a diagram illustrating the memory array 2 and its peripheral circuitry according to the fifth embodiment;

[0062] Figure 52 This is a diagram illustrating the detection unit 140 of the detection circuit 132 according to the fifth embodiment;

[0063] Figure 53 This is a diagram illustrating the detection result of the detection circuit 132 according to the fifth embodiment;

[0064] Figure 54 This is a diagram illustrating the synthesis circuit 134 of the detection circuit 132 according to the fifth embodiment;

[0065] Figure 55 This is a diagram illustrating an anomaly of the row decoder 4 and column decoder 10 according to the fifth embodiment;

[0066] Figure 56This is the first part of a timing diagram illustrating the operation of the semiconductor device 100 according to Embodiment 5;

[0067] Figure 57 This is the second part of a timing diagram illustrating the operation of the semiconductor device 100 according to the fifth embodiment;

[0068] Figure 58 This is the third part of a timing diagram illustrating the operation of the semiconductor device 100 according to the fifth embodiment;

[0069] Figure 59 This is the fourth part of a timing diagram illustrating the operation of the semiconductor device 100 according to the fifth embodiment;

[0070] Figure 60 This is a diagram illustrating the circuit configuration of the detection circuit 5Q according to the sixth embodiment;

[0071] Figure 61 This is a diagram illustrating the configuration of the detector 5X according to the seventh embodiment;

[0072] Figure 62 This is a diagram illustrating the test mode of DFT circuits 140 and 142 according to the seventh embodiment;

[0073] Figure 63 This is a diagram illustrating the configuration of detector 5Y according to the seventh embodiment of modified 1;

[0074] Figure 64 This is a diagram illustrating the test mode of the DFT circuits 140 and 142 according to the seventh embodiment of the modified 1;

[0075] Figure 65 This is a diagram illustrating the decoder fault detection circuit 210 on the horizontal side according to the seventh embodiment of the modified 2;

[0076] Figure 66 This is a diagram illustrating the circuit configuration of the decoder fault detection circuit 110#X and the determination circuit 120#X according to the seventh embodiment of the modified 3.

[0077] Figure 67 This is a diagram illustrating the detection unit 140# of the detection circuit 132 according to the seventh embodiment of the modified 4. Detailed Implementation

[0078] In the accompanying drawings, the same or corresponding components are identified by the same reference numerals and their descriptions will not be repeated.

[0079] <Example 1>

[0080] Figure 1 This is a diagram illustrating the general outline of the semiconductor device 1 according to the first embodiment.

[0081] Reference Figure 1 The semiconductor device 1 includes a memory macro 15 and a CPU 20.

[0082] CPU 20 controls memory macro 15 to retrieve data stored in memory macro 15.

[0083] The memory macro 15 includes a memory array 2, a word driver 3, a row decoder 4, a detection circuit 5, a row encoder 6, a column selection circuit 7, a pre-decoder 8, a column encoder 9, and a column decoder 10.

[0084] The memory array 2 includes multiple memory cells MC arranged in a matrix.

[0085] The memory array 2 includes multiple word lines WL and multiple bit lines BL, each corresponding to a row of memory cells.

[0086] Word driver 3 drives one of the multiple word lines WL that are set up corresponding to the rows of memory cells.

[0087] Set multiple line selection lines (RWL) between line decoder 4 and word driver 3.

[0088] The pre-decoder 8 decodes the input address information IAD and splits it into input row address information RAD and input column address information CAD, which are output to row decoder 4 and column decoder 10, respectively. As an example, in this example, the 4-bit input row address information RAD is split into 7-bit input row address information RAD and 3-bit input column address information CAD, and they are output to row decoder 4 and column decoder 10, respectively.

[0089] The line decoder 4 outputs the line selection signal to multiple line selection lines RWL based on the input line address information RAD.

[0090] Word driver 3 selects word line WL based on the line selection signal and raises it to the "H" level.

[0091] The detection circuit 5 detects faults in the row decoder 4 and the column decoder 10.

[0092] The line encoder 6 is connected to multiple word lines WL and encodes the line address information based on the rising edge of the selected word line WL.

[0093] The column selection circuit 7 selects one bit line from multiple bit lines BL.

[0094] Multiple column selection lines Y are provided between the column decoder 10 and the column selection circuit 7.

[0095] The column decoder 10 outputs column selection signals to multiple column selection lines Y based on the input column address information CAD.

[0096] The column encoder 9 is connected to multiple column select lines Y and encodes column address information based on the rising edge of the selected column select line Y.

[0097] Figure 2 This is a diagram illustrating the memory array 2 and its peripheral circuitry according to the first embodiment.

[0098] Reference Figure 2 The memory array 2 includes multiple memory cells MC arranged in a matrix, multiple word lines WL corresponding to each row of memory cells, and multiple bit lines BL, / BL corresponding to each row of memory cells.

[0099] In this exemplary embodiment, word lines WL[0] to WL

[15] are provided corresponding to the memory cell rows, respectively.

[0100] Bit lines BL[0] to BL[7] and complementary bit lines / BL[0] to / BL[7] are respectively set to correspond to the memory cell columns.

[0101] The line decoder 4 outputs the line selection signal to multiple line selection lines RWL[0] to RWL

[15] based on the input line address information RAD.

[0102] Word driver 3 is connected to multiple line select lines RWL[0] to RWL

[15] and includes a driver unit for driving one of the word lines WL[0] to WL

[15] . For example, when line select line RWL[0] is set to "H" level, word driver 3 selects word line WL[0]. Specifically, word line WL[0] is set to "H" level. The same applies to the other word lines WL.

[0103] The column decoder 10 outputs the column selection signal to multiple column selection lines Y[0] to Y[7] based on the input column address information CAD.

[0104] Column selection circuit 7 is connected to multiple column selection lines Y[0] to Y[7] to select one of multiple bit lines BL. Specifically, it connects read / write circuit 12 to bit line BL. When reading data, read / write circuit 12 outputs the data signal read through the selected bit line BL as read data DTO. When writing data, read / write circuit 12 writes the input write data DTI to memory cell MC via the selected bit line BL. Although one-bit data read and write are described in this example, the invention is not limited to this and can certainly perform parallel read and parallel write of multiple bits (8 bits, 16 bits, etc.).

[0105] Figure 3 This is a diagram illustrating the circuit configuration of the detection circuit 5, the row encoder 6, and the column encoder 9 according to the first embodiment.

[0106] Reference Figure 3 The row encoder 6 includes a first row encoder 6A, a second row encoder 6B, a pre-charge circuit 6C, and a driver circuit 6D.

[0107] The first line encoder 6A includes multiple word lines WL[0] to WL

[15] , multiple data lines DL[0] to DL[3], and multiple dummy units DMC, which are arranged in a matrix in a predetermined first pattern at the intersection of the word lines WL and the data lines DL.

[0108] The second line encoder 6B includes multiple word lines WL[0] to WL

[15] , multiple data lines DL[4] to DL[7], and multiple dummy units DMC, which are arranged in a matrix in a predetermined second pattern.

[0109] The pre-charge circuit 6C is respectively provided with multiple data lines DL[0] to DL[7], and includes multiple pre-charge transistors PT for pre-charging the multiple data lines DL[0] to DL[7] to a predetermined voltage. The pre-charge transistors PT operate according to the control signal PCB, and when the control signal PCB is at the "L" level, they pre-charge the multiple data lines DL[0] to DL[7] to the predetermined voltage.

[0110] The driver circuit 6D includes inverters that are respectively configured to correspond to multiple data lines DL[0] to DL[7], and the inverters invert and output the data of the multiple data lines DL[0] to DL[7].

[0111] Figure 4 This is a diagram illustrating the configuration of the dummy unit DMC according to the first embodiment.

[0112] Reference Figure 4 The dummy cell DMC includes a transistor TRS. The transistor TRS is connected between a fixed voltage VSS and the data line DL, and its gate is connected to the word line WL. Therefore, when the word line WL is at the "H" level, the transistor TRS is turned on, and the data line DL is set to the "L" level.

[0113] Therefore, when word line WL is set to "H" level, the dummy cell DMC located at the intersection of word line WL and data line DL becomes on, and data line DL is set to "L" level.

[0114] Return to reference Figure 3The multiple dummy units DMC provided in the first line encoder 6A are arranged in a predetermined first pattern to encode the address information used to select any one of the word lines WL when the word line WL is selected.

[0115] For example, when word line WL[0] is selected, the dummy cell DMC is not positioned at the intersection of word line WL[0] and data lines DL[0] to DL[3].

[0116] Therefore, data lines DL[0] to DL[3] maintain a predetermined pre-charge voltage level (“H” level).

[0117] In response, the driver circuit 6D inverts the data on data lines DL[0] to DL[3] and outputs the inverted data ("L" level).

[0118] In this example, when the output of driver circuit 6D is at the "H" level, the data is set to "1". When the output of driver circuit 6D is at the "L" level, the data should be "0".

[0119] In this scenario, when word line WL[0] is selected, the first row encoder 6A generates the first row address data RT (“0000”) via the data lines DL through the driver circuits 6D[0] to DL[3]. Even when another word line WL is selected, the first row encoder 6A generates the first row address data RT for selecting word line WL in the same manner via the data lines DL[0] to DL[3].

[0120] The second row encoder 6B generates the second row address information RB, which is complementary to the first row encoder 6A.

[0121] The plurality of dummy units DMCs provided in the second row encoder 6B are arranged in a predetermined second pattern to encode the address information used to select any word line WL when a word line WL is selected. Incidentally, according to the logic of the detection circuit 5, the first pattern of the plurality of dummy units DMCs provided in the first row encoder 6A and the second pattern of the plurality of dummy units DMCs provided in the second row encoder 6B may be opposite patterns to each other.

[0122] For example, when word line WL[0] is selected, the dummy cell DMC is positioned at the intersection of word line WL[0] and data lines DL[4]-DL[7].

[0123] Therefore, data lines DL[4] to DL[7] are set to the "L" level from the predetermined pre-charge voltage level. Driver circuit 6D inverts the data on data line DL and outputs the inverted data. When driver circuit 6D is at the "L" level, the data should be "0". When driver circuit 6D is at the "H" level, the data should be "1".

[0124] In this scenario, when word line WL[0] is selected, the second row encoder 6B generates second row address data RB (“1111”) via data lines DL[4] to DL[7] through driver circuit 6D. When another word line WL is selected, the second row encoder 6B generates second row address data RB for selecting word line WL in the same manner via data lines DL[4] to DL[7].

[0125] Figure 5 This is a diagram illustrating the relationship between the selection of word line WL and the first row of address information RT and the second row of address information RB in the encoding.

[0126] like Figure 5 As shown, the first row of address information RT and the second row of address information RB are shown according to the selection of word lines WL[0] to WL

[15] .

[0127] The first line of address information RT and the second line of address information RB are shown to be complementary to each other.

[0128] Return to reference Figure 3 The column encoder 9 includes a first column encoder 9A and a second column encoder 9B.

[0129] The first column encoder 9A includes multiple column selection lines Y[0]-Y[7], multiple NOR circuits 41, 42, 44, 45, 46, 48 and multiple NAND circuits 40, 43, 47.

[0130] Multiple NOR circuits and multiple NAND circuits provided in the first column encoder 9A are connected to the column select line Y in a predetermined combination so as to decode the address information used to select the column select line Y when any set of column select lines Y is selected.

[0131] Specifically, NOR circuit 41 receives input from column select line Y[7] and column select line Y[6], and outputs the result of NOR logic operation. NOR circuit 42 receives input from column select line Y[5] and column select line Y[4], and outputs the result of NOR logic operation. NOR circuit 44 receives input from column select line Y[7] and column select line Y[6], and outputs the result of NOR logic operation. NOR circuit 45 receives input from column select line Y[3] and column select line Y[2], and outputs the result of NOR logic operation. NOR circuit 46 receives input from column select line Y[7] and column select line Y[5], and outputs the result of NOR logic operation. NOR circuit 48 receives input from column select line Y[3] and column select line Y[1], and outputs the result of NOR logic operation.

[0132] NAND circuit 40 outputs the NAND logic operation result by receiving inputs from NOR circuits 41 and 42.

[0133] NAND circuit 43 outputs the result of NAND logic operation by receiving inputs from NOR circuits 44 and 45.

[0134] NAND circuit 45 outputs the results of NAND logic operations by receiving inputs from NOR circuits 46 and 48.

[0135] For example, when column select line Y[7] is selected, NOR circuits 41, 44 and 46 connected to column select line Y[7] output an "L" level. Accordingly, NAND circuits 40, 43 and 47 output an "H" level respectively.

[0136] In this case, when column selection line Y[7] is selected, the first column encoder 9A generates the first column address information CT (“111”). When multiple column selection lines Y are selected, the first column encoder 9A generates the first column address information CT for selecting column selection lines Y in the same manner.

[0137] The second column encoder 9B generates a second column address information CB that is complementary to the first column encoder 9A.

[0138] The second column encoder 9B includes multiple column selection lines Y[0]-Y[7], multiple NOR circuits 49, 51, 52, 54, 55, 57 and multiple NAND circuits 50, 53, 56. Similar to the first row encoder 6A and the second row encoder 6B, the first column encoder 9A and the second column encoder 9B can be configured using a dummy unit DMC.

[0139] Multiple NOR circuits and multiple NAND circuits provided in the second column encoder 9B are connected to the column selection line Y in a predetermined combination so as to decode the address information used to select the column selection line Y when any column selection line Y is selected.

[0140] Specifically, NOR circuit 49 receives input from column select line Y[3] and column select line Y[2], and outputs the result of NOR logic operation. NOR circuit 51 receives input from column select line Y[1] and column select line Y[0], and outputs the result of NOR logic operation. NOR circuit 52 receives input from column select line Y[5] and column select line Y[4], and outputs the result of NOR logic operation. NOR circuit 54 receives input from column select line Y[1] and column select line Y[0], and outputs the result of NOR logic operation. NOR circuit 55 receives input from column select line Y[6] and column select line Y[4], and outputs the result of NOR logic operation. NOR circuit 57 receives input from column select line Y[2] and column select line Y[0], and outputs the result of NOR logic operation.

[0141] NAND circuit 50 outputs the results of NAND logic operations by receiving inputs from NOR circuits 49 and 51.

[0142] NAND circuit 53 outputs the results of NAND logic operations by receiving inputs from NOR circuits 52 and 54.

[0143] NAND circuit 56 outputs the results of NAND logic operations by receiving inputs from NOR circuits 55 and 57.

[0144] For example, if column select line Y[7] is selected, the NOR circuit is not connected. Therefore, NAND circuits 50, 53, and 56 remain at the "L" level.

[0145] In this case, when column selection line Y[7] is selected, the second column encoder 9B generates the second column address information CB(“000”). When multiple column selection lines Y are selected, the second column encoder 9B generates the second column address information CB for selecting column selection lines Y in the same manner.

[0146] Figure 6 This is a diagram used to illustrate the relationship between the selection of column selection line Y and the encoded first column address information CT and second column address information CB.

[0147] like Figure 6 As shown, the first column address information CT and the second column address information CB are shown according to the selection of column selection lines Y[0] to Y[7].

[0148] The case where the first column of address information CT and the second column of address information CB are complementary is shown.

[0149] Return to reference Figure 3The detection circuit 5 includes a first row determination circuit 5A, a second row determination circuit 5B, a first column determination circuit 5C, a second column determination circuit 5D, and a synthesis circuit 5E.

[0150] The first row determination circuit 5A includes EXOR circuits 64-67 and NAND circuit 70.

[0151] The second-row decision circuit 5B includes EXOR circuits 60-63 and NOR circuit 72.

[0152] The first column determination circuit 5C includes EXOR circuits 33-35 and NAND circuit 36.

[0153] The second column of the decision circuit 5D includes EXOR circuits 30-32 and NAND circuit 37.

[0154] The combinational circuit 5E includes a NAND circuit 74, an OR circuit 75, and a flip-flop (FF) 76.

[0155] The first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG based on the comparison result.

[0156] EXOR circuits 64 to 67 receive one bit of the first row address information RT and the second row address information RB, respectively, and output the EXOR logic operation result RBO to NAND circuit 70.

[0157] When the first line of address information RT and the second line of address information RB are normal, they complement each other.

[0158] Therefore, when the first row address information RT and the second row address information RB are complementary (normal), the EXOR logic operation results RBO of EXOR circuits 64 to 67 all output "H" level. In this case, NAND circuit 70 outputs the first row determination signal RFLG ("L" level). Conversely, when the first row address information RT and the second row address information RB are not complementary (when they are abnormal), at least one of the EXOR logic operation results RBO of EXOR circuits 64 to 67 outputs "L" level. In this case, NAND circuit 70 outputs the first row determination signal RFLG ("H" level).

[0159] The first line determination signal RFLG ("H" level) determines that the first line address information RT and the second line address information RB are not complementary (in the case of an abnormality). That is, it determines that the line decoder 4 is abnormal and has not been decoded normally.

[0160] Specifically, the line decoder 4 determines the following exceptions: non-selection exception when multiple word lines WL are not selected and multi-selection exception when multiple word lines WL are selected.

[0161] The second row determination circuit 5B compares the input row address information RAD with the first row address information RT, and outputs the second row determination signal RCMP based on the comparison result.

[0162] EXOR circuits 60 to 63 receive the input row address information RAD and the first row address information RT bit by bit, and output the EXOR logic operation result RTO to NOR circuit 72.

[0163] When the input row address information RAD and the first row address information RT are normal, they have the same relationship.

[0164] Therefore, when the input row address information RAD and the first row address information RT are in the same relationship (when they are normal), the EXOR logic operation results RTO of all EXOR circuits 60 to 63 output an "L" level. In this case, the NOR circuit 72 outputs the second row determination signal RCMP ("H" level). On the other hand, when the input row address information RAD and the first row address information RT are not in the same relationship (when the input row address information RAD and the first row address information RT are abnormal), at least one of the EXOR logic operation results RTO of EXOR circuits 60 to 63 outputs an "H" level. In this case, the NOR circuit 72 outputs the second row determination signal RCMP ("L" level).

[0165] The second line determination signal RCMP ("L" level) determines that the input line address information RAD and the first line address information RT are not the same (if abnormal). That is, it determines that the line decoder 4 is abnormal and has not been decoded normally.

[0166] Specifically, an error selection anomaly is determined by an anomaly in line decoder 4, in which an incorrect word line WL is selected among multiple word lines WL.

[0167] The first column determination circuit 5C compares the first column address information CT with the second column address information CB, and outputs the first column determination signal CFLG based on the comparison result.

[0168] EXOR circuits 33 to 35 receive one bit of the first column address information CT and the second column address information CB respectively, and output the EXOR logic operation result CBO to NAND circuit 36.

[0169] When the first column of address information CT and the second column of address information CB are normal, they complement each other.

[0170] Therefore, when the first column address information CT and the second column address information CB are complementary (normal), the EXOR logic operation results CBO of EXOR circuits 33 to 35 all output "H" level. In this case, NAND circuit 36 ​​outputs the first column decision signal CFLG ("L" level). Conversely, when the first column address information CT and the second column address information CT are not complementary (when they are abnormal), at least one of the EXOR logic operation results CBO of EXOR circuits 33 to 35 outputs "L" level. In this case, NAND circuit 36 ​​outputs the first column decision signal CFLG ("H" level).

[0171] Based on the first column determination signal CFLG (“H” level), it is determined that the first column address information CT and the second column address information CB have no complementary relationship (when they are abnormal). That is, it is determined that the column decoder 10 is abnormal and has not been decoded normally.

[0172] Specifically, the following situations are determined by the column decoder 10: non-selection anomaly when multiple column selection lines Y are not selected and multi-selection anomaly when multiple column selection lines Y are selected among multiple column selection lines Y.

[0173] The second column determination circuit 5D compares the input column address information CAD with the first column address information CT, and outputs the second column determination signal CCMP based on the comparison result.

[0174] EXOR circuits 30 to 32 receive the input column address information CAD and the first column address information CT one bit at a time, and output the EXOR logic operation result CTO to NOR circuit 37.

[0175] When the input column address information CAD and the first column address information CT are normal, they have the same relationship.

[0176] Therefore, when the input column address information CAD and the first column address information CT are in the same relationship (when they are normal), the EXOR logic operation result CTO of all EXOR circuits 30 to 32 outputs an "L" level. In this case, the NOR circuit 37 outputs the second column determination signal CCMP ("H" level). On the other hand, when the input column address information CAD and the first column address information CT are not in the same relationship (when the input column address information CAD and the first column address information CT are abnormal), at least one of the EXOR logic operation results CTO of the EXOR circuits 30 to 32 outputs an "H" level. In this case, the NOR circuit 37 outputs the second column determination signal CCMP ("L" level).

[0177] Based on the second column determination signal CCMP (“L” level), it is determined that the input column address information CAD and the first column address information CT do not have the same relationship (when they are abnormal). That is, it is determined that the column decoder 10 is abnormal and has not been decoded normally.

[0178] More specifically, an error selection anomaly is determined by an anomaly in column decoder 10, wherein an incorrect column selection line Y is selected among multiple column selection lines Y.

[0179] In combinational circuit 5E, NAND circuit 74 responds to the inputs of the second row decision signal RCMP and the second column decision signal RCMP, and outputs the NAND logic operation result to OR circuit 75. OR circuit 75 receives the first row decision signal RFLG, the first column decision signal CFLG, and the output of NAND circuit 74, and outputs the OR logic operation result to flip-flop 76.

[0180] If the OR circuit 75 includes the first row decision signal RFLG (“L” level), the second row decision signal RCMP (“H” level), the first column decision signal CFLG (“L” level), and the second column decision signal CCMP (“H” level), the “L” level is stored in the flip-flop 76. On the other hand, if the OR circuit 75 includes any of the states of the first row decision signal RFLG (“H” level), the second row decision signal RCMP (“H” level), the first column decision signal CFLG (“H” level), and the second column decision signal CCMP (“L” level), the “H” level is stored in the flip-flop 76.

[0181] Trigger 76 outputs an exception signal FLAG based on the stored data.

[0182] Figure 7 This is a diagram used to illustrate the anomalies of the row decoder 4 and column decoder 10 according to the first embodiment.

[0183] like Figure 7 As shown, when a non-selection anomaly occurs due to an anomaly in the line decoder 4, where multiple word lines WL are not selected, or a multi-selection anomaly occurs where multiple word lines WL are selected, the anomaly signal FLAG (H level) is set according to the first line determination signal RFLG (H level).

[0184] When an erroneous selection exception occurs due to an anomaly in the line decoder 4, in which an incorrect word line WL is selected from multiple word lines WL, the exception signal FLAG (H level) is set according to the second line decision signal RCMP (L level).

[0185] When a non-selection anomaly occurs due to an anomaly in column decoder 10, such that multiple column selection lines Y are not selected, or a multi-selection anomaly occurs when multiple column selection lines Y are selected, the anomaly signal FLAG (H level) is set according to the first column determination signal CFLG (H level).

[0186] When an erroneous selection of a column selection line Y occurs due to an anomaly in the column decoder 10, in which an incorrect column selection line Y is selected, the anomaly signal FLAG (H level) is set according to the second column determination signal CCMP (L level).

[0187] When both row decoder 4 and column decoder 10 are functioning correctly, the error signal FLAG is set to the "L" level.

[0188] The detection circuit 5 of the first embodiment outputs an abnormal signal FLAG to the CPU 20.

[0189] According to the first embodiment, detector 5 outputs an abnormality signal FLAG during data reading and data writing. Therefore, according to the configuration of the first embodiment, faults in the address decoders (row decoder 4 and column decoder 10) can be detected at an early stage in a simple manner.

[0190] Figure 8 This is a first timing diagram illustrating the operation of the semiconductor device 1 according to the first embodiment.

[0191] This example will describe the normal operating condition.

[0192] like Figure 8 As shown, at time T0, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0193] Furthermore, at time T0, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0194] At time T1, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0195] Therefore, since the first column relation circuit 5C compares the first column address information CT and the second column address information CB and they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0196] At time T2, because the input column address information CAD and the first column address information CT are compared and matched, the second column determination circuit 5D outputs the second column determination signal CCMP (“H” level).

[0197] Furthermore, at time T2, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0198] At time T3, the first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. In this example, the first row address information RT and the second row address information RB are generated as complementary to each other.

[0199] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0200] At time T4, the second row determination circuit 5B outputs the second row determination signal RCMP for matching by comparing the input row address information RAD and the first row address information RT ("H" level).

[0201] At time T5, the detection circuit 5 outputs an abnormal signal FLAG ("L" level) based on the first row determination signal RFLG ("L" level), the second row determination signal RCMP ("H" level), the first column determination signal CFLG ("L" level), and the second column determination signal CCMP ("H" level).

[0202] Figure 9 This is a timing diagram (part 2) illustrating the operation of the semiconductor device 1 according to the first embodiment.

[0203] This example will describe the case where the word line WL is not selected.

[0204] like Figure 9 As shown, at time T6, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0205] Furthermore, at time T7, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0206] At time T7, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0207] Therefore, since the first column determination circuit 5C and the second column address information CB are complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and outputs the first column determination signal CFLG (“L” level).

[0208] At time T8, because the input column address information CAD and the first column address information CT are compared and matched, the second column determination circuit 5D outputs the second column determination signal CCMP (“H” level).

[0209] Furthermore, in this exemplary embodiment, due to an error, the line decoder 4 did not select one of the multiple word lines WL based on the input line address information RAD.

[0210] The first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. However, in this embodiment, the first row address information RT and the second row address information RB are not generated as complementary to each other.

[0211] Therefore, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and maintains the first row determination signal RFLG ("H" level) because they are not complementary to each other.

[0212] At time T9, the second row determination circuit 5B compares the input row address information RAD with the first row address information RT and outputs the second row determination signal RCMP (“L” level) because they do not match.

[0213] At time T10, the detection circuit 5 outputs an abnormal signal FLAG ("H" level) based on the first row determination signal RFLG ("H" level), the second row determination signal RCMP ("L" level), the first column determination signal CFLG ("L" level), and the second column determination signal CCMP ("H" level).

[0214] Therefore, an anomaly can be detected when an unselected anomaly occurs, where one of the multiple word lines WL is not selected.

[0215] Figure 10 This is a timing diagram (part 3) used to illustrate the operation of the semiconductor device 1 according to the first embodiment.

[0216] This example will describe the case where multiple word lines WL are selected among multiple word lines WL.

[0217] like Figure 10 As shown, at time T11, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0218] Furthermore, at time T12, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0219] At time T12, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0220] Therefore, since the first column relation circuit 5C compares the first column address information CT and the second column address information CB and they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0221] At time T13, because the input column address information CAD and the first column address information CT are compared and matched, the second column determination circuit 5D outputs the second column determination signal CCMP (“H” level).

[0222] Furthermore, at time T13, the line decoder 4 selects the multiple word lines WL that are affected by the anomaly from the multiple word lines WL based on the input line address information RAD.

[0223] At time T14, the first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. However, in this embodiment, the first row address information RT and the second row address information RB are not generated as complementary relationships.

[0224] Therefore, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and maintains the first row determination signal RFLG ("H" level) because they are not complementary to each other.

[0225] At time T15, because the input row address information RAD is inconsistent with the first row address information RT, the second row determination circuit 5B compares the input row address information RAD with the first row address information RT and outputs the second row determination signal RCMP (“L” level). In this embodiment, the case of outputting the second row determination signal RCMP (“L” level) will be described; however, depending on the conditions, it can be considered that the case of outputting the second row determination signal RCMP (“H” level) is consistent with the case of comparing the input row address information RAD and the first row address information RT.

[0226] At time T16, the detection circuit 5 outputs an abnormal signal FLAG ("H" level) based on the first row determination signal RFLG ("H" level), the second row determination signal RCMP ("L" level), the first column determination signal CFLG ("L" level), and the second column determination signal CCMP ("H" level).

[0227] An anomaly can be detected when multiple selection anomalies occur, where multiple word lines WL are selected among multiple word lines WL.

[0228] Figure 11 This is a timing diagram (part 4) used to illustrate the operation of the semiconductor device 1 according to the first embodiment.

[0229] This example describes a case of incorrect selection exception where an incorrect word line WL is selected from multiple word lines WL.

[0230] like Figure 11 As shown, at time T17, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0231] Furthermore, at time T17, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0232] At time T18, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0233] Therefore, since the first column relation circuit 5C compares the first column address information CT and the second column address information CB and they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0234] At time T19, because the input column address information CAD and the first column address information CT are compared and matched, the second column determination circuit 5D outputs the second column determination signal CCMP (“H” level).

[0235] Furthermore, at time T19, the line decoder 4 selects the erroneous word line WL caused by the error from multiple word lines WL based on the input line address information RAD.

[0236] At time T20, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. However, in this example, the first line address information RT and the second line address information RB are generated as complementary to each other based on the erroneous word line WL.

[0237] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0238] At time T21, because the input row address information RAD is inconsistent with the first row address information RT, the second row determination circuit 5B compares the input row address information RAD with the first row address information RT and outputs the second row determination signal RCMP (“L” level).

[0239] At time T22, the detection circuit 5 outputs an abnormal signal FLAG ("H" level) based on the first row determination signal RFLG ("L" level), the second row determination signal RCMP ("L" level), the first column determination signal CFLG ("L" level), and the second column determination signal CCMP ("H" level).

[0240] An anomaly can be detected when an incorrect word line WL is selected from multiple word lines WL.

[0241] Figure 12 This is a timing diagram (part 5) illustrating the operation of the semiconductor device 1 according to the first embodiment.

[0242] In this example, we will describe the case where the selection operation for column selection line Y is not performed.

[0243] like Figure 12 As shown, at time T23, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0244] In this example, column decoder 10 does not select one of the multiple column selection lines Y based on the input column address information CAD.

[0245] The first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are not generated as complementary relationships.

[0246] Therefore, since the first column determination circuit and the second column address information CB are not complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and maintains the first column determination signal CFLG (“H” level).

[0247] At time T23, because the input column address information CAD and the first column address information CT are compared and do not match, the second column determination circuit 5D outputs the second column determination signal CCMP (“L” level).

[0248] Furthermore, at time T23, the line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0249] At time T24, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0250] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0251] At time T25, the second row determination circuit 5B compares the input row address information RAD with the first row address information RT ("H" level) to output the second row determination signal RCMP for matching.

[0252] At time T26, the detection circuit 5 outputs an abnormal signal FLAG ("H" level) based on the first row determination signal RFLG ("L" level), the second row determination signal RCMP ("H" level), the first column determination signal CFLG ("H" level), and the second column determination signal CCMP ("L" level).

[0253] Therefore, an anomaly can be detected when an unselected anomaly occurs, where one of the multiple column selection lines Y is not selected.

[0254] Figure 13 This is a timing diagram (part 6) used to illustrate the operation of the semiconductor device 1 according to the first embodiment.

[0255] This example will describe the situation where multiple column selection lines Y are selected out of multiple column selection lines Y.

[0256] like Figure 13 As shown, at time T26, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0257] Furthermore, at time T26, in this exemplary embodiment, the column decoder 10 selects multiple column selection lines Y based on the input column address information CAD.

[0258] At time T27, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are not generated as complementary to each other.

[0259] Therefore, since the first column determination circuit and the second column address information CB are not complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and maintains the first column determination signal CFLG (“H” level).

[0260] At time T28, because the input column address information CAD and the first column address information CT are compared and do not match, the second column determination circuit 5D outputs the second column determination signal CCMP (“L” level).

[0261] Furthermore, at time T28, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0262] At time T29, the first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. In this example, the first row address information RT and the second row address information RB are generated as complementary to each other.

[0263] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0264] At time T30, the second row determination circuit 5B outputs the second row determination signal RCMP by comparing the input row address information RAD and the first row address information RT ("H" level) and finding that they match.

[0265] At time T31, the detection circuit 5 outputs an abnormal signal FLAG ("H" level) based on the first row determination signal RFLG ("L" level), the second row determination signal RCMP ("H" level), the first column determination signal CFLG ("H" level), and the second column determination signal CCMP ("L" level).

[0266] Therefore, an anomaly can be detected when multiple selection anomalies occur, where multiple column selection lines Y out of multiple column selection lines Y are selected.

[0267] Figure 14 This is a timing diagram (part 7) used to illustrate the operation of the semiconductor device 1 according to the first embodiment.

[0268] In this example, a case of incorrect selection exception will be described, where an incorrect column selection line Y is selected from multiple column selection lines Y.

[0269] like Figure 14 As shown, at time T32, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0270] Furthermore, at time T32, in this exemplary embodiment, the column decoder 10 selects the incorrect column selection line Y among multiple column selection lines Y based on the input column address information CAD.

[0271] At time T33, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are generated as complementary to each other based on the incorrect column selection line Y.

[0272] Therefore, the first column determination circuit 5C compares the first column address information CT with the second column address information CB, and because the first column address information CT and the second column address information CB are complementary, it outputs the first column determination signal CFLG (“L” level).

[0273] At time T34, because the input column address information CAD and the first column address information CT are compared and do not match, the second column determination circuit 5D outputs the second column determination signal CCMP (“L” level).

[0274] Furthermore, at time T34, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0275] At time T35, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0276] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0277] At time T36, the second row determination circuit 5B compares the input row address information RAD with the first row address information RT ("H" level) to output the second row determination signal RCMP for matching.

[0278] At time T37, the detection circuit 5 outputs an abnormal signal FLAG ("H" level) based on the first row determination signal RFLG ("L" level), the second row determination signal RCMP ("H" level), the first column determination signal CFLG ("H" level), and the second column determination signal CCMP ("L" level).

[0279] Therefore, an anomaly can be detected when an incorrect selection anomaly occurs, in which an incorrect column selection line Y is selected among multiple column selection lines Y.

[0280] <Example 2>

[0281] Figure 15 This is a diagram illustrating the outline of the semiconductor device 1# according to the second embodiment.

[0282] Reference Figure 15 Semiconductor device 1# includes memory macro 15#, CPU 20 and comparator 11.

[0283] CPU 20 controls memory macro 15# to retrieve data stored in memory macro 15#.

[0284] The difference between memory macro 15# and memory macro 15 is that detection circuit 5 is replaced by detection circuit 5P. Since the other configurations are the same, their detailed description will not be repeated.

[0285] The detection circuit 5P outputs output address information AQ based on the first row address information RT and the second row address information RB output from the row encoder 6, and the first column address information CT and the second column address information CB output from the column encoder 9. The output address information AQ includes output row address information ORAD and output column address information OCAD.

[0286] The comparator circuit 11 compares the output address information AQ output from the detector circuit 5P with the input address information IAD, and outputs the comparison result to the CPU 20.

[0287] Figure 16 This is a diagram illustrating the circuit configuration of the detection circuit 5P, the row encoder 6, and the column encoder 9 according to a second exemplary embodiment.

[0288] Refer to 16, and Figure 3 Compared to the detection circuit 5, the detection circuit 5P includes a first row determination circuit 5A, a second row determination circuit 5B#, a first column determination circuit 5C, and a second column determination circuit 5D#.

[0289] The first row determination circuit 5A includes EXOR circuits 64-67 and NAND circuit 70.

[0290] The second row of decision circuit 5B# includes EXOR circuits 60# to 63# and flip-flops (FF) 80 to 83.

[0291] The first column determination circuit 5C includes EXOR circuits 33-35 and NAND circuit 36.

[0292] The second column of decision circuit 5D# includes EXOR circuits 30# to 32# and flip-flops (FF) 77 to 79.

[0293] The first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG based on the comparison result.

[0294] As described in the first embodiment, the first line determination signal RFLG ("H" level) determines that the first line address information RT and the second line address information RB are not complementary (in the case of an abnormality). That is, it determines that the line decoder 4 is abnormal and has not been decoded normally.

[0295] Specifically, due to the anomaly of line decoder 4, the following situations are determined: multi-selection anomaly when multiple word lines WL are not selected, and multi-selection anomaly when multiple word lines WL are selected.

[0296] The second row determination circuit 5B# generates the output row address information ORAD based on the first row address information RT and the first column determination signal CFLG.

[0297] EXOR circuits 60# to 63# receive the first row address information RT and the first column determination signal CFLG by 1 bit respectively, and output the EXOR logic operation result RTO to flip-flops 80 to 83 respectively.

[0298] If there is no anomaly in column decoder 10, the first column determination signal CFLG is set to the "L" level. On the other hand, when column decoder 10 is faulty, the first column determination signal CFLG is set to the "H" level.

[0299] EXOR circuits 60# to 63# receive the first row address information RT and the first column determination signal CFLG (“L” level) as inputs, and output the EXOR logic operation result RTO to flip-flops 80 to 83 respectively.

[0300] Because the first column decision signal CFLG ("L" level) is set, the first row address information RT is directly output to flip-flops 80 to 83 as the result of the EXOR logic operation RTO.

[0301] The first row address information RT is latched by flip-flops 80 to 83 and output as the output row address information ORAD to comparator circuit 11.

[0302] EXOR circuits 60# to 63# receive the first row address information RT and the first column determination signal CFLG (“H” level) as inputs, and output the EXOR logic operation result RTO to flip-flops 80 to 83 respectively.

[0303] Because the first column determination signal CFLG ("H" level) is set, the first row address information RT is inverted. For example, when the first row address information RT is "1111", the EXOR logic operation result RTO becomes "0000". That is, the first row address information RT is changed to inverted address information according to the first column determination signal CFLG ("H" level). The inverted first row address information RT is latched by flip-flops 80 to 83 and output as output row address information ORAD to comparator circuit 11.

[0304] Therefore, in comparator 11, the output address information AQ and the input address information IAD are compared. Since the output row address information ORAD has been changed, the comparison results are inconsistent. That is, an inconsistency test signal is output to CPU 20.

[0305] The first column determination circuit 5C compares the first column address information CT with the second column address information CB, and outputs the first column determination signal CFLG based on the comparison result.

[0306] As described in the first embodiment, the first column determination signal CFLG (“H” level) determines that the first column address information CT and the second column address information CB are not complementary (when they are abnormal). That is, it determines that the column decoder 10 is abnormal and has not been decoded normally.

[0307] Specifically, based on the anomalies of column decoder 10, the following situations are determined: non-selection anomalies when multiple column selection lines Y are not selected, and multi-selection anomalies when multiple column selection lines Y are selected among multiple column selection lines Y.

[0308] The second column determination circuit 5D# generates the output column address information OCAD based on the second column address information CB and the first row determination signal RFLG.

[0309] EXOR circuits 30# to 32# receive the first column address information CT and the first row determination signal RFLG as input, and output the EXOR logic operation result CTO to flip-flops 77 to 79 respectively.

[0310] When there is no anomaly in line decoder 4, the first line determination signal RFLG is set to the "L" level. On the other hand, when there is an anomaly in line decoder 4, the first line determination signal RFLG is set to the "H" level.

[0311] EXOR circuits 30# to 32# receive the input of the first column address information CT and the first row determination signal RFLG (“L” level), and output the EXOR logic operation result CTO to flip-flops 77 to 79 respectively.

[0312] In this case, since the first row determination signal RFLG ("L" level) is set, the first column address information CT is output as EXOR logic operation result CTO to flip-flops 77 to 79 respectively.

[0313] The first column address information CT is latched by flip-flops 77 to 79 and is output as the output column address information OCAD to comparator circuit 11.

[0314] EXOR circuits 30# to 32# receive the input of the first column address information CT and the first row determination signal RFLG (“H” level), and output the EXOR logic operation result CTO to flip-flops 77 to 79 respectively.

[0315] Because the first row determination signal RFLG is set to "H" level, the data of the first column address information CT is inverted. For example, when the first column address information CT is "111", the EXOR logic operation result CTO becomes "000". That is, the first column address information CT is changed to inverted address information according to the first row determination signal RFLG ("H" level). The inverted first column address information CT is latched by flip-flops 77 to 79 and output as output column address information OCAD to comparator circuit 11.

[0316] Therefore, in comparator 11, the output address information AQ and the input address information IAD are compared. Since the output column address information OCAD has been changed, the comparison results are inconsistent. That is, an inconsistency test signal is output to CPU 20.

[0317] Figure 17 This is a diagram used to illustrate the anomalies of the row decoder 4 and column decoder 10 according to the second embodiment.

[0318] like Figure 17 As shown in (A), when a non-selection anomaly occurs due to an anomaly in the line decoder 4, where multiple word lines WL are not selected, or when multiple word lines WL are selected among multiple word lines WL, a first line determination signal RFLG (“H” level) is output.

[0319] like Figure 17 As shown in (B), when a non-selection anomaly occurs due to an anomaly of the column decoder 10, such that multiple column selection lines Y are not selected, or when a multi-selection anomaly occurs when multiple column selection lines Y are selected among multiple column selection lines Y, the first column determination signal CFLG (“H” level) is output.

[0320] like Figure 17As shown in (C), when a non-selection anomaly occurs due to an anomaly in the row decoder 4 when multiple word lines WL are not selected, or when a non-selection anomaly occurs due to an anomaly in the column decoder 10 when multiple column selection lines Y are not selected, a portion of the row address information or column address information of the output address information AQ output from the detection circuit 5P is inverted.

[0321] Therefore, even if the input address information IAD is correct, when comparing the input address information IAD and the output address information AQ, the comparison circuit 11 will output a judgment signal (failure) indicating that the comparison result is inconsistent to the CPU 20.

[0322] When one word line from multiple word lines WL is selected normally, and when one column selection line from multiple column selection lines Y is selected normally, the output address information AQ output from the detection circuit 5P includes the correct row address information and column address information.

[0323] Therefore, when the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a determination signal (pass) that matches the comparison result to the CPU 20.

[0324] When a multi-selection anomaly occurs due to an anomaly in the row decoder 4, where multiple word lines WL are selected from multiple word lines WL, or when a multi-selection anomaly occurs due to an anomaly in the column decoder 10, a portion of the row address information or column address information of the output address information AQ output from the detection circuit 5P is inverted.

[0325] Therefore, even if the input address information IAD is correct, when comparing the input address information IAD and the output address information AQ, the comparison circuit 11 will output a judgment signal (failure) indicating that the comparison result is inconsistent to the CPU 20.

[0326] When an erroneous word line selection error occurs due to a fault in the row decoder 4, or when an erroneous column selection error occurs due to a fault in the column selection line Y, the output address information AQ output from the detection circuit 5P includes erroneous row address information or column address information.

[0327] Therefore, even if the input address information IAD is correct, when comparing the input address information IAD and the output address information AQ, the comparison circuit 11 will output a judgment signal (failure) indicating that the comparison result is inconsistent to the CPU 20.

[0328] Figure 18This is a timing diagram illustrating the operation of semiconductor device 1# according to the second embodiment.

[0329] This example will describe the normal operating condition.

[0330] like Figure 18 As shown, at time T40, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0331] Furthermore, at time T40, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0332] At time T41, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0333] Therefore, the first column relational circuit 5C compares the first column address information CT and the second column address information CB and outputs the first column determination signal CFLG (“L” level) because they are complementary to each other.

[0334] At time T42, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0335] At time T43, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0336] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0337] At time T44, because the first row determination signal RFLG ("L" level) is set, the first column address information CT, as the EXOR logic operation result CTO, is output as is to flip-flops 77 to 79. Because the first column determination signal CFLG ("L" level) is set, the first row address information RT, as the EXOR logic operation result RTO, is directly output to flip-flops 80 to 83.

[0338] The detector 5P output includes the correct row address information and column address information, as well as the output address information AQ.

[0339] When the input address information IAD is correct, the comparator 11 compares the input address information IAD and the output address information AQ, and outputs a consistency determination signal (pass) to the CPU 20.

[0340] Figure 19 This is a timing diagram (part 2) used to illustrate the operation of the semiconductor device 1# according to the second embodiment.

[0341] This example will describe the case where the word line WL is not selected.

[0342] like Figure 19 As shown, at time T45, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0343] Furthermore, at time T45, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0344] At time T46, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0345] Therefore, since the first column address information CT and the second column address information CB are complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and outputs the first column determination signal CFLG (“L” level).

[0346] In this example, line decoder 4 failed to select one of the multiple word lines WL based on the input line address information RAD due to an error.

[0347] The first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. However, in this embodiment, the first row address information RT and the second row address information RB are not generated as complementary to each other.

[0348] At time T47, since the first row determination signal RFLG ("H" level) is set, the first column address information CT is inverted and output as the EXOR logic operation result CTO to flip-flops 77 to 79 respectively. Since the word line WL is not selected, the first row address information RT ("1111") is directly output as the EXOR logic operation result RTO to flip-flops 80 to 83.

[0349] The output of detector 5P includes the output address information AQ, which includes erroneous row address information and inverted column address information.

[0350] When the input address information IAD is correct, and the input address information IAD and the output address information AQ are compared with each other, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0351] Therefore, an anomaly can be detected when an unselected anomaly occurs, where one of the multiple word lines WL is not selected.

[0352] Figure 20 This is a timing diagram (part 3) used to illustrate the operation of the semiconductor device 1# according to the second embodiment.

[0353] This example will describe the case where multiple word lines WL are selected among multiple word lines WL.

[0354] like Figure 20 As shown, at time T49, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0355] Furthermore, at time T49, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0356] At time T50, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0357] Therefore, the first column relational circuit 5C compares the first column address information CT and the second column address information CB, and since they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0358] At time T51, line decoder 4 selects multiple word lines WL that are incorrect from multiple word lines WL based on the input line address information RAD.

[0359] At time T52, the first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. However, in this embodiment, the first row address information RT and the second row address information RB are not generated as complementary relationships.

[0360] Therefore, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and maintains the first row determination signal RFLG ("H" level) because they are not complementary to each other.

[0361] At time T53, since the first row determination signal RFLG ("H" level) is set, the first column address information CT is inverted and output as the EXOR logic operation result CTO to flip-flops 77 to 79 respectively. Since multiple word lines WL are selected, the first row address information RT (unknown) is output as the EXOR logic operation result RTO to flip-flops 80 to 83.

[0362] The output of detector 5P includes the output address information AQ, which includes erroneous row address information and inverted column address information.

[0363] When the input address information IAD is correct, and the input address information IAD and the output address information AQ are compared with each other, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0364] An anomaly can be detected when multiple selection anomalies occur, where multiple word lines WL are selected among multiple word lines WL.

[0365] Figure 21 This is a timing diagram (4) used to illustrate the operation of the semiconductor device 1# according to the second embodiment.

[0366] This example describes a case of incorrect selection exception where an incorrect word line WL is selected from multiple word lines WL.

[0367] like Figure 21 As shown, at time T54, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0368] Furthermore, at time T54, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0369] At time T55, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0370] The first column determination circuit 5C compares the first column address information CT and the second column address information CB. Since they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0371] Furthermore, at time T56, the line decoder 4 selects the word line WL that is erroneous due to an error from among multiple word lines WL based on the input line address information RAD.

[0372] At time T57, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. However, in this example, the first line address information RT and the second line address information RB are generated as complementary to each other based on the erroneous word line WL.

[0373] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0374] At time T58, because the first row determination signal RFLG ("L" level) is set, the first column address information CT, as the EXOR logic operation result CTO, is output as is to flip-flops 77 to 79. Because the first column determination signal CFLG ("L" level) is set, the first row address information RT, as the EXOR logic operation result RTO, is directly output to flip-flops 80 to 83.

[0375] The detector 5P output includes the output address information AQ, which includes row address information and column address information for errors.

[0376] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0377] An anomaly can be detected when an incorrect word line WL is selected from multiple word lines WL.

[0378] Figure 22 This is a timing diagram (part 5) used to illustrate the operation of the semiconductor device 1# according to the second embodiment.

[0379] In this example, we will describe the case where the selection operation for column selection line Y is not performed.

[0380] like Figure 22 As shown, at time T59, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0381] In this example, column decoder 10 does not select one of the multiple column selection lines Y based on the input column address information CAD.

[0382] The first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are not generated as complementary relationships.

[0383] Therefore, since the first column address information CT and the second column address information CB are not complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and maintains the first column determination signal CFLG ("H" level).

[0384] At time T60, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0385] At time T61, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0386] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0387] At time T62, since the first row determination signal RFLG (“L” level) is set, the first column address information CT is output as is to flip-flops 77 to 79 as the result of the EXOR logic operation CTO. Since the first column determination signal CFLG is set to the “H” level, the first row address information RT is inverted and output as the result of the EXOR logic operation RTO to flip-flops 80 to 83.

[0388] The detector 5P output includes the output address information AQ, which includes the inverted row address information and the erroneous column address information.

[0389] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0390] Therefore, an anomaly can be detected when an unselected anomaly occurs, where one of the multiple column selection lines Y is not selected.

[0391] Figure 23 This is a timing diagram (part 6) used to illustrate the operation of the semiconductor device 1# according to the second embodiment.

[0392] This example will describe the situation where multiple column selection lines Y are selected out of multiple column selection lines Y.

[0393] like Figure 23 As shown, at time T64, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0394] Furthermore, at time T64, in this example, column decoder 10 selects one of multiple column selection lines Y based on the input column address information CAD.

[0395] At time T65, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are not generated as complementary to each other.

[0396] Therefore, since the first column address information CT and the second column address information CB are not complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and maintains the first column determination signal CFLG ("H" level).

[0397] At time T66, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0398] At time T67, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0399] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0400] At time T68, since the first row determination signal RFLG (“L” level) is set, the first column address information CT is output as is to flip-flops 77 to 79 as the result of the EXOR logic operation CTO. Since the first column determination signal CFLG is set to the “H” level, the first row address information RT is inverted and output as the result of the EXOR logic operation RTO to flip-flops 80 to 83.

[0401] The detector 5P output includes the output address information AQ, which includes the inverted row address information and the erroneous column address information.

[0402] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0403] Therefore, an anomaly can be detected when multiple selection anomalies occur, where multiple column selection lines Y out of multiple column selection lines Y are selected.

[0404] Figure 24 This is a seventh timing diagram illustrating the operation of semiconductor device 1# according to the second embodiment.

[0405] In this example, a case of incorrect selection exception will be described, where an incorrect column selection line Y is selected from multiple column selection lines Y.

[0406] like Figure 24 As shown, at time T69, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0407] Furthermore, at time T69, in this exemplary embodiment, the column decoder 10 selects the erroneous column selection line Y among multiple column selection lines Y based on the input column address information CAD.

[0408] At time T70, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are generated as complementary to each other based on the incorrect column selection line Y.

[0409] Therefore, since the first column address information CT and the second column address information CB are complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and outputs the first column determination signal CFLG (“L” level).

[0410] Furthermore, at time T71, the line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0411] At time T72, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0412] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0413] At time T73, since the first row determination signal RFLG ("L" level) is set, the first column address information CT, as the EXOR logic operation result CTO, is output as is to flip-flops 77 to 79. In addition, since the first column determination signal CFLG ("L") is set, the first row address information RT, as the EXOR logic operation result RTO, is directly output to flip-flops 80 to 83.

[0414] The detector 5P output includes the row address information and the column address information of the error, AQ.

[0415] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0416] Therefore, an anomaly can be detected when an incorrect selection anomaly occurs, in which an incorrect column selection line Y is selected among multiple column selection lines Y.

[0417] <Example 3>

[0418] Figure 25 This is a diagram illustrating the outline of the semiconductor device 1#A according to the third embodiment.

[0419] Reference Figure 25 The semiconductor device 1#A includes a memory macro 15#A, a CPU 20, and a comparator 11.

[0420] CPU 20 controls memory macro 15#A to retrieve data stored in memory macro 15#A.

[0421] The difference between memory macro 15#A and memory macro 15 is that detection circuit 5 is replaced by detection circuit 5Q. Since the other configurations are the same, their detailed description will not be repeated.

[0422] The detection circuit 5Q outputs output address information AQ based on the first row address information RT and the second row address information RB output from the row encoder 6, and the first column address information CT and the second column address information CB output from the column encoder 9. The output address information AQ includes output row address information ORAD and output column address information OCAD.

[0423] The comparator circuit 11 compares the output address information AQ output from the detector circuit 5Q with the input address information IAD, and outputs the comparison result to the CPU 20.

[0424] Figure 26 This is a diagram illustrating the circuit configuration of the detection circuit 5Q, the row encoder 6, and the column encoder 9 according to the third embodiment.

[0425] Reference Figure 26 ,and Figure 16 Compared to the detection circuit 5P, the difference lies in the addition of an OR circuit 84. The detection circuit 5Q includes a first row determination circuit 5A, a second row determination circuit 5B#, a first column determination circuit 5C, and a second column determination circuit 5D#.

[0426] The first row determination circuit 5A includes EXOR circuits 64-67 and NAND circuit 70.

[0427] The second row of decision circuit 5B# includes EXOR circuits 60# to 63# and flip-flops (FF) 80 to 83.

[0428] The first column determination circuit 5C includes EXOR circuits 33-35 and NAND circuit 36.

[0429] The second column of decision circuit 5D# includes EXOR circuits 30# to 32# and flip-flops (FF) 77 to 79.

[0430] The first row determination circuit 5A compares the first row address information RT and the second row address information RB, and outputs the first row determination signal RFLG based on the comparison result.

[0431] The first column determination circuit 5C compares the first column address information CT with the second column address information CB, and outputs the first column determination signal CFLG based on the comparison result.

[0432] OR circuit 84 outputs the OR logic operation result XFLG of the first row decision signal RFLG and the first column decision signal CFLG to the second row decision circuit 5B# and the second column decision circuit 5D#, respectively.

[0433] The second line determination circuit 5B# generates the output line address information ORAD based on the first line address information RT and the OR logic operation result XFLG.

[0434] The second column determination circuit 5D# generates the output column address information OCAD based on the second column address information CB and the OR logic operation result XFLG.

[0435] When the OR logic operation result XFLG (“L” level) is input in the same manner as described in the second embodiment, the second row determination circuit 5B# stores the first row address information RT as the EXOR logic operation result RTO in flip-flops 80 to 83 respectively.

[0436] When the OR logic operation result XFLG (“L” level) is input, the second column determination circuit 5D# stores the first column address information CT as the EXOR logic operation result CTO in flip-flops 77 to 79 respectively.

[0437] On the other hand, when the result of the OR logic operation XFLG (“H” level) is input, the second row determination circuit 5B# inverts the first row address information RT and stores the inverted first row address information RT as the result of the EXOR logic operation RTO in flip-flops 80 to 83.

[0438] In addition, when the OR logic operation result XFLG (“H” level) is input, the second column determination circuit 5D# inverts the first column address information CT and stores it as the EXOR logic operation result CTO in flip-flops 77 to 79 respectively.

[0439] Therefore, when an anomaly exists in row decoder 4 or column decoder 10, the OR logic operation result XFLG is set to H level because one of the first row decision signal RFLG and the first column decision signal CFLG becomes H level.

[0440] Therefore, when the result of the OR logic operation XFLG is at the "H" level, the first row address information RT and the second column address information CT are both inverted and stored in the flip-flop.

[0441] Therefore, when the input address information IAD is correct, and the input address information IAD and the output address information AQ are compared with each other, the comparison circuit 11 outputs a mismatch determination signal (failure) to the CPU 20.

[0442] Figure 27 This is a diagram used to illustrate the anomalies of the row decoder 4 and column decoder 10 according to the third embodiment.

[0443] like Figure 27 As shown, when a non-selection anomaly occurs due to an anomaly in the row decoder 4, resulting in multiple word lines WL not being selected, or when a non-selection anomaly occurs due to an anomaly in the column decoder 10, resulting in multiple column selection lines Y not being selected, the row address information and column address information in the output address information AQ output from the detection circuit 5Q are inverted.

[0444] Therefore, even if the input address information IAD is correct, when comparing the input address information IAD and the output address information AQ, the comparison circuit 11 will output a judgment signal (failure) indicating that the comparison result is inconsistent to the CPU 20.

[0445] When one word line from multiple word lines WL is selected normally, and when one column selection line from multiple column selection lines Y is selected normally, the output address information AQ output from the detection circuit 5Q includes the correct row address information and column address information.

[0446] Therefore, when the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a determination signal (pass) that matches the comparison result to the CPU 20.

[0447] When a multi-selection anomaly occurs due to an anomaly in the row decoder 4, where multiple word lines WL are selected from multiple word lines WL, or when a multi-selection anomaly occurs due to an anomaly in the column decoder 10, where multiple column selection lines Y are selected from multiple column selection lines Y, the row address information and column address information in the output address information AQ output from the detection circuit 5Q are inverted.

[0448] Therefore, even if the input address information IAD is correct, when comparing the input address information IAD and the output address information AQ, the comparison circuit 11 will output a judgment signal (failure) indicating that the comparison result is inconsistent to the CPU 20.

[0449] When an erroneous word line selection error occurs due to a fault in the row decoder 4, where an incorrect word line WL is selected from among multiple word lines WL, or when an erroneous column selection error occurs where an incorrect column selection line Y is selected from among multiple column selection lines Y, the output address information AQ output from the detection circuit 5Q includes erroneous row address information or column address information.

[0450] Therefore, even if the input address information IAD is correct, when comparing the input address information IAD and the output address information AQ, the comparison circuit 11 will output a judgment signal (failure) indicating that the comparison result is inconsistent to the CPU 20.

[0451] Figure 28 This is a first timing diagram illustrating the operation of semiconductor device 1#A according to a third embodiment.

[0452] This example will describe the normal operating condition.

[0453] like Figure 28 As shown, at time T74, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0454] Furthermore, at time T74, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0455] At time T75, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0456] Therefore, the first column relational circuit 5C compares the first column address information CT and the second column address information CB, and since they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0457] At time T76, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0458] At time T77, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0459] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and outputs the first row determination signal RFLG (“L” level) because they are complementary to each other.

[0460] At time T78, since the OR logic operation result XFLG ("L" level) between the first row determination signal RFLG ("L" level) and the first column determination signal CFLG ("L" level) is set, the first column address information CT is directly output to flip-flops 77 to 79 as the EXOR logic operation result CTO. Since the first column determination signal CFLG ("L" level) is set, the first row address information RT is directly output to flip-flops 80 to 83 as the EXOR logic operation result RTO.

[0461] The detector 5Q output includes the correct row address information and column address information, as well as the output address information AQ.

[0462] When the input address information IAD is correct, the comparator 11 compares the input address information IAD and the output address information AQ, and outputs a consistency determination signal (pass) to the CPU 20.

[0463] Figure 29 This is a timing diagram (part 2) used to illustrate the operation of the semiconductor device 1#A according to the third embodiment.

[0464] This example will describe the case where the word line WL is not selected.

[0465] like Figure 29 As shown, at time T79, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0466] Furthermore, at time T79, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0467] At time T80, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0468] Therefore, since the first column address information CT and the second column address information CB are complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and outputs the first column determination signal CFLG (“L” level).

[0469] In this example, line decoder 4 failed to select one of the multiple word lines WL based on the input line address information RAD due to an error.

[0470] The first and second row encoders 6A and 6B generate the first row address information RT and the second row address information, respectively. However, in this embodiment, the first row address information RT and the second row address information CT are not generated as complementary to each other.

[0471] At time T81, since the OR logic operation result XFLG ("H" level) between the first row decision signal RFLG ("H" level) and the first column decision signal CFLG ("L" level) is set, the first column address information CT is inverted and output as the EXOR logic operation result CTO to flip-flops 77 to 79 respectively. Since the OR logic operation result XFLG ("H" level) between the first row decision signal RFLG ("H" level) and the first column decision signal CFLG ("L" level) is set, the first row address information RT ("1111") is inverted and output as the EXOR logic operation result RTO ("0000") to flip-flops 80 to 83 respectively.

[0472] The detector 5Q output includes output address information AQ, which includes inverted row address information and inverted column address information.

[0473] When the input address information IAD is correct, and the input address information IAD and the output address information AQ are compared with each other, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0474] Therefore, an anomaly can be detected when an unselected anomaly occurs, where one of the multiple word lines WL is not selected.

[0475] Figure 30 This is a timing diagram (part 3) used to illustrate the operation of the semiconductor device 1#A according to the third embodiment.

[0476] This example will describe the case where multiple word lines WL are selected among multiple word lines WL.

[0477] like Figure 30 As shown, at time T83, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0478] Furthermore, at time T84, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0479] At time T84, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0480] Therefore, the first column relational circuit 5C compares the first column address information CT and the second column address information CB, and since they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0481] At time T85, line decoder 4 selects multiple word lines WL that are incorrect from multiple word lines WL based on the input line address information RAD.

[0482] At time T86, the first and second row encoders 6A and 6B generate the first row address information RT and the second row address information RB, respectively. However, in this embodiment, the first row address information RT and the second row address information RB are not generated as complementary relationships.

[0483] Therefore, the first row determination circuit 5A compares the first row address information RT and the second row address information RB and maintains the first row determination signal RFLG ("H" level) because they are not complementary to each other.

[0484] At time T87, since the OR logic operation result XFLG ("H" level) between the first row decision signal RFLG ("H" level) and the first column decision signal CFLG ("L" level) is set, the first column address information CT is inverted and output as the EXOR logic operation result CTO to flip-flops 77 to 79 respectively. Since the OR logic operation result XFLG ("H" level) between the first row decision signal RFLG ("H" level) and the first column decision signal CFLG ("L" level) is set, the first row address information RT (unknown) is inverted and output as the EXOR logic operation result RTO to flip-flops 80 to 83.

[0485] The detector 5Q output includes output address information AQ, which includes inverted row address information and inverted column address information.

[0486] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0487] An anomaly can be detected when multiple selection anomalies occur, where multiple word lines WL are selected among multiple word lines WL.

[0488] Figure 31 This is a timing diagram (4) used to illustrate the operation of the semiconductor device 1#A according to the third embodiment.

[0489] This example will describe a case of incorrect selection exception, where the wrong word line WL is selected from multiple word lines WL.

[0490] like Figure 31 As shown, at time T88, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0491] Furthermore, at time T88, the column decoder 10 selects one of the multiple column selection lines Y based on the input column address information CAD.

[0492] At time T89, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0493] Therefore, the first column relational circuit 5C compares the first column address information CT and the second column address information CB, and since they are complementary to each other, it outputs the first column determination signal CFLG (“L” level).

[0494] Furthermore, at time T90, the line decoder 4 selects the word line WL that is erroneous due to an error from multiple word lines WL based on the input line address information RAD.

[0495] At time T91, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. However, in this example, the first line address information RT and the second line address information RB are generated as complementary to each other based on the erroneous word line WL.

[0496] Subsequently, the first row determination circuit 5A outputs the first row determination signal RFLG (“L” level) by comparing the first row address information RT and the second row address information RB, since they are complementary to each other.

[0497] At time T92, since the OR logic operation result XFLG ("L" level) between the first row decision signal RFLG ("L" level) and the first column decision signal CFLG ("L" level) is set, the first column address information CT is directly output to flip-flops 77 to 79 as the EXOR logic operation result CTO. Since the OR logic operation result XFLG ("L" level) between the first row decision signal RFLG ("L" level) and the first column decision signal CFLG ("L" level) is set, the first row address information RT is directly output to flip-flops 80 to 83 as the EXOR logic operation result RTO.

[0498] The detector 5P output includes the output address information AQ, which includes row address information and column address information for errors.

[0499] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0500] An anomaly can be detected when an incorrect word line WL is selected from multiple word lines WL.

[0501] Figure 32 This is a timing diagram (5) illustrating the operation of the semiconductor device 1#A according to the third embodiment.

[0502] In this example, we will describe the case where the selection operation for column selection line Y is not performed.

[0503] like Figure 32 As shown, at time T93, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0504] In this example, column decoder 10 does not select one of the multiple column selection lines Y based on the input column address information CAD.

[0505] The first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are not generated as complementary relationships.

[0506] Therefore, since the first column determination circuit and the second column address information CB are not complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and maintains the first column determination signal CFLG (“H” level).

[0507] At time T94, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0508] At time T95, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0509] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and because they are complementary, outputs the first row determination signal RFLG (“L” level).

[0510] At time T96, because the OR logic operation result XFLG ("H" level) between the first row decision signal RFLG ("L" level) and the first column decision signal CFLG ("H" level) is set, the first column address information CT is inverted and output as the EXOR logic operation result CTO to flip-flops 77 to 79 respectively. Because the OR logic operation result XFLG ("H" level) between the first row decision signal RFLG ("L" level) and the first column decision signal CFLG ("H" level) is set, the first row address information RT is inverted and output as the EXOR logic operation result RTO to flip-flops 80 to 83 respectively.

[0511] The detector 5Q output includes output address information AQ, which includes inverted row address information and inverted column address information.

[0512] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0513] Therefore, an anomaly can be detected when no anomaly is selected, where one of the multiple column selection lines Y is not selected.

[0514] Figure 33 This is a timing diagram (part 6) used to illustrate the operation of the semiconductor device 1#A according to the third embodiment.

[0515] This example will describe the situation where multiple column selection lines Y are selected out of multiple column selection lines Y.

[0516] like Figure 33 As shown, at time T97, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0517] Furthermore, at time T97, in this example, the column decoder 10 selects one of multiple column selection lines Y based on the input column address information CAD.

[0518] At time T98, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are not generated as complementary to each other.

[0519] Therefore, since the first column determination circuit and the second column address information CB are not complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and maintains the first column determination signal CFLG (“H” level).

[0520] At time T99, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0521] At time T100, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0522] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and because they are complementary, outputs the first row determination signal RFLG (“L” level).

[0523] At time T101, since the OR logic operation result XFLG ("H" level) between the first row determination signal RFLG ("L" level) and the first column determination signal CFLG ("H" level) is set, the first column address information CT is inverted and output as the EXOR logic operation result CTO to flip-flops 77 to 79 respectively. Furthermore, since the OR logic operation result XFLG ("H" level) between the first row determination signal RFLG ("L" level) and the first column determination signal CFLG ("H" level) is set, the first row address information RT is inverted and output as the EXOR logic operation result RTO to flip-flops 80 to 83 respectively.

[0524] The detector 5Q output includes output address information AQ, which includes inverted row address information and inverted column address information.

[0525] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0526] Therefore, an anomaly can be detected when multiple selection anomalies occur, where multiple column selection lines Y out of multiple column selection lines Y are selected.

[0527] Figure 34 This is a timing diagram (part 7) illustrating the operation of the semiconductor device 1#A according to the third embodiment.

[0528] In this example, a case of incorrect selection exception will be described, where an incorrect column selection line Y is selected from multiple column selection lines Y.

[0529] like Figure 34 As shown, at time T102, the control signal PCB is set to the "H" level. Subsequently, the pre-charging operation for the data lines DL[0] to DL[7] of the pre-charging circuit 6C is completed.

[0530] Furthermore, at time T102, in this exemplary embodiment, the column decoder 10 selects the erroneous column selection line Y among multiple column selection lines Y based on the input column address information CAD.

[0531] At time T103, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. However, in this embodiment, the first column address information CT and the second column address information CB are generated as complementary to each other based on the incorrect column selection line Y.

[0532] Therefore, since the first column determination circuit and the second column address information CB are complementary, the first column determination circuit 5C compares the first column address information CT with the second column address information CB and outputs the first column determination signal CFLG (“L” level).

[0533] Furthermore, at time T104, the line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0534] At time T105, the first and second line encoders 6A and 6B generate the first line address information RT and the second line address information RB, respectively. In this example, the first line address information RT and the second line address information RB are generated as complementary to each other.

[0535] Subsequently, the first row determination circuit 5A compares the first row address information RT and the second row address information RB, and because they are complementary, outputs the first row determination signal RFLG (“L” level).

[0536] At time T106, since the OR logic operation result XFLG ("L" level) between the first row determination signal RFLG ("L" level) and the first column determination signal CFLG ("L" level) is set, the first column address information CT is output as EXOR logic operation result CTO to flip-flops 77 to 79 as is. Since the OR logic operation result XFLG ("L" level) between the first row determination signal RFLG ("L" level) and the first column determination signal CFLG ("L" level) is set, the first row address information RT is directly output as EXOR logic operation result RTO to flip-flops 80 to 83.

[0537] The detector 5Q output includes the row address information and the column address information of the error, which is the output address information AQ.

[0538] When the input address information IAD and the output address information AQ are compared with each other if the input address information IAD is correct, the comparator 11 outputs a mismatch judgment signal (failure) to the CPU 20.

[0539] Therefore, an anomaly can be detected when an incorrect selection anomaly occurs, in which an incorrect column selection line Y is selected among multiple column selection lines Y.

[0540] <Example 4>

[0541] Figure 35 This is a diagram illustrating the general outline of the semiconductor device 100 according to the fourth embodiment.

[0542] Reference Figure 35 The semiconductor device 100 includes a memory macro 16 and a CPU 20.

[0543] CPU 20 controls memory macro 16 to retrieve data stored in memory macro 16.

[0544] The memory macro 16 includes a memory array 2, a word driver 3, a row decoder 4, a decoder fault detection circuit 110, a column selection circuit 7, a pre-decoder 8, a column decoder 10, and a decision circuit 120.

[0545] Since the memory array 2, word driver 3, row decoder 4, column select circuit 7, pre-decoder 8 and column decoder 10 are the same as those described in the above embodiments, their detailed descriptions will not be repeated.

[0546] Decoder fault detection circuit 110 detects anomalies in row decoder 4 and column decoder 10.

[0547] The determination circuit 120 outputs an abnormal signal to the CPU 20 based on the detection signal from the fault detection circuit 110 of the decoder.

[0548] In this example, the detection of non-selection anomalies and multi-selection anomalies using row decoder 4 and column decoder 10 will be described.

[0549] Figure 36 This is a diagram illustrating a decoder fault detection circuit 200 on the row side according to the fourth embodiment.

[0550] Referring to 36, the horizontal decoder fault detection circuit 200 includes horizontal data lines RDL0 and RDL1, horizontal reference data lines RDL0REF and RDL1REF, P-channel MOS transistors 201, 202, 204, and 205, N-channel MOS transistors 203 and 206, and gate transistors GT0 and GT1.

[0551] An N-channel MOS transistor 203 is placed between the reference data line RDL0REF and the fixed voltage VSS, with its gate receiving the input of the control signal ACT.

[0552] A P-channel MOS transistor 202 is disposed between the power supply voltage VDD and the reference data line RDL0REF, with its gate connected to the drain-side node N0. A P-channel MOS transistor 201 is disposed between the power supply voltage VDD and the data line RDL0, with its gate connected to node N0. P-channel MOS transistors 201 and 202 form a current mirror circuit.

[0553] An N-channel MOS transistor 206 is positioned between the reference data line RDL1REF and the fixed voltage VSS, with its gate receiving the input of the control signal ACT.

[0554] A P-channel MOS transistor 205 is placed between the power supply voltage VDD and the reference data line RDL1REF, with its gate connected to the drain-side node N1. A P-channel MOS transistor 204 is placed between the power supply voltage VDD and the data line RDL1, with its gate connected to node N1. P-channel MOS transistors 204 and 205 form a current mirror circuit.

[0555] Furthermore, in this exemplary embodiment, gate transistors GT0 and GT1 are provided corresponding to word lines WL. Gate transistors GT0 and GT1 are N-channel MOS transistors. In this exemplary embodiment, gate transistors GT0 and GT1 are provided corresponding to one word line WL.

[0556] A gate transistor GT0 is placed between the data line RDL0 and the fixed voltage VSS, with its gate connected to the word line WL.

[0557] A gate transistor GT1 is placed between the data line RDL1 and the fixed voltage VSS, and its gate is connected to the word line WL.

[0558] In this example, the size of the N-channel MOS transistor 203 is set to 1.5 times that of the gate transistors GT0 and GT1, and the size of the N-channel MOS transistor 201 is set to 0.5 times.

[0559] When the word line WL is set to the "H" level, gate transistors GT0 and GT1 are turned on. This causes current to flow through gate transistors GT0 and GT1.

[0560] On the other hand, the size of N-channel MOS transistor 203 is set to 1.5 times that of gate transistors GT0 and GT1, and the size of N-channel MOS transistor 201 is set to 0.5 times. Data line RDL0 is set to "H" level, and data line RDL1 is set to "L" level.

[0561] If word line WL is not selected, i.e. is set to "L" level, then gate transistors GT0 and GT1 will not be turned on.

[0562] In this situation, data lines RDL0 and RDL1 are both held at the "H" level.

[0563] When multiple word lines WL are set to "H" level, multiple gate transistors GT0 and GT1 are turned on. This causes current to flow through gate transistors GT0 and GT1.

[0564] The size of N-channel MOS transistor 203 is set to 1.5 times that of gate transistors GT0 and GT1, and the size of N-channel MOS transistor 201 is set to 0.5 times. However, since multiple gate transistors GT0 and GT1 are turned on, the data lines RDL0 and RDL1 are both set to "L" level.

[0565] The decoder fault detection circuits on the column side have the same configuration.

[0566] Specifically, the gate transistor GT is configured correspondingly to each column select line Y. The column-side data lines CDL0, RDL1, and the column-side reference data lines RDL0REF, RDL1REF, etc., are provided in the same manner.

[0567] When column select line Y is set to "H" level, gate transistor GT is turned on. Data line CDL0 is set to "H" level, and data line CDL1 is set to "L" level.

[0568] If column select line Y is not selected, i.e., set to "L" level, the gate transistor GT will not conduct. Both data lines CDL0 and CDL1 are held at "H" level.

[0569] When multiple column select lines Y are set to "H" level, multiple gate transistors GT are turned on. Both data lines CDL0 and CDL1 are set to "L" level.

[0570] Figure 37 This is a diagram illustrating the detection results of the decoder fault detection circuit 110 according to the fourth embodiment.

[0571] like Figure 37 As shown, a non-selection exception occurs when one of the multiple word lines WL is not selected due to an anomaly in the line decoder 4, and both data lines RDL0 and RDL1 are set to "H" level. A multi-selection exception occurs when multiple word lines WL are selected due to an anomaly in the line decoder 4, and both data lines RDL0 and RDL1 are set to "L" level.

[0572] When the line decoder 4 is working properly, the data lines RDL0 and RDL1 are set to "H" level and "L" level, respectively.

[0573] In the event of a non-selection anomaly caused by an anomaly in column decoder 10, resulting in multiple column select lines Y being unselected, data lines CDL0 and CDL1 are both set to "H" level. When multiple selection anomalies occur due to an anomaly in column decoder 10, resulting in multiple column select lines Y being selected, data lines CDL0 and CDL1 are both set to "L" level.

[0574] When the column decoder 10 is working properly, the data lines CDL0 and CDL1 are set to "H" level and "L" level, respectively.

[0575] Figure 38 This is a circuit configuration diagram of the determination circuit 120 according to the fourth embodiment.

[0576] Reference Figure 38 The determination circuit 120 includes first and second determination units 310 and 320, a NOR circuit 330, an inverter 332, and a flip-flop (FF) 334.

[0577] The first determination unit 310 includes NAND circuits 312 and 314.

[0578] The NAND circuit 314 receives signals from the data line and RDL1 input and outputs the NAND logic operation result to the RDL0 circuit 312.

[0579] NAND circuit 312 receives signals from data line RDL0 and outputs from NAND circuit 314, and outputs the NAND logic operation results to NOR circuit 330.

[0580] In this embodiment, when both data lines RDL0 and RDL1 are at "H" level and both are at "L" level, the output of NAND circuit 312 is set to "H" level.

[0581] On the other hand, when the data lines RDL0 and RDL1 are at "H" level and "L" level respectively, the output of NAND circuit 312 is set to "L" level.

[0582] The second determination unit 320 includes NAND circuits 322 and 324.

[0583] The NAND circuit 324 receives signals from the data line and CDL1 input and outputs the NAND logic operation result to the CDL0 circuit 322.

[0584] NAND circuit 322 receives signals from data line CDL0 and outputs from NAND circuit 324, and outputs the NAND logic operation results to NOR circuit 330.

[0585] In this embodiment, when both data lines CDL0 and CDL1 are at "H" level and both are at "L" level, the output of NAND circuit 322 is set to "H" level.

[0586] On the other hand, when data lines CDL0 and CDL1 are at "H" level and "L" level respectively, the output of NAND circuit 322 is set to "L" level.

[0587] NOR circuit 330 receives inputs from NAND circuits 312 and 322 and outputs the result of NOR logic operation to inverter 332.

[0588] Inverter 332 inverts the signal of NOR circuit 330 and stores it in flip-flop (FF) 334.

[0589] In this exemplary embodiment, when the output of one of the NAND circuits 312 and 322 is at the “H” level, the “H” level is stored in the flip-flop (FF) 334, and the exception signal FLAG (“H” level) is output.

[0590] Figure 39 This is a diagram used to illustrate the anomalies of the row decoder 4 and column decoder 10 according to the fourth embodiment.

[0591] like Figure 39 As shown, when a non-selection anomaly occurs due to an anomaly in the line decoder 4, where multiple word lines WL are not selected, or when multiple word lines WL are selected among multiple word lines WL, the anomaly signal FLAG (H level) is set according to the output (H level) of the NAND circuit 312.

[0592] When a non-selection anomaly occurs due to an anomaly in column decoder 10, such that multiple column select lines Y are not selected, or a multi-selection anomaly occurs when multiple column select lines Y are selected, the anomaly signal FLAG (H level) is set according to the output (H level) of NAND circuit 322.

[0593] When both row decoder 4 and column decoder 10 are functioning correctly, the error signal FLAG is set to the "L" level.

[0594] Figure 40 This is a timing diagram illustrating the operation of a semiconductor device 100 according to a fourth embodiment.

[0595] This example will describe the normal operating condition.

[0596] like Figure 40 As shown, at time T110, the control signal ACT is set to the "H" level. The decoder fault detection circuit 110 operates accordingly.

[0597] The reference data lines RDL0REF and RDL1REF begin to drop to the "L" level depending on the transistor size.

[0598] At time T111, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD. Subsequently, gate transistors GT0 and GT1 are turned on.

[0599] At time T112, data lines RDL0 and RDL1 are amplified to "H" and "L" levels, respectively.

[0600] Next, at time T113, the determination circuit 120 outputs an abnormal signal FLAG ("L" level) based on the data lines RDL0 ("H" level) and RDL1 ("L" level).

[0601] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0602] Figure 41 This is a timing diagram (part 2) illustrating the operation of the semiconductor device 100 according to the fourth embodiment.

[0603] This example will describe the case where the word line WL is not selected.

[0604] like Figure 41 As shown, at time T114, the control signal ACT is set to the "H" level. The decoder fault detection circuit 110 operates accordingly.

[0605] The reference data lines RDL0REF and RDL1REF begin to drop to the "L" level depending on the transistor size.

[0606] In this example, line decoder 4 fails to select one word line from multiple word lines WL based on the input line address information RAD due to an error. In this case, gate transistors GT0 and GT1 will not conduct.

[0607] At time T115, each of the data lines RDL0 and RDL1 maintains an "H" level.

[0608] Next, at time T116, the determination circuit 120 outputs an abnormal signal FLAG ("H" level) based on data lines RDL0 ("H" level) and RDL1 ("H" level).

[0609] Therefore, an anomaly can be detected when an unselected anomaly occurs when one of the multiple word lines WL is not selected.

[0610] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0611] Figure 42 This is a timing diagram (part 3) illustrating the operation of the semiconductor device 100 according to the fourth embodiment.

[0612] This example will describe the case where multiple word lines WL are selected among multiple word lines WL.

[0613] like Figure 42 As shown, at time T117, the control signal ACT is set to the "H" level. The decoder fault detection circuit 110 operates accordingly.

[0614] The reference data lines RDL0REF and RDL1REF begin to drop to the "L" level depending on the transistor size.

[0615] At time T118, line decoder 4 selects multiple word lines WL based on the input line address information RAD. Subsequently, multiple gate transistors GT0 and GT1 are turned on.

[0616] At time T119, both data lines RDL0 and RDL1 are set to "L" level.

[0617] Next, at time T120, the determination circuit 120 outputs an abnormal signal FLAG ("H" level) based on the data lines RDL0 ("L" level) and RDL1 ("L" level).

[0618] An anomaly can be detected when a multi-selection anomaly occurs, where multiple word lines WL are selected from multiple word lines WL.

[0619] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0620] <Modification of Example 4>

[0621] Figure 43 This is a diagram illustrating the circuit configuration of the decoder fault detection circuit 110# and the determination circuit 120# according to the fourth embodiment.

[0622] Reference Figure 43 The decoder fault detection circuit 110# includes the column encoder 9 and the row-side decoder fault detection circuit 210.

[0623] The column encoder 9 is the same as that described in the first embodiment.

[0624] The column encoder 9 is connected to multiple column select lines Y and encodes column address information based on the rising edge of the selected column select line Y.

[0625] The horizontal decoder fault detection circuit 210 includes data line DL, reference data lines DREF1 and DREF2, N-channel MOS transistors TRS0-TRS15, pre-charge circuit 6C#, and dummy circuits 410 and 412.

[0626] The pre-charge circuit 6C# includes data lines DL corresponding to reference data lines DREF1 and DREF2, a plurality of pre-charge transistors PT for pre-charging data lines DL and reference data lines DREF1 and DREF2 to a predetermined voltage, and regulating transistors TRSP and TRSQ. The pre-charge transistors PT operate according to the control signal PCB, and when the control signal PCB is at the "L" level, they pre-charge data lines DL and reference data lines DREF1 and DREF2 to the predetermined voltage.

[0627] The regulating transistor TRSP is set in correspondence with the reference data line DREF1.

[0628] The regulating transistor TRSQ is set in accordance with the reference data line DREF2.

[0629] The regulating transistors TRSP and TRSQ are N-channel MOS transistors, which adjust the corresponding voltages of the reference data lines DREF1 and DREF2 according to the control signal PCB.

[0630] By turning on the regulating transistors TRSP and TRSQ from the pre-charged predetermined voltage, the reference data lines DREF1 and DREF2 are regulated to the reference voltages VREF1 and VREF2.

[0631] When the drive capability of N-channel MOS transistors TRS0-TRS15 is set to 1, the drive capability of regulating transistor TRSP is set to 1.5. Furthermore, when the drive capability of N-channel MOS transistors TRS0-TRS15 is set to 1, the drive capability of regulating transistor TRSQ is set to 0.5.

[0632] The dummy circuits 410 and 412 are used to add a dummy data line DL and the same capacitor to each reference data line DREF1 and DREF2. Specifically, 15 N-channel MOS transistors TRS are connected to the reference data lines DREF1 and DREF2 respectively to receive the input of control signals TIEL1 and TIEL2.

[0633] Under normal circumstances, when a word line WL is selected, one word line WL among word lines WL[0]-WL

[15] is activated, while the other word lines WL are inactive.

[0634] That is, among the 16 N-channel MOS transistors TRS0-TRS15, one N-channel MOS transistor TRS connected to the data line DL is turned on, while the remaining 15 N-channel MOS transistors TRS are not turned on.

[0635] Therefore, the data line DL represents the state with the drain capacitance of the remaining 15 N-channel MOS transistors TRS added.

[0636] In this embodiment, by setting the control signals TIEL1 and TIEL2 of the dummy circuits 410 and 412 to the corresponding "L" level, the same drain capacitance as the drain capacitance to be added to the data line DL can be provided for each reference data line DREF1 and DREF2.

[0637] Then, based on the control signal PCB being set to "H" level, the transistors TRSP and TRSQ are turned on.

[0638] In this case, when the drive capability of the N-channel MOS transistors TRS0-TRS15 is set to 1, the drive capability of the regulating transistor TRSP is set to 1.5, and the drive capability of the regulating transistor TRSQ is set to 0.5.

[0639] Therefore, the voltage of the data line DL when the word line WL is selected is set between the reference voltage VREF1 and the reference voltage VREF2.

[0640] The decision circuit 120# includes EXOR circuits 33-35, sense amplifiers (SA) 401 and 402, transmission gates TF0-TF4, NOR circuit 403, NAND circuit 404, flip-flop (FF) 405, and inverter -INV.

[0641] The transmission gates TF0-TF4 are turned on after receiving the input of the control signal ADSAE and the input of the inverted signal of the control signal ADSAE via the inverter INV.

[0642] More specifically, transmission gate TF0 connects one input node of sense amplifier 401 to data line DL. Transmission gate TF1 connects the other input node of sense amplifier 401 to reference data line DREF1.

[0643] Transmission gate TF2 also connects one input node of the sense amplifier (SA) 402 to the reference data line DREF2. Transmission gate TF3 connects the other input node of the sense amplifier 402 to the data line DL.

[0644] The sensing amplifier (SA) 401 is activated by the input of the control signal ADSAE, amplifies the voltage between the data line DL and the reference data line DREF1, and outputs the control signal NONE. The data line DL is connected to one input node of the sensing amplifier (SA) 401, and the reference data line DREF1 is connected to the other input node.

[0645] The sensing amplifier (SA) 402 is activated by the input of the control signal ADSAE and amplified by comparing the voltage between the reference data line DREF2 and the data line DL, and outputs the control signal MULTI. The reference data line DREF2 is connected to one input node of the sensing amplifier (SA) 402, and the data line DL is connected to the other input node.

[0646] The NOR circuit 403 receives the inputs of the control signals NONE and MULTI, and outputs the result of the NOR logic operation to the NAND circuit 404.

[0647] If both control signals NONE and MULTI are at the "L" level, the NAND circuit 404 outputs an "H" level. Conversely, if either control signal NONE or MULTI is at the "H" level, the NAND circuit 404 outputs an "L" level.

[0648] EXOR circuits 33 to 35 compare the first column address information CT with the second column address information CB and output the EXOR logic operation result CBO.

[0649] When the first column address information CT and the second column address information CB are complementary (when they are normal), the EXOR logic operation results CBO of EXOR circuits 33 to 35 all output "H" level. In relation to this, if the first column address information CT and the second column address information CT are not complementary (if they are abnormal), at least one of the EXOR logic operation results CBO of EXOR circuits 33-35 outputs "L" level.

[0650] Therefore, when the column encoder 9 does not detect an anomaly, all EXOR logic operation results CBO are set to "H" level. Furthermore, when the decoder fault detection circuit 210 on the row side does not detect an anomaly, the control signal NONE is set to "L" level, and the control signal MULTI is set to "L" level.

[0651] Therefore, the NAND circuit 404 outputs an "L" level, and the flip-flop (FF) 405 stores the "L" level. Then, it outputs a control signal FLAG ("L" level).

[0652] On the other hand, when the column encoder 9 detects an error, any bit of the EXOR logic operation result CBO is set to the "L" level. Furthermore, when an anomaly is detected in the row-side decoder fault detection circuit 210, the control signal NONE or the control signal MULTI is set to the "H" level.

[0653] Therefore, the NAND circuit 404 outputs an "H" level, and the flip-flop (FF) 405 stores the "H" level. Then, it outputs a control signal FLAG ("H" level).

[0654] Figure 44 This is a diagram illustrating an anomaly of the modified row decoder 4 and column decoder 10 according to the fourth embodiment.

[0655] like Figure 44 As shown in (A), when a non-selection exception occurs due to an anomaly in column decoder 10, where multiple column selection lines Y are not selected, the result of the EXOR logic operation CBO is not "111", and any bit in CBO is set to the "L" level.

[0656] Furthermore, even if a multiselect error occurs when multiple column select lines Y are selected among multiple column select lines Y, the result of the EXOR logic operation CBO is not "111", but one of its bits is set to the "L" level.

[0657] When one of the multiple column selection lines Y is selected, the result of the EXOR logical operation, CBO, is set to "111".

[0658] like Figure 44As shown in (B), when a non-selection anomaly occurs because one of the multiple word lines WL is not selected due to an anomaly of the line decoder 4, the control signal NONE ("H" level) is set to the control signal MULTI ("L" level).

[0659] When one of the multiple word lines WL is successfully selected, the control signal NONE (“L” level) and the control signal MULTI (“L” level) are set.

[0660] In the event of a multi-selection anomaly where multiple word lines WL are selected among multiple word lines WL due to an anomaly in line decoder 4, the control signal NONE (“L” level) and the control signal MULTI (“H” level) are set.

[0661] like Figure 44 As shown in (C), when a non-selection anomaly occurs due to an anomaly in the line decoder 4, where multiple word lines WL are not selected, or when a multi-selection anomaly occurs due to multiple word lines WL being selected among multiple word lines WL, the anomaly signal FLAG (H) is set according to the output (L) of the NOR circuit 403.

[0662] When an error in column decoder 10 causes the following anomalies: the error signal FLAG (“H” level) is set according to any bit (“L” level) of the EXOR logic operation result CBO, a non-selection anomaly occurs when no more than one column select line Y is selected, or a multi-selection anomaly occurs when multiple column select lines Y are selected from multiple column select lines Y.

[0663] When both row decoder 4 and column decoder 10 are functioning correctly, the error signal FLAG is set to the "L" level.

[0664] Figure 45 This is a first timing diagram illustrating the operation of a modified semiconductor device 100 according to a fourth embodiment.

[0665] This example will describe the normal operating condition.

[0666] like Figure 45 As shown, at time T121, column decoder 10 selects one of multiple column selection lines Y based on the input column address information CAD.

[0667] At time T122, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0668] Since the first column address information CT and the second column address information CB are compared and complement each other, the output EXOR logic operation result is CBO (all "H" levels).

[0669] At time T123, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD.

[0670] In addition, the reference data lines DREF1 and DREF2 are set to reference voltages VREF1 and VREF2 respectively according to the input ("H" level) of the control signal PCB.

[0671] Here, the voltage of the data line DL is set between the reference voltages VREF1 and VREF2.

[0672] At time T124, the control signal ADSAE (“H” level) is activated. Therefore, sense amplifiers (SA) 401 and 402 are activated, and control signals NONE (L level) and MULTI (L level) are output.

[0673] At time T125, the judgment circuit 120# outputs an abnormal signal FLAG ("L" level) based on the EXOR logic operation result CBO (all "H" level), the control signal NONE ("L" level), and MULTI ("L" level).

[0674] Figure 46 This is a timing diagram (part 2) illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment.

[0675] This example will describe the case where the word line WL is not selected.

[0676] like Figure 46 As shown, at time T126, column decoder 10 selects one of multiple column selection lines Y based on the input column address information CAD.

[0677] At time T127, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0678] Since the first column address information CT and the second column address information CB are compared and complement each other, the output EXOR logic operation result is CBO (all "H" levels).

[0679] Furthermore, in this exemplary embodiment, the line decoder 4 fails to select one word line from the multiple word lines WL based on the input line address information RAD due to an error. Therefore, the data line DL maintains a predetermined pre-charge voltage.

[0680] In addition, the reference data lines DREF1 and DREF2 are set to reference voltages VREF1 and VREF2 respectively based on the input ("H" level) and ("HL" level) of the control signal PCB.

[0681] Here, the voltage on the data line DL is greater than the reference voltages VREF1 and VREF2.

[0682] At time T129, the control signal ADSAE (“H” level) is activated. Therefore, sense amplifiers (SA) 401 and 402 are activated, and control signals NONE (“H” level) and MULTI (“L” level) are output.

[0683] At time T130, the decision circuit 120# outputs an abnormal signal FLAG ("H" level) based on the EXOR logic operation result CBO (all H level), the control signal NONE ("H" level), and MULTI ("L" level).

[0684] Therefore, an anomaly can be detected when an unselected anomaly occurs when one of the multiple word lines WL is not selected.

[0685] Figure 47 This is a timing diagram (part 3) illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment.

[0686] This example will describe the situation where multiple word lines WL are selected out of multiple word lines WL.

[0687] like Figure 47 As shown, at time T131, column decoder 10 selects one of multiple column selection lines Y based on the input column address information CAD.

[0688] At time T132, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively. In this example, the first column address information CT and the second column address information CB are generated as complementary to each other.

[0689] Since the first column address information CT and the second column address information CB are compared and complement each other, the output EXOR logic operation result is CBO (all "H" levels).

[0690] At time T133, the line decoder 4 selects multiple word lines WL caused by an anomaly from multiple word lines WL based on the input line address information RAD.

[0691] In addition, the reference data lines DREF1 and DREF2 are set to reference voltages VREF1 and VREF2 respectively based on the input ("H" level) and ("HL" level) of the control signal PCB.

[0692] Here, the voltage on the data line DL is lower than the reference voltages VREF1 and VREF2.

[0693] At time T134, the control signal ADSAE (“H” level) is activated. Therefore, sense amplifiers (SA) 401 and 402 are activated, and control signals NONE (L level) and MULTI (H level) are output.

[0694] At time T135, the decision circuit 120# outputs an abnormal signal FLAG ("H" level) based on the EXOR logic operation result CBO (all "H" level), the control signal NONE ("L" level), and MULTI ("H" level).

[0695] An anomaly can be detected when a multi-selection anomaly occurs, where multiple word lines WL are selected from multiple word lines WL.

[0696] Figure 48 This is a timing diagram (part 4) illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment.

[0697] In this example, we will describe the case where the selection operation for column selection line Y is not performed.

[0698] like Figure 48 As shown, in the first and second column encoders 9A and 9B, the first column address information CT and the second column address information CB are both set to "L" level. Therefore, the first column address information CT and the second column address information CB are not generated as complementary to each other.

[0699] The first column address information CT and the second column address information CB are compared, and since they are not complementary to each other, the output EXOR logic operation result CBO (all "L" levels) is output.

[0700] At time T136, line decoder 4 selects multiple word lines WL caused by an anomaly from multiple word lines WL based on the input line address information RAD.

[0701] In addition, the reference data lines DREF1 and DREF2 are set to reference voltages VREF1 and VREF2 respectively based on the input ("H" level) and ("HL" level) of the control signal PCB.

[0702] Here, the voltage of the data line DL is set between the reference voltages VREF1 and VREF2.

[0703] At time T137, the control signal ADSAE (“H” level) is activated. Therefore, sense amplifiers (SA) 401 and 402 are activated, and control signals NONE (L level) and MULTI (L level) are output.

[0704] At time T138, the decision circuit 120# outputs an abnormal signal FLAG ("H" level) based on the EXOR logic operation result CBO (all "L" level), the control signal NONE ("L" level), and MULTI ("L" level).

[0705] Therefore, an anomaly can be detected when one of the multiple column selection lines Y is not selected.

[0706] Figure 49 This is a timing diagram (part 5) illustrating the operation of a modified semiconductor device 100 according to the fourth embodiment.

[0707] This example will describe the situation where multiple column selection lines Y are selected out of multiple column selection lines Y.

[0708] like Figure 49 As shown, at time T139, column decoder 10 selects multiple column selection lines Y based on the input column address information CAD.

[0709] At time T140, the first and second column encoders 9A and 9B generate the first column address information CT and the second column address information CB, respectively, but they are not generated as complementary to each other.

[0710] Therefore, since the first column address information CT and the second column address information CB are compared with each other and are not complementary, the result of the EXOR logic operation CBO (at least one signal is at the "L" level) is output.

[0711] At time T141, line decoder 4 selects one word line from multiple word lines WL that has been affected by an error, based on the input line address information RAD.

[0712] In addition, the reference data lines DREF1 and DREF2 are set to reference voltages VREF1 and VREF2 respectively based on the input ("H" level) and ("HL" level) of the control signal PCB.

[0713] Here, the voltage of the data line DL is set between the reference voltages VREF1 and VREF2.

[0714] At time T142, the control signal ADSAE (“H” level) is activated. Therefore, sense amplifiers (SA) 401 and 402 are activated, and control signals NONE (L level) and MULTI (L level) are output.

[0715] At time T143, the determination circuit 120# outputs an abnormal signal FLAG ("H" level) based on the EXOR logic operation result CBO (at least one signal is at "L" level), the control signal NONE ("L" level), and MULTI ("L" level).

[0716] Therefore, an anomaly can be detected when multiple selection lines Y are selected out of multiple selection lines Y.

[0717] <Example 5>

[0718] Figure 50 This is a diagram illustrating the outline of the semiconductor device 1P according to the fifth embodiment.

[0719] Reference Figure 50 The semiconductor device 1P includes a memory macro 15P and a CPU 20.

[0720] CPU 20 controls memory macro 15P to retrieve data stored in memory macro 15P.

[0721] The difference between memory macro 15P and memory macro 15P is that it provides a sub-decoder 130 instead of row encoder 6 and column encoder 9, and provides detection circuit 132 instead of detection circuit 5. Since the other configurations are the same, their detailed description will not be repeated.

[0722] Sub-decoder 130 includes sub-row decoder 4# and sub-column decoder 10#, similar to row decoder 4 and column decoder 10.

[0723] The detection circuit 132 detects faults in the row decoder 4 and the column decoder 10.

[0724] Figure 51 This is a diagram illustrating the memory array 2 and its peripheral circuitry according to the fifth embodiment.

[0725] Reference Figure 51 It and Figure 2 The difference in configuration is that it provides sub-row decoder 4# and sub-column decoder 10#.

[0726] Sub-row decoder 4# outputs the row selection signal to multiple dummy row selection lines DRWL based on the input row address data RAD. Sub-column decoder 10# outputs the column selection signal to multiple dummy column selection lines DY based on the input column address information CAD. In this embodiment, dummy row selection lines DRWL[0] to DRWL

[15] are set. In addition, dummy column selection lines DY[0] to DY[7] are provided.

[0727] Figure 52 This is a diagram illustrating the detection unit 140 of the detection circuit 132 according to the fifth embodiment.

[0728] Reference Figure 52 The detection circuit 132 is used to detect anomalies in the row-side row decoder 4 corresponding to the rows of memory cells, and includes multiple detection units 140, data lines 145 and 146, P-channel MOS transistors 141 and 142, and inverters 143 and 144. The P-channel MOS transistors 141 and 142 are pre-charge transistors for pre-charging the data lines 145 and 146.

[0729] P-channel MOS transistors 141 and 142 are connected to data lines 145 and 146 and are turned on according to the control signal PCB (“L” level). Data lines 145 and 146 are set to “H” level.

[0730] Data cables 145 and 146 are jointly provided to multiple detection units 140.

[0731] Specifically, data lines 145 and 146 are precharged to a predetermined voltage according to the control signal PCB (“L” level).

[0732] The inverter 143 outputs a control signal PDL0 obtained by inverting the voltage signal on the data line 145.

[0733] The inverter 144 outputs a control signal PDL1 obtained by inverting the voltage signal on the data line 146.

[0734] In this example, a detection unit 140 is shown.

[0735] The detection unit 140 includes gate transistors GT0-GT3 and inverter-INV.

[0736] Gate transistors GT0 and GT2 are connected in series between data line 145 and fixed voltage VSS. Their gates receive signals from word line WL and the corresponding dummy row select line DRWL, respectively.

[0737] Gate transistors GT1 and GT3 are connected in series between data line 146 and fixed voltage VSS. Their gates receive the signal from word line WL and the signal from the corresponding dummy row select line DRWL, which is inverted by inverter INV.

[0738] For example, when line decoder 4 and sub-line decoder 4# are operating normally, when word line WL is set to "H" level, the corresponding dummy line select line DRWL is also set to "H" level.

[0739] Therefore, both gate transistors GT0 and GT2 are turned on, and data line 145 is connected to a fixed voltage VSS. That is, data line 145 is set to the "L" level.

[0740] On the other hand, because the signal of the dummy row select line DRWL, which is inverted via inverter INV, is input, gate transistor GT3 is not turned on. That is, data line 146 is set to the "H" level.

[0741] The control signal PDL0 is set to the "H" level, and the control signal PDL1 is set to the "L" level.

[0742] Figure 53 This is a diagram illustrating the detection result of the detection circuit 132 according to the fifth embodiment.

[0743] like Figure 53 As shown, for example, if line decoder 4 and sub-line decoder 4# are not operating properly and word line WL is not selected, gate transistors GT0 and GT1 will not be turned on. That is, data lines 145 and 146 will both remain at the "H" level.

[0744] Control signals PDL0 and PDL1 are both set to "L" level.

[0745] For example, when line decoder 4 and sub-line decoder 4# are operating normally and a word line WL is selected, gate transistors GT0 and GT2 are both turned on. Data line 145 is connected to a fixed voltage VSS. That is, data line 145 is set to the "L" level. Data line 146 is not connected to the fixed voltage VSS. That is, data line 145 is set to the "H" level.

[0746] The control signal PDL0 is set to the "H" level, and the control signal PDL1 is set to the "L" level.

[0747] For example, when line decoder 4 and sub-line decoder 4# are not operating normally and multiple word lines WL are selected, the gate transistors GT0 and GT2 of detection unit 140 are both turned on. Data line 145 is connected to a fixed voltage VSS. That is, data line 145 is set to the "L" level. The gate transistors GT1 and GT3 of another sensing unit 140 are also turned on. Data line 146 is connected to a fixed voltage VSS. That is, data line 145 is set to the "L" level.

[0748] Control signals PDL0 and PDL1 are both set to "H" level.

[0749] For example, if line decoder 4 and sub-line decoder 4# malfunction and the wrong word line WL is selected, gate transistors GT0 and GT2 will not conduct. Similarly, gate transistors GT1 and GT3 will also not conduct. That is, data lines 145 and 146 will both remain at the "H" level.

[0750] Control signals PDL0 and PDL1 are both set to "L" level.

[0751] Although the detection unit 140 for detecting row decoder 4 and sub-row decoder 4# has been described in this example, column decoder 10 and sub-column decoder 10# are similarly provided with column-side detection units.

[0752] Specifically, the column-side detection unit is connected to the gates of gate transistors GT0 and GT1 in the same manner as the row-side detection unit by replacing the word line WL with the column select line Y. Additionally, a dummy column select line DY is connected to gate transistor GT2 in place of the dummy row select line DRWL and is connected to gate transistor GT3 via inverter INV.

[0753] For example, when column decoder 10 and dummy column decoder 10# are operating normally, and when column select line Y is set to "H" level, the corresponding dummy column select line DY is also set to "H" level.

[0754] Therefore, both gate transistors GT0 and GT2 are turned on, and data line 145 is connected to a fixed voltage VSS. That is, data line 145 is set to the "L" level.

[0755] On the other hand, because the inverted signal of the dummy column select line DY via the inverter INV is input, the gate transistor GT3 is not turned on. That is, data line 146 is set to the "H" level.

[0756] The control signal QDL0 is set to the "H" level, and the control signal QDL1 is set to the "L" level.

[0757] For example, if column decoder 10 and sub-column decoder 10# malfunction and column select line Y is not selected, gate transistors GT0 and GT1 will not conduct. That is, data lines 145 and 146 will both remain at the "H" level.

[0758] Control signals QDL0 and QDL1 are both set to "L" level.

[0759] For example, if column decoder 10 and sub-column decoder 10# are not operating correctly and multiple column select lines Y are selected, then gate transistors GT0 and GT2 are both turned on. Data line 145 is connected to a fixed voltage VSS. That is, data line 145 is set to "L" level. Data line 146 is connected to a fixed voltage VSS. That is, data line 146 is set to "L" level.

[0760] Control signals QDL0 and QDL1 are both set to "H" level.

[0761] For example, if column decoder 10 and sub-column decoder 10# malfunction and an incorrect column select line Y is selected, gate transistors GT0 and GT2 will both be off. Similarly, gate transistors GT1 and GT3 will also be off. That is, data lines 145 and 146 will both remain at the "H" level.

[0762] Control signals QDL0 and QDL1 are both set to "L" level.

[0763] Figure 54 This is a diagram illustrating the synthesis circuit 134 of the detection circuit 132 according to the fifth embodiment.

[0764] Reference Figure 54 The combinational circuit 134 includes combinational units 340 and 350, a NOR circuit 360, an inverter 362, and a flip-flop (FF) 364.

[0765] The combination unit 340 includes NAND circuits 342 and 344.

[0766] The combination unit 350 includes NAND circuits 352 and 354.

[0767] When NAND circuit 344 receives signals input from control signals PDL0 and PDL1, it outputs the result of NAND logic operation to 342.

[0768] NAND circuit 342 receives control signal PDL0 and output from NAND circuit 344, and outputs the NAND logic operation result to NOR circuit 360.

[0769] If control signals PDL0 and PDL1 are both at "H" level and both at "L" level, then the output of NAND circuit 342 is set to "H" level.

[0770] On the other hand, when the control signals PDL0 and PDL1 are at “H” level and “L” level respectively, the output of NAND circuit 342 is set to “L” level.

[0771] When the NAND circuit 354 receives signals input from control signals QDL0 and QDL1, it outputs the result of the NAND logic operation to 352.

[0772] NAND circuit 352 receives control signal QDL0 and output from NAND circuit 354, and outputs the NAND logic operation result to NOR circuit 360.

[0773] If control signals QDL0 and QDL1 are both at "H" level and both at "L" level, then the output of NAND circuit 352 is set to "H" level.

[0774] On the other hand, when the control signals QDL0 and QDL1 are at "H" level and "L" level respectively, the output of NAND circuit 352 is set to "L" level.

[0775] NOR circuit 360 receives inputs from NAND circuits 342 and 352 and outputs the result of NOR logic operation to inverter 362.

[0776] Inverter 362 inverts the signal of NOR circuit 360 and stores it in flip-flop (FF) 364.

[0777] In this exemplary embodiment, when the output of one of the NAND circuits 342 and 352 is at the “H” level, the “H” level is stored in the flip-flop (FF) 364, and the exception signal FLAG (“H” level) is output.

[0778] Figure 55 This is a diagram used to illustrate the anomalies of the row decoder 4 and column decoder 10 according to the fifth embodiment.

[0779] like Figure 55 As shown, due to an anomaly in line decoder 4, a non-selection anomaly occurs when multiple word lines WL are not selected, a multi-selection anomaly occurs when multiple word lines WL are selected from among multiple word lines WL, or an incorrect selection anomaly occurs when an incorrect word line WL is selected from among multiple word lines WL. If an anomaly occurs, it is set to an anomaly signal FLAG ("H" level) based on the output ("H" level) of NAND circuit 342.

[0780] An anomaly in column decoder 10 results in: a non-selection anomaly when multiple column select lines Y are not selected, a multi-selection anomaly when multiple column select lines Y are selected, or an incorrect selection anomaly when an incorrect column select line Y is selected from among multiple column select lines Y. If an anomaly occurs, it is set to an anomaly signal FLAG ("H" level) based on the output ("H" level) of NAND circuit 352.

[0781] When both row decoder 4 and column decoder 10 are functioning correctly, the error signal FLAG is set to the "L" level.

[0782] Figure 56 This is a first timing diagram illustrating the operation of a semiconductor device 100 according to a fifth embodiment.

[0783] This example will describe the normal operating condition.

[0784] like Figure 56 As shown, at time T150, the control signal PCB is set to the "H" level. The detection circuit 132 operates accordingly. The pre-charge transistor is thus set to non-conducting, thereby completing the pre-charge operation of data lines 145 and 146.

[0785] At time T151, line decoder 4 selects one word line from multiple word lines WL based on the input line address information RAD. Sub-line decoder 4# selects one dummy word line from multiple dummy word lines DWL based on the input line address information RAD. Subsequently, gate transistors GT0 and GT2 are turned on.

[0786] Therefore, data lines 145 and 146 are set to "L" level and "H" level, respectively.

[0787] During time T152, control signals PDL0 and PDL1 are amplified to "H" and "L" levels, respectively.

[0788] Next, at time T153, the detection circuit 132 outputs an abnormal signal FLAG ("L" level) based on the control signals PDL0 ("H" level) and PDL1 ("L" level).

[0789] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0790] Figure 57 This is a timing diagram (part 2) illustrating the operation of the semiconductor device 100 according to the fifth embodiment.

[0791] This example will describe the case where the word line WL is not selected.

[0792] like Figure 57As shown, at time T154, the control signal PCB is set to the "H" level. The detection circuit 132 operates accordingly. The pre-charge transistor is thus set to non-conducting, thereby completing the pre-charge operation for data lines 145 and 146.

[0793] In this example, line decoder 4 and sub-line decoder 4# fail to select one word line from multiple word lines WL and one dummy word line from multiple dummy word lines DWL based on the input line address information RAD due to an error. In this case, gate transistors GT0 and GT2 will not conduct. Similarly, gate transistors GT1 and GT3 will not conduct.

[0794] Data lines 145 and 146 both maintain an "H" level.

[0795] Next, at time T155, the determination circuit 132 will output an abnormal signal FLAG ("H" level) based on the control signals PDL0 ("L" level) and PDL1 ("L" level).

[0796] Therefore, an anomaly can be detected when an unselected anomaly occurs when one of the multiple word lines WL is not selected.

[0797] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0798] Figure 58 This is a timing diagram (part 3) illustrating the operation of the semiconductor device 100 according to the fifth embodiment.

[0799] This example will describe the case where multiple word lines WL are selected among multiple word lines WL.

[0800] like Figure 58 As shown, at time T156, the control signal PCB is set to the "H" level. The detection circuit 132 operates accordingly. The pre-charge transistor is thus set to non-conducting, thereby completing the pre-charge operation for data lines 145 and 146.

[0801] At time T157, line decoder 4 selects multiple word lines WL based on the input line address information RAD. Sub-line decoder 4# selects multiple dummy word lines DWL based on the input line address information RAD. Subsequently, the gate transistors GT0 and GT2 of detection unit 140 are turned on. Furthermore, the gate transistors GT1 and GT3 of another detection unit 140 are turned on.

[0802] Therefore, data lines 145 and 146 are both set to "L" level.

[0803] Next, at time T158, control signals PDL0 and PDL1 are amplified to the "H" level.

[0804] Next, at time T159, the determination circuit 132 outputs an abnormal signal FLAG ("H" level) based on the control signals PDL0 ("H" level) and PDL1 ("H" level).

[0805] An anomaly can be detected when a multi-selection anomaly occurs, where multiple word lines WL are selected from multiple word lines WL.

[0806] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0807] Figure 59 This is a timing diagram (part 4) illustrating the operation of the semiconductor device 100 according to the fifth embodiment.

[0808] This example will describe the situation where an incorrect word line WL is selected among multiple word lines WL.

[0809] like Figure 59 As shown, at time T160, the control signal PCB is set to the "H" level. This operates the detection circuit 132. The pre-charge transistor is thus set to non-conducting, thereby completing the pre-charge operation on data lines 145 and 146.

[0810] At time T161, line decoder 4 selects the erroneous word line from multiple word lines WL based on the input line address information RAD. Sub-line decoder 4# selects the erroneous dummy word line from multiple dummy word lines DWL based on the input line address information RAD. Subsequently, the gate transistors GT0 and GT2 of detection unit 140 are de-energized. Furthermore, the gate transistors GT1 and GT3 of another sensing unit 140 are de-energized.

[0811] Therefore, data lines 145 and 146 both maintain the "H" level.

[0812] Next, at time T162, the determination circuit 132 outputs an abnormal signal FLAG ("H" level) based on the control signals PDL0 ("H" level) and PDL1 ("H" level).

[0813] An anomaly can be detected when an incorrect word line WL is selected from multiple word lines WL.

[0814] Although the word line WL has been described in this example, the same applies to the column selection line Y.

[0815] <Example 6>

[0816] Figure 60 This is a diagram illustrating the circuit configuration of the detection circuit 5Q according to the sixth embodiment.

[0817] Reference Figure 60 The detection circuit 5Q is illustrated in a configuration that can be replaced by the detection circuit 5 of the first embodiment.

[0818] The detection circuit 5Q includes a first row determination circuit 5A#, a second row determination circuit 5B#, a first column determination circuit 5C#, a second column determination circuit 5D#, and a synthesis circuit 5E#.

[0819] The first row of decision circuit 5A# includes EXNOR circuits 64# to 67#.

[0820] The second row of decision circuit 5B# includes EXOR circuits 60-63.

[0821] The first column of the decision circuit 5C# includes EXNOR circuits 33# to 35#.

[0822] The second column of the decision circuit 5D# includes EXOR circuits 30-32.

[0823] Synthesizer 5E# includes N-channel MOS transistors 85 to 98, precharge transistors 99A and 99B, an inverter 99C, a flip-flop 76, and data lines LN0 and LN1. Precharge transistor 99A is a P-channel MOS transistor. Precharge transistor 99B is an N-channel MOS transistor.

[0824] N-channel MOS transistors 85-98 are connected in parallel between data lines LN0 and LN1. Precharge transistor 99A is positioned between the power supply voltage VDD and data line LN0, with its gate receiving the control signal input from PCB2. Precharge transistor 99B is positioned between a fixed voltage VSS and data line LN1, with its gate also receiving the control signal input from PCB2.

[0825] The control signal PCB2 is set to "L" level before the detection operation and to "H" level during the detection operation. Therefore, data line LN0 is pre-charged to "H" level. During the detection operation, data line LN1 is set to "L" level.

[0826] The inverter 99C stores data in a flip-flop (FF) by inverting the signal on the data line LN0.

[0827] The outputs of EXNOR circuits 64# to 67# are connected to the gates of N-channel MOS transistors 95 to 98, respectively.

[0828] The outputs of EXOR circuits 60-63 are connected to the gates of N-channel MOS transistors 91-94, respectively.

[0829] The outputs of EXNOR circuits 33# to 35# are connected to the gates of N-channel MOS transistors 88 to 90, respectively.

[0830] EXOR circuits 30-32 are respectively connected to the gates of N-channel MOS transistors 85-87.

[0831] The first line determination circuit 5A# compares the first line address information RT and the second line address information RB to turn on the N-channel MOS transistors 95 to 98 based on the comparison result.

[0832] EXNOR circuits 64# to 67# receive one bit of the first row of address information RT and the second row of address information RB, respectively, and output the EXNOR logic operation result RBO.

[0833] When the first line of address information RT and the second line of address information RB are normal, they complement each other.

[0834] Therefore, when the first row of address information RT and the second row of address information RB are complementary (normal), the EXNOR logic operation results RBO of EXNOR circuits 64# to 67# are all output at "L" level. In this case, all N-channel MOS transistors 95-98 are not turned on. Therefore, the data line LN0 remains at "H" level.

[0835] Regarding the relationship, when the first row address information RT and the second row address information RB are not complementary (when they are abnormal), at least one of the EXNOR logic operation results RBO of EXNOR circuits 64# to 67# outputs a "H" level. In this case, any one of the N-channel MOS transistors 95-98 is turned on. Therefore, data line LN0 is connected to data line LN1 and is set to a "L" level.

[0836] By setting the data line LN0 to the "L" level, it is determined that the first row address information RT and the second row address information RB are not complementary (if this is abnormal). That is, it is determined that the row decoder 4 is abnormal and has not been decoded normally.

[0837] Specifically, due to the anomaly of line decoder 4, the following situations are determined: multi-selection anomaly when multiple word lines WL are not selected, and multi-selection anomaly when multiple word lines WL among multiple word lines WL are selected.

[0838] The second row determination circuit 5B# compares the input row address information RAD with the first row address information RT, and turns on the N-channel MOS transistors 91 to 94 based on the comparison result.

[0839] EXOR circuits 60 to 63 receive the input row address information RAD and the first row address information RT bit by bit, and output the EXOR logic operation result RTO.

[0840] When the input row address information RAD and the first row address information RT are normal, they have the same relationship.

[0841] Therefore, when the input row address information RAD and the first row address information RT are in the same relationship (when they are normal), the output of RTO, the result of all EXOR logic operations of EXOR circuits 60 to 63, is at a "L" level. In this case, all N-channel MOS transistors 91-94 are not turned on. Therefore, the data line LN0 remains at a "H" level.

[0842] On the other hand, when the input row address information RAD and the first row address information RT do not have the same relationship (when the input row address information RAD and the first row address information RT are abnormal), at least one of the EXOR logic operation results RTO of the EXOR circuits 60 to 63 outputs a "H" level. In this case, at least one of the N-channel MOS transistors 91-94 is turned on. Therefore, data line LN0 is connected to data line LN1 and is set to a "L" level.

[0843] By setting the data line LN0 to the "L" level, it is determined that the input row address information RAD and the first row address information RT are not in the same relationship (if this is abnormal). That is, it is determined that the row decoder 4 is abnormal and has not been decoded normally.

[0844] Specifically, an error selection anomaly is determined by an anomaly in line decoder 4, in which an incorrect word line WL is selected among multiple word lines WL.

[0845] The first column determination circuit 5C# compares the first column address information CT and the second column address information CB to turn on the N-channel MOS transistors 88 to 90 based on the comparison result.

[0846] EXNOR circuits 33# to 35# receive one bit of the first column address information CT and the second column address information CB respectively, and output the EXNOR logic operation result CBO.

[0847] When the first column of address information CT and the second column of address information CB are normal, they complement each other.

[0848] Therefore, when the first column address information CT and the second column address information CB are complementary (normal), the EXNOR logic operation results CBO of EXNOR circuits 33# to 35# all output "L" level. In this case, the N-channel MOS transistors 88-90 are not turned on. Therefore, the data line LN0 remains at "H" level.

[0849] Regarding the relationship, when the first column address information CT and the second column address information CT are not complementary to each other (when they are abnormal), at least one of the EXNOR logic operation results CBO of EXNOR circuits 33# to 35# outputs a "H" level. In this case, any one of the N-channel MOS transistors 88-90 is turned on. Therefore, data line LN0 is connected to data line LN1 and is set to a "L" level.

[0850] By setting the data line LN0 to the "L" level, it is determined that the first column address information CT and the second column address information CB are not complementary (if this is abnormal). That is, it is determined that the column decoder 10 is abnormal and has not been decoded normally.

[0851] Specifically, due to the anomaly of column decoder 10, the following situations are determined: non-selection anomaly when multiple column selection lines Y are not selected, and multi-selection anomaly when multiple column selection lines Y are selected among multiple column selection lines Y.

[0852] The second column determination circuit 5D# compares the input column address information CAD with the first column address information CT, and turns on the N-channel MOS transistors 85-87 based on the comparison result.

[0853] Each of the EXOR circuits 30 to 32 receives one bit of input column address information CAD and first column address information CT, and outputs the EXOR logic operation result CTO.

[0854] When the input column address information CAD and the first column address information CT are normal, they have the same relationship.

[0855] Therefore, when the input column address information CAD and the first column address information CT are in the same relationship (when they are normal), the output of all EXOR logic operations CTO from EXOR circuits 30 to 32 is at an "L" level. In this case, all N-channel MOS transistors 85-87 are off. Therefore, the data line LN0 remains at an "H" level.

[0856] On the other hand, when the input column address information CAD and the first column address information CT do not have the same relationship (when the input column address information CAD and the first column address information CT are abnormal), at least one of the EXOR logic operation results CTO of the EXOR circuits 30 to 32 outputs a "H" level. In this case, any one of the N-channel MOS transistors 85-87 is turned on. Therefore, data line LN0 is connected to data line LN1 and is set to a "L" level.

[0857] When data line LN0 is set to "L" level, it is determined that the input column address information CAD and the first column address information CT are not in the same relationship (when abnormal). That is, it is determined that the column decoder 10 is abnormal and has not been decoded normally.

[0858] More specifically, an error selection anomaly is determined by an anomaly in column decoder 10, wherein an incorrect column selection line Y is selected among multiple column selection lines Y.

[0859] In the synthesis circuit 5E#, when the data line LN0 is at the "L" level, the "H" level is stored in the flip-flop 76. When the data line LN0 is at the "H" level, the data line stores the "L" level in the flip-flop 76.

[0860] Trigger 76 outputs an exception signal FLAG based on the stored data.

[0861] Compared to the configuration of the first embodiment, this configuration reduces the number of logic circuit components. That is, by reducing the number of N-channel MOS transistors and the like, the same detection circuit 5Q as the detection circuit 5 described in the first embodiment can be implemented in a simpler way. Therefore, the layout area can also be reduced.

[0862] <Example 7>

[0863] In the seventh embodiment, a description of the configuration of the test circuit for the semiconductor device will be given.

[0864] Figure 61 This is a diagram illustrating the configuration of the detection circuit 5X according to the seventh embodiment.

[0865] Referring to 61, the detection circuit 5X and Figure 3 The difference between the detection circuit 5 and the detection circuit 5 is that DFT (Design for Testing) circuits 140 and 142 are added.

[0866] Since the other configurations are the same, their detailed description will not be repeated.

[0867] The DFT circuit 142 sets the first row address information RT and the second row address information RB based on the control signal PTN, the control signal SELXOR, and the input row address information RAD.

[0868] The DFT circuit 140 sets the first column address information CT and the second column address information CB based on the control signal PTN, the control signal SELXOR, and the input column address information CAD.

[0869] Therefore, the test operation can be performed on the detection circuit 5 without operating the row decoder 4 and column decoder 10.

[0870] Figure 62 This is a diagram illustrating the test mode of DFT circuits 140 and 142 according to the seventh embodiment.

[0871] like Figure 62 As shown, DFT circuits 140 and 142 are configured to output various test modes based on control signal PTN, control signal SELXOR, input row address information RAD, and input column address information CAD.

[0872] For example, the second row address information RB and the second column address information CB are set according to the control signal PTN.

[0873] For example, DFT circuits 140 and 142 set the second row address information RB[0] to RB[3] and the second column address information CB[0] to CB[2] to “H” level according to the control signal PTN (“L” level).

[0874] DFT circuits 140 and 142 set the second row address information RB[0] to RB[3] and the second column address information CB[0] to CB[2] to “L” level according to the control signal PTN (“H” level).

[0875] In addition, the DFT circuit 142 sets the first row address information RT[0] to RT[3] based on the combination of the control signal SELXOR and the input row address information RAD.

[0876] In addition, the DFT circuit 140 sets the first column address information CT[0] to CT[2] based on the combination of the control signal SELXOR and the input column address information CAD.

[0877] In this embodiment, based on the settings of the second row address information RB, the second column address information CB, the first row address information RT, and the first column address information CT, the settings of the EXOR circuit output and the control signal FLAG are shown.

[0878] The second row address information RB, the second column address information CB, the first row address information RT, and the first column address information CT are set based on the test mode. When the output of the control signal FLAG and the EXOR circuit based on this setting is different from the expected result, the abnormality of the target EXOR circuit can be determined.

[0879] By providing DFT circuits 140 and 142 as described in this method, the EXOR circuits 30 to 35 and 60 to 67 provided in the detection circuit 5 can be tested one by one, and it can be confirmed whether the EXOR circuits are operating normally.

[0880] Modification 1 of Example 7

[0881] Figure 63 This is a diagram illustrating the configuration of detector 5Y according to the first modification of the seventh embodiment.

[0882] Referring to 63, the detection circuit 5Y and Figure 60 The difference between the detection circuit 5Q and the detection circuit 5Q is that DFT (Design for Testing) circuits 140 and 142 are added.

[0883] Since the other configurations are the same, their detailed description will not be repeated.

[0884] The DFT circuit 142 sets the first row address information RT and the second row address information RB based on the control signal PTN, the control signal SELXOR, and the input row address information RAD.

[0885] The DFT circuit 140 sets the first column address information CT and the second column address information CB based on the control signal PTN, the control signal SELXOR, and the input column address information CAD.

[0886] Therefore, the test operation can be performed on the detection circuit 5 without operating the row decoder 4 and column decoder 10.

[0887] Figure 64 This is a diagram illustrating the test mode of the DFT circuits 140 and 142 according to the seventh embodiment of the modified 1.

[0888] like Figure 64 As shown, DFT circuits 140 and 142 are configured to output various test modes based on control signal PTN, control signal SELXOR, input row address information RAD, and input column address information CAD.

[0889] For example, the second row address information RB and the second column address information are set according to the control signal PTN.

[0890] For example, DFT circuits 140 and 142 set the second row address information RB[0] to RB[3] and the second column address information CB[0] to CB[2] to “H” level according to the control signal PTN (“L” level).

[0891] DFT circuits 140 and 142 set the second row address information RB[0] to RB[3] and the second column address information CB[0] to CB[2] to “L” level according to the control signal PTN (“H” level).

[0892] In addition, the DFT circuit 142 sets the first row address information RT[0] to RT[3] based on the combination of the control signal SELXOR and the input row address information RAD.

[0893] In addition, the DFT circuit 140 sets the first column address information CT[0] to CT[2] based on the combination of the control signal SELXOR and the input column address information CAD.

[0894] In this embodiment, based on the settings of the second row address information RB, the second column address information CB, the first row address information RT, and the first column address information CT, the settings of the EXOR circuit output and the control signal FLAG are shown.

[0895] Based on the test mode, the second row address information RB, the second column address information CB, the first row address information RT, and the first column address information CT are set. When the control signal FLAG and the output of the EXOR circuit and EXNOR circuit based on this setting are different from the expected results, the abnormality of the EXOR circuit and EXNOR circuit 2 can be determined.

[0896] By providing DFT circuits 140 and 142 as described in this method, the EXOR circuits 30 to 32, 60 to 63 and EXNOR circuits 33 to #35 and #64 to #67 provided in the detection circuit 5 can be tested one by one, and it can be confirmed whether the EXNOR circuit and the circuit are operating normally.

[0897] Modification 2 of Example 7

[0898] Figure 65 This is a diagram illustrating a decoder fault detection circuit 210 on the row side of a modified version 2 according to the seventh embodiment. In this example, the provision of a test circuit in the decoder fault detection circuit will be described.

[0899] Reference Figure 65 ,and Figure 36 Compared to the decoder fault detection circuit 200 on the row side, the difference is that a word line TWL for testing and gate transistors TGT0 and TGT1 for testing are further added.

[0900] The gate transistor TGT0 used for testing is positioned between the data line RDL0 and the fixed voltage VSS, and its gate is connected to the word line TWL used for testing.

[0901] The gate transistor TGT1 used for testing is positioned between the data line RDL1 and the fixed voltage VSS, and its gate is connected to the word line TWL used for testing.

[0902] Using this configuration, test operations can be performed by driving the word line TWL for testing, without driving the line decoder 4 to operate the gate transistors TGT0 and TGT1 for testing to set the data lines RDL0 and RDL1.

[0903] Therefore, it can be confirmed whether the decoder fault detection circuit 210 on the line side is operating normally.

[0904] The proper functioning of the decoder fault detection circuit on the column side can also be confirmed by providing a test circuit in the decoder fault detection circuit on the column side, but not limited to the row side.

[0905] Modification 3 of Example 7

[0906] Figure 66 This is a diagram illustrating the circuit configuration of the decoder fault detection circuit 110#X and the determination circuit 120#X according to the third modification of the seventh embodiment. In this example, the provision of test circuits in the decoder fault detection circuit 110#X and the determination circuit 120#X will be described.

[0907] Reference Figure 66 ,and Figure 43 The difference compared to the configuration described in the previous section is that a DFT circuit 140 is provided in the decision circuit 120#X, the word line TWL for testing is further added to the decoder fault detection circuit 110#, and a gate transistor TRST for testing is further added.

[0908] The gate transistor TRST used for testing is positioned between the data line DL and the fixed voltage VSS, with its gate connected to the word line TWL used for testing.

[0909] The DFT circuit 140 is the same as described above, so its detailed description will not be repeated.

[0910] In addition, by driving the word line TWL used for testing, the gate transistor TRST can be operated to set the data line DL.

[0911] Using this configuration, without driving the row decoder 4 and column decoder 10, test operations can be performed using the word line TWL and DFT circuit 140 for testing to confirm whether the decoder fault detection circuit 110#X and the judgment circuit 120#X are operating normally.

[0912] Modification 4 of Example 7

[0913] Figure 67 This is a diagram illustrating the detection unit 140# of the detection circuit 132 according to the fourth modification of the seventh embodiment.

[0914] Referring to 67, the difference between detection unit 140# and detection unit 140 is that NAND circuit 145 is provided to replace inverter-INV.

[0915] NAND circuit 145 receives the input signals of dummy row select line DRWL and control signal DFTN, and outputs the NAND logic operation result to gate transistor GT3.

[0916] If the control signal DFTN is set to "H" level, then the NAND circuit 145 acts as an inverter. That is, this configuration is the same as... Figure 52 The configuration of the detection unit 140 described herein is the same.

[0917] Furthermore, when the control signal DFTN is set to the "L" level, the gate transistor GT3 is turned on. Therefore, by setting the word line WL to the "H" level, any combination of voltage signals for data lines 145 and 146 can be intentionally set.

[0918] Using this configuration, test operations can be performed on the detection circuit 132 to confirm whether the detection circuit 132 is operating normally.

[0919] Although this disclosure has been specifically described based on the above embodiments, this disclosure is not limited to the embodiments, and needless to say, various modifications can be made without departing from its spirit.

Claims

1. A semiconductor device, comprising: A matrix-arranged array of memory cells; Multiple word lines are arranged corresponding to each row of the matrix of the memory cell array; Multiple bit lines are arranged corresponding to each column of the matrix of the memory cell array; A word driver is configured to drive one of the plurality of word lines; A column selection circuit is configured to select one of the plurality of bit lines; Multiple row select lines are coupled to the word driver; Multiple column select lines are coupled to the column select circuit; The first line encoder is coupled to the plurality of word lines and configured to generate the first line address information based on the signal levels of the plurality of word lines; The second line encoder is coupled to the plurality of word lines and configured to generate second line address information that is complementary to the first line address information; The first row determination circuit is configured to output a first row determination signal based on a comparison between the first row address information and the second row address information. A column decoder is configured to output column selection signals to the plurality of column selection lines based on input column address information; A first column encoder is coupled to the plurality of column select lines and configured to output first column address information based on the signal levels of the plurality of column select lines; The second column encoder is coupled to the plurality of column select lines and configured to output second column address information that is complementary to the first column address information based on the signal levels of the plurality of column select lines. The first column determination circuit is configured to output a first column determination signal based on a comparison between the first column address information and the second column address information. The output row address information generation circuit is configured to generate output row address information based on the first column determination signal and the first row address information; and The output column address information generation circuit is configured to generate output column address information based on the first row determination signal and the first column address information.

2. The semiconductor device according to claim 1, further comprising: The second row determination circuit is configured to output a second row determination signal based on a comparison between the input row address information and the first row address information. and The second column determination circuit is configured to output a second column determination signal based on a comparison between the input row address information and the first column address information.

3. The semiconductor device according to claim 1, further comprising: The comparison result determination circuit is configured to generate a comparison result signal based on the first row determination signal and the first column determination signal; The output row address information generation circuit is configured to generate output row address information based on the comparison result signal and the first row address information; as well as The output column address information generation circuit is configured to output an output column address information based on the comparison result signal and the first column address information.

4. The semiconductor device of claim 1, further comprising an address comparison circuit configured to compare input address information and output address information. The input address information includes the input row address information and the input column address information, and The output address information includes the output row address information and the output column address information.

5. The semiconductor device according to claim 1, further comprising: A first test circuit is configured to output a first test mode signal to the first row encoder and the second row encoder during a test state.

6. The semiconductor device of claim 1, further comprising a second test circuit configured to output a second test mode signal to the first column encoder and the second column encoder in a test state.

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