Display device

Abstract

A display device is provided, including: a display panel including a plurality of light emitting areas and non-light emitting areas between the light emitting areas; an insulating layer disposed on the display panel; a first conductive pattern overlapping the non-light emitting areas and directly disposed on the insulating layer; a color filter layer overlapping the light emitting areas and disposed on the insulating layer; a first insulating layer disposed on the first conductive pattern and the color filter layer, and having an opening portion overlapping the light emitting areas defined therein; and a second conductive pattern overlapping the non-light emitting areas and disposed on the first insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0021039, filed on February 20, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept described herein relates to a display device. Background Technology

[0004] Electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs, include display devices configured to display images. The display device includes a display panel configured to generate images and an input device, such as an input detection section.

[0005] An input detection unit is located on the display panel and detects the user's touch. The signal detected by the input detection unit is converted into an input signal. The display panel provides the user with an image corresponding to the input signal from the input detection unit.

[0006] The display device includes a polarizing film disposed on the display panel to prevent the reflection of external light. The polarizing film is defined as an external light anti-reflection film. The polarizing film reduces the reflectivity of external light incident from the outside of the display device toward the display panel. Inventively, the polarizing film (POL) may include a phase retarder and / or a polarizer. However, due to the thickness of the polarizing film, the thickness of the display device can be increased when using a polarizing film.

[0007] The information disclosed in this background section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0008] This disclosure provides a display device capable of reducing thickness.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0010] An embodiment of the present invention provides a display device, comprising: a display panel including a plurality of light-emitting areas and non-light-emitting areas between the light-emitting areas; an insulating layer disposed on the display panel; a first conductive pattern overlapping the non-light-emitting areas and disposed directly on the insulating layer; a color filter layer overlapping the light-emitting areas and disposed on the insulating layer; a first insulating layer disposed on the first conductive pattern and the color filter layer, and defining an opening portion overlapping the light-emitting areas in the first insulating layer; and a second conductive pattern overlapping the non-light-emitting areas and disposed on the first insulating layer.

[0011] It should be understood that both the foregoing general description and the following specific description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0013] Figure 1 This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention;

[0014] Figure 2 This is an illustrative diagram. Figure 1 A cross-sectional view of the display device shown in the figure;

[0015] Figure 3 Illustrated through examples Figure 2 The diagram shows a cross-section of the display panel.

[0016] Figure 4 yes Figure 2 The diagram shows a floor plan of the display panel.

[0017] Figure 5 It is a diagram. Figure 4 The diagram shows the equivalent circuit of one pixel.

[0018] Figure 6 Illustrated with examples Figure 5 The diagram shows a cross-sectional view of the corresponding part of the light-emitting element.

[0019] Figure 7 This is a plan view illustrating an input detection section according to an embodiment of the concept of the present invention;

[0020] Figure 8 yes Figure 7 An enlarged view of the first region A1 shown in the figure;

[0021] Figure 9 It is only an illustration. Figure 8 The diagram shows the first detection part, the second detection part, and the extended pattern.

[0022] Figure 10 It is only an illustration. Figure 8 The diagram of the first conductive pattern in the image;

[0023] Figure 11 It is along Figure 8 A cross-sectional view taken from line I-I';

[0024] Figure 12 yes Figure 7 An enlarged view of the second region A2 shown in the figure;

[0025] Figure 13 It is a schematic diagram. Figure 12 The diagram shows the cross-sectional configuration of the display panel and input detection section.

[0026] Figure 14 This is a schematic diagram illustrating a cross-sectional configuration of a display device according to another embodiment of the concept of the present invention;

[0027] Figure 15 This is a plan view of the input detection section of a display device according to another embodiment of the present invention;

[0028] Figure 16 It is a schematic diagram. Figure 15 A cross-sectional view of a portion of the input detection section shown in the figure;

[0029] Figure 17 It is a schematic diagram including Figure 15 The diagram shows the cross-sectional configuration of the display device for the input detection section.

[0030] Figure 18 This is a schematic diagram illustrating a cross-sectional configuration of a display device according to another embodiment of the concept of the present invention; and

[0031] Figure 19 This is a schematic diagram illustrating a cross-sectional configuration of a display device according to another embodiment of the concept of the present invention. Detailed Implementation

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly so specified herein.

[0034] In this specification, when a component (or area, layer, part, etc.) is referred to as being “on”, “connected to”, or “combined to” another component, it means that the component may be directly on, connected to, or combined to the other component, or that a third component may be present between the component and the other component.

[0035] The same reference numerals refer to the same elements. Additionally, the thickness, scale, and dimensions of components are exaggerated in the accompanying drawings for the purpose of effective description.

[0036] "And / or" includes all of one or more combinations defined by the relevant components.

[0037] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The terms above are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of the inventive concept, and vice versa. Singular terms may include plural forms unless otherwise specified.

[0038] Additionally, terms such as "below," "lower side," "upper," and "upper side" are used to describe the relationships of the configurations illustrated in the accompanying drawings. These terms are described as relative concepts based on the directions illustrated in the drawings.

[0039] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Generally, terms defined in dictionaries should be assumed to have the same meaning as in the context of the relevant field and should not be interpreted unreasonably or as having an overly formal meaning, unless expressly defined herein.

[0040] In various embodiments of the present invention, the terms "comprising" or "including" specify attributes, areas, fixed quantities, steps, processes, elements and / or components, but do not exclude other attributes, areas, fixed quantities, steps, processes, elements and / or components.

[0041] In the following, embodiments of the inventive concept are described in more detail with reference to the accompanying drawings.

[0042] Figure 1This is a perspective view illustrating a display device according to an embodiment of the concept of the present invention.

[0043] refer to Figure 1 According to an embodiment of the present invention, the display device DD may have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the present invention is not limited thereto, and the display device DD may have various shapes such as circles or polygons.

[0044] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3.

[0045] The upper surface of the display device DD can be defined as a display surface DS, and can have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD can be provided to the user through the display surface DS.

[0046] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and may define the outline of the display device DD printed in a predetermined color.

[0047] The display device DD can be used in large electronic devices such as televisions, monitors, or billboards. Additionally, the display device DD can be used in small and medium-sized electronic devices such as personal computers, laptops, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented only as exemplary embodiments and can be used in other electronic devices without departing from the scope of the inventive concept.

[0048] Figure 2 It is a diagram. Figure 1 The diagram shows a cross-section of the display device.

[0049] refer to Figure 2 The display device DD may include a display panel DP, an input detection section ISP, a window WIN, a printed layer PIT, a protective film PFM, a buffer layer CSL, and first to third adhesives ADH1, ADH2, and ADH3.

[0050] The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The display panel DP may be a flexible display panel. For example, the display panel DP may include multiple electronic components disposed on a flexible substrate.

[0051] The display panel DP according to embodiments of the present invention can be a light-emitting display panel, and is not specifically limited thereto. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0052] The input detection section (ISP) can be disposed on the display panel (DP). The input detection section (ISP) may include multiple detection sections (not shown) configured to detect external inputs. The detection sections may detect external inputs capacitively. The input detection section (ISP) can be manufactured directly on the display panel (DP) during the manufacturing process. However, the inventive concept is not limited thereto, and the input detection section (ISP) can be manufactured as a separate panel from the display panel (DP) and then attached to the display panel (DP) by adhesive.

[0053] The WIN window can be set on the input detection section (ISP). The WIN window protects the display panel (DP) and the input detection section (ISP) from external scratches and impacts. Images generated by the display panel (DP) can be provided to the user through the WIN window.

[0054] A protective film (PFM) can be applied beneath the display panel (DP). The PFM can be defined as a protective substrate. The PFM protects the lower portion of the display panel (DP). The PFM can comprise a flexible plastic material. For example, the PFM can comprise polyethylene terephthalate (PET).

[0055] A buffer layer (CSL) can be placed beneath the protective film (PFM). The CSL protects the display panel (DP) by absorbing external impacts applied to the lower portion of the DP. The CSL may include a foam sheet with predetermined elasticity.

[0056] The printed layer PIT can overlap with the non-display area NDA and can be placed on the lower surface of the window WIN facing the display panel DP. The printed layer PIT can have a predetermined color, and exemplaryly, it can be black. The non-display area NDA can be printed with the printed layer PIT in a predetermined color.

[0057] The first adhesive ADH1 can be applied between the window WIN and the input detection section ISP. The window WIN and the input detection section ISP can be bonded together using the first adhesive ADH1. The second adhesive ADH2 can be applied between the display panel DP and the protective film PFM. The display panel DP and the protective film PFM can be bonded together using the second adhesive ADH2. The third adhesive ADH3 can be applied between the protective film PFM and the buffer layer CSL. The protective film PFM and the buffer layer CSL can be bonded together using the third adhesive ADH3.

[0058] The first adhesive ADH1 may include an optically transparent adhesive. Each of the second adhesive ADH2 and the third adhesive ADH3 may include a pressure-sensitive adhesive.

[0059] Figure 3 Illustrated through examples Figure 2 The diagram shows a cross-section of the display panel.

[0060] refer to Figure 3 The display panel DP may include a substrate SUB, a pixel layer PXL disposed on the substrate SUB, and a thin film encapsulation layer TFE disposed on the substrate SUB to cover the pixel layer PXL.

[0061] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include a flexible plastic material. For example, the substrate SUB may include polyimide (PI). The pixel layer PXL may include multiple pixels. The configuration of the pixels will be described in detail below.

[0062] The thin-film encapsulation layer TFE may include at least two inorganic layers and an organic layer disposed between the inorganic layers.

[0063] Figure 4 yes Figure 2 The diagram shows a floor plan of the display panel.

[0064] refer to Figure 4 According to an embodiment of the present invention, the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, and a transmit driver EDV. The scan driver SDV, the data driver DDV, and the transmit driver EDV may be disposed in a non-display area NDA.

[0065] The display panel DP may have a rectangular shape, having a long side in a first direction DR1 and a short side in a second direction DR2. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0066] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, and multiple emission lines EL1 to ELm, where m and n are natural numbers. The pixels PX can be arranged in a matrix, but are not limited to this, and can be arranged in various other forms. The pixels PX can be set in the display area DA and can be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm.

[0067] The scan driver (SDV), data driver (DDV), and transmit driver (EDV) can be located in the non-display area (NDA). The scan driver (SDV) and transmit driver (EDV) can each be positioned adjacent to the long side of the display panel (DP). The data driver (DDV) can be manufactured as an integrated circuit chip and positioned adjacent to any of the short sides of the display panel (DP).

[0068] Scan lines SL1 to SLm can extend in the second direction DR2 and can be connected to the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 and can be connected to the data driver DDV. Transmit lines EL1 to ELm can extend in the second direction DR2 and can be connected to the transmit driver EDV.

[0069] The scan driver SDV generates multiple scan signals, which can be applied to pixel PX via scan lines SL1 to SLm. The scan signals can be applied to pixel PX sequentially. The data driver DDV generates multiple data voltages, which can be applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV generates multiple transmit signals, which can be applied to pixel PX via transmit lines EL1 to ELm.

[0070] Although not shown in the accompanying drawings, the display device DD may further include a timing controller (not shown) configured to control the operation of the scan driver SDV, the data driver DDV, and the transmit driver EDV.

[0071] A pixel PX can be supplied with a data voltage in response to a scan signal. A pixel PX can display an image by emitting light with a brightness corresponding to the data voltage in response to a transmission signal. The emission time of a pixel PX can be controlled by the transmission signal.

[0072] Figure 5 It is a diagram. Figure 4 The diagram shows the equivalent circuit of one pixel.

[0073] refer to Figure 5A pixel PX may include a light-emitting element (OLED) and a pixel circuit CC. The pixel circuit CC may include multiple transistors T1 to T7 and a capacitor CAP. The pixel circuit CC may control the amount of current flowing through the light-emitting element OLED in response to a data voltage. The light-emitting element OLED may generate light with a predetermined brightness in response to the amount of current supplied from the pixel circuit CC.

[0074] Each of transistors T1 through T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In the specification, for convenience, either the input electrode or the output electrode may be referred to as the first electrode, and the other may be referred to as the second electrode.

[0075] The first electrode of the first transistor T1 can receive a first voltage ELVDD through the fifth transistor T5, and the second electrode can be connected to the anode electrode of the light-emitting element OLED through the sixth transistor T6. The cathode electrode of the light-emitting element OLED can receive a second voltage ELVSS having a lower level than the first voltage ELVDD.

[0076] The first transistor T1 can be defined as a driving transistor. The first transistor T1 can control the amount of current flowing through the light-emitting element OLED according to the voltage applied to the control electrode of the first transistor T1.

[0077] The second transistor T2 can be connected between the data line DL and the first electrode of the first transistor T1, and the control electrode of the second transistor T2 can be connected to the i-th scan line SLi. The second transistor T2 can be turned on by receiving the i-th scan signal via the i-th scan line SLi to electrically connect the data line DL and the first electrode of the first transistor T1.

[0078] The third transistor T3 can be connected between the second electrode and the control electrode of the first transistor T1. The control electrode of the third transistor T3 can be connected to the i-th scan line SLi. The third transistor T3 can be turned on by receiving the i-th scan signal via the i-th scan line SLi to electrically connect the second electrode and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 can be connected in the form of a diode.

[0079] The fourth transistor T4 can be connected between node ND and the initialization power generation unit (not shown). The control electrode of the fourth transistor T4 can be connected to the (i-1)th scan line SLi-1. The fourth transistor T4 can be turned on by receiving the (i-1)th scan signal via the (i-1)th scan line SLi-1 to provide the initialization voltage Vint to node ND.

[0080] The fifth transistor T5 can be connected between the power line PL and the first electrode of the first transistor T1. The control electrode of the fifth transistor T5 can be connected to the i-th emitter line ELi.

[0081] The sixth transistor T6 can be connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element OLED. The control electrode of the sixth transistor T6 can be connected to the i-th emitter line ELi.

[0082] The seventh transistor T7 is connected between the initialization power generation unit (not shown) and the anode electrode of the OLED. The control electrode of the seventh transistor T7 can be connected to the (i+1)th scan line SLi+1. The seventh transistor T7 receives the (i+1)th scan signal through the (i+1)th scan line SLi+1 and is turned on to provide the initialization voltage Vint to the anode electrode of the OLED.

[0083] A capacitor CAP can be positioned between the power line PL and node ND. Capacitor CAP can store a data voltage. When the first transistor T1 is turned on based on the voltage stored in capacitor CAP, the amount of current flowing through the first transistor T1 can be determined.

[0084] exist Figure 5 The diagram illustrates transistors T1 to T7 based on PMOS. However, the inventive concept is not limited thereto, and in another embodiment of the inventive concept, transistors T1 to T7 may be NMOS.

[0085] Figure 6 It is an illustrative diagram and Figure 5 The diagram shows a cross-sectional view of the portion corresponding to the light-emitting element.

[0086] refer to Figure 6 A pixel (PX) includes an OLED light-emitting element and a transistor (TR) connected to the OLED. The transistor (TR) can refer to... Figure 5 The sixth transistor T6 is illustrated in the figure. An OLED light-emitting element may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a light-emitting layer EML.

[0087] The first electrode AE ​​can be an anode electrode, and the second electrode CE can be a cathode electrode.

[0088] Transistors (TR) and light-emitting elements (OLEDs) can be disposed on the substrate SUB. The display area DA of the display panel DP may include a light-emitting area PA corresponding to each pixel PX and a non-light-emitting area NPA surrounding the light-emitting area PA. The light-emitting elements OLED of the pixel PX may be disposed in the light-emitting area PA, and the transistors (TR) of the pixel PX may be disposed in the non-light-emitting area NPA. A buffer layer BFL is disposed on the substrate SUB, and the buffer layer BFL may include inorganic materials.

[0089] The semiconductor layer SM of the transistor TR can be disposed on the buffer layer BFL. The semiconductor layer SM can comprise an inorganic semiconductor or an organic semiconductor, such as amorphous silicon or polycrystalline silicon. Alternatively, the semiconductor layer SM can comprise an oxide semiconductor. Although in Figure 6 Not illustrated, but the semiconductor layer SM may include a source region, a drain region, and a channel region between the source and drain regions.

[0090] A first insulating layer INS1 can be disposed on a buffer layer BFL to cover the semiconductor layer SM. The first insulating layer INS1 may include an inorganic material. The gate electrode GE of the transistor TR, which overlaps with the semiconductor layer SM, can be disposed on the first insulating layer INS1. The gate electrode GE can be configured to overlap with the channel region of the semiconductor layer SM.

[0091] A second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the gate electrode GE. The second insulating layer INS2 may include organic and / or inorganic materials.

[0092] The source electrode SE and drain electrode DE of transistor TR are spaced apart from each other and are disposed on the second insulating layer INS2. The source electrode SE can be connected to the source region of semiconductor layer SM through a first contact hole CH1 defined in the first insulating layer INS1 and the second insulating layer INS2. The drain electrode DE can be connected to the drain region of semiconductor layer SM through a second contact hole CH2 defined in the first insulating layer INS1 and the second insulating layer INS2.

[0093] A third insulating layer INS3 can be disposed on the second insulating layer INS2 to cover the source electrode SE and drain electrode DE of the transistor TR. The third insulating layer INS3 may include an organic material. A connection electrode CNE can be disposed on the third insulating layer INS3. The connection electrode CNE can be connected to the drain electrode DE through a third contact hole CH3 defined in the third insulating layer INS3.

[0094] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the connection electrode CNE. The fourth insulating layer INS4 may include an organic material. A first electrode AE ​​may be disposed on the fourth insulating layer INS4. The first electrode AE ​​may include a connection electrode portion that can be connected to the connection electrode CNE through a fourth contact hole CH4 defined in the fourth insulating layer INS4.

[0095] A pixel-defining film (PDL) exposing a predetermined portion of the first electrode AE ​​can be disposed on the first electrode AE ​​and the fourth insulating layer INS4. An opening portion PX_OP for exposing the predetermined portion of the first electrode AE ​​can be defined in the pixel-defining film (PDL).

[0096] A hole control layer HCL can be disposed on the first electrode AE ​​and the pixel defining film PDL. A portion of the hole control layer HCL that is coplanar with the pixel defining film PDL can be disposed in the light-emitting region PA. The remaining portion of the hole control layer HCL can be disposed on a plane above the pixel defining film PDL in the non-light-emitting region NPA.

[0097] A hole control layer (HCL) can be co-located in the light-emitting region (PA) and the non-light-emitting region (NPA). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0098] The emissive layer EML can be disposed on the hole control layer HCL. The emissive layer EML can be disposed along the contour of the hole control layer HCL. A large portion of the portion of the emissive layer EML that is coplanar with the pixel defining film PDL can be disposed in the emissive region PA. A smaller portion of the emissive layer EML can be disposed on a plane above the pixel defining film PDL in the non-emissive region NPA.

[0099] The emissive layer EML can be disposed in the region corresponding to the opening portion PX_OP. That is, the emissive layers EML can be formed separately from each other in the pixel PX. The emissive layer EML may include organic and / or inorganic materials. The emissive layer EML can be configured to generate any one of red, green, and blue light. However, the inventive concept is not limited thereto, and the emissive layer EML can generate white light by using combinations of organic materials that generate red, green, and blue light.

[0100] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML). The ECL can follow the contour of the EML. A portion of the ECL that is coplanar with the pixel defining film (PDL) can be disposed in the light-emitting region (PA). Other portions of the ECL can extend into the non-light-emitting region (NPA) on the plane above the PDL.

[0101] An electronic control layer (ECL) can be disposed on a hole control layer (HCL) to cover the light-emitting layer (EML). That is, the ECL can be jointly disposed in the light-emitting region (PA) and the non-light-emitting region (NPA). The ECL may include an electron transport layer and may further include an electron injection layer. A second electrode (CE) can be disposed on the ECL. The second electrode (CE) can be jointly disposed in the pixel (PX).

[0102] A thin-film encapsulation layer (TFE) can be disposed on the light-emitting element (OLED). The TFE can also be disposed on the second electrode (CE) to cover the OLED. The layer between the substrate (SUB) and the TFE can be defined as a pixel layer (PXL).

[0103] The thin-film encapsulation layer TFE may include a first sealing layer EN1 disposed on the second electrode CE, a second sealing layer EN2 disposed on the first sealing layer EN1, and a third sealing layer EN3 disposed on the second sealing layer EN2. The first sealing layer EN1 may follow the contour of the second electrode CE. The bottom surface of the second sealing layer EN2 may follow the contour of the first sealing layer EN1. The first sealing layer EN1 and the third sealing layer EN3 may include inorganic materials and protect the pixel layer PXL from moisture and / or oxygen. The second sealing layer EN2 may include organic materials and protect the pixel layer PXL from foreign matter such as dust particles.

[0104] A first voltage, ELVDD, can be applied to the first electrode, AE, and a second voltage, ELVSS, can be applied to the second electrode, CE. In one aspect of the device, excitons are formed during the recombination of holes and electrons injected into the light-emitting layer, EML, and the light-emitting element, OLED, can emit light when the excitons transition to the ground state. The light-emitting element, OLED, can emit light, allowing an image to be displayed.

[0105] Figure 7 This is a plan view of the input detection section according to an embodiment of the present invention.

[0106] refer to Figure 7 The input detection section (ISP) may include multiple detection electrodes SE1 and SE2, multiple wirings SNL1 and SNL2, and multiple pads PD. The detection electrodes SE1 and SE2, wirings SNL1 and SNL2, and pads PD can be disposed on the thin-film encapsulation layer TFE.

[0107] The planar area of ​​the input detection section (ISP) can include an active area AA and an inactive area NAA surrounding the active area AA. Detection electrodes SE1 and SE2 can be located in the active area AA, and pads PD can be located in the inactive area NAA.

[0108] Wiring SNL1 and SNL2 can be connected to one end of detection electrodes SE1 and SE2 respectively, and can extend to the non-active region NAA to connect to pad PD. Pad PD can be connected to an input detection control unit (not shown) configured to control the input detection section ISP via a flexible printed circuit board (not shown).

[0109] The detection electrodes SE1 and SE2 may include a plurality of first detection electrodes SE1 extending in a first direction DR1 and arranged in a second direction DR2, and a plurality of second detection electrodes SE2 extending in the second direction DR2 and arranged in the first direction DR1. The wiring SNL1 and SNL2 may include a plurality of first signal wirings SNL1 connected to the first detection electrodes SE1 and a plurality of second signal wirings SNL2 connected to the second detection electrodes SE2.

[0110] The second detection electrode SE2 may be extended to be insulated from and intersect with the first detection electrode SE1. The first detection electrode SE1 may be defined as an output detection electrode, and the second detection electrode SE2 may be defined as an input detection electrode.

[0111] The input detection section (ISP) can be driven in a mutual inductance mode. For example, each of the second detection electrodes SE2 can be operated as a drive electrode, and each of the first detection electrodes SE1 can be operated as a sensing electrode. A drive signal can be applied to the second detection electrodes SE2 via the second signal wiring SNL2, and a sensing signal can be output from the first detection electrodes SE1 via the first signal wiring SNL1.

[0112] Each of the first detection electrodes SE1 may include a plurality of first detection portions SP1 arranged in a first direction DR1 and a plurality of first conductive patterns CP connecting the first detection portions SP1. Each of the first conductive patterns CP may be disposed between two adjacent first detection portions SP1 in the first direction DR1 to electrically connect the two first detection portions SP1. The first conductive pattern CP may be defined as a bridging pattern or a connecting pattern.

[0113] Each of the second detection electrodes SE2 may include a plurality of second detection portions SP2 arranged on the second direction DR2 and a plurality of extended patterns EP connecting the second detection portions SP2. Each of the extended patterns EP may be disposed between two adjacent second detection portions SP2 on the second direction DR2 to electrically connect the two second detection portions SP2.

[0114] The first detection portion SP1 and the second detection portion SP2 can have a grid shape. The first detection portion SP1 and the second detection portion SP2 do not overlap with each other and are spaced apart from each other, and can be arranged alternately. The capacitor can be formed by the first detection portion SP1 and the second detection portion SP2. The extended pattern EP can not overlap with the first conductive pattern CP.

[0115] The first detection portion SP1, the second detection portion SP2, and the extended pattern EP can be disposed on the same layer. The first conductive pattern CP can be disposed on a different layer from the first detection portion SP1, the second detection portion SP2, and the extended pattern EP.

[0116] Figure 8 yes Figure 7 The image shows an enlarged view of the first region A1. Figure 9 It is only an illustration. Figure 8 The diagram shows the first detection section, the second detection section, and the extended pattern. Figure 10 It is only an illustration. Figure 8 The diagram of the first conductive pattern in the image.

[0117] For example, Figure 8 The diagram illustrates two first detection portions SP1 that are adjacent to each other and spaced apart from each other, and two second detection portions SP2 that are adjacent to each other and connected to each other.

[0118] refer to Figure 8 , Figure 9 and Figure 10 Each of the first detection portion SP1 and the second detection portion SP2 may include a plurality of first branch portions BP1 extending in the first diagonal direction DDR1 and a plurality of second branch portions BP2 extending in the second diagonal direction DDR2. The first branch portions BP1 and the second branch portions BP2 are combined to have a grid shape.

[0119] The first diagonal direction DDR1 can be defined as a direction that intersects the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2. The second diagonal direction DDR2 can be defined as a direction that intersects the first diagonal direction DDR1 on a plane defined by the first direction DR1 and the second direction DR2. For example, the first direction DR1 and the second direction DR2 can intersect each other perpendicularly, and the first diagonal direction DDR1 and the second diagonal direction DDR2 can intersect each other perpendicularly.

[0120] The first branch portion BP1 of each of the first detection portion SP1 and the second detection portion SP2 may intersect with the second branch portion BP2 of each of the first detection portion SP1 and the second detection portion SP2, and may be integrally formed with each other. The diamond-shaped touch opening portion TOP may be defined by the first branch portion BP1 and the second branch portion BP2.

[0121] The first conductive pattern CP can extend without overlapping with the extended pattern EP, so as to electrically connect to the first detection portions SP1 adjacent to each other in the first direction DR1. The first conductive pattern CP can be connected to the first detection portion SP1 through a plurality of contact holes TC-CH. The first conductive pattern CP can extend toward the first detection portion SP1 through the area that overlaps with the second detection portions SP2 adjacent to each other in the second direction DR2.

[0122] An extended pattern EP can be disposed between the first detection portions SP1 and can extend from the second detection portion SP2. The second detection portion SP2 and the extended pattern EP can be integrally formed. The extended pattern EP has a grid shape and can extend from each of the second detection portions SP2. The extended pattern EP, the first detection portion SP1, and the second detection portion SP2 can be formed by simultaneously patterning the same material. The extended pattern EP, the first detection portion SP1, and the second detection portion SP2 disposed on the same layer can be defined as a second conductive pattern.

[0123] The first conductive pattern CP may include a first extension EX1 and a second extension EX2 having a shape symmetrical to the first extension EX1. The extension pattern EP may be disposed between the first extension EX1 and the second extension EX2.

[0124] The first extension EX1 can extend through an area overlapping with one of the second detection portions SP2, and can be connected to the upper and lower first detection portions SP1. The second extension EX2 can extend through another area overlapping with the second detection portion SP2, and can be connected to the upper and lower first detection portions SP1.

[0125] exist Figure 8 and Figure 9 In the accompanying drawings, based on the relative arrangement positions, the first detection portion SP1 is referred to as the upper first detection portion SP1 and the lower first detection portion SP1. Furthermore, based on the relative arrangement positions in the accompanying drawings, the second detection portion SP2 is defined as the left second detection portion SP2 and the right second detection portion SP2.

[0126] The predetermined portions of the first extension portion EX1 and the second extension portion EX2 adjacent to one side of the first extension portion EX1 and the second extension portion EX2 can be connected to the lower first detection portion SP1 through multiple contact holes TC-CH. The predetermined portions of the first extension portion EX1 and the second extension portion EX2 adjacent to the other side of the first extension portion EX1 and the second extension portion EX2 can be connected to the upper first detection portion SP1 through multiple contact holes TC-CH.

[0127] The contact hole TC-CH is defined in an insulating layer disposed on the first conductive pattern CP, and will be described below. Figure 11 The diagram shows the structure of the contact hole TC-CH.

[0128] The first extension EX1 may include a first sub-extension EX1_1 and a second sub-extension EX1_2 extending in the first diagonal direction DDR1, a third sub-extension EX1_3 and a fourth sub-extension EX1_4 extending in the second diagonal direction DDR2, a first sub-conductive pattern SCP1 extending in the second diagonal direction DDR2, and a second sub-conductive pattern SCP2 extending in the first diagonal direction DDR1. The first sub-conductive pattern SCP1 is a part of the fourth sub-extension EX1_4. The second sub-conductive pattern SCP2 is a part of the second sub-extension EX1_2.

[0129] The predetermined portions of the first sub-extension EX1_1 and the second sub-extension EX1_2 adjacent to one side of the first sub-extension EX1_1 and the second sub-extension EX1_2 can be connected to the lower first detection portion SP1 at region A through multiple contact holes TC-CH. The predetermined portions of the third sub-extension EX1_3 and the fourth sub-extension EX1_4 adjacent to one side of the third sub-extension EX1_3 and the fourth sub-extension EX1_4 can be connected to the upper first detection portion SP1 at region B through multiple contact holes TC-CH.

[0130] The other side of the first sub-extension EX1_1 can extend from the other side of the third sub-extension EX1_3 and is adjacent to the other side of the third sub-extension EX1_3. The other side of the second sub-extension EX1_2 can extend from the other side of the fourth sub-extension EX1_4 and is adjacent to the other side of the fourth sub-extension EX1_4. The first sub-conductive pattern SCP1 can extend from the other side of the fourth sub-extension EX1_4 in the second diagonal direction DDR2 and can extend to the first sub-extension EX1_1. The second sub-conductive pattern SCP2 can extend from the other side of the second sub-extension EX1_2 in the first diagonal direction DDR1 and can extend to the third sub-extension EX1_3.

[0131] The first sub-extension EX1_1, the second sub-extension EX1_2, the third sub-extension EX1_3, the fourth sub-extension EX1_4, the first sub-conductive pattern SCP1, and the second sub-conductive pattern SCP2 can be formed as a single unit.

[0132] The first sub-extension EX1_1 and the second sub-extension EX1_2 can be extended to intersect with a predetermined number of second branch portions BP2 in the second branch portion BP2 of the right second detection portion SP2 that are adjacent to the lower first detection portion SP1. For example... Figure 9 As illustrated in the diagram, some parts of the first branch BP1 of the second detection section SP2 on the right may not be placed in the area overlapping with the first sub-extension EX1_1, the second sub-extension EX1_2, and the second sub-conductive pattern SCP2.

[0133] The third sub-extension EX1_3 and the fourth sub-extension EX1_4 can be extended to intersect with a predetermined number of first branch sections BP1 in the first branch section BP1 of the right second detection section SP2 that are adjacent to the upper first detection section SP1. For example... Figure 9 As illustrated in the diagram, some parts of the second branch BP2 of the second detection section SP2 on the right may not be placed in the area overlapping with the third sub-extension EX1_3, the fourth sub-extension EX1_4, and the first sub-conductive pattern SCP1.

[0134] The second extension EX2 may include a fifth sub-extension EX2_1 and a sixth sub-extension EX2_2 extending in the second diagonal direction DDR2, a seventh sub-extension EX2_3 and an eighth sub-extension EX2_4 extending in the first diagonal direction DDR1, a third sub-conductive pattern SCP3 extending in the first diagonal direction DDR1, and a fourth sub-conductive pattern SCP4 extending in the second diagonal direction DDR2.

[0135] The left second detection portion SP2 may have a structure symmetrical to the right second detection portion SP2, and the second extension portion EX2 may have a structure symmetrical to the first extension portion EX1. Therefore, the fifth sub-extension portion EX2_1 to the eighth sub-extension portion EX2_4 can be connected to the first detection portion SP1 through the left second detection portion SP2. Furthermore, predetermined portions of the fifth sub-extension portion EX2_1 to the eighth sub-extension portion EX2_4 can be connected to the first detection portion SP1 through multiple contact holes TC-CH.

[0136] The fifth sub-extension EX2_1 to the eighth sub-extension EX2_4 may intersect with some of the first branch BP1 and the second branch BP2 of the left second detection section SP2. Additionally, the first branch BP1 and the second branch BP2 of the left second detection section SP2 may not be located in areas overlapping with the fifth sub-extension EX2_1 to the eighth sub-extension EX2_4, as well as the third sub-conductive pattern SCP3 and the fourth sub-conductive pattern SCP4.

[0137] Figure 11 It is along Figure 8 The cross-sectional view taken from line I-I'.

[0138] refer to Figure 11 The input detection section (ISP) may further include an insulating layer (IOL) disposed on the thin-film encapsulation layer (TFE). The insulating layer (IOL) may include inorganic materials. An insulating layer (IOL) is illustrated, but is not limited thereto. Multiple inorganic insulating layers may be disposed on the thin-film encapsulation layer (TFE).

[0139] A first conductive pattern CP can be disposed on an insulating layer IOL. The first conductive pattern CP can be directly disposed on the insulating layer IOL. When multiple insulating layers IOL are provided, the first conductive pattern CP can be directly disposed on the uppermost insulating layer IOL. A first insulating layer TC-OL1 can be disposed on the first conductive pattern CP and the insulating layer IOL. The first insulating layer TC-OL1 may include an organic material.

[0140] The first detection portion SP1 and the second detection portion SP2 can be disposed on the first insulating layer TC-OL1. An extended pattern EP integrally formed with the second detection portion SP2 can also be disposed on the first insulating layer TC-OL1. The first conductive pattern CP can be connected to the first detection portion SP1 through a plurality of contact holes TC-CH defined in the first insulating layer TC-OL1.

[0141] A black matrix BM can be disposed on a first insulating layer TC-OL1 to cover a first detection portion SP1 and a second detection portion SP2. A second insulating layer TC-OL2 can be disposed on the black matrix BM. The second insulating layer TC-OL2 may include an organic material.

[0142] Figure 12 yes Figure 7 The image shows an enlarged view of the second region A2.

[0143] For example, Figure 12 The diagram illustrates the luminescent regions PA1, PA2, and PA3, as well as the first detection section SP1 and the second detection section SP2.

[0144] refer to Figure 12, Figure 6 The light-emitting region PA shown in the figure can be any one of the light-emitting regions PA1, PA2, and PA3. The light-emitting regions PA1, PA2, and PA3 can be arranged along the first diagonal direction DDR1 and the second diagonal direction DDR2. The first branch portion BP1 and the second branch portion BP2 of the first detection portion SP1 and the second detection portion SP2 can overlap with the non-light-emitting region NPA between the light-emitting regions PA1, PA2, and PA3.

[0145] The light-emitting areas PA1, PA2, and PA3 may include a plurality of first light-emitting areas PA1 configured to display red, a plurality of second light-emitting areas PA2 configured to display green, and a plurality of third light-emitting areas PA3 configured to display blue. The third light-emitting areas PA3 may be larger than the first light-emitting areas PA1, and the first light-emitting areas PA1 may be larger than the second light-emitting areas PA2.

[0146] The light-emitting areas PA1, PA2, and PA3 can be rhomboid in shape. The touch opening portion TOP can overlap with the light-emitting areas PA1, PA2, and PA3. The touch opening portion TOP can have a rhomboid shape or other polygonal shape corresponding to the shape of the light-emitting areas PA1, PA2, and PA3, and can have dimensions corresponding to the light-emitting areas PA1, PA2, and PA3.

[0147] Since the first detection section SP1 and the second detection section SP2 are set in the non-light-emitting region NPA, the light generated in the light-emitting regions PA1, PA2 and PA3 can be emitted normally without being affected by the first detection section SP1 and the second detection section SP2.

[0148] Figure 13 It is a schematic diagram. Figure 12 The diagram shows the cross-sectional configuration of the display panel and input detection section.

[0149] Figure 13 The luminescent region PA shown in the figure can correspond to Figure 12 The luminescent regions PA1, PA2, and PA3 are illustrated in the diagram. For example, Figure 13 The illustration shows that the light-emitting regions PA have the same size. Additionally, in... Figure 13 For example, the first conductive pattern CP, the first detection portion SP1, and the second detection portion SP2 are illustrated one by one.

[0150] refer to Figure 13The display panel (DP) may include multiple light-emitting areas (PAs) and non-light-emitting areas (NPAs) between the light-emitting areas (PAs). The input detection section (ISP) may include an insulating layer (IOL), a first conductive pattern (CP), a second conductive pattern (CNP2), a color filter layer (CF), a first insulating layer (TC-OL1), a black matrix (BM), and a second insulating layer (TC-OL2). The first insulating layer (TC-OL1), the black matrix (BM), and the second insulating layer (TC-OL2) can be respectively... Figure 11 The diagram shows the first insulating layer TC-OL1, the black matrix BM, and the second insulating layer TC-OL2.

[0151] A color filter layer CF and a first conductive pattern CP can be disposed on the thin-film encapsulation layer TFE of the display panel DP. Specifically, the color filter layer CF can overlap with the light-emitting area PA and can be disposed on the insulating layer IOL. The color filter layer CF can be directly disposed on the insulating layer IOL. When multiple insulating layers IOL are provided, the color filter layer CF can be directly disposed on the uppermost insulating layer IOL. The first conductive pattern CP can overlap with the non-light-emitting area NPA and can be disposed on the insulating layer IOL.

[0152] The color filter layer CF can extend to each adjacent portion of the non-luminescent region NPA and the luminescent region PA. The color filter layer CF can include multiple color filters CF1, CF2, and CF3. Color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0153] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can have different colors. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can respectively include a red color filter, a green color filter, and a blue color filter.

[0154] The red filter can be set Figure 12 The green color filter can be set on the first luminescent area PA1 shown in the diagram. Figure 12 The blue filter can be set on the second luminescent area PA2 shown in the diagram. Figure 12 The third luminescent region PA3 is shown in the diagram.

[0155] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can extend into the portion of the non-luminescent region NPA adjacent to the corresponding luminescent region PA. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be spaced apart from each other in the non-luminescent region NPA. The larger middle portions of color filters CF1, CF2, and CF3 can be disposed in the luminescent region PA, while the smaller side portions are disposed in the non-luminescent region NPA.

[0156] The first conductive pattern CP can be disposed between some of the color filters CF1, CF2, and CF3. For example, the first conductive pattern CP can be disposed between the first color filter CF1 and the second color filter CF2. Figure 11 It is a cross-sectional view of the non-luminescent region NPA in which the first branch portion BP1 and the second branch portion BP2 are set, and therefore Figure 11 There is no illustration in the middle. Figure 13 The color filters CF1, CF2 and CF3 are shown in the diagram.

[0157] A first insulating layer TC-OL1 can be disposed on an insulating layer IOL. The first insulating layer TC-OL1 can be disposed on a first conductive pattern CP and a color filter layer CF. An opening portion OP overlapping with the light-emitting region PA can be defined in the first insulating layer TC-OL1. Therefore, the first insulating layer TC-OL1 can be disposed in the non-light-emitting region NPA to cover color filters CF1, CF2, and CF3 and the first conductive pattern CP. Color filters CF1, CF2, and CF3 can be exposed by the opening portion OP in the light-emitting region PA.

[0158] The side surface SLP of the first insulating layer TC-OL1, which defines the opening portion OP, can have an inclined surface forming an acute angle AAL relative to the upper surface of the display panel DP. For example, based on a direction parallel to the upper surface of the display panel DP, the width of the first insulating layer TC-OL1 can decrease in an upward direction perpendicular to the upper surface of the display panel DP. The width W1 of the first insulating layer TC-OL1 can be defined as the distance between the opening portions OP. The side surface SLP of the first insulating layer TC-OL1 can be defined as a reflective side surface. The first insulating layer TC-OL1 is mainly disposed in the non-light-emitting region NPA. The side surface SLP of the first insulating layer TC-OL1 can extend into the light-emitting region PA.

[0159] The second conductive pattern CNP2 can overlap with the non-light-emitting region NPA and can be disposed on the first insulating layer TC-OL1. The second conductive pattern CNP2 may include a first detection portion SP1 and a second detection portion SP2. Although in Figure 13 Not shown in the figure, but the second conductive pattern CNP2 may include an extended pattern EP extending from the second detection portion SP2. The second conductive pattern CNP2 may be connected to the first conductive pattern CP.

[0160] The black matrix BM can overlap with the non-emitting region NPA and can be disposed on the second conductive pattern CNP2. The black matrix BM can be disposed on the first insulating layer TC-OL1 to cover the second conductive pattern CNP2. The black matrix BM can be disposed entirely within the non-emitting region NPA.

[0161] The second insulating layer TC-OL2 can be disposed on the color filter layer CF, the first insulating layer TC-OL1, and the black matrix BM. The second insulating layer TC-OL2 can be configured to fill the opening portion OP. For example, the second insulating layer TC-OL2 can be provided on the color filter layer CF, the first insulating layer TC-OL1, and the black matrix BM using an inkjet process. The refractive index of the second insulating layer TC-OL2 can be greater than the refractive index of the first insulating layer TC-OL1.

[0162] The light L generated in the luminescent region PA can propagate upwards. Since the refractive index of the second insulating layer TC-OL2 is greater than that of the first insulating layer TC-OL1, total internal reflection can occur at the interface between the first insulating layer TC-OL1 and the second insulating layer TC-OL2. Therefore, the light L propagating towards the side surface SLP of the first insulating layer TC-OL1 can be reflected from the side surface SLP of the first insulating layer TC-OL1 and propagate upwards. As a result, the brightness in the luminescent region PA can be increased.

[0163] Black matrix (BM) can block unwanted light in the non-emitting area (NPA). Black matrix (BM) can include light-absorbing black material.

[0164] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can convert external light into red, green, and blue. This external light can be directed towards the display panel DP and provided to the display device DD. If the first color filter CF1, the second color filter CF2, and the third color filter CF3 are not used, the external light can be reflected from the display panel DP and provided to the user. In this case, the external light is visible to the user, for example, light reflected from a mirror.

[0165] However, as illustrated and described, external light is supplied to the first color filter CF1, the second color filter CF2, and the third color filter CF3, so that it is absorbed by the first color filter CF1, the second color filter CF2, and the third color filter CF3, or converted into red, green, and blue in the first color filter CF1, the second color filter CF2, and the third color filter CF3. Therefore, even if external light is supplied to the display device DD, like the light-emitting area PA, the external light can be converted into red, green, and blue in the first color filter CF1, the second color filter CF2, and the third color filter CF3. As a result, reflection of external light is prevented, making the visibility of external light impossible.

[0166] A first layer, comprising a color filter layer CF and a black matrix BM, is disposed on the input detection section ISP, and a second layer, comprising a first insulating layer TC-OL1 and a second insulating layer TC-OL2, may be disposed on the first layer. In this case, the input detection section ISP may include other inorganic insulating layers and other organic insulating layers instead of the first insulating layer TC-OL1 and the second insulating layer TC-OL2. Additionally, an additional organic insulating layer may be disposed between the first and second layers.

[0167] Therefore, when the first and second layers are stacked on the input detection section (ISP) respectively, the number of organic insulating layers used may increase, the manufacturing process may become more complex, and the thickness of the display device (DD) may increase.

[0168] In embodiments of the present invention, the color filter layer CF, the black matrix BM, and the first insulating layer TC-OL1 and the second insulating layer TC-OL2 can be integrated and disposed in the input detection section ISP. Therefore, the number of organic insulating layers used is reduced, simplifying the process and reducing the thickness of the display device DD.

[0169] Figure 14 This is a schematic diagram illustrating a cross-sectional configuration of a display device according to another embodiment of the concept of the present invention.

[0170] For example, in Figure 14 In, with Figure 13 The corresponding cross-sections are shown as the cross-sections of the display panel DP and the input detection section ISP_1.

[0171] The following text will be primarily based on and Figure 13 The different configurations shown in the diagram are used to describe the different configurations. Figure 14 The configuration of the display device DD_1 shown in the figure is illustrated, and the same configuration is illustrated using the same reference numerals.

[0172] refer to Figure 14 The black matrix BM can overlap with the non-emitting region NPA and can be disposed on the insulating layer IOL. The black matrix BM can be disposed between color filters CF1, CF2, and CF3. Parts of color filters CF1, CF2, and CF3 can partially overlap with parts of the black matrix BM. The black matrix BM can be disposed on the first conductive pattern CP. The black matrix BM can be disposed on the insulating layer IOL to cover the first conductive pattern CP. The first insulating layer TC-OL1 can be disposed on the black matrix BM.

[0173] exist Figure 13 In this context, the black matrix BM can be set on the first insulating layer TC-OL1, but unlike this, in... Figure 14In this configuration, the first insulating layer TC-OL1 can be disposed on the black matrix BM. Figure 14 In addition to the locations of the black matrix BM and the first insulating layer TC-OL1, Figure 14 Other configurations shown in the figure can be compared with Figure 13 The other configurations shown in the figure are basically the same.

[0174] The second conductive pattern CNP2 can be disposed on the first insulating layer TC-OL1. The first conductive pattern CP can be connected to the first detection portion SP1 of some of the second conductive patterns CNP2 defined in the first insulating layer TC-OL1 and the black matrix BM through the contact hole TC-CH' defined in the first insulating layer TC-OL1 and the black matrix BM.

[0175] The second insulating layer TC-OL2 can be disposed on the color filter layer CF, the first insulating layer TC-OL1, and the second conductive pattern CNP2, and can fill the opening portion OP.

[0176] Figure 15 This is a plan view of the input detection section of a display device according to another embodiment of the present invention.

[0177] refer to Figure 15 The input detection section ISP_2 may include multiple detection sections SP, multiple routing lines SNL, and multiple pads PD. The detection sections SP, routing lines SNL, and pads PD can be disposed on the thin-film encapsulation layer TFE.

[0178] The detection units SP can be arranged in a matrix shape along the first direction DR1 and the second direction DR2, but the arrangement of the detection units SP is not limited to this. The detection units SP can be placed on the same layer. The detection units SP can have a grid shape.

[0179] and Figure 7 Similar to the first detection portion SP1 and the second detection portion SP2 illustrated, the detection portion SP may include a plurality of first branch portions BP1 extending in the first diagonal direction DDR1 and a plurality of second branch portions BP2 extending in the second diagonal direction DDR2. The first branch portions BP1 and the second branch portions BP2 may be integrally formed and disposed in the non-light-emitting region NPA. The touch opening portion TOP overlapping the light-emitting region PA may be defined by the first branch portions BP1 and the second branch portions BP2.

[0180] The planar area of ​​the input detection section ISP_2 can include an active area AA and an inactive area NAA surrounding the active area AA. The detection section SP can be set within the active area AA, and the pad PD can be set within the inactive area NAA. The routing section SNL can connect to the detection section SP, extend into the inactive area NAA, and connect to the pad PD.

[0181] The input detection section ISP_2 can be driven in self-inductive mode to obtain coordinate information using a self-capacitance method. For example, each of the detection sections SP can be operated as both a drive electrode and a detection electrode. A drive signal can be applied to the detection section SP, and a detection signal can be output from the detection section SP.

[0182] Figure 16 It is a schematic diagram. Figure 15 The diagram shows a cross-section of a portion of the input detection section ISP_2.

[0183] Illustratively, Figure 16 The diagram illustrates the relationship with Figure 11 The corresponding cross-section. That is, in Figure 16 The figure shows a cross-section of a portion of the detection section SP located in the non-luminescent region NPA.

[0184] refer to Figure 16 An insulating layer IOL can be disposed on the thin-film encapsulation layer TFE, and a first insulating layer TC-OL1 can be disposed on the insulating layer IOL. A conductive pattern CNP can be disposed on the first insulating layer TC-OL1. The conductive pattern CNP may include a detection portion SP. A black matrix BM can be disposed on the first insulating layer TC-OL1 to cover the detection portion SP. A second insulating layer TC-OL2 can be disposed on the black matrix BM.

[0185] The insulating layer IOL, the first insulating layer TC-OL1, the black matrix BM, and the second insulating layer TC-OL2 can be essentially... Figure 11 The diagram shows the insulating layer IOL, the first insulating layer TC-OL1, the black matrix BM, and the second insulating layer TC-OL2.

[0186] Figure 17 It is a schematic diagram including Figure 15 The diagram shows a cross-sectional configuration of the display device for the input detection section.

[0187] For example, in Figure 17 In, with Figure 13 The corresponding cross-sections are shown as the cross-sections of the display panel DP and the input detection section ISP_2.

[0188] The following text will be primarily based on and Figure 13The different configurations shown in the diagram are used to describe the different configurations. Figure 17 The configuration of the display device DD_2 is shown in the figure, and the same configuration is illustrated using the same reference numerals.

[0189] refer to Figure 17 The conductive pattern CNP can overlap with the non-emitting region NPA and can be disposed on the first insulating layer TC-OL1. The black matrix BM can overlap with the non-emitting region NPA and can be disposed on the first insulating layer TC-OL1 and the conductive pattern CNP. Other configurations can be combined with... Figure 13 The other configurations shown in the figure are basically the same.

[0190] Figure 18 This is a schematic diagram illustrating a cross-sectional configuration of a display device according to another embodiment of the concept of the present invention.

[0191] For example, in Figure 18 In, with Figure 14 The corresponding cross-sections are shown as the cross-sections of the display panel DP and the input detection section ISP_3.

[0192] The following text will be primarily based on and Figure 14 The different configurations shown in the diagram are used to describe the different configurations. Figure 18 The configuration of the display device DD_3 is shown in the figure, and the same configuration is illustrated using the same reference numerals.

[0193] refer to Figure 18 The conductive pattern CNP can overlap with the non-light-emitting region NPA and can be disposed on the insulating layer IOL, and the black matrix BM can be disposed on the conductive pattern CNP. The black matrix BM can be disposed on the insulating layer IOL to cover the conductive pattern CNP. The first insulating layer TC-OL1 can be disposed on the black matrix BM. Figure 18 The conductive pattern CNP illustrated in the figure can be defined as the first conductive pattern. Other configurations can be... Figure 14 The other configurations shown in the figure are basically the same.

[0194] Figure 19 This is a schematic diagram illustrating a cross-sectional configuration of a display device according to another embodiment of the concept of the present invention.

[0195] For example, in Figure 19 In, with Figure 17 The corresponding cross-sections are shown as the cross-sections of the display panel DP and the input detection section ISP_4.

[0196] The following text will be primarily based on and Figure 17 The different configurations shown in the diagram are used to describe the different configurations. Figure 19The configuration of the display device DD_4 is shown in the figure, and the same configuration is illustrated using the same reference numerals.

[0197] refer to Figure 19 The conductive pattern CNP can overlap with the non-emitting region NPA and can be disposed on the insulating layer IOL, and the first insulating layer TC-OL1 can be disposed on the conductive pattern CNP. The first insulating layer TC-OL1 can be disposed on the insulating layer IOL to cover the conductive pattern CNP. The black matrix BM can overlap with the non-emitting region NPA and can be disposed on the first insulating layer TC-OL1. Other configurations can be combined with... Figure 17 The other configurations shown in the figure are basically the same.

[0198] According to an embodiment of the present invention, a detection portion for sensing external input, a color filter for preventing reflection of external light, and an insulating layer having a reflective side surface to improve brightness are integrated into the input detection portion, thereby reducing the thickness of the display device.

[0199] Although exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the claimed inventive concept.

Claims

1. A display device, comprising: The display panel includes multiple light-emitting areas and non-light-emitting areas between the light-emitting areas; An insulating layer is disposed on the display panel; The first conductive pattern overlaps with the non-light-emitting area and is directly disposed on the insulating layer; A color filter layer overlaps with the light-emitting area and is disposed on the insulating layer; A first insulating layer is disposed on the first conductive pattern and the color filter layer, and an opening portion overlapping the light-emitting area is defined in the first insulating layer; as well as A second conductive pattern overlaps with the non-light-emitting area and is disposed on the first insulating layer. The color filter layer and the first conductive pattern are directly disposed on the insulating layer and are disposed in the same layer.

2. The display device according to claim 1, wherein, The first insulating layer defines the side surface of the opening portion as having a sloped surface.

3. The display device according to claim 2, wherein, The width of the first insulating layer, which is defined as the distance between the openings, decreases as the first insulating layer moves upward in a direction perpendicular to the upper surface of the display panel.

4. The display device according to claim 1, further comprising: A black matrix overlaps with the non-light-emitting area and is disposed on the second conductive pattern and the first insulating layer.

5. The display device according to claim 4, further comprising: A second insulating layer is disposed on the color filter layer, the first insulating layer and the black matrix, and is configured to fill the opening portion.

6. The display device according to claim 5, wherein, The refractive index of the second insulating layer is greater than that of the first insulating layer.

7. The display device according to claim 5, wherein, The first insulating layer and the second insulating layer comprise organic materials.

8. The display device according to claim 1, wherein, The color filter layer includes: The first color filter; and The second color filter is spaced apart from the first color filter. Each of the first and second color filters extends into the portion of the non-luminous region adjacent to the corresponding luminous region within the luminous region.

9. The display device according to claim 1, wherein, The color filter layer includes multiple color filters. The first conductive pattern is disposed between some of the color filters in the color filter.

10. The display device according to claim 1, wherein, The second conductive pattern includes: Multiple first detection portions, having a grid shape, are arranged in a first direction and connected to each other by the first conductive pattern; Multiple second detection portions, having the grid shape, are arranged in a second direction intersecting the first direction and alternately arranged with the first detection portions; and An extended pattern is disposed between the second detection portions and is integrally formed with the second detection portions to extend from the second detection portions.

11. The display device according to claim 10, wherein, The first conductive pattern is connected to the first detection portion through a contact hole defined in the first insulating layer.

12. The display device according to claim 10, wherein, The first conductive pattern includes a first extension portion and a second extension portion. The extended pattern is disposed between the first extended portion and the second extended portion. The first extension portion and the second extension portion are connected to the first detection portion through a region that overlaps with the second detection portion.

13. The display device according to claim 1, wherein, The display panel further includes: Light-emitting elements are disposed in each of the light-emitting regions; and A thin-film encapsulation layer is disposed on the light-emitting element. The insulating layer is disposed on the thin film encapsulation layer.

14. The display device according to claim 1, further comprising: A black matrix, overlapping the non-light-emitting area and disposed on the first conductive pattern, is formed. The first insulating layer is disposed on the black matrix.

15. The display device according to claim 14, wherein, The first conductive pattern is connected to some of the second conductive patterns in the second conductive pattern through contact holes defined in the first insulating layer and the black matrix.

16. The display device according to claim 14, further comprising: A second insulating layer is disposed on the color filter layer, the first insulating layer, and the second conductive pattern and is configured to fill the opening portion.

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