Iterative binary division with carry prediction

Abstract

A method for binary division includes the steps of providing a current remainder as a sum bit vector and a carry bit vector, performing a carry-save addition operation between the sum bit vector, the carry bit vector, and a two's complement representation of a divisor to produce a temporary sum and a temporary carry, predicting a sign bit of a total sum of the temporary sum and the temporary carry, and updating the remainder with the temporary sum and the temporary carry, and incrementing a quotient if the sign bit is zero.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 981,579, filed February 26, 2020, and U.S. Provisional Patent Application No. 63 / 138,467, filed January 17, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention generally relates to joint computation, and to iterative binary division with carry prediction. Background Technology

[0004] Division is the process of counting the number of times one number (denominator D) is contained within another number (numerator N). One mathematical representation of division is given by Formula 1:

[0005] N / D = (Q, R) Formula 1

[0006] Where Q is the quotient, which represents the number of times D is included in N, and R is the remainder R, which represents the remaining part of N in the process of calculating Q, which is no longer able to allocate a complete block of size D.

[0007] Euclidean division is the mathematical representation of the result of integer division, and it can be expressed by formula 2:

[0008] N = Q * D + R Formula 2

[0009] Where D≠0 and 0≤R<|D|.

[0010] Long division is a method for partitioning large numbers. It breaks down the division problem into a series of easier steps, each of which includes steps described in the current reference as... Figure 1 The operation shown in the diagram is part of the long division flow 100.

[0011] In step 110, stream 100 begins and receives the numerator N and denominator D as input. In step 120, the quotient Q and the temporary remainder variable X are initialized to 0, variable n is initialized to the number of bits in the numerator N, and variable i (which will be used as an indicator of the current processed bit of N) is initialized to the position of the most significant bit (MSB) of N (i.e., position n-1), where the calculation begins (note that the long division process begins with the MSB shifting to the right until the last bit (i.e., LSB) is processed). The temporary remainder variable X can be used to compare the current remainder with D during the calculation to determine the next step of the stream. In step 130, the temporary remainder X is shifted one bit to the left (note that when a binary number shifts to the left, 0 is appended to its LSB, and the size of the binary number increases by one), the value of bit i of N is assigned to the least significant bit (LSB) of X, and Q is shifted one bit to the left.

[0012] In step 140, X is compared with D. If X is less than D, the flow continues to the next digit of N in step 160 (the current remainder is less than the denominator, so the next digit should be processed). On the other hand, if X is equal to or greater than D, the flow continues to step 150, where D is subtracted from X(X–D) before proceeding to step 160, and Q is incremented by 1 (setting the LSB of Q to 1).

[0013] In step 160, stream 100 updates the value of i to the next position (the next bit to the right) in the LSB direction N by decrementing the value of i by 1. In step 170, stream 100 checks if the most recently processed bit is an LSB of N. If the processed bit is not an LSB, stream 100 returns to step 130 to continue processing the next bit in N. If an LSB has already been processed, the remainder R receives the value of X, and in step 180, the final values ​​of Q and R are returned as output.

[0014] It should be noted that the long division process described in Stream 100 requires multiple subtraction operations. In fact, the number of operations required to complete a long division process is proportional to the size of N. When N is a large number, this can be a rather long process. It should also be noted that the subtraction operation itself requires carry propagation proportional to the size of D. As D and N increase, the entire division operation becomes a process of gradually increasing computational cost, and the complexity of the above long division method is O(n*d), where n is the number of digits in N, and d is the number of digits in D. Summary of the Invention

[0015] According to a preferred embodiment of the present invention, an iterative method is provided for binary division of an n-bit numerator by a d-bit denominator. The method includes the following steps in each iteration: performing bitwise summation and carry operations on the current remainder provided as a sum and carry, and the two's complement of the denominator; predicting the sign bit of the total sum and carry; updating the bits of the current remainder and quotient if the sign bit is positive; and creating a final remainder based on the total sum and carry of the current remainder from the last iteration after all iterations are completed.

[0016] According to a preferred embodiment of the present invention, a method for binary division is also provided. The method includes the following steps: providing the current remainder as a sum bit vector and a carry bit vector; performing a carry-preserving addition operation between the sum bit vector, the carry bit vector, and the two's complement representation of the denominator to generate a temporary sum and a temporary carry; predicting the sign bit of the total of the temporary sum and the temporary carry; updating the current remainder with the temporary sum and the temporary carry; and incrementing the quotient if the sign bit is 0.

[0017] In addition, according to a preferred embodiment of the present invention, the method further includes setting the index to the most significant bit (MSB) of the molecule, setting the least significant bit (LSB) of the summation bit vector to the value of a bit in the position index of the molecule, decrementing the index and repeating the steps of providing, performing, predicting, updating and decrementing until the index points to the LSB of the molecule, and creating a final remainder by adding a temporary sum and a temporary carry.

[0018] Furthermore, according to a preferred embodiment of the present invention, the carry-saving addition operation is performed in parallel on all bits of the bit vector.

[0019] Furthermore, according to a preferred embodiment of the present invention, the prediction step includes the following steps: finding the first summation sequence of "1" in the temporary summation, shifting the temporary carry one position to the left, finding the first carry sequence of "1" in the temporary carry, and predicting the carry if the first summation sequence overlaps with the first carry sequence.

[0020] According to a preferred embodiment of the present invention, a method for comparing a first number and a second number is provided, the method comprising the steps of: storing the first number in a first row of an associative memory array, storing the two's complement representation of the second number in a second row of the associative memory array such that bit i of the second number is stored in the same column of the associative memory array as bit i of the first number, performing carry-saving operations in parallel on multiple columns of the associative memory array to create a sum and a carry, predicting the value of the higher carry bit without adding the sum and the carry, and indicating that the first number is less than the second number if the value of the higher carry bit is 1.

[0021] According to a preferred embodiment of the present invention, a long divider system is provided. The system includes a carry-preserving calculator for receiving a remainder in the form of a sum vector and a carry vector, and performing a carry-preserving addition operation between the remainder and the two's complement representation of one of the denominator vectors to create a temporary sum and a temporary carry. The system also includes a carry predictor for predicting the sign of the sum of the temporary sum and the temporary carry and incrementing the quotient when the sign is 0; and a full adder for adding the temporary sum and the temporary carry to create a final remainder after all bits of the numerator have been processed.

[0022] In addition, according to a preferred embodiment of the present invention, the system further includes an associative memory array for storing the sum vector, carry vector, remainder, one's complement representation of the denominator vector, temporary sum, and temporary low-order carry in the rows of the memory array, such that each bit i of the vector is stored in column i of the memory array.

[0023] In addition, the carry-preserving calculator activates the rows and columns of the bits storing the sum vector, carry vector and remainder in parallel, thereby calculating multiple bits, including temporary sums and temporary low-order carry, in parallel with a computational complexity of O(1).

[0024] Furthermore, the carry predictor activates in parallel the row storing the temporary sum and the temporary carry bit, as well as multiple columns storing the bit, thereby predicting the sign of the total of the temporary sum and the temporary low-order carry in O(1) complexity. Attached Figure Description

[0025] The subject matter considered to be the present invention is specifically pointed out and explicitly claimed in the concluding section of the specification. However, the organization and operation of the invention, as well as its objects, features, and advantages, can be best understood by reading the following detailed description in conjunction with the accompanying drawings, which are:

[0026] Figure 1 This is a schematic diagram of a long division algorithm, a state-of-the-art technique for dividing binary numbers;

[0027] Figure 2 This is a schematic illustration of an alternative algorithm for long division binary numbers that is operable according to an embodiment of the present invention, which replaces the step of subtracting the denominator with the step of adding the two's complement of the denominator.

[0028] Figure 3 This is a schematic illustration of an enhanced substitution algorithm for long division binary numbers, operable according to an embodiment of the present invention, for replacing the step of adding the two's complement of two by predicting the sign of the sum.

[0029] Figure 4 This is a schematic illustration of a long divider system constructed and operable according to an embodiment of the present invention;

[0030] Figure 5 It is a construction and operable implementation according to embodiments of the present invention. Figure 4 A schematic diagram of the associated memory device for the function of a long divider system is shown;

[0031] Figure 6 It is operable according to embodiments of the present invention and can be operated by... Figure 4 A schematic diagram of the stream of numbers to be compared is shown in the long divider system.

[0032] Figure 7A , Figure 7B , Figure 7C and Figure 7D It shows the result of Figure 6 Various scenarios of stream processing; and

[0033] Figure 8 It is possible to be Figure 4 A schematic diagram of a long divider system implemented as microcode to perform a carry prediction stream is shown.

[0034] It should be recognized that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be enlarged relative to others for clarity. Furthermore, where deemed appropriate, reference numerals may be repeated between figures to indicate corresponding or similar elements. Detailed Implementation

[0035] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail so as not to obscure the invention.

[0036] The applicant has acknowledged that, as currently cited Figure 2 As shown in stream 200, a long division algorithm can be implemented by replacing the subtraction operation of D with the addition operation of the inverse value of D (-D). The applicant also realized that the two's complement representation of -D can be easily implemented on an associative processor unit (APU) for long integers (thousands of bits), and the computation can be significantly improved by taking advantage of the massively parallel data processing features of the APU.

[0037] The steps of stream 200, which are identical to those of stream 100, share the same reference numerators. In step 110, stream 200 may receive the numerator N and denominator D as input, and in step 210 may create the value of the two's complement representation of -D (here referred to as W, and calculated by adding 1 to the one's complement representation of D), and in step 120 may initialize the temporary remainder variable X to 0, initialize the variable n to the number of bits in the numerator N, and initialize the variable i (used as an indicator of the current processing bit of N) to the position of the most significant bit (MSB) of N at the start of the calculation. In step 130, stream 200 may perform a left shift operation on X and Q, and may set the value of the LSB (least significant bit) of X to the current bit of N.

[0038] In step 220, stream 200 calculates the sum S of W and X (S = X + W), and in step 230, stream 200 determines whether the sum S is positive. If S is positive, stream 200 proceeds to step 240, and the value of X is set to S, and the LSB of Q is set to "1" (Q is incremented by 1). The remainder of stream 200 (steps 160, 170, 180, 190) can operate in a manner similar to the individual steps of stream 100 (updating the number of remaining bits, determining whether the process is complete, and if complete, assigning the value of R to the value of X and returning the final values ​​of Q and R as output).

[0039] The applicant has recognized that using W (two's complement representation of -D) during division processes on associated memory devices (such as those described in U.S. Patent Nos. 9,558,812 and 10,832,746, the entire contents of which are incorporated herein by reference and assigned to the co-assigned persons of this invention) and using full adders (such as those described in U.S. Patent No. 10,534,836, the entire contents of which are incorporated herein by reference and assigned to the co-assigned persons of this invention) can significantly reduce the overall complexity of long division operations.

[0040] It should be noted that in the two's complement representation of a binary number, MSB is the sign bit. Furthermore, the two's complement value of any binary number can be easily calculated by adding the value of 1 to the two's complement value of the binary number (by inverting the bits of the binary number and adding 1 to the result).

[0041] The applicant has also realized that the actual value of the sum is not really needed during long division calculations, but only at the end. During the calculation, the only fact needed is whether the sum is positive or negative, which is reflected in the value of the carry bit (it should be noted that when adding the bits of two binary numbers, a carry bit can be created in addition to the sum bit when the sum of the two bits is greater than 1).

[0042] The one currently being referenced Figure 3The following is a description of what is shown below. Figure 4 The long divider 400 implements stream 300. It should be noted that the existing stream 300 and stream 100 ( Figure 1 The steps shared between the steps share the same reference numerals, while new steps (320, 330, 340, 350, 360 and 370) are emphasized in bold.

[0043] In step 110 of stream 300, long divider 400 may receive two unsigned integers N and D as input. In step 310, long divider 400 may invert the bits of D and may create a two's complement value of D (this is the first step in converting D to its two's complement representation). In step 120, long divider 400 may initialize several bit vectors and several scalars. The initialized vectors may include Q (which is a bit vector containing the quotient) and temporary vectors X.sum and X.carry (which can be used when comparing the remainder with D). X.sum may be a temporary bit vector containing the intermediate sum calculated without carry propagation, and X.carry may be a temporary bit vector containing the intermediate carry. The scalars may be n, which is the number of bits in N; or d, which is the number of bits in D, and may be index i, which initially points to the MSB of N (i.e., the (n-1)th bit), and may be decremented after each step of the division performed by long divider 400 to point to the next position in N where the stream should continue.

[0044] In step 320, the long divider 400 can perform a left shift operation on X.sum and X.carry, and can set the LSB of X.sum[0] to the value of N[i], that is, it can proceed to the next bit.

[0045] As described above, the two's complement representation of D can be calculated by adding 1 to the one's complement representation of D. It should be noted that the two's complement representation of D can be created in two steps of stream 300. First, the creation of the one's complement representation can be completed in one step (step 310), and second, the addition of 1 to the result can be completed in another step (step 330).

[0046] As indicated above, the one-complement of D is created in step 310. To complete the creation of the two-complement representation of D, the long divider 400 can add 1 to the vector involved in the "addition" operation with the inverse of D (instead of directly adding it to the inverse of D), and in step 330, the long divider 400 can complete the creation of the two-complement representation of D by adding 1 to the X.carry bit vector (setting its LSB to 1). The long divider 400 can then perform bitwise summation and carry operations between X.sum, X.carry, and ~D to obtain a temporary bit vector T.sum containing bitwise summation and a temporary bit vector T.carry containing bitwise carry. It should be noted that in this application, the symbol §(bit vector, bit vector, bit vector) represents bitwise summation and carry operations.

[0047] In step 340, the long divider 400 can predict the sign of the sum of T.sum and T.carry (i.e., the high-order carry Tc that can be created when adding T.sum and T.carry). out The value of the carry can be predicted without actually calculating it through carry propagation. In step 340, the actual sum is not calculated; only the value of the carry bit, which may be the high-order carry bit of the sign bit, can be predicted.

[0048] In step 350, the long divider 400 can check the predicted carry Tc. out Is the value equal to 0 (i.e., is the sum of the predictions of T.sum and T.carry positive)?

[0049] When the sum is positive, flow 300 can continue to step 360, where the long divider 400 can assign the value of T.sum to X.sum and the value of T.carry to X.carry, and can increment the value of Q (by setting its LSB to 1). When the sum is negative, flow 300 can continue to step 160, where the long divider 400 can proceed to the next bit by decrementing index i by 1.

[0050] In step 170, the long divider 400 can check if the last bit (LSB) of N has been reached. If the calculation is incomplete (the bit being processed is not an LSB of N), the long divider 400 can return to step 320 and continue processing the next bit. If the calculation is complete, the long divider 400 can continue to step 370, where the full adder 450 can calculate the value of R as the final sum of T.sum and T.carry, and can provide Q and R as outputs in step 190.

[0051] It can be appreciated that the associative memory array 410 can store very large binary numbers with thousands of bits (e.g., 2K, 4K), and even so, the complexity of each step of the stream 300, including steps 310, 330 and 340, can be performed with a per-step complexity of O(1), and all computations can be performed in parallel on all bits of all bit vectors.

[0052] Now quote Figure 4 This is a schematic illustration of a long divider 400 constructed and operated according to an embodiment of the present invention. The long divider 400 may include an associative memory array 410, a two's complement creator 420, a carry saver calculator 430, a carry predictor 440, and a full adder 450.

[0053] The associative memory array 410 includes a plurality of cells 411 arranged in a matrix, the matrix having bit lines 413 (columns) and word lines 415 (rows). All cells 411 in the same column are connected to the same bit line 413, and all cells 411 in the same row are connected to the same word line 415.

[0054] The one's complement creator 420 can receive any bit vector (e.g., D) stored in the rows of the associative memory array 410 (i.e., in the word lines) and can create a one's complement representation of the received vector by inverting each bit in the bit vector and storing the one's complement of the vector in the rows of the associative memory array 410.

[0055] The carry-and-carry calculator 430 can accept any three bit vectors as input (e.g., X.sum, X.carry, and ~D) and can perform bitwise summation and carry operations that create two bit vectors as output: a summation bit vector (e.g., T.sum) and a high-order carry bit vector (e.g., T.carry).

[0056] It should be noted that each bit vector (X.sum, X.carry, and ~D) can be stored in a separate row of the associative memory array 410. It should also be noted that bits j of each bit vector can be located in the same column (j) of the associative memory array 410, and therefore can be connected via the same bit line, enabling parallel computation of the summation and carry of all bits of the bit vector, thus computing the summation and carry vector in O(1) complexity. The following discussion... Figure 5 The placement of various vectors in the associative memory array 410 is described in detail.

[0057] Carry predictor 440 can predict the sign of the sum of two bit vectors without performing the addition operation and calculating the actual sum of the two vectors. Carry predictor 440 can predict the sign of the sum by searching for a sequence of 1s in one of the vectors starting from the MSB (a single "1" is considered a sequence). If no such sequence is found, the predicted sign is 0. If a sequence of 1s is found, carry predictor 440 can search for "1"s at any position along the corresponding part of the second vector after shifting the second vector one position to the left. If at least one instance of "1" is found in the second shifted vector, the predicted sign is 1; otherwise, the predicted sign is 0.

[0058] The following text is about Figure 8 The carry predictor 440, described in more detail, can use a first set lookup (FFS) function implemented on the associative memory array 410 to locate the first occurrence of the value "1" in a row of the memory array 410. The FFS can perform an XOR operation between each cell in a row and the cell to its right (on the same row). The FFS logic can set the values ​​of all bits to the right of the first occurrence of "1" to "0", retaining only the first position where the sequence "1" begins.

[0059] The full adder 450 can accept three bit vectors as input, use carry propagation to calculate the sum of the vectors, and return a bit vector with the sum and a carry bit.

[0060] The one currently being referenced Figure 5 An associative memory device 500 is shown that implements the function of a long divider 400. The associative memory device 500 includes an associative memory array 410, a multi-line decoder 520, an RL 521, an RSP 522, a sensing circuit 530, a selective write unit 540, and a controller 550.

[0061] Associative memory array 410 can be any suitable memory array, volatile or non-volatile, destructive or non-destructive, and can include pure memory cells. Data including inputs, intermediate results, and outputs can be stored in rows of associative memory array 410. Rows labeled N and D can store input numbers, rows labeled Q and R can store output numbers, while other rows can store intermediate data used throughout the computation, as well as other data items such as X.sum and X.carry, MSB indices of N and D, etc. Additional rows (not shown in the figure) can be used for temporary computation and storage. Row allocation in associative memory array 410 is not specified, and Figure 5 The line order in the text is for illustrative purposes only.

[0062] The multi-row decoder 520 can be any suitable row decoder capable of activating multiple rows in parallel. The row decoder 520 can activate two or more rows of the associative memory array 410 at a time. When multiple rows are activated, all columns of the associative memory array 410 can be activated in parallel, providing parallel computation on all columns of the associative memory array 410 for the activated rows during read operations and providing parallel write operations during write operations.

[0063] RL 521 can read a row from the associative memory array 410 and perform various logical operations ("OR", "XOR", etc.) between cells in that row. It can be noted that the RL function operates at the row level and provides row-level computation when column-level logical operations can be provided by the associative memory array 410.

[0064] RSP 522 can return an indication of whether at least one cell in a row has a value of 1. The RSP operation can be performed on any active row of the associated memory array 410 and can be based on US9,859,005 assigned to the ordinary assignee of this application.

[0065] The sensing circuit 530 can be formed by any suitable sensing circuit and is capable of sensing the value on any bit line of the cells in the connected column, and can provide the result of a Boolean function performed between selected cells in each column.

[0066] The selective write unit 540 can select which sensed columns to write back to the associated memory array 410 and can write the value from multiple sense circuit components in parallel.

[0067] The controller 550 can instruct the multi-line decoder 520 which line to activate, read, or write for the current operation, and can also instruct the selective write unit 540 from which column to write the output of the sensing circuit 530 back to the associative memory array 410 and which line data can be written to in a selective write operation. The controller 550 may include various parts of the long divider 400, such as a two's complement creator 420, a carry-preserving calculator 430, a carry predictor 440, and a full adder 450.

[0068] It can be recognized that, as a result of multiple read operations, computation can occur within the associative memory array. Therefore, the associative memory device 500 can perform any Boolean operation in parallel across all columns of the associative array 410, resulting in large-scale, in-situ, parallel computation. The long divider 400 can be part of a controller 550 that controls the activation of rows and columns of the associative memory array 410 according to stream 300.

[0069] The one currently being referenced Figure 6It is a schematic illustration of stream 600, which can be executed by the long divider 400 to compare between two numbers so as to determine whether the result is positive or negative as made in step 350.

[0070] In step 601, stream 600 can receive any two numbers A and B for comparison and determine which is larger. In step 610, stream 600 can perform a carry-save operation among A, ~B, and 1 to generate an S.sum bit vector and an S.carry bit vector. It can be noted that the operands ~B and 1 in the carry-save operation generate the two's complement representation of B, just like subtracting B from A. In step 612, stream 600 can perform a left shift operation on S.carry.

[0071] In step 620, the index of the MSB can be detected (A and B can be stored in vectors of the same size, and "0" is appended to the left of the shorter value). The index of the first occurrence of "1" in each of the vectors S.sum and S.carry is assigned to j and k respectively, and the size of the detected "1" sequence in each vector is assigned to size(k) and size(j) respectively.

[0072] In step 630, the sizes of the sequences are evaluated. If size(j) or size(k) is equal to 0, there is no chance of carry propagation, and thus the stream continues to step 660 to determine A≥B.

[0073] In step 640, the positions of the two sequences are evaluated. If the positions of both vectors do not overlap with the position of the MSB, then even if there is a carry, it will not propagate at the MSB, so the stream continues to step 660 to determine A≥B.

[0074] In step 650 (at least one sequence starts from the MSB of one of the vectors), the positions of the sequences of the two vectors are evaluated. If the sequences do not overlap, there will be no carry propagation at the MSB, and thus the stream continues to step 660 to determine A≥B. On the other hand, if the sequences do overlap, the carry will propagate at the MSB, and the stream continues to step 670 to determine A<B.

[0075] It can be realized that stream 600 can be used by the carry predictor 440 to predict that the carry can be 0 when A≥B, while the carry can be 1 when A<B.

[0076] Now cited Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D illustrate various cases processed by stream 600. Figure 7AAn example is provided where S.Sum has all zeros. Therefore, the size of the sequence of 1s in S.sum is zero, indicating that no carry propagation will occur. Figure 7B An example is provided where the sequence of 1s in S.Sum and S.Carry does not start in the MSB, indicating that there will be no carry propagation. Figure 7C An example is provided, processed by step 650, where the sequences of 1s in S.sum and S.carry overlap, indicating a carry is coming, and Figure 7D An example is provided, which is processed by step 612 in conjunction with step 640, indicating that there will be a carry.

[0077] The one currently being referenced Figure 8 This is a schematic diagram of stream 800, which can be generated by carry predictor 440 ( Figure 4 It is implemented as microcode to perform carry prediction.

[0078] In the streams and microcode discussed below, when used as part of a long divider 400, TS is the summation vector, and TC is the carry vector, both derived from carry-saving operations between two numbers. Vector 1m is used to isolate operations performed on the sign bit (a value of "1" in the sign bit column and "0" in all other columns), while vector ~1m is used to isolate operations performed on the contents of a vector (a value of "0" in the sign bit column and "1" in all other columns). RL is a vector that holds the result of one or more logical operations performed between cells of a vector stored in rows of memory array 410, and RSP includes the same indication in all bits related to the presence of a value of "1" in that row. If at least one cell in the row has a value of 1, all bits of RSP will be "1"; otherwise, they will be "0".

[0079] The carry predictor 440 can predict the sign of the sum by searching for a sequence of 1s in two vectors from left to right (a single "1" is considered a sequence) and checking for overlap between the sequences in the two vectors (which indicates the expected carry).

[0080] In step 801, stream 800 may receive two vectors TC and TS, and stream 800 predicts the sign of their sum for these two vectors.

[0081] In step 805, vector TC may be shifted one position to the left to simulate potential propagation from a remote disconnect sequence (to handle the case shown in Example 7D).

[0082] In step 810, the carry predictor 440 can calculate the disjunction ignore sign bit between TS and TC using, for example, the following microcode RL = ~(TS|TC|1m) and store the result in RL (stored in Figure 5(in RL 521), thereby finding the sequences in TC and TS.

[0083] In step 820, the carry predictor 440 can maintain only the leftmost disjunction sequence by using, for example, the following microcode RL = ~FFS-logic(RL) to remove remotely broken sequences that may not affect carry prediction.

[0084] In step 830, the carry predictor 440 may perform a conjunction between two vectors to find, for example, the following microcode: RL = RL & TS & TC & (~1m) whether the sequences found in TS and TC overlap (which indicates a carry). A value of "1" in any bit of RL may indicate that a carry will be created.

[0085] In step 840, the carry predictor 440 may use, for example, the following microcode: RL = RSP(RL) to broadcast the carry indication to all bits of RL.

[0086] In step 850, the carry predictor 440 can perform a full adder operation on the sign bit by using, for example, the following microcode: RL = (RL^TS^TC) & 1m, performing a logical XOR operation between RL (with carry indication in all bits) and TS to receive the predicted sign of the sum.

[0087] In step 860, the carry predictor 440 can broadcast the sign bit to a vector S (all bits of S include the value of the sign bit) using, for example, the following microcode: S = RSP(RL). All bits of vector S have the same value and have the sum of the predicted sign bit values.

[0088] It can be recognized that each step in the microcode, which can be executed across all bits stored in the column (between rows), can be executed in parallel on all bits of TC and TS, and steps in the microcode, which can be executed on all bits of the row, can be executed in parallel on all bits. Therefore, the complexity of the entire microcode is O(1).

[0089] It can be recognized that, with the associative memory array 410 ( Figure 4 The addition operation (two's complement) on the carry bit vector (where the addition and carry bit vector can be calculated by the carry save calculator 430 in O(1) complexity and the carry can be predicted by the carry predictor 440 in O(1) complexity) can provide an alternative operation to the traditional long division operation to provide an overall long division operation performed in O(n) complexity, which is significantly different from the standard complexity of the division operation, especially when n (the number of bits in the numerator N) is about several thousand (resulting in O(n*n) complexity).

[0090] It will be appreciated that the steps shown with respect to the exemplary flow described above are not intended to be limiting, and that the flow can be implemented in variations. These variations may include more steps, fewer steps, changes in the order of steps, skipping steps, and other variations that are obvious to those skilled in the art.

[0091] Although certain features of the invention have been illustrated and described herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations falling within the true spirit of the invention.

Claims

1. An iterative method for binary division by an n-bit numerator and a d-bit denominator on an associative memory device, the method comprising: In each iteration, bitwise summation and carry operations are performed on the current remainder, which is provided as a summation and carry, and on the two's complement of the d-bit denominator, on the associative memory device. The two's complement representation of the denominator, the carry, the remainder, and each bit i in the summation are stored in column i of the associated memory device. Predict the sign bit of the summation and the carry, update the current remainder on the associated memory device, and update the quotient bit if the sign bit is positive; and After all iterations are complete, a final remainder is created on the associated memory device based on the sum of the current remainders from the last iteration and the total of the carry. The number of positions n in the numerator and the number of positions d in the denominator are both on the order of several thousand.

2. A method for performing binary division on an associative memory device, the method comprising: The current remainder is provided as a sum bit vector and a carry bit vector on the associated memory device; On the associative memory device, a carry-store addition operation is performed between the sum bit vector and the carry bit vector and the two's complement representation of the denominator to produce a temporary sum and a temporary carry. Wherein, the two's complement representation of the denominator, the carry bit vector, the current remainder, and each bit i in the summation bit vector are stored in column i of the associated memory device; Predict the sign bit of the total of the temporary sum and the temporary carry; as well as If the sign bit is 0, the current remainder is updated on the associated memory device using the temporary sum and the temporary carry, and the quotient is incremented.

3. The method according to claim 2, further comprising: Further, the index is made to point to the most significant bit (MSB) of the molecule; On the associative memory device, the least significant bit (LSB) of the summation bit vector is set to the value of the bit in the position index of the molecule; Decrease the index; Repeat the process of providing, executing, predicting, updating, and decrementing until the index points to the LSB of the molecule; as well as The final remainder is created on the associated memory device by adding the temporary sum to the temporary carry.

4. The method according to claim 2, wherein, The carry-save addition operation is performed in parallel on all bits of the sum bit vector and the carry bit vector.

5. The method according to claim 2, wherein, The predictions include: On the associated memory device, find the first summation sequence of "1" in the temporary summation; The temporary carry is moved one position to the left on the associated memory device; On the associated memory device, find the first carry sequence of "1" in the temporary carry; and If the first summation sequence overlaps with the first carry sequence on the associated memory device, then the carry is predicted.

6. A long divider system implemented on an associative memory device, the associative memory device comprising an associative memory array storing vectors in its rows, the long divider system comprising: A carry-preserving calculator, implemented on an associative memory device, receives remainders in the form of sum vectors and carry vectors stored in the rows, and performs carry-preserving addition between the remainders and the two's complement representation of one of the denominator vectors to create temporary sums and temporary carry. Wherein, the two's complement representation of the denominator vector, the carry bit vector, the remainder, and each bit i in the sum bit vector are stored in column i of the associative memory array; A carry predictor, implemented on an associative memory device, predicts the sign of the sum of the temporary sum and the temporary carry, and increments the quotient if the sign is 0; and A full adder, implemented on an associative memory device, is used to add the temporary sum to the temporary carry after all bits of the numerator have been processed to create a final remainder. The number of digits in the numerator and the number of digits in the denominator are both on the order of several thousand.

7. The system according to claim 6, wherein the carry-saving calculator is used to activate in parallel the rows and columns storing the bits of the sum vector, the carry vector and the remainder, thereby computing in parallel the multiple bits including the temporary sum and the temporary carry with a computational complexity of O(1).

8. The system of claim 6, wherein the carry predictor is configured to activate in parallel rows storing the temporary sum and the temporary carry bits and multiple columns storing the bits, thereby predicting the sign of the total of the temporary sum and the temporary carry in complexity O(1).

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