Image sensor, forming method thereof and integrated chip

Abstract

Various embodiments of the present disclosure relate to an image sensor. The image sensor includes an image sensor element disposed in a substrate. The substrate includes a first material. The image sensor element includes an active layer, and the active layer includes a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along the outer sidewall and bottom surface of the active layer. A top cover structure overlies the active layer. The outer sidewalls of the active layer are spaced apart laterally between the outer sidewalls of the top cover structure, so that the top cover structure extends continuously over the outer edge of the active layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to an image sensor, a forming method thereof and an integrated chip. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices. In recent years, complementary metal-oxide semiconductor (CMOS) image sensors (CIS) have begun to be widely used, largely replacing charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CIS is increasingly favored due to its low power consumption, small size, fast data processing, direct data output and low manufacturing cost. Summary of the invention

[0003] An embodiment of the present invention provides an image sensor, comprising: a substrate comprising a first material; an image sensor element arranged in the substrate, wherein the image sensor element comprises an active layer, and the active layer comprises a second material different from the first material; a buffer layer arranged between the active layer and the substrate, wherein the buffer layer extends along the outer side wall and bottom surface of the active layer; and a top cover structure overlying the active layer, wherein the outer side wall of the active layer is laterally spaced apart between the outer side walls of the top cover structure, so that the top cover structure extends continuously above the outer edge of the active layer.

[0004] An embodiment of the present invention provides an integrated chip, comprising: a substrate, comprising a first material, wherein the substrate comprises opposite side walls and a lower surface, the opposite side walls and the lower surface defining a groove, and the groove extending into the front surface of the substrate; an active layer, arranged in the groove, wherein the active layer comprises a second material different from the first material; a buffer layer, lining the groove so that the buffer layer is arranged between the substrate and the groove, wherein the buffer layer comprises a compound of the first material and the second material; a top cover structure, extending continuously above the active layer and the buffer layer, wherein the top cover structure overlies the opposite side walls of the substrate defining the groove, wherein the top cover structure comprises the first material; and a silicide layer, arranged in the top cover structure.

[0005] An embodiment of the present invention provides a method for forming an image sensor, comprising: forming a dielectric layer along the surface of a substrate, wherein the substrate comprises a first material; etching the dielectric layer and the substrate to define a groove in the substrate; forming a buffer layer in the groove so that the dielectric layer contacts the buffer layer; forming an active layer in the groove, wherein the active layer comprises a second material different from the first material; and forming a top cover structure on the active layer so that the top cover structure extends continuously along the top surface of the active layer, wherein the top cover structure comprises the first material and wherein the top cover structure overlies the uppermost edge of the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of image sensors are shown that include a cap structure that extends continuously over an outer edge of an image sensor element.

[0008] Figures 2A to 2E Show according to Figure 1 Cross-sectional views of some embodiments of image sensors of some alternative embodiments of image sensors.

[0009] FIG. 3A to FIG. 3B Cross-sectional views of some embodiments of an integrated chip including an interconnect structure over a substrate are shown, wherein the cap structure extends continuously over a top surface of an image sensor element.

[0010] Figures 4 to 14 Cross-sectional views of some embodiments of a first method of forming an image sensor including a cap structure along an image sensor element are shown.

[0011] Fig.15 , Fig.16 , FIG. 17A to FIG. 17B Cross-sectional views of some embodiments of a second method of forming an image sensor including a cap structure along an image sensor element are shown.

[0012] Fig.18 A method is shown in a flow chart format illustrating some embodiments of forming an image sensor including a cap structure along with an image sensor element. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0014] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] A CMOS image sensor (CIS) typically includes an array of pixel regions, each of which has an image sensor element arranged in a semiconductor substrate. Upon receiving incident radiation, the image sensor element is configured to generate an electrical signal corresponding to the received incident radiation. The electrical signal from the image sensor element may be processed by a signal processing unit. The semiconductor substrate may include a first material (e.g., silicon) and the image sensor element may include an active layer, the active layer including a second material (e.g., germanium) different from the first material. The active layer is disposed in the semiconductor substrate. In addition, a second material may be selected to enhance the absorption of incident electromagnetic radiation within a first wavelength range (e.g., the first wavelength range includes infrared (IR) radiation). This may increase the ability of the image sensor element to perform depth detection and / or phase detection. The enhancement of the ability to obtain incident electromagnetic radiation within the first wavelength range may improve the performance of the image sensor element in time of flight (TOF) applications.

[0016] One challenge of the above-mentioned CIS is the damage to the active layer during the production of the image sensor element. For example, the production of the CIS may include forming a groove in a semiconductor substrate and then forming a buffer layer that lines the groove. An active layer is deposited on the buffer layer and the active layer fills the groove, and a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed in the active layer. A cap structure is formed on the active layer so that the outer sidewall of the cap structure is aligned with the outer sidewall of the active layer and / or is spaced apart laterally between the outer sidewalls of the active layer. An upper dielectric layer is formed on the cap structure and the semiconductor substrate. In addition, one or more silicide layers may be formed in the cap structure and / or the semiconductor substrate. The formation of the one or more silicide layers may include depositing a conductive layer (e.g., containing nickel) on the cap structure and / or the semiconductor substrate and performing an annealing process to form the one or more silicide layers. Subsequently, a removal process (e.g., a wet etching process) is performed on the semiconductor substrate to remove the remaining portion of the conductive layer that is not formed as silicide. The removal process includes exposing the semiconductor substrate to one or more etchants, such as hydrogen peroxide (e.g., H2O2). The one or more etchants may damage the active layer by penetrating a seam located at an upper edge of the active layer. The seam is located at the interface between the dielectric layer and the active layer. This may result in the formation of voids in the active layer and / or damage to the active layer, thereby degrading the performance of the image sensor element.

[0017] Therefore, some embodiments of the present disclosure relate to an image sensor including a cap structure overlying an active layer, and a related method for forming an image sensor. For example, the method for forming an image sensor may include forming a groove in a semiconductor substrate and then forming a buffer layer lining the groove. An active layer is deposited on the buffer layer and the active layer fills the groove, and a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed in the active layer. A cap structure is formed on the active layer so that the outer sidewalls of the active layer are laterally spaced apart between the outer sidewalls of the cap structure. Therefore, the width of the cap structure is greater than the width of the active layer and the cap structure directly covers the outer edge of the active layer and extends continuously over the outer edge of the active layer. An upper dielectric layer is formed on the cap structure and the semiconductor substrate. In addition, one or more silicide layers may be formed in the cap structure and / or the semiconductor substrate. Subsequently, a removal process (e.g., a wet etching process) is performed on the semiconductor substrate (e.g., removing the remaining portion of the conductive layer that is not formed as silicide). The removal process includes exposing the semiconductor substrate to one or more etchants, such as hydrogen peroxide (e.g., H2O2). Since the cap structure covers the outer edge of the active layer, the one or more etchants may be prevented from reaching the active layer during the removal process. This in turn reduces damage to the active layer by the one or more etchants, thereby improving the performance of the image sensor.

[0018] Figure 1 A cross-sectional view of some embodiments of an image sensor 100 is shown that includes a cap structure 112 that extends continuously over outer edges 108 e 1 , 108 e 2 of an active layer 108 .

[0019] The image sensor 100 includes a dielectric structure 116 overlying a substrate 102. An image sensor element 106 is disposed within the substrate 102. The image sensor element 106 is configured to convert electromagnetic radiation 120 (e.g., photons) into electrical signals (i.e., generate electron-hole pairs from the electromagnetic radiation 120). The electromagnetic radiation 120 may be disposed on a backside surface 102b of the substrate. Thus, in some embodiments, the electromagnetic radiation 120 is back-side illuminated (BSI) on the image sensor 100. In some embodiments, the image sensor element 106 may be configured, for example, to generate electrical signals from infrared (IR) radiation (e.g., electromagnetic radiation having a wavelength in a range of about 800 nanometers (nm) to 2,500 nm).

[0020] In some embodiments, substrate 102 is composed of a first material (e.g., silicon). In addition, image sensor element 106 includes an active layer 108 disposed in a recess of substrate 102 and a buffer layer 110 disposed between active layer 108 and substrate 102. In yet other embodiments, active layer 108 includes a second material (e.g., germanium) that is different from the first material. In yet other embodiments, buffer layer 110 includes a combination of the first material and the second material and provides a transition region between substrate 102 and active layer 108. A first isolation structure 104 is disposed in substrate 102 and provides electrical isolation to image sensor element 106 from other devices and / or doped regions (not shown) disposed in / on substrate 102. First isolation structure 104 may laterally surround image sensor element 106. Active layer 108 may, for example, include photodetector regions and / or layers (e.g., charge storage regions, floating nodes, surface pinning regions, contact regions, guard rings, etc. (not shown)) configured to convert electromagnetic radiation 120 (e.g., photons) into electrical signals and / or facilitate readout of the electrical signals. In some embodiments, the second material (e.g., germanium) of active layer 108 is selected to ensure high quantum efficiency (QE) of IR radiation of image sensor element 106, thereby improving the performance of image sensor 100.

[0021] The cap structure 112 overlies the front side surface 102 f of the substrate 102 and extends continuously over the top surface of the active layer 108 and the top surface of the buffer layer 110. The dielectric layer 114 overlies the front side surface 102 f of the substrate 102 and the cap structure 112. The dielectric structure 116 overlies the dielectric layer 114. In some other embodiments, the thickness of the cap structure 112 is greater than the thickness of the dielectric layer 114. In some embodiments, the cap structure 112 may be or include, for example, a first material (e.g., silicon), epitaxial silicon, amorphous silicon, crystalline silicon, a high dielectric constant dielectric material (e.g., aluminum oxide, hafnium oxide), another suitable material, or any combination of the foregoing materials. In addition, the cap structure 112 extends continuously over the opposite sidewalls of the image sensor element 106. Therefore, the cap structure 112 directly covers and overlies the outer edges 108e1, 108e2 of the active layer 108. In still other embodiments, the maximum width of the cap structure 112 is greater than the maximum width of the image sensor element 106.

[0022] In some embodiments, during the fabrication of the image sensor 100, a silicide layer (not shown) may be formed within the cap structure 112 to facilitate electrical connection between a conductive contact (not shown) and a photodetector region and / or layer (not shown) disposed within the active layer 108. Forming the silicide layer may include depositing a conductive layer (e.g., including nickel) over the cap structure 112 and performing an annealing process to form a silicide layer (e.g., including nickel silicide (NiSi)) within the cap structure 112. Subsequently, a removal process (e.g., a wet etching process) is performed on the cap structure 112 to remove excess material from the conductive layer that is not converted into the silicide layer. The removal process includes exposing the substrate 102 and the cap structure 112 to one or more etchants (e.g., hydrogen peroxide (e.g., H2O2)). Since the cap structure 112 covers the outer edges 108e1, 108e2 of the active layer 108, the one or more etchants may not reach the active layer 108 and / or react with the active layer 108 during the removal process. This in turn reduces damage to the active layer 108 by the one or more etchants, thereby improving the performance of the image sensor 100. In still other embodiments, another silicide layer (not shown) may be formed within the substrate 102, so that the cap structure 112 protects the active layer during the formation of the other silicide layer.

[0023] Figure 2A Show according to Figure 1 FIG. 2 is a cross-sectional view of an image sensor 200 a of some alternative embodiments of image sensor 100 .

[0024] In some embodiments, the image sensor 200a includes a substrate 102, wherein the substrate 102 includes a protrusion 102p disposed laterally adjacent to the image sensor element 106. The top surface of the protrusion 102p is located vertically above the top surface of the image sensor element 106. In some further embodiments, a cap structure 112 and a dielectric layer 114 overlie the protrusion 102p and conform to the shape of the protrusion 102p. A height h1 of the active layer 108 is defined between the backside surface 102b of the substrate 102 and the top surface of the active layer 108, and a height h2 of the buffer layer 110 is defined between the backside surface 102b of the substrate 102 and the top surface of the buffer layer 110. In some embodiments, the height h1 is less than the height h2.

[0025] Figure 2B Show according to Figure 2A 200a. FIG. 200B is a cross-sectional view of an image sensor 200b of some alternative embodiments to image sensor 200a.

[0026] In some embodiments, the image sensor 200b includes a cap structure 112 overlying the active layer 108. The active layer 108 includes a curved upper surface 108us, such that the cap structure 112 includes a protrusion in contact with the curved upper surface 108us of the active layer 108. The curved upper surface 108us of the active layer 108 is disposed below the top surface of the active layer 108.

[0027] Figure 2C Show according to Figure 2A 200a. FIG. 200B is a cross-sectional view of an image sensor 200c of some alternative embodiments to image sensor 200a.

[0028] In some embodiments, the image sensor 200c includes an oxide layer 202 disposed between a portion of the active layer 108 and the cap structure 112. In addition, the oxide layer 202 is disposed between the buffer layer 110 and the cap structure 112. In some embodiments, the oxide layer 202 may be, for example, or include an oxide of a second material (e.g., germanium oxide (e.g., GeO2)) or another material. The oxide layer 202 may extend from the top surface of the buffer layer 110 along the sidewalls of the buffer layer 110 to the curved upper surface 108us of the active layer 108.

[0029] Figure 2D Show according to Figure 2A FIG. 2 is a cross-sectional view of an image sensor 200 d of some alternative embodiments of the image sensor 200 a .

[0030] The image sensor 200d includes a cap structure 112 overlying the active layer 108. In some embodiments, the cap structure 112 includes a plurality of protrusions 112p, wherein each of the protrusions 112p overlies an edge and / or a sidewall of the active layer 108. The dielectric layer 114 extends continuously along the protrusions 112p of the cap structure 112. The protrusions 112p may directly overlie the oxide layer 202. In still other embodiments, the oxide layer 202 may be omitted (not shown).

[0031] Figure 2E Show according to Figure 2D 200e of some alternative embodiments of image sensor 200d are shown, wherein the outer sidewalls of cap structure 112 are laterally offset from the sidewalls of image sensor element 106 by one or more non-zero distances. Thus, in some embodiments, the width of cap structure 112 is greater than the width of image sensor element 106. In still other embodiments, oxide layer 202 may be omitted (not shown).

[0032] Figure 3A A cross-sectional view of some embodiments of an integrated chip 300 a is shown, which includes an interconnect structure 302 overlying a substrate 102 .

[0033] The interconnect structure 302 is disposed along the front side surface 102f of the substrate 102 and an anti-reflective coating (ARC) structure 314 is disposed along the back side surface 102b of the substrate 102. In some embodiments, the substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, crystalline silicon, P-type doped silicon, or another suitable material. Thus, the substrate 102 may include a first material, such as, for example, silicon. The interconnect structure 302 includes a dielectric structure 116, a conductive contact 303, a plurality of vias 306, and a plurality of conductive wires 304. In some embodiments, the interconnect structure 302 may be, for example, or include silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, another material, or any combination of the foregoing materials. In some further embodiments, the conductive contact 303, the plurality of vias 306 and / or the plurality of conductive wires 304 may be, for example, respectively or include aluminum, copper, ruthenium, tungsten, titanium nitride, tantalum nitride, another suitable material, or any combination of the foregoing materials. The interconnect structure 302 is configured to electrically couple the doped regions and / or semiconductor devices disposed within the integrated chip 300a to each other. In addition, the dielectric layer 114 is disposed between the substrate 102 and the dielectric structure 116. In some embodiments, the dielectric layer 114 may be, for example, or include an oxide (e.g., silicon dioxide), another suitable material, or any combination of the foregoing materials.

[0034] An image sensor element 106 is disposed within the substrate 102 and includes an active layer 108 and a buffer layer 110. The buffer layer 110 is disposed between the active layer 108 and the substrate 102. The image sensor element 106 is configured, for example, to generate an electrical signal from infrared (IR) radiation (e.g., electromagnetic radiation having a wavelength in the range of about 700 nanometers (nm) to about 2,500 nm). It should be understood that the image sensor element 106 is configured to generate an electrical signal from other frequency wavelength values. In some embodiments, the active layer 108 may be or include a second material (e.g., germanium), or another suitable material. In yet other embodiments, the buffer layer 110 is composed of a first material (e.g., silicon) and a second material (e.g., germanium) such that the concentration of the first material decreases continuously from the inner surface of the substrate 102 to the outer surface of the active layer 108 and the concentration of the second material increases continuously from the inner surface of the substrate 102 to the outer surface of the active layer 108.

[0035] A first isolation structure 104 is disposed in the substrate 102 and surrounds the image sensor element 106 in the lateral direction. The first isolation structure 104 extends from the front side surface 102f of the substrate 102 to a point below the front side surface 102f of the substrate 102. The first isolation structure 104 is configured to electrically isolate the image sensor element 106 from other devices disposed on and / or in the substrate 102. In some embodiments, the first isolation structure 104 is configured as a shallow trench isolation (STI) structure or another suitable isolation structure. In yet other embodiments, the first isolation structure 104 may be, for example, or include an oxide (e.g., silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide), another dielectric material, or any combination of the foregoing materials.

[0036] In addition, a cap structure 112 is overlaid on the front side surface 102f of the substrate 102 and is disposed between the image sensor element 106 and the dielectric layer 114. The outer sidewalls of the image sensor element 106 are laterally spaced apart between the sidewalls of the cap structure 112. Therefore, the cap structure 112 extends continuously over the top surface of the active layer 108 and the buffer layer 110. In some embodiments, the cap structure 112 may be, for example, or include a first material (e.g., silicon), epitaxial silicon, amorphous silicon, crystalline silicon, a high dielectric constant dielectric material (e.g., aluminum oxide, hafnium oxide), another suitable material, or any combination of the foregoing materials. The cap structure 112 is configured to protect the active layer 108 from one or more etchants used during the manufacture of the integrated chip 300a, thereby increasing the reliability, durability, and performance of the image sensor element 106. In addition, a silicide layer 301 is disposed within the cap structure 112. The silicide layer 301 is configured to electrically couple the conductive contact 303 to a photodetector region and / or layer (not shown) disposed within the active layer 108. In some embodiments, the silicide layer 301 may be or include, for example, nickel silicide, titanium silicide, another material, or any combination of the foregoing materials. In still other embodiments, the thickness of the silicide layer 301 may be equal to the thickness of the cap structure 112.

[0037] The second isolation structure 308 extends from the backside surface 102b of the substrate 102 to a point above the backside surface 102b of the substrate 102. In some embodiments, the top surface of the second isolation structure 308 may contact the bottom surface of the first isolation structure 104. The second isolation structure 308 surrounds the image sensor element 106 in the lateral direction and is configured to electrically isolate the image sensor element 106 from other devices disposed in and / or on the substrate 102. In some embodiments, the second isolation structure 308 is configured as a deep trench isolation (DTI) structure or another suitable isolation structure. The second isolation structure 308 includes a passivation layer 310 and a trench layer 312. In some embodiments, the passivation layer 310 may be, for example, or include a dielectric material (e.g., silicon dioxide, silicon oxynitride, silicon oxycarbide), another material, or any combination of the foregoing materials. In addition, the passivation layer 310 may extend continuously along the backside surface 102b of the substrate 102. The passivation layer 310 is disposed between the substrate 102 and the trench layer 312. In some embodiments, trench layer 312 may be, for example, or include aluminum, tungsten, copper, another material, or any combination of the foregoing materials. In yet other embodiments, second isolation structure 308 may be configured to direct electromagnetic radiation 120 toward image sensor element 106. In such embodiments, electromagnetic radiation 120 may be reflected from the sidewalls of trench layer 312 toward image sensor element 106, rather than electromagnetic radiation 120 traveling to an adjacent image sensor element (not shown). In such embodiments, second isolation structure 308 may reduce crosstalk between adjacent image sensor elements, thereby improving the performance of integrated chip 300a.

[0038] ARC structure 314 is disposed along backside surface 102b of substrate 102 and is configured to reduce reflection of electromagnetic radiation 120 away from substrate 102, thereby improving performance of integrated chip 300a. Grid structure 316 is located below ARC structure 314. Grid structure 316 may, for example, include a metal grid structure and / or a dielectric grid structure. Grid structure 316 is configured to direct electromagnetic radiation 120 to image sensor element 106. In some embodiments, when grid structure 316 includes a metal grid structure (e.g., aluminum, copper, tungsten, another material, or any combination of the foregoing materials), electromagnetic radiation 120 may be reflected from the sidewalls of the metal grid structure to image sensor element 106 instead of traveling to an adjacent image sensor element (not shown). In such an embodiment, grid structure 316 may reduce crosstalk between adjacent image sensor elements, thereby improving performance of integrated chip 300a.

[0039] In addition, a filter 318 (e.g., a color filter, an IR filter, etc.) is located below the ARC structure 314 and is laterally disposed between the sidewalls of the grid structure 316. The filter 318 is configured to transmit incident radiation of a specific wavelength. For example, the filter 318 may transmit radiation having a wavelength in a first range while blocking radiation having a wavelength in a second range different from the first range. Furthermore, a microlens 320 is disposed below the filter 318 and the grid structure 316. The microlens 320 is configured to focus the electromagnetic radiation 120 toward the substrate 102, thereby increasing the QE of the image sensor element 106.

[0040] Figure 3B Shown with Figure 3A Some alternative embodiments of the integrated chip 300a are cross-sectional views of some embodiments of the integrated chip 300b corresponding thereto.

[0041] The substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, P-type doped silicon, N-type doped silicon, or another suitable material. In some embodiments, the substrate 102 is lightly doped with a dopant of a first conductivity type (e.g., p-type). In various embodiments, the image sensor element 106 is configured as a single photon avalanche diode (SPAD) that can detect incident radiation (e.g., a single photon) with very low intensity. In some further embodiments, the image sensor element 106 may be used, for example, in IR direct-timeofflight (D-TOF) applications. In some embodiments, the active layer 108 is lightly doped with a dopant of a first conductivity type (e.g., p-type). In some further embodiments, the active layer 108 includes a first deep well 326 of a first conductivity type and a first heavily doped region 324 of a second conductivity type (e.g., n-type) opposite to the first conductivity type. The first deep well 326 is disposed below the first heavily doped region 324. A multiplication junction region is formed at the interface between the first heavily doped region 324 and the first deep well 326. In some embodiments, the first deep well 326 is vertically spaced apart from the first heavily doped region 324 (not shown) so that the multiplication junction region is formed at the interface between the first heavily doped region 324 and the active layer 108.

[0042] In some embodiments, the image sensor element 106 further includes a second deep well 322 heavily doped with a dopant of the first conductivity type. The second deep well 322 extends from the front side surface 102f of the substrate 102 to a point below the first heavily doped region 324. The second deep well 322 can be configured as a guard ring to prevent premature edge breakdown of the image sensor element 106 in a SPAD configuration. In addition, a buffer layer 110 is disposed between the active layer 108 and the substrate 102. The buffer layer 110 can include the same dopant and doping concentration as the active layer 108. In some embodiments, the buffer layer 110 can be omitted so that the active layer 108 directly contacts the substrate 102 (not shown). In some embodiments, the dopant of the first conductivity type is P-type (e.g., boron, some other suitable P-type dopant, or any combination of the foregoing materials), and the dopant of the second conductivity type is N-type (e.g., arsenic, phosphorus, some other suitable N-type dopant, or any combination of the foregoing materials), or vice versa.

[0043] In some embodiments, during operation in the SPAD configuration, the image sensor element 106 is reverse biased to exceed its own breakdown voltage, and incident photons (e.g., wavelengths in the IR radiation range) strike the image sensor element 106 to generate charge carriers. The charge carriers generated by the photons move to the multiplication region and trigger an avalanche current, which amplifies the signals generated by the photons to make them more easily detectable. In some embodiments, the doping type and / or concentration of the first deep well 326 can be configured to adjust the breakdown voltage of the image sensor element 106 in the SPAD configuration. A plurality of conductive contacts 303 are directly overlying the image sensor element 106, and the plurality of conductive contacts 303 are electrically coupled to doped regions within the active layer 108 to facilitate reading out the signals generated by the photons. In addition, a plurality of silicide layers 301 are disposed within the cap structure 112 between the active layer 108 and the plurality of conductive contacts 303. The silicide layer 301 is configured to facilitate electrical connection between the doped regions within the active layer 108 and the conductive contacts 303 .

[0044] Figures 4 to 14 Cross-sectional views 400 to 1400 illustrate some embodiments of a first method of forming an integrated chip having a cap structure extending continuously over the outer edge of an image sensor element according to the present disclosure. Figures 4 to 14 The cross-sectional views 400 to 1400 shown are described with reference to the first method, but it should be understood that Figures 4 to 14 The structure shown is not limited to the first method, but can be independently independent of the first method. Figures 4 to 14It is described as a series of actions, but it should be understood that these actions are not limited thereto, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0045] like Figure 4 As shown in the cross-sectional view 400 of , a substrate 102 is provided and a first isolation structure 104 is formed in the substrate 102. In some embodiments, the substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some further embodiments, the first isolation structure 104 may be formed by selectively etching the substrate 102 to form a trench in the substrate 102, and then filling the trench with a dielectric material (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process). In some further embodiments, the substrate 102 is selectively etched by forming a masking layer (not shown) over the front side surface 102f of the substrate 102, and then exposing the substrate 102 to one or more etchants configured to selectively remove unmasked portions of the substrate 102. In some embodiments, the dielectric material may be, for example, or include an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), another dielectric material, or any combination of the foregoing materials. In addition, an upper dielectric layer 402 is deposited on the substrate 102. The upper dielectric layer 402 may be, for example, or include silicon dioxide, undoped silicon glass (USG), another suitable material, or any combination of the foregoing materials. In yet other embodiments, the upper dielectric layer 402 may be deposited by ALD, CVD, PVD, or another suitable growth or deposition process.

[0046] like Figure 5 As shown in the cross-sectional view 500 of , a patterning process is performed on the substrate 102 to form an opening 502 in the substrate 102. In some embodiments, the patterning process includes: forming a masking layer (not shown) on the substrate 102; and exposing the substrate 102 to one or more etchants to remove the unmasked area of ​​the substrate 102 and form the opening 502. Subsequently, a removal process may be performed to remove the masking layer. In some further embodiments, the patterning process may include performing a wet etching process, a dry etching process, another suitable etching process, or any combination of the foregoing processes.

[0047] like Figure 6 As shown in the cross-sectional view 600 of FIG. 1 , a buffer layer 110 is selectively formed along the sidewalls and the lower surface of the substrate 102. In addition, an active structure 602 is selectively formed on the buffer layer 110 to fill the opening ( Figure 5 502). In some embodiments, the buffer layer 110 and / or the active structure 602 may be formed, for example, by molecular-beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), some other suitable epitaxial process, or another suitable growth or deposition process. In still other embodiments, the buffer layer 110 may serve as a seed layer for forming the active structure 602.

[0048] In some embodiments, the buffer layer 110 may be, for example, or include silicon germanium, another suitable material, or any combination of the foregoing materials. In yet other embodiments, the buffer layer 110 is composed of a first material (e.g., silicon) and a second material (e.g., germanium), such that the concentration of the first material decreases continuously from the inner surface of the substrate 102 to the outer surface of the active structure 602, and the concentration of the second material increases continuously from the inner surface of the substrate 102 to the outer surface of the active structure 602. In some embodiments, the active structure 602 may be, for example, or include the second material (e.g., germanium), another suitable material, or any combination of the foregoing materials.

[0049] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , the active structure ( Figure 6 602) performs a planarization process (eg, a chemical mechanical planarization (CMP) process) to form active layer 108 and image sensor element 106. In some embodiments, during the planarization process, active structures ( Figure 6 602) is removed faster than the upper dielectric layer 402, so that the top surface of the active layer 108 is disposed below the top surface of the upper dielectric layer 402. In addition, a planarization process can be performed so that the top surface of the active layer 108 is aligned with the front side surface 102f of the substrate 102. In addition, forming the image sensor element 106 may include performing one or more formation processes (e.g., including a selective ion implantation process, or other suitable processing steps) to define a well region, a doped region, or other suitable region and / or structure in the active layer 108. For example, the one or more formation processes may be performed to form a well region, a doped region, or other suitable region and / or structure in the active layer 108. Figure 3B The second deep well 322, the first heavily doped region 324 and / or the first deep well 326 are formed.

[0050] like Figure 8As shown in the cross-sectional view 800 of FIG. 1 , an etch-back process is performed on the upper dielectric layer 402, thereby removing a portion of the upper dielectric layer 402 from the front side surface 102f of the substrate 102. In some embodiments, the etch-back process includes performing a wet etching process and / or removing the upper dielectric layer 402 from the front side surface 102f of the substrate 102. Figure 7 The structure of the upper dielectric layer 402 is exposed to one or more etchants, and a masking layer (not shown) is formed on the upper dielectric layer 402. The one or more etchants may be, for example, or include hydrofluoric acid (HF), another etchant, or any combination of the foregoing materials. During the etch-back process, the upper dielectric layer 402 is etched at a first etch rate, the buffer layer 110 is etched at a second etch rate, and the active layer 108 is etched at a third etch rate. In some embodiments, the first etch rate is greater than the second etch rate and the third etch rate, so that during the etch-back process, the upper dielectric layer 402 is removed faster than the buffer layer 110 and / or the active layer 108. For example, the first etch rate may be about 90 angstroms / minute or another suitable value and the third etch rate may be about 1.4 angstroms / minute or another suitable value. In some further embodiments, the third etch rate may be greater than the second etch rate.

[0051] In addition, after the etch-back process, the height h1 of the active layer 108 is defined between the backside surface 102b of the substrate 102 and the top surface of the active layer 108, and the height h2 of the buffer layer 110 is defined between the backside surface 102b of the substrate 102 and the top surface of the buffer layer 110. In some embodiments, the height h1 is less than the height h2. It should be understood that in some embodiments, the height h2 may be omitted and / or skipped. Figure 8 The first method can be used from the etch-back process Figures 4 to 7 Proceed to Figures 9 to 13 (i.e., skip Figure 8 processing steps).

[0052] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a cap structure 112 is formed on the image sensor element 106 and the substrate 102. Before forming the cap structure 112, a cleaning process is performed on the substrate 102, the active layer 108, and the buffer layer 110. The cleaning process may include Figure 8The structure of the image sensor element 106 is exposed to one or more chemicals to clean (e.g., remove impurities and / or other materials) the surface of the substrate 102, the active layer 108, and the buffer layer 110. The one or more chemicals may be, for example, or include hydrofluoric acid (HF), deionized (DI) water, another suitable chemical, or any combination of the foregoing materials. The top cover structure 112 is formed so that the top cover structure 112 extends continuously along the top surface of the active layer 108 and the top surface of the buffer layer 110. In addition, the top cover structure 112 continuously covers the outer edge of the image sensor element 106 and extends over the outer edge of the image sensor element 106. In some embodiments, the top cover structure 112 is formed, for example, by CVD, PVD, ALD, MBE, VPE, LPE, some other suitable epitaxial process, or another suitable growth or deposition process. In some embodiments, the top cover structure 112 may be, for example, or include silicon, epitaxial silicon, amorphous silicon, crystalline silicon, a high dielectric constant dielectric material (e.g., aluminum oxide, hafnium oxide), another suitable material, or any combination of the foregoing materials. Subsequently, a removal process is performed to remove the upper dielectric layer 402 (not shown).

[0053] like Fig.10 As shown in the cross-sectional view 1000 of , a dielectric layer 114 is formed on the top cover structure 112 and the substrate 102. The dielectric layer 114 can be deposited, for example, by CVD, ALD, PVD, or another suitable growth or deposition process. In some embodiments, the dielectric layer 114 can be, for example, or include an oxide (e.g., silicon dioxide), another suitable material, or any combination of the foregoing materials. Subsequently, a thinning process is performed on the back side surface 102b of the substrate 102 to reduce the initial thickness Ti of the substrate 102 to a thickness Ts. The thickness Ts is defined between the front side surface 102f of the substrate 102 and the back side surface 102b of the substrate 102. In some embodiments, the thinning process may include performing a mechanical grinding process, a CMP process, another suitable thinning process, or any combination of the foregoing processes.

[0054] like Fig.11As shown in the cross-sectional view 1100 of , a patterning process is performed on the dielectric layer 114 to define an opening 1102. In some embodiments, the patterning process may include: exposing the dielectric layer 114 to one or more etchants according to a photomask (not shown) and / or a masking layer (not shown) to form the opening 1102. The opening 1102 may expose the upper surface of the cap structure 112. Subsequently, a silicide layer 301 is formed in the cap structure 112 and the silicide layer 301 directly overlies the active layer 108. In some embodiments, the silicide layer 301 directly overlies the doped region (not shown) of the active layer 108 and is electrically coupled to the doped region. In some other embodiments, the silicide layer 301 may be, for example, or include nickel silicide, cobalt silicide, titanium silicide, another suitable material, or any combination of the foregoing materials.

[0055] In some further embodiments, the process of forming the silicide layer 301 includes: depositing (e.g., by sputtering, electroless plating, electroplating, PVD, CVD, or another suitable growth or deposition process) a conductive layer (e.g., containing nickel, titanium, cobalt, or another conductive material) on the cap structure 112 to fill the opening 1102; performing a rapid thermal annealing on the conductive layer to form the silicide layer 301 in the cap structure 112; and performing a removal process (e.g., a wet etching process) to remove materials that are not converted into the silicide layer 301 from the conductive layer. The removal process includes ... on the cap structure 112 to fill the opening 1102. Fig.11 The structure of the image sensor element 106 is exposed to one or more reactive etchants (e.g., hydrogen peroxide (e.g., H2O2)). In some embodiments, if the one or more reactive etchants contact the second material (e.g., germanium) of the active layer 108, they may form a compound of the second material and the reactive etchant. The compound may tend to diffuse from the active layer 108 to adjacent structures and / or layers. In such embodiments, the diffusion of the compound may cause voids to form within the active layer 108, thereby reducing the structural integrity and / or performance of the image sensor element 106. The compound may, for example, be or include germanium oxide (GeO2), H2GeO3, another chemical compound, or any combination of the foregoing compounds. Since the cap structure 112 continuously extends over and covers the outer edge of the active layer 108 and the outer edge of the buffer layer 110, the one or more reactive etchants may not reach the active layer 108 and / or react with the active layer 108 during the removal process. This, in turn, mitigates the formation of voids within active layer 108 , thereby increasing the durability, reliability, and overall performance of image sensor element 106 .

[0056] It should be understood that one or more additional silicide layers (not shown) may be formed within the substrate 102, such that the cap structure 112 is configured to protect the active layer 108 during the formation of the one or more additional silicide layers. In still other embodiments, forming the silicide layer 301 within the cap structure 112 may be omitted.

[0057] like Fig.12 As shown in the cross-sectional view 1200 of , an interconnect structure 302 is formed on the front side surface 102f of the substrate 102. The interconnect structure includes a dielectric structure 116, a conductive contact 303, a plurality of conductive wires 304, and a plurality of vias 306. In some embodiments, the dielectric structure 116 may be, for example, or include an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a low-k dielectric material, another suitable dielectric material, or any combination of the foregoing materials. The dielectric structure 116 may be formed by one or more deposition processes (e.g., CVD, PVD, ALD, or another suitable deposition or growth process). The conductive contact 303, the plurality of conductive wires 304, and / or the plurality of vias 306 may be formed, for example, by a single damascene process, a dual damascene process, or another suitable formation process. In some embodiments, the conductive contact 303, the plurality of conductive wires 304 and / or the plurality of vias 306 may be or include aluminum, copper, titanium nitride, tantalum nitride, ruthenium, another conductive material, or any combination of the foregoing materials, for example. In still other embodiments, the conductive contact 303 overlies the silicide layer 301 and is electrically coupled to the image sensor element 106 through the silicide layer 301.

[0058] like Fig.13 As shown in the cross-sectional view 1300, Fig.12The structure of is flipped and a second isolation structure 308 is formed into the backside surface 102b of the substrate 102. In various embodiments, the second isolation structure 308 may be configured as a deep trench isolation (DTI) structure and / or may include a passivation layer 310 and a trench layer 312. In some embodiments, the process of forming the second isolation structure 308 includes: patterning the backside surface 102b of the substrate 102 to form a DTI opening (not shown) extending into the backside surface 102b of the substrate; depositing (e.g., by CVD, PVD, ALD, or another suitable deposition or growth process) a passivation layer 310 on the substrate 102 to line the DTI opening; depositing (e.g., by CVD, PVD, electroless plating, sputtering, electroplating, or another suitable deposition or growth process) a trench material (e.g., aluminum, tungsten, copper, another material, or any combination of the foregoing materials) on the backside surface 102b of the substrate to fill the DTI opening; and performing a planarization process in the trench material to form a trench layer 312 and the second isolation structure 308. In some embodiments, the passivation layer 310 may be, for example, or include a dielectric material, such as silicon dioxide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing materials.

[0059] like Fig.14As shown in the cross-sectional view 1400 of , an anti-reflective coating (ARC) structure 314 is formed on the backside surface 102b of the substrate 102. In some embodiments, the ARC structure 314 can be deposited, for example, by CVD, PVD, ALD, or another suitable deposition or growth process. In addition, a grid structure 316 is formed on the ARC structure 314. The grid structure 316 can include a metal grid structure and / or a dielectric grid structure. In some embodiments, the metal grid structure and / or the dielectric grid structure can be formed by, for example, CVD, PVD, ALD, sputtering, electroless plating, or another suitable deposition or growth process. In addition, after the metal grid structure and / or the dielectric grid structure are deposited, a patterning process is performed on the metal grid structure and / or the dielectric grid structure to define an opening directly overlying the image sensor element 106. Subsequently, a filter 318 (e.g., a color filter, an IR filter, etc.) is formed in the opening and on the ARC structure 314. The optical filter 318 is formed of a material that allows transmission of incident electromagnetic radiation (e.g., light) having a specific wavelength range while blocking an incident wavelength having another wavelength outside the specific range. In yet other embodiments, the optical filter 318 may be formed by CVD, PVD, ALD, sputtering, etc. and / or may be planarized (e.g., by a chemical mechanical planarization (CMP) process) after formation. In addition, a microlens 320 is formed over the optical filter 318 and the grid structure 316. In some embodiments, the microlens 320 may be formed by depositing (e.g., by CVD, PVD, etc.) a lens material on the optical filter 318. A lens template (not shown) having a curved upper surface is patterned over the lens material. The microlens 320 is then formed by selectively etching the lens material according to the lens template.

[0060] Figures 15 to 17B Cross-sectional views 1500 through 1700b illustrate some embodiments of a second method of forming an integrated chip having a cap structure extending continuously over the outer edge of an image sensor element according to the present disclosure. Figures 15 to 17B The cross-sectional views 1500 to 1700b are described with reference to the second method, but it should be understood that Figures 15 to 17B The structure shown is not limited to the second method, but can be independently independent of the second method. Figures 15 to 17B It is described as a series of actions, but it should be understood that these actions are not limited thereto, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0061] Figures 15 to 17B The second method can be shown Figures 4 to 14 Some alternative embodiments of the first method. For example, Figures 15 to 17B Shows alternative Figure 8 to Figure 9 The cross-sectional views 1500 to 1700b of some embodiments of the actions performed by the actions at the Figures 4 to 16 The first method can be alternatively Figures 4 to 7 Go to Figures 15 to 17B And then from Fig.17A or Fig. 17B Go to Figure 10 to Figure 14 (jump over Figure 8 to Figure 9 ).

[0062] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , an oxide layer 202 may be formed along the upper surface 108us of the active layer 108. In some embodiments, the upper surface 108us may be curved and may be used as Figure 7 In some other embodiments, the oxide layer 202 may extend from the top surface of the buffer layer 110 along the sidewalls of the buffer layer 110 to the upper surface 108us of the active layer 108. In some embodiments, the oxide layer 202 may be or include, for example, an oxide of a second material (e.g., germanium oxide (e.g., GeO2)), or another material.

[0063] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a removal process is performed to remove the oxide layer ( Fig.15 202). In some embodiments, the removal process includes removing Fig.15 The structure is exposed to a layer configured to remove the oxide layer ( Fig.15 In some other embodiments, the removal process may include using one or more etchants (e.g., H2O2) configured to remove the oxide layer ( Fig.15 202) of chemical substances (e.g., hydrogen (H2)) Fig.15 Therefore, the removal process is configured to remove the oxide layer ( Fig.15 202).

[0064] like Fig.17A As shown in the cross-sectional view 1700a of FIG. 17 , a cap structure 112 is formed on the active layer 108 and the substrate 102. The cap structure 112 is formed so that the cap structure 112 extends continuously along the top surface of the active layer 108 and covers the outer edge of the active layer 108. In some embodiments, the cap structure 112 is formed, for example, by CVD, PVD, ALD, MBE, VPE, LPE, some other suitable epitaxial process, or another suitable growth or deposition process. Subsequently, a removal process may be performed to remove the upper dielectric layer 402 (not shown).

[0065] Fig. 17B Show Fig.17A Cross-sectional views 1700b of some alternative embodiments of the processing steps of cross-sectional view 1700a are shown. Fig. 17B As shown in the cross-sectional view 1700b of , the cap structure 112 may be formed such that the cap structure 112 includes a protrusion 112p directly overlying the outer edge of the active layer 108. For example, the cap structure 112 may be formed by CVD, PVD, ALD, MBE, VPE, LPE, some other suitable epitaxial process, or another suitable growth or deposition process.

[0066] Fig.18 A method 1800 of forming an image sensor including a cap structure along an image sensor element in accordance with the present disclosure is shown. Although method 1800 is shown and / or described as a series of actions or events, it should be understood that method 1800 is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0067] At act 1802, a first isolation structure is formed into a front side of a substrate, wherein the substrate comprises a first material. Figure 4 A cross-sectional view 400 corresponding to some embodiments of act 1802 is shown.

[0068] At act 1804, an image sensor element is formed in a substrate, wherein the image sensor element includes an active layer and a buffer layer, the active layer comprising a second material different from the first material. The buffer layer is disposed between the active layer and the substrate. Figures 5 to 8 Cross-sectional views 500 through 800 corresponding to some embodiments of act 1804 are shown.

[0069] At act 1806, a cap structure is formed over the image sensor element and the substrate such that the cap structure extends continuously over the top surface and outer edges of the active layer. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1806 is shown. Fig.17A and Fig. 17B Cross-sectional views 1700a and 1700b corresponding to some alternative embodiments of act 1806 are shown.

[0070] At act 1808, one or more silicide layers are formed within the substrate and / or within the cap structure. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1808 is shown.

[0071] At act 1810, an interconnect structure is formed over the front side of a substrate. Fig.12 Cross-sectional view 1200 corresponding to some embodiments of act 1810 is shown.

[0072] At act 1812, an antireflective coating (ARC) structure is formed over the backside of the substrate. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1812 is shown.

[0073] At act 1814, a filter is formed over the ARC structure and a microlens is formed over the filter. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1814 is shown.

[0074] Therefore, in some embodiments, the present disclosure is directed to an image sensor element disposed within a substrate, wherein the image sensor element includes an active layer and a cap structure extending continuously over a top surface of the active layer and overlying an outer edge of the active layer.

[0075] In some embodiments, the present application provides an image sensor, comprising: a substrate comprising a first material; an image sensor element disposed in the substrate, wherein the image sensor element comprises an active layer, and the active layer comprises a second material different from the first material; a buffer layer disposed between the active layer and the substrate, wherein the buffer layer extends along the outer side wall and bottom surface of the active layer; and a top cover structure overlying the active layer, wherein the outer side wall of the active layer is laterally spaced apart between the outer side walls of the top cover structure so that the top cover structure extends continuously over the outer edge of the active layer.

[0076] In some other embodiments, in the image sensor, the maximum width of the top cover structure is greater than the maximum width of the active layer.

[0077] In some other embodiments, in the image sensor, the top cover structure includes the first material.

[0078] In some other embodiments, in the image sensor, the first material is silicon and the second material is germanium.

[0079] In some other embodiments, in the image sensor, the width of the active layer decreases continuously in a direction extending from a bottom surface of the cap structure to a bottom surface of the buffer layer.

[0080] In some other embodiments, the image sensor further includes: a dielectric layer disposed on the top cover structure and the substrate, wherein the dielectric layer continuously extends from the top surface of the substrate along the side wall of the top cover structure to the top surface of the top cover structure.

[0081] In some other embodiments, in the image sensor, the top cover structure includes a protrusion extending below the top surface of the active layer and contacting an upper surface of the active layer, wherein the upper surface of the active layer is curved.

[0082] In some other embodiments, the image sensor further includes: a silicide layer disposed in the top cover structure, wherein the silicide layer includes silicide of the first material and a conductive material, wherein the silicide layer directly overlies the active layer and is electrically coupled to the active layer.

[0083] In some other embodiments, the image sensor further includes: an interconnect structure overlying the substrate, wherein the interconnect structure includes a conductive contact, the conductive contact directly overlying the top cover structure and electrically coupled to the active layer through the silicide layer. In some embodiments, the present application provides an integrated chip, the integrated chip including: a substrate including a first material, wherein the substrate includes opposite sidewalls and a lower surface, the opposite sidewalls and the lower surface defining a groove, the groove extending into the front side surface of the substrate; an active layer disposed in the groove, wherein the active layer includes a second material different from the first material; a buffer layer lining the groove so that the buffer layer is disposed between the substrate and the groove, wherein the buffer layer includes a compound of the first material and the second material; a top cover structure extending continuously over the active layer and the buffer layer, wherein the top cover structure directly overlies the opposite sidewalls of the substrate defining the groove, wherein the top cover structure includes the first material; and a silicide layer disposed in the top cover structure.

[0084] In some other embodiments, the integrated chip further includes: an internal connection structure overlying the front surface of the substrate, wherein the internal connection structure includes a plurality of conductive vias and a plurality of conductive wirings arranged in a dielectric structure, wherein the conductive vias and the conductive wirings are electrically coupled to the active layer through the silicide layer.

[0085] In some other embodiments, in the integrated chip, a doped region is provided in the active layer, wherein the silicide layer directly overlies the doped region and is electrically coupled to the doped region.

[0086] In some other embodiments, in the integrated chip, the substrate comprises a crystalline form of the first material and the cap structure comprises an amorphous form of the first material.

[0087] In some other embodiments, in the integrated chip, the top surface of the active layer is located below the top surface of the buffer layer in the vertical direction, and the top surface of the buffer layer is located below the front side surface of the substrate in the vertical direction.

[0088] In some other embodiments, in the integrated chip, the cap structure continuously extends from the front side surface of the substrate along the top surface of the buffer layer to the top surface of the active layer.

[0089] In some other embodiments, the integrated chip further includes: an oxide layer disposed between the top cover structure and the active layer, wherein the oxide layer contains an oxide of the second material.

[0090] In some embodiments, the present application provides a method for forming an image sensor, the method comprising: forming a dielectric layer along a surface of a substrate, wherein the substrate comprises a first material; etching the dielectric layer and the substrate to define a groove in the substrate; forming a buffer layer in the groove so that the dielectric layer contacts the buffer layer; forming an active layer in the groove, wherein the active layer comprises a second material different from the first material; and forming a top cover structure on the active layer so that the top cover structure extends continuously along the top surface of the active layer, wherein the top cover structure comprises the first material and wherein the top cover structure directly overlies the uppermost edge of the active layer.

[0091] In some other embodiments, the method further includes: performing an etch-back process on the dielectric layer so that the dielectric layer is laterally offset from the buffer layer by a non-zero distance, wherein the dielectric layer is etched faster than the active layer during the etch-back process.

[0092] In some other embodiments, in the method described, the top cover structure, the active layer and the buffer layer are respectively formed by epitaxial processes.

[0093] In some other embodiments, the method further includes: forming a silicide layer in the cap structure so that the silicide layer directly overlies the active layer, wherein the silicide layer includes a compound of the first material and a conductive material.

[0094] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: a substrate comprising a first material; an image sensor element disposed within the substrate, wherein the image sensor element includes an active layer comprising a second material different from the first material; a buffer layer, disposed between the active layer and the substrate, wherein the buffer layer extends along an outer sidewall and a bottom surface of the active layer; as well as a cap structure overlying the active layer, wherein the outer sidewalls of the active layer are laterally spaced apart between the outer sidewalls of the cap structure such that the cap structure extends continuously over the outer edges of the active layer; as well as A silicide layer is disposed in the cap structure and electrically coupled to the active layer. 2 . The image sensor according to claim 1 , wherein a maximum width of the cap structure is greater than a maximum width of the active layer. The image sensor of claim 1 , wherein the cap structure comprises the first material. 4 . The image sensor of claim 1 , wherein the first material is silicon and the second material is germanium. 5 . The image sensor according to claim 1 , wherein a width of the active layer continuously decreases in a direction extending from a bottom surface of the cap structure to a bottom surface of the buffer layer.

6. The image sensor according to claim 1, further comprising: A dielectric layer is disposed on the top cover structure and the substrate, wherein the dielectric layer continuously extends from the top surface of the substrate along the sidewall of the top cover structure to the top surface of the top cover structure. 7 . The image sensor of claim 1 , wherein the cap structure comprises a protrusion extending below a top surface of the active layer and contacting an upper surface of the active layer, wherein the upper surface of the active layer is curved.

8. The image sensor according to claim 1, wherein: The silicide layer includes silicide of the first material and a conductive material and the silicide layer directly overlies the active layer.

9. The image sensor according to claim 1, further comprising: An interconnect structure overlies the substrate, wherein the interconnect structure includes a conductive contact directly overlies the cap structure and is electrically coupled to the active layer through the silicide layer.

10. An integrated chip, comprising: a substrate comprising a first material, wherein the substrate includes opposing sidewalls and a lower surface, the opposing sidewalls and the lower surface defining a trench extending into a front side surface of the substrate; an active layer disposed in the trench, wherein the active layer comprises a second material different from the first material; a buffer layer lining the trench so that the buffer layer is disposed between the substrate and the trench, wherein the buffer layer comprises a compound of the first material and the second material; a cap structure extending continuously over the active layer and the buffer layer, wherein the cap structure overlies the opposite sidewalls of the substrate defining the trench, wherein the cap structure comprises the first material; as well as A silicide layer is disposed in the cap structure and electrically coupled to the active layer.

11. The integrated chip according to claim 10, further comprising: An internal connection structure is overlying the front surface of the substrate, wherein the internal connection structure includes a plurality of via holes and a plurality of conductive wirings arranged in a dielectric structure, wherein the via holes and the conductive wirings are electrically coupled to the active layer through the silicide layer. 12 . The integrated chip according to claim 10 , wherein a doped region is disposed in the active layer, wherein the silicide layer directly overlies the doped region and is electrically coupled to the doped region.

13. The integrated chip of claim 10, wherein the substrate comprises a crystalline form of the first material and the cap structure comprises an amorphous form of the first material. 14 . The integrated chip according to claim 10 , wherein a top surface of the active layer is located below a top surface of the buffer layer in a vertical direction, and the top surface of the buffer layer is located below the front side surface of the substrate in a vertical direction. 15 . The integrated chip according to claim 10 , wherein the cap structure continuously extends from the front side surface of the substrate along a top surface of the buffer layer to a top surface of the active layer.

16. The integrated chip according to claim 10, further comprising: An oxide layer is disposed between the cap structure and the active layer, wherein the oxide layer comprises an oxide of the second material.

17. A method of forming an image sensor, comprising: forming a dielectric layer along a surface of a substrate, wherein the substrate comprises a first material; etching the dielectric layer and the substrate to define a trench in the substrate; forming a buffer layer in the trench so that the dielectric layer contacts the buffer layer; forming an active layer in the trench, wherein the active layer comprises a second material different from the first material; forming a cap structure over the active layer so that the cap structure extends continuously along a top surface of the active layer, wherein the cap structure comprises the first material, and wherein the cap structure overlies an uppermost edge of the active layer; as well as A silicide layer is formed within the cap structure such that the silicide layer is electrically coupled to the active layer.

18. The method according to claim 17, further comprising: An etch-back process is performed on the dielectric layer such that the dielectric layer is laterally offset from the buffer layer by a non-zero distance, wherein the dielectric layer is etched faster than the active layer during the etch-back process. 19 . The method according to claim 17 , wherein the cap structure, the active layer and the buffer layer are formed by epitaxial processes respectively.

20. The method of claim 17, wherein: Forming the silicide layer includes forming the silicide layer directly overlying the active layer, wherein the silicide layer includes a compound of the first material and a conductive material.

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