Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a structure includes: a contact etch stop layer (CESL) on a substrate; a fin extending through the CESL; an epitaxial source / drain region in the fin, the epitaxial source / drain region extending through the CESL; a silicide contacting an upper facet of the epitaxial source / drain region; a source / drain contact contacting the silicide, a lower facet of the epitaxial source / drain region, and a first surface of the CESL; and an interlayer dielectric (ILD) layer surrounding the source / drain contact, the ILD layer contacting the first surface of the CESL.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: etching a source / drain recess in a fin, the source / drain recess extending through a contact etch stop layer (CESL); growing an epitaxial source / drain region in the source / drain recess; depositing an interlayer dielectric (ILD) layer on the epitaxial source / drain region and the CESL; etching an opening through the ILD layer using isotropic etching, the isotropic etching removing a portion of the ILD layer below the epitaxial source / drain region to expose a lower facet of the epitaxial source / drain region and the CESL; and forming a source / drain contact in the opening, the source / drain contact extending along the lower facet of the epitaxial source / drain region.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: an isolation region on a substrate; a contact etch stop layer CESL on the isolation region; a first fin extending through the CESL and the isolation region; a second fin extending through the CESL and the isolation region; an epitaxial source / drain region, in which the epitaxial source / drain region is arranged above a first portion of the CESL in the first fin and the second fin, and the first portion of the CESL is laterally arranged between the first fin and the second fin; an interlayer dielectric ILD layer on the epitaxial source / drain region and the second portion of the CESL; and a source / drain contact extending through the ILD layer, the source / drain contact contacting the second portion of the CESL and a lower facet of the epitaxial source / drain region.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a contact etch stop layer CESL on a substrate; a fin extending through the CESL; an epitaxial source / drain region, in which the epitaxial source / drain region extends through the CESL; a metal-semiconductor alloy region contacting an upper facet of the epitaxial source / drain region; a source / drain contact contacting the metal-semiconductor alloy region, a lower facet of the epitaxial source / drain region, and a first surface of the CESL; and an interlayer dielectric ILD layer surrounding the source / drain contact, the ILD layer contacting the first surface of the CESL. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 is a three-dimensional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A and Fig. 15B is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments.

[0011] Fig.16A and Fig. 16B is a cross-sectional view of a FinFET according to some other embodiments.

[0012] Fig.17A and Fig. 17B is a cross-sectional view of a FinFET according to some other embodiments.

[0013] Fig.18A and Fig.18B is a cross-sectional view of a FinFET according to some other embodiments.

[0014] Fig.19 is a cross-sectional view of a FinFET according to some other embodiments.

[0015] Fig. 20 is a cross-sectional view of a FinFET according to some other embodiments.

[0016] Fig.21A and Fig. 21B is a cross-sectional view of a FinFET according to some other embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0019] According to some embodiments, a contact etch stop layer (CESL) is formed before forming the epitaxial source / drain regions of the FinFET. For example, the CESL can be deposited before forming the fins of the FinFET in a fin-last process. Since the epitaxial source / drain regions are formed after the CESL, the CESL is located below the faceted surface of the epitaxial source / drain regions. During the subsequent contact formation process, the upper (one or more) interlayer dielectric (ILD) layers can be overetched to form contact openings without damaging the underlying shallow trench isolation (STI) regions. Overetching the ILD layer during contact formation helps remove portions of the ILD layer below the epitaxial source / drain regions. Removing these portions of the ILD layer allows more of the surface of the epitaxial source / drain regions to be exposed, thereby increasing the surface area available for contacts that will subsequently be formed to the epitaxial source / drain regions.

[0020] Figure 1 An example of a simplified fin field effect transistor (FinFET) according to some embodiments is shown in a three-dimensional view. For clarity of illustration, some other features of the FinFET (discussed below) are omitted. The FinFET shown can be electrically coupled in a manner that functions as, for example, one transistor or multiple transistors (such as four transistors).

[0021] The FinFET includes a fin 62 extending from a substrate 50. STI regions 64 are arranged above the substrate 50, and the fin 62 protrudes from above and between adjacent STI regions 64. Although the STI regions 64 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to a semiconductor substrate alone or to a semiconductor substrate including an isolation region. In addition, although the fin 62 is shown as a single continuous material of the substrate 50, the fin 62 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 62 refers to a portion extending between adjacent STI regions 64.

[0022] The gate structure 90 is above the channel region of the fin 62. The gate structure 90 includes a gate dielectric 92 and a gate electrode 94. The gate dielectric 92 is along the sidewalls of the fin 62 and above its top surface, and the gate electrode 94 is above the gate dielectric 92. The source / drain region 84 is arranged on the opposite side of the fin 62 relative to the gate dielectric 92 and the gate electrode 94. The gate spacer 80 separates the source / drain region 84 from the gate structure 90. In embodiments where multiple transistors are formed, the source / drain region 84 can be shared between the respective transistors. In embodiments where one transistor is formed from multiple fins 62, adjacent source / drain regions 84 can be electrically coupled, for example by epitaxially growing the source / drain regions 84 together, or by coupling the source / drain regions 84 to the same source / drain contact. One or more inter-layer dielectric (ILD) layers (discussed further below) are over the source / drain regions 84 and / or the gate electrode 94 , through which contacts are formed to the source / drain regions 84 and the gate electrode 94 (discussed further below).

[0023] Figure 1 Several reference cross sections are further shown. Cross section AA is along the longitudinal axis of the fin 62 and in the direction of current flow, for example, between the source / drain regions 84 of the FinFET. Cross section BB is perpendicular to cross section AA and extends through the source / drain regions 84 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0024] Some embodiments discussed herein are discussed in the context of forming a FinFET using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0025] Figures 2 to 6 is a three-dimensional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. In addition to showing three gate structures, Figures 2 to 6 Shown with Figure 1 Similar 3D view.

[0026] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide); alloy semiconductors (including silicon-germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenic phosphide); or combinations thereof.

[0027] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device such as an NMOS transistor (e.g., an n-type FinFET). The region 50P can be used to form a p-type device such as a PMOS transistor (e.g., a p-type FinFET). The region 50N can be physically separated from the region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the region 50N and the region 50P.

[0028] Then, a dielectric layer 52 is formed on the substrate 50. As discussed further below, the dielectric layer 52 will be patterned to form the STI region. The dielectric layer 52 can be formed of an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof, and can be formed by chemical vapor deposition (CVD), high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it to another material (e.g., oxide)), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In an embodiment, the dielectric layer 52 is a silicon oxide layer formed by an FCVD process. Although the dielectric layer 52 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, the dielectric layer 52 includes a liner sublayer and a fill sublayer. The liner sublayer can be first formed along the top surface of the substrate 50, and the fill sublayer can be formed above the liner. In some embodiments, the liner sublayer is formed of a nitride such as silicon nitride, and the fill sublayer is formed of an oxide such as silicon oxide.

[0029] Then, CESL 54 is formed on dielectric layer 52. CESL 54 is formed of a dielectric material having a different etch rate than the material of the subsequently formed ILD layer (hereinafter referred to as FIG. 12A to FIG. 12D . For example, CESL 54 may be formed of silicon nitride, silicon oxide, silicon oxynitride, etc., and may be deposited by CVD, atomic layer deposition (ALD), etc. In an embodiment, CESL 54 is formed of silicon nitride.

[0030] Then, dielectric layer 56 is formed on CESL 54. Dielectric layer 56 may be formed of a material selected from the candidate material group of dielectric layer 52, and may be formed using a method selected from the candidate method group for forming dielectric layer 52. Dielectric layers 52, 56 may be formed of the same material, or may include different materials. In an embodiment, dielectric layer 56 is a silicon oxide layer formed by a FCVD process.

[0031] One or more annealing processes are performed after forming dielectric layer 52 and / or dielectric layer 56. In some embodiments, a first annealing process is performed after depositing dielectric layer 52, and a second annealing process is performed after depositing dielectric layer 56. In some embodiments, a single annealing process is performed after depositing both dielectric layers 52, 56 and CESL 54, and no annealing process is performed between depositing dielectric layer 52 and depositing dielectric layer 56. The annealing process(es) densifies dielectric layers 52, 56. Dielectric layer 56 may then be planarized. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized.

[0032] exist Figure 3 In the embodiment of the present invention, the dielectric layers 52, 56 and the CESL 54 are patterned to form trenches 58 that expose the substrate 50. The trenches 58 may be patterned using acceptable photolithography and etching techniques (e.g., using one or more etching processes). The etching may be any acceptable etching process, such as reactive ion etching (RIE), etc. The etching may be anisotropic. In some embodiments, the etching is performed using a gas that can etch both the material of the dielectric layers 52, 56 (e.g., silicon oxide) and the material of the CESL 54 (e.g., silicon nitride), such as a fluorine-containing gas, such as tetrafluoromethane (CF4), trifluoromethane (fluoroform, CHF3), fluoromethane (CH3F), octafluorocyclopentene (C5F8), octafluorocyclobutane (C4F8), combinations thereof, etc. In some embodiments, the dielectric layers 52, 56 and the CESL 54 may each be patterned by a different etching process.

[0033] exist Figure 4 , an epitaxial structure 60 is formed in the trench 58. The epitaxial structure 60 is formed of a semiconductor material. In some embodiments, the semiconductor material of the epitaxial structure 60 may include silicon; germanium; a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); an alloy semiconductor (including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenic phosphide); or a combination thereof. The epitaxial structure 60 may be formed of the same material as the substrate 50, or may include a different material from the substrate 50.

[0034] The epitaxial structure 60 is formed by an epitaxial growth process. For example, a homoepitaxial structure can be epitaxially grown in the trench 58. In addition, in some embodiments, a heteroepitaxial structure can be used for the epitaxial structure 60. For example, the epitaxial structure 60 can be recessed, and a material different from the epitaxial structure 60 can be epitaxially grown on the recessed epitaxial structure 60. In these embodiments, the final epitaxial structure 60 includes the recessed material and the epitaxially grown material arranged on the recessed material. In another embodiment, a heteroepitaxial structure can be epitaxially grown in the trench 58 using a material different from the substrate 50. In some embodiments, the epitaxially grown material can be in-situ doped during growth, which can save previous and subsequent implants, but in-situ doping and implant doping can be used together.

[0035] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of epitaxial structure 60 may be made of silicon-germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0036] exist Figure 5, dielectric layer 56 is removed. Dielectric layer 56 may be removed using an acceptable etch process, such as an etch process that is selective to the material of dielectric layer 56 (e.g., etches the material of dielectric layer 56 at a faster rate than the material of CESL 54 and epitaxial structure 60). The etch process used to remove dielectric layer 56 may be different from the etch process used to form trench 58 (e.g., performed with different etch parameters, a different etchant, and / or a different type of etch). For example, oxide removal, such as using dilute hydrofluoric acid (dHF), may be used. CESL 54 stops the oxide removal, thereby protecting dielectric layer 52. After oxide removal, the remaining portions of dielectric layer 52 form STI regions 64, and epitaxial structure 60 (see Figure 5 ) protrude from between adjacent portions of STI region 64 and adjacent portions of CESL 54 to form fin 62. Fin 62 is a semiconductor strip.

[0037] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the generation of patterns with, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. For example, spacers may be used to pattern the trench 58 in which the fin 62 is formed.

[0038] Furthermore, appropriate wells may be formed in fin 62 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0039] In embodiments with different well types, a photoresist or other mask may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 62 and STI region 64 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., and may be formed at a rate equal to or less than 10 18 cm-3 The concentration (e.g., at about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0040] After implanting region 50P, a photoresist is formed over fin 62 and STI region 64 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity may be boron, boron fluoride, indium, etc., and may be formed at a density equal to or less than 10 18 cm -3 The concentration (e.g., at about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0041] After implantation of regions 50N and 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the grown material of fin 62 may be in-situ doped during growth, which may eliminate implantation, but in-situ doping and implantation doping may be used together.

[0042] exist Figure 6 In the embodiment of the present invention, a dummy dielectric 70 is formed over the fin 62, and a dummy gate 72 is formed over the dummy dielectric 70. The dummy dielectric 70 and the dummy gate 72 may be collectively referred to as a “dummy gate stack”, each of which includes the dummy dielectric 70 and the dummy gate 72. The dummy gate stack extends along the sidewalls of the fin 62. The dummy dielectric 70 may contact the CESL 54, including portions 54A of the CESL 54 between the respective fins 62, and portions 54B of the CESL 54 between the groups of fins 62.

[0043] As an example of forming a dummy dielectric 70 and a dummy gate 72, a dummy dielectric layer is formed on the fin 62. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask layer is formed on the dummy gate layer. The dummy gate layer can be deposited on the dummy dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited on the dummy gate layer. The dummy gate layer can be a conductive material or a non-conductive material, and can be selected from a group including amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide and metal. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit selected materials. The dummy gate layer can be made of other materials with high etching selectivity to the etching of CESL 54. The mask layer can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer and a single mask layer are formed across regions 50N and 50P. The mask layer is then patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of mask 74 is then transferred to the dummy gate layer by an acceptable etching technique to form a dummy gate 72. The pattern of mask 74 may optionally be further transferred to a dummy dielectric layer to form a dummy dielectric 70. The dummy gate 72 covers the corresponding channel region 66 of the fin 62. The pattern of mask 74 may be used to physically separate each dummy gate in the dummy gate 72 from an adjacent dummy gate. The dummy gate 72 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding fin 62 (within process limitations). Although the dummy dielectric 70 is shown as covering the CESL 54, it should be understood that the dummy dielectric 70 may be formed in other ways. In some embodiments, for example, when the dummy dielectric layer is thermally grown, the dummy dielectric 70 is formed to cover only the fin 62.

[0044] 7A to 15B is a cross-sectional view of another intermediate stage of the fabrication of a FinFET according to some embodiments. In addition to showing three gate structures, Fig. 7A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A is along Figure 1 The cross-sectional view shown in reference section AA is shown in FIG. Except that only two fins are shown, Figure 7B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 12C, Fig.12D , Fig. 13B , Fig. 14B and Fig. 15B is along Figure 1 A cross-sectional view shown in reference section BB. 7A to 15B Features in either region 50N or region 50P are shown. For example, 7A to 15B The structure shown may apply to both region 50N and region 50P. Differences, if any, in the structure of region 50N and region 50P are described herein.

[0045] exist Fig. 7A and Figure 7B In the embodiment of the present invention, a gate spacer 80 is formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 62. The gate spacer 80 can be formed by forming an insulating material and then etching the insulating material. The insulating material of the gate spacer 80 can be silicon nitride, silicon carbonitride, silicon carbon nitride oxide, a combination thereof, etc., and can be formed by thermal oxidation, deposition, a combination thereof, etc. In some embodiments, the gate spacer 80 is formed of a multilayer insulating material and includes a plurality of layers. For example, the gate spacer 80 can include a plurality of silicon carbonitride layers, can include a plurality of silicon carbon nitride oxide layers, or can include a silicon oxide layer arranged between two silicon nitride layers. The etching of the gate spacer 80 can be anisotropic and selective to the material of the gate spacer 80 (e.g., etching the material of the gate spacer 80 at a faster rate than the material of the CESL 54). After etching, the gate spacer 80 can have straight sidewalls or curved sidewalls.

[0046] Prior to or during formation of gate spacers 80, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments having different device types, similar to the implantation discussed, a mask (e.g., photoresist) may be formed over region 50N while exposing region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into exposed fins 62 in region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over region 50P while exposing region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into exposed fins 62 in region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have a thickness of approximately 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage and activate implanted impurities.

[0047] Then, source / drain recesses 82 are formed in fin 62. Acceptable photolithography and etching techniques may be used to form source / drain recesses 82. Source / drain recesses 82 may extend into portions of fin 62 that are below the top surface of CESL 54 and optionally below the top surface of STI region 64. In this way, source / drain recesses 82 extend through CESL 54. Thus, sidewalls of CESL 54 and STI region 64 are exposed by source / drain recesses 82.

[0048] exist Fig. 8A and Figure 8B In the embodiment of the present invention, epitaxial source / drain regions 84 are formed in the source / drain recesses 82. Thus, epitaxial source / drain regions 84 are formed in the fins 62 such that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 84. Thus, the epitaxial source / drain regions 84 extend through the CESL 54 and may extend into a portion of the fin 62 below the top surface of the STI region 64. In some embodiments, the gate spacers 80 are used to separate the epitaxial source / drain regions 84 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 84 do not short-circuit a subsequently formed gate of the resulting FinFET. The epitaxial source / drain regions 84 may exert stress in the channel region 66 of the fin 62, thereby improving performance.

[0049] The epitaxial source / drain regions 84 may be formed in the region 50N (e.g., NMOS region) by masking the region 50P (e.g., PMOS region). The epitaxial source / drain regions 84 in the region 50N are then epitaxially grown in the source / drain recesses 82 in the region 50N. The epitaxial source / drain regions 84 may include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 62 is silicon, the epitaxial source / drain regions 84 in the region 50N may include a material that applies tensile strain in the channel region 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 84 in the region 50N may have surfaces that protrude from the corresponding surfaces of the fin 62 and may have facets.

[0050] The epitaxial source / drain regions 84 may be formed in the region 50P (e.g., the PMOS region) by masking the region 50N (e.g., the NMOS region). The epitaxial source / drain regions 84 in the region 50P are then epitaxially grown in the source / drain recesses 82 in the region 50P. The epitaxial source / drain regions 84 may include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 62 is silicon, the epitaxial source / drain regions 84 in the region 50P may include a material that applies compressive strain in the channel region 66, such as silicon-germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 84 in the region 50P may also have surfaces that protrude from the corresponding surfaces of the fin 62 and may have facets.

[0051] The epitaxial source / drain regions 84 and / or the fins 62 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 84 may be doped in situ during growth.

[0052] As a result of the epitaxial process used to form epitaxial source / drain regions 84, the upper surface of epitaxial source / drain regions 84 has facets 84S. U 、84S L , these facets protrude (e.g., extend laterally outward) beyond the sidewalls of fin 62. Since epitaxial source / drain regions 84 are formed after CESL 54, CESL 54 is located below the protruding portions of epitaxial source / drain regions 84 and is not located along facets 84S of epitaxial source / drain regions 84. U 、84S L Therefore, the facet 84S of the epitaxial source / drain region 84 U 、84S L There is no CESL 54. In some embodiments, facet 84S U 、84S L Adjacent epitaxial source / drain regions 84 of the same FinFET are merged, as shown. For example, when a transistor is formed from multiple fins 62, merged epitaxial source / drain regions 84 may be formed. Thus, portions 54B of CESL 54 are disposed between fins 62 of the transistor, and epitaxial source / drain regions 84 cover portions 54B of CESL 54. In other embodiments (described below with respect to Fig.17A and Fig. 17B 54 ), adjacent epitaxial source / drain regions 84 remain separated after the epitaxial process is completed. For example, when a transistor is formed from a single fin 62, unmerged epitaxial source / drain regions 84 may be formed. In the illustrated embodiment, a spacer etch used to form gate spacers 80 is used to remove spacer material to allow epitaxial source / drain regions 84 to extend to the top surface of CESL 54. In some other embodiments, gate spacers 80 are formed to cover a portion of the sidewalls of fin 62 that extend above CESL 54, thereby preventing epitaxial growth.

[0053] Note that the above disclosure generally describes the process of forming spacers, LDD regions, and source / drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, steps in different sequences may be used, spacers may be formed and removed, etc. In some embodiments, gate spacers 80 are formed after epitaxial source / drain regions 84. In addition, different structures and steps may be used to form n-type and p-type devices. In some embodiments, dummy spacers may be formed in region 50N, and source / drain grooves 82 may be formed in region 50N by dummy spacers and CESL 54. Then, epitaxial source / drain regions 84 in region 50N are grown in source / drain grooves 82. Then, dummy spacers in region 50N may be removed. Dummy spacers may be formed in region 50P, and source / drain grooves 82 may be formed in region 50P by dummy spacers and CESL 54. Then, epitaxial source / drain regions 84 in region 50P are grown in source / drain grooves 82. The dummy spacers in region 50P may then be removed. Gate spacers 80 may be formed after epitaxial source / drain regions 84 are formed in both region 50N and region 50P.

[0054] Then, a first ILD layer 86 is deposited over the epitaxial source / drain regions 84, the gate spacers 80, the mask 74 (if present) or the dummy gate 72, and the STI regions 64. The first ILD layer 86 is formed of a dielectric material having a different etch rate than the material of the CESL 54 and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride such as silicon nitride; etc. Other insulating materials formed by any acceptable process may be used. After formation, the first ILD layer 86 may be planarized, for example, by CMP. Because the epitaxial source / drain regions 84 are formed after the CESL 54, the first ILD layer 86 physically contacts the facets 84S of the epitaxial source / drain regions 84. U 、84S L , without an etch stop layer between the first ILD layer 86 and the epitaxial source / drain regions 84. In addition, the first ILD layer 86 physically contacts the portion 54A of the CESL 54, and may also be formed below the epitaxial source / drain regions 84 to physically contact the portion 54B of the CESL 54.

[0055] exist Fig. 9A and Fig. 9B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD layer 86 flush with the top surface of the mask 74 (if present) or the dummy gate 72. The planarization process may remove the mask 74 on the dummy gate 72, and the portion of the gate spacer 80 along the sidewall of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate spacer 80, and the first ILD layer 86 are coplanar. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD layer 86. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD layer 86 flush with the top surface of the mask 74.

[0056] exist Fig. 10A and Fig. 10BIn the embodiment of the present invention, the dummy gate 72 and the optional dummy dielectric layer 70 are removed and replaced by the gate structure 90. The gate structure 90 includes a gate dielectric 92 and a gate electrode 94. As an example of forming the gate structure 90, the dummy gate 72 and the mask 74 (if present) are removed in one or more etching steps to form a groove. The portion of the dummy dielectric 70 in the groove may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric 70 is retained and exposed by the groove. In some embodiments, the dummy dielectric 70 is removed from the groove in the first area of ​​the die (e.g., the core logic area) and retained in the groove in the second area of ​​the die (e.g., the input / output area). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etch the dummy gate 72 without etching the first ILD layer 86 or the gate spacer 80. Each groove exposes and / or covers the channel region 66 of the corresponding fin 62. Each channel region 66 is arranged between adjacent pairs of epitaxial source / drain regions 84. During removal, when etching the dummy gate 72, the dummy dielectric 70 can be used as an etch stop layer. Then, after removing the dummy gate 72, the dummy dielectric 70 can be optionally removed. After removal, the gate dielectric 92 is conformally deposited in the groove, for example, on the top surface and sidewalls of the fin 62 and on the sidewalls of the gate spacer 80. The gate dielectric 92 can also be formed on the top surface of the first ILD layer 86. According to some embodiments, the gate dielectric 92 includes silicon oxide, silicon nitride or a multilayer thereof. In some embodiments, the gate dielectric 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric 92 can have a k value greater than about 7.0, and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and combinations thereof. The formation method of the gate dielectric 92 can include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In an embodiment where a portion of the dummy dielectric 70 remains in the recess, the gate dielectric 92 includes the material of the dummy dielectric 70 (e.g., silicon oxide). The gate electrodes 94 are deposited on the gate dielectrics 92, respectively, and fill the remaining portions of the recesses. The gate electrodes 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 94 is shown, each gate electrode 94 may include any number of liner layers, any number of work function adjustment layers, and fill materials. After filling the gate electrodes 94, a planarization process such as CMP may be performed to remove the material of the gate electrodes 94 and excess portions of the gate dielectric 92 that are above the top surface of the first ILD layer 86.The material of gate electrode 94 and the remainder of gate dielectric 92 form a gate structure 90 of the resulting FinFET. Gate structure 90 may also be referred to as a “gate stack” or a “metal gate.” Gate structure 90 may extend along the sidewalls of channel region 66 of fin 62 .

[0057] The formation of gate structures 90 in regions 50N and 50P may occur simultaneously, such that gate dielectrics 92 in each region are formed of the same material, and gate electrodes 94 in each region are formed of the same material. In some embodiments, gate structures 90 in each region may be formed by different processes, such that gate dielectrics 92 in each region may be different materials, and / or gate electrodes 94 in each region may be different materials. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0058] exist Fig.11A and Fig. 11B In the embodiment of the present invention, the second ILD layer 100 is deposited on the first ILD layer 86. The second ILD layer 100 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride, such as silicon nitride, etc. After formation, the second ILD layer 100 may be planarized, for example, by CMP. In some embodiments, an etch stop layer is formed between the first ILD layer 86 and the second ILD layer 100. The etch stop layer may include a dielectric material having an etch rate different from the etch rate of the material of the second ILD layer 100, such as silicon nitride, silicon oxide, silicon oxynitride, etc. In some embodiments, before forming the second ILD layer 100 , a gate mask may be formed over the gate dielectric 92 and the gate electrode 94 , which may protect the gate dielectric 92 and the gate electrode 94 during contact formation.

[0059] exist Fig. 12A and Fig. 12B , source / drain contact openings 102 are formed through the ILD layers 86, 100. Acceptable photolithography and etching techniques may be used to form the source / drain contact openings 102. The etching is selective to the material of the ILD layers 86, 100 (e.g., the material of the ILD layers 86, 100 is etched at a faster rate than the material of the CESL 54). The CESL 54 stops etching of the source / drain contact openings 102. Because the CESL 54 is located below the protruding portion of the epitaxial source / drain regions 84, the facets 84S of the epitaxial source / drain regions 84 are U、84S L The STI regions 64 may be exposed by aggressively etching (e.g., overetching) the ILD layers 86, 100 without damaging them. Specifically, the first ILD layer 86 may be etched until the source / drain contact openings 102 extend completely through the first ILD layer 86 and expose all facets 84S of the CESL 54 and the epitaxial source / drain regions 84 above the CESL 54. U 、84S L All facets 84S of the epitaxial source / drain region 84 are exposed. U 、84S L The available surface area for subsequently formed contacts to the epitaxial source / drain regions 84 is increased.

[0060] The etching process for forming the source / drain contact openings 102 may include wet etching, dry etching, or a combination thereof. Specifically, the etching process includes multiple etching steps, wherein at least one step has a greater degree of isotropy than the other steps. For example, the etching process for forming the source / drain contact openings 102 may include a first etch followed by a second etch, wherein the second etch has a greater degree of isotropy than the first etch, and wherein both etches are selective to the material of the ILD layers 86, 100. Performing the isotropic etching steps helps remove the portion of the first ILD layer 86 below the epitaxial source / drain region 84, thereby exposing the lower facet 84S of the epitaxial source / drain region 84. L After etching, the lower facet 84S of the epitaxial source / drain region 84 L There is no CESL54. Fig. 12C and Fig.12D is a cross-sectional view of an intermediate stage in etching source / drain contact openings 102 in accordance with some embodiments. Fig. 12C and 12D The figure shows the Fig. 12B Similar cross section.

[0061] exist Fig. 12C In the embodiment, an anisotropic etch is performed to initially form source / drain contact openings 102 through the ILD layers 86, 100 and expose the upper facets 84S of the CESL 54 and the epitaxial source / drain regions 84. U The anisotropic etch removes some of the first ILD layer 86 on the CESL 54. After the anisotropic etch, some portions 86R, 86B of the first ILD layer 86 remain covering portions of the CESL 54 and the lower facet 84S of the epitaxial source / drain regions 84. L .

[0062] exist Fig.12DIn the embodiment, an isotropic etch is then performed to expand the source / drain contact openings 102 and remove portions 86R, 86B of the first ILD layer 86 below the epitaxial source / drain regions 84, thereby exposing more of the CESL 54 and the lower facet 84S of the epitaxial source / drain regions 84. L Thus, a portion 54B of the CESL 54 is exposed. As described above, the ILD layers 86, 100 are overetched. Overetching can be achieved by continuously performing an isotropic etch for a long time (discussed further below). The long etch helps expose all facets 84S of the epitaxial source / drain regions 84 above the CESL 54. U 、84S L . In addition, overetching can widen the source / drain contact opening 102. For example, the width of the source / drain contact opening 102 can increase by a distance D2, which can be about 5% to about 50% of the original width of the source / drain contact opening 102. In some embodiments, the distance D2 can be about 1 nm to about 6 nm. Widening the source / drain contact opening 102 can help avoid the formation of seams or gaps in subsequently formed contacts by avoiding a pinch-off effect. Further, overetching can change the contour shape of the source / drain contact opening 102. Specifically, the sidewalls of the source / drain contact opening 102 can become tilted or more tilted by overetching. For example, before etching, the sidewalls of the source / drain contact opening 102 each form a first angle with a plane parallel to the main surface of the substrate 50, and after etching, the sidewalls of the source / drain contact opening 102 each form a second angle with a surface parallel to the main surface of the substrate 50, wherein the first angle is different from the second angle.

[0063] It should be understood that even when an over-etch is performed, some of the portions 86R, 86B of the first ILD layer 86 may remain beneath the epitaxial source / drain regions 84. For example, after etching, a trace amount of material of the first ILD layer 86 may remain beneath the epitaxial source / drain regions 84. However, in these embodiments, the exposed facets 84S of the epitaxial source / drain regions 84 may be exposed. U 、84S L The amount can still be increased, thereby increasing the available surface area of ​​the subsequently formed contacts.

[0064] In some embodiments, when the ILD layers 86, 100 are formed of oxide (e.g., silicon oxide) and the CESL 54 is formed of nitride (e.g., silicon nitride), the selective anisotropic etching of the ILD layers 86, 100 may be performed by dry etching such as reactive ion etching (RIE), and the selective isotropic etching of the ILD layers 86, 100 may be performed by wet etching such as oxide etching. The dry etching may be performed using one or more reactive gases (e.g., tetrafluoromethane (CF4), hexafluoro-1,3-butadiene (C4F6), octafluorocyclobutane (C4F8), octafluorocyclopentene (C5F8), etc. or a combination thereof), while plasma is generated using H2, O2, CO2, CO, etc. The plasma is generated using an inductively coupled plasma (ICP) generator, a capacitively coupled plasma (CCP) generator, a remote plasma generator, etc. A bias may be applied between the plasma generator and a chuck supporting the substrate 50 to bombard the ILD layers 86, 100 with ions. The wet etching may be performed using diluted hydrofluoric acid (dHF) or a chemical oxide etchant such as CERTAS (hydrogen fluoride (HF) and ammonia (NH3)), SiCONi (nitrogen trifluoride (NF3) and ammonia (NH3)), etc. As described above, the ILD layers 86 and 100 are overetched, and the overetching may be achieved by continuously performing the wet etching for a long time, for example, in the range of about 5 seconds to about 60 seconds.

[0065] In some embodiments, when the ILD layers 86, 100 are formed of oxide (e.g., silicon oxide) and the CESL 54 is formed of nitride (e.g., silicon nitride), the selective anisotropic etching of the ILD layers 86, 100 may be performed by a first dry etching method such as reactive ion etching (RIE), and the selective isotropic etching of the ILD layers 86, 100 may also be performed by a second dry etching method such as reactive ion etching (RIE). The first dry etching may be performed using one or more reactive gases (e.g., tetrafluoromethane (CF4), hexafluoro-1,3-butadiene (C4F6), octafluorocyclobutane (C4F8), octafluorocyclopentene (C5F8), etc. or a combination thereof), and plasma may be generated using H2, O2, CO2, CO, etc. The plasma may be generated using an inductively coupled plasma (ICP) generator, a capacitively coupled plasma (CCP) generator, a remote plasma generator, etc. A bias voltage may be applied between the plasma generator and the chuck supporting the substrate 50 to bombard the ILD layers 86, 100 with ions. The second dry etch may be performed using similar reactive gases and similar plasma generation as the first dry etch, but the second dry etch may be performed at a higher pressure and / or lower bias voltage than the first dry etch. For example, the pressure during the second dry etch may be about 200% to about 30000% higher than the pressure during the first dry etch, and the bias voltage during the second dry etch may be about 2% to about 50% lower than the bias voltage during the first dry etch. More specifically, the first dry etch may be performed at a pressure in the range of about 3mTorr to about 30mTorr and at an applied bias voltage in the range of about 100V to about 500V, while the second dry etch may be performed at a pressure in the range of about 60mTorr to about 900mTorr and at an applied bias voltage in the range of about 10V to about 50V. Performing the second dry etch at a greater pressure and / or lower bias than the first dry etch makes the second dry etch have a greater degree of isotropy than the first dry etch. As described above, the ILD layers 86, 100 are overetched. Overetching can be achieved by continuously performing the second dry etch for a long time, for example, in the range of about 5 seconds to about 60 seconds.

[0066] After forming the source / drain contact openings 102, the etched portions of the epitaxial source / drain regions 84 may have a reduced height. The height of the epitaxial source / drain regions 84 may be reduced by one or more etching processes used to form the source / drain contact openings 102. For example, the height of the epitaxial source / drain regions 84 may be reduced by a distance D1, which may be about 2% to about 20% of the original height of the epitaxial source / drain regions 84. In some embodiments, the distance D1 may be about 1 nm to about 10 nm.

[0067] exist Fig.13Aand Fig. 13B In the embodiment of the present invention, a metal-semiconductor alloy region 106 is formed in the source / drain contact opening 102, for example, on the portion of the epitaxial source / drain region 84 exposed by the source / drain contact opening 102. The metal-semiconductor alloy region 106 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanium region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 106 may be formed by depositing a metal in the source / drain contact opening 102 and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain region 84 to form a low-resistance metal semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. In an embodiment, the metal-semiconductor alloy region 106 is a silicide region formed of titanium-silicon. After the thermal annealing process, a cleaning process such as wet cleaning may be performed to remove any residual metal from the source / drain contact openings 102.

[0068] In the illustrated embodiment, the metal for the metal-semiconductor alloy region 106 is deposited by a line-of-sight deposition process such as PVD, so that the metal-semiconductor alloy region 106 is formed on the upper facet 84S of the epitaxial source / drain region 84. U (see Fig. 12B ), and the lower facet 84S of the epitaxial source / drain region 84 L There is no metal-semiconductor alloy region 106. In another embodiment (discussed further below with respect to FIG. 21), the metal for the metal-semiconductor alloy region 106 is deposited by a blanket deposition process such as CVD or ALD, and thus the metal-semiconductor alloy region 106 is formed on the upper facet 84S of the epitaxial source / drain region 84. U and lower facet 84S L The metal-semiconductor alloy region 106 is physically and electrically coupled to the epitaxial source / drain regions 84 .

[0069] exist Fig.14A and Fig. 14BIn the source / drain contact opening 102, a source / drain contact 110 is formed. In the source / drain contact opening 102, a liner and a conductive material such as a diffusion barrier layer, an adhesion layer, etc. are formed on the metal-semiconductor alloy region 106. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 100. The remaining liner and conductive material form a source / drain contact 110 in the source / drain contact opening 102. The source / drain contact 110 is physically and electrically coupled to the metal-semiconductor alloy region 106, and is therefore connected to the epitaxial source / drain region 84.

[0070] After formation, the source / drain contacts 110 extend through the ILD layers 86, 100. The source / drain contacts 110 may fill portions of the source / drain contact openings 102 not occupied by the metal semiconductor alloy regions 106. The source / drain contacts 110 extend along the lower facets 84S of the epitaxial source / drain regions 84. L Extending and contacting, for example, the lower facet 84S exposed by the source / drain contact opening 102 L The metal-semiconductor alloy region 106 is formed only on the upper facet 84S of the epitaxial source / drain region 84. U (See Fig. 12B ), the source / drain contact 110 and the lower surface 84S of the epitaxial source / drain region 84 L Source / drain contacts 110 and first ILD layer 86 also contact portion 54A of CESL 54, but do not contact portion 54B of CESL 54. Since CESL 54 is located below the protruding portion of epitaxial source / drain regions 84, all interfaces of CESL 54 and source / drain contacts 110 are planar relative to the major surface of substrate 50, and CESL 54 does not extend along facets 84S of epitaxial source / drain regions 84. U 、84S L In fact, no intermediate layers are disposed between epitaxial source / drain regions 84 and source / drain contacts 110 except metal-semiconductor alloy regions 106. In addition, voids 104 may not be filled by metal-semiconductor alloy regions 106 and / or source / drain contacts 110, and only portion 54B of CESL 54 is located in voids 104. In other words, voids 104 expose surfaces of CESL 54 and epitaxial source / drain regions 84, but do not expose surfaces of metal-semiconductor alloy regions 106 or source / drain contacts 110.

[0071] exist Fig.15A and Fig. 15B In the embodiment of the present invention, a gate contact 112 is formed through the second ILD layer 100. An opening of the gate contact 112 is formed through the second ILD layer 100. The opening can be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD layer 100. The remaining liner and conductive material form a gate contact 112 in the opening. The gate contact 112 is physically coupled and electrically coupled to the gate electrode 94, and is therefore connected to the gate electrode 94. The gate contact 112 can pass through a gate mask (if present) above the gate electrode 94. After formation, the top surfaces of the second ILD layer 100, the source / drain contact 110, and the gate contact 112 are coplanar.

[0072] Other processes and sequences may be used to form the gate contact 112. For example, the source / drain contact 110 and the gate contact 112 may be formed in different processes, or may be formed in the same process. In some embodiments, the gate contact 112 is formed simultaneously with the source / drain contact 110, for example, the opening of the gate contact 112 is formed simultaneously with the opening of the source / drain contact 110. In addition, although the source / drain contact 110 and the gate contact 112 are shown in the same cross section, each of the source / drain contact 110 and the gate contact 112 may be formed in different cross sections, which may avoid shorting of the contacts.

[0073] Fig.16A and Fig. 16B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to the embodiment described above except that the source / drain contact 110 includes a separate lower source / drain contact 110A and an upper source / drain contact 110B. Fig.15A and Fig. 15B The lower source / drain contact 110A extends through the first ILD layer 86 and the upper source / drain contact 110B extends through the second ILD layer 100. Thus, the lower source / drain contact 110A is disposed between the upper source / drain contact 110B and the metal-semiconductor alloy region 106.

[0074] As an example of forming the lower source / drain contact 110A, an opening for the lower source / drain contact 110A may be formed through the first ILD layer 86 before forming the second ILD layer 100. FIG. 12A to FIG. 12DThe opening is then formed using a process similar to that discussed above. FIG. 13A to FIG. 14B A metal-semiconductor alloy region 106 and a lower source / drain contact 110A are formed in the openings in a similar process to that discussed above. After formation, the top surfaces of the gate spacer 80, the first ILD layer 86, the gate electrode 94, and the lower source / drain contact 110A are coplanar.

[0075] As an example of forming an upper source / drain contact 110B, after forming the second ILD layer 100, an opening for an upper source / drain contact 110B is formed through the second ILD layer 100. Acceptable photolithography and etching techniques can be used to form the opening. A liner such as a diffusion barrier, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 100. The remaining liner and conductive material form an upper source / drain contact 110B in the opening. The upper source / drain contact 110B is connected to the lower source / drain contact 110A, and the lower source / drain contact 110A is connected to the epitaxial source / drain region 84. The upper source / drain contacts 110B and the gate contact 112 may be formed in different processes, or may be formed in the same process. After formation, the top surfaces of the second ILD layer 100 , the upper source / drain contacts 110B, and the gate contact 112 are coplanar.

[0076] It should be understood that some embodiments may be combined with FIG. 15A to FIG. 16B For example, the source / drain contacts in the first region of the die (eg, the input / output region) may be extended through multiple ILD layers (eg, Fig.15A and Fig. 15B ), while the source / drain contacts in the second region of the die (e.g., the core logic region) may have separate upper and lower conductive features in the corresponding ILD layer (e.g., Fig.16A and Fig. 16B shown).

[0077] Fig.17A and Fig. 17B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to the embodiment described above except that adjacent epitaxial source / drain regions 84 remain separated after epitaxial growth. Fig.15A and Fig. 15B The described embodiment is similar. In this embodiment, the same source / drain contacts 110 are used to connect adjacent epitaxial source / drain regions 84.

[0078] Fig.18A and Fig.18B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to that described with respect to FIG. 1 , except that adjacent epitaxial source / drain regions 84 remain separated and are not connected by the same source / drain contacts. Fig.17A and Fig. 17B Differently, each respective epitaxial source / drain region 84 is connected to a respective source / drain contact 110 .

[0079] Fig.19 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to the embodiment of FIG. 1 except that various shapes of source / drain contacts 110 are used. Fig.18B For example, the first source / drain contact 110C may contact some lower facets 84S of the epitaxial source / drain region 84 L , but not all lower facets 84S L , and the other lower facet 84S of the epitaxial source / drain region 84 L The second source / drain contact 110D may not contact the lower facet 84S of the epitaxial source / drain region 84. L . Fig.19 It can be shown that some material of the first ILD layer 86 remains below the epitaxial source / drain regions 84, but the exposed facets 84S U 、84S L The amount of embodiments still increases.

[0080] Fig. 20 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to the embodiment of FIG. 1 except that the same source / drain contact 110 is used to connect multiple merged epitaxial source / drain regions 84. Fig. 15B In addition, the source / drain contacts 110 may contact some lower facets 84S of the epitaxial source / drain regions 84. L , but not all lower facets 84S L , and the other lower facet 84S of the epitaxial source / drain region 84 L The first ILD layer 86 is contacted. Fig. 20 It can be shown that some material of the first ILD layer 86 remains below the epitaxial source / drain regions 84, but the exposed facets 84S U 、84S L The amount of embodiments still increases.

[0081] Fig.21A and Fig. 21BFIG. 8 is a cross-sectional view of a FinFET according to some other embodiments. U and lower facet 84S L Except for forming the metal-semiconductor alloy region 106 on the Fig.15A and Fig. 15B In this embodiment, the metal for the metal-semiconductor alloy region 106 is deposited by a blanket deposition process such as CVD or ALD. In some embodiments, the metal-semiconductor alloy region 106 has a uniform thickness. In some embodiments, the upper facet 84S of the metal-semiconductor alloy region 106 U The portion on the metal-semiconductor alloy region 106 is larger than the lower facet 84S. L For example, when the metal for the metal-semiconductor alloy region 106 is deposited by CVD or ALD, crowding under the epitaxial source / drain region 84 can reduce or hinder the diffusion of precursors under the epitaxial source / drain region 84. In addition, in this embodiment, the void 104 may (may not) be partially filled with the metal-semiconductor alloy region 106. Therefore, the portion of the metal-semiconductor alloy region 106 in the void 104 may also be thicker than the portion of the metal-semiconductor alloy region 106 on the upper facet 84S. U The upper part is thinner.

[0082] Embodiments can achieve advantages. Because the CESL 54 is located below the protruding portion of the epitaxial source / drain region 84, the ILD layer 86, 100 can be overetched without damaging the STI region 64, thereby allowing the portions 86R, 86B of the first ILD layer 86 below the epitaxial source / drain region 84 to be removed (see Fig. 12C Removing the portions 86R, 86B of the first ILD layer 86 below the epitaxial source / drain regions 84 allows the lower facets 84S of the epitaxial source / drain regions 84 to be L Exposed by the source / drain contact opening 102. Exposing more of the surface of the epitaxial source / drain region 84 allows the metal-semiconductor alloy region 106 and the source / drain contact 110 to contact a larger surface area of ​​the epitaxial source / drain region 84. Increasing the contact surface area can help reduce the contact resistance to the epitaxial source / drain region 84, especially when forming the resulting FinFET at a small technology node. In addition, by reducing the amount of dielectric material around the epitaxial source / drain region 84, the parasitic capacitance between the gate electrode 94 and the source / drain contact 110 can be reduced. Therefore, the performance of the FinFET can be improved.

[0083] In an embodiment, a method includes: etching source / drain recesses in a fin, the source / drain recesses extending through a contact etch stop layer (CESL); and growing epitaxial source / drain regions in the source / drain recesses; depositing an interlayer dielectric (ILD) layer on the epitaxial source / drain regions and the CESL; etching openings through the ILD layer using an isotropic etch, the isotropic etch removing a portion of the ILD layer below the epitaxial source / drain regions to expose a lower facet of the epitaxial source / drain regions and the CESL; and forming source / drain contacts in the openings, the source / drain contacts extending along the lower facet of the epitaxial source / drain regions.

[0084] In some embodiments, the method further comprises, before etching the source / drain recesses in the fins, performing the following operations: depositing a first dielectric layer on the substrate; depositing CESL over the first dielectric layer; depositing a second dielectric layer over the CESL; etching a trench in the second dielectric layer, the CESL, and the first dielectric layer; growing the fin in the trench; and removing the second dielectric layer. In some embodiments of the method, etching an opening through the ILD layer comprises: performing an anisotropic etch to form an opening, after the anisotropic etch, the opening exposes an upper facet of the epitaxial source / drain region, the lower facet of the epitaxial source / drain region remaining covered after the anisotropic etch; performing an isotropic etch to enlarge the opening, after the isotropic etch, the opening exposes a lower facet of the epitaxial source / drain region. In some embodiments of the method, the ILD layer includes silicon oxide; the CESL includes silicon nitride; the anisotropic etch is a dry etch performed with tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the isotropic etch is a wet etch performed with dilute hydrofluoric acid, hydrogen fluoride and ammonia, or nitrogen trifluoride and ammonia. In some embodiments of the method, the ILD layer includes silicon oxide; and the CESL includes silicon nitride; the anisotropic etch is a first dry etch performed with tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; the isotropic etch is a second dry etch performed with tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the second dry etch is performed at a greater pressure and a lower bias than the first dry etch. In some embodiments of the method, the isotropic etch is performed for a duration in the range of 5 seconds to 60 seconds. In some embodiments of the method, performing the isotropic etch widens the opening by 5% to 50%. In some embodiments, the method further comprises: forming a silicide on the upper facets of the epitaxial source / drain regions, the source / drain contacts contacting the silicide and contacting a subset of the lower facets of the epitaxial source / drain regions. In some embodiments of the method, before etching the openings, the ILD layer physically contacts the epitaxial source / drain regions. In some embodiments of the method, after forming the source / drain contacts, a void remains below the epitaxial source / drain regions, the void exposing a portion of the CESL.

[0085] In an embodiment, a structure includes: an isolation region on a substrate; a contact etch stop layer (CESL) on the isolation region; a first fin extending through the CESL and the isolation region; a second fin extending through the CESL and the isolation region; epitaxial source / drain regions in the first fin and the second fin, the epitaxial source / drain regions being arranged above a first portion of the CESL, the first portion of the CESL being laterally arranged between the first fin and the second fin; an interlayer dielectric (ILD) layer on the epitaxial source / drain regions and the second portion of the CESL; and a source / drain contact extending through the ILD layer, the source / drain contact contacting the second portion of the CESL and a lower facet of the epitaxial source / drain regions.

[0086] In some embodiments, the structure further comprises: a silicide on an upper facet of the epitaxial source / drain region, the source / drain contact contacting the silicide. In some embodiments, the structure further comprises: a void below the epitaxial source / drain region, the void exposing a first portion of the CESL and exposing a subset of a lower facet of the epitaxial source / drain region. In some embodiments of the structure, an interface of the CESL and the source / drain contact is parallel to a major surface of the substrate. In some embodiments of the structure, the lower facet of the epitaxial source / drain region is free of the CESL. In some embodiments of the structure, the lower facet of the epitaxial source / drain region is free of an ILD layer. In some embodiments of the structure, the ILD layer comprises silicon oxide, and the CESL comprises silicon nitride. In some embodiments of the structure, the first fin and the second fin are each an epitaxial structure disposed on the substrate. In some embodiments, the structure further comprises: a gate structure on the first fin and the second fin, the gate structure contacting a first portion and a second portion of the CESL.

[0087] In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source / drain region in the fin, the epitaxial source / drain region extending through the CESL; a silicide contacting an upper facet of the epitaxial source / drain region; a source / drain contact contacting the silicide, a lower facet of the epitaxial source / drain region, and a first surface of the CESL; and an interlayer dielectric (ILD) layer surrounding the source / drain contact, the ILD layer contacting the first surface of the CESL.

[0088] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0089] Example 1. A method for manufacturing a semiconductor device, comprising: etching a source / drain recess in a fin, the source / drain recess extending through a contact etch stop layer (CESL); growing an epitaxial source / drain region in the source / drain recess; depositing an interlayer dielectric (ILD) layer on the epitaxial source / drain region and the CESL; etching an opening through the ILD layer using an isotropic etch, the isotropic etch removing a portion of the ILD layer below the epitaxial source / drain region to expose a lower facet of the epitaxial source / drain region and the CESL; and forming a source / drain contact in the opening, the source / drain contact extending along the lower facet of the epitaxial source / drain region.

[0090] Example 2. The method according to Example 1 also includes: performing the following operations before etching the source / drain groove in the fin: depositing a first dielectric layer on a substrate; depositing the CESL on the first dielectric layer; depositing a second dielectric layer on the CESL; etching a trench in the second dielectric layer, the CESL and the first dielectric layer; growing the fin in the trench; and removing the second dielectric layer.

[0091] Example 3. A method according to Example 1, wherein etching the opening through the ILD layer includes: performing anisotropic etching to form the opening, after the anisotropic etching, the opening exposes the upper facet of the epitaxial source / drain region, and the lower facet of the epitaxial source / drain region remains covered after the anisotropic etching; and performing the isotropic etching to expand the opening, after the isotropic etching, the opening exposes the lower facet of the epitaxial source / drain region.

[0092] Example 4. The method of Example 3, wherein the ILD layer comprises silicon oxide; the CESL comprises silicon nitride; the anisotropic etching is a dry etching performed using tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the isotropic etching is a wet etching performed using dilute hydrofluoric acid, hydrogen fluoride and ammonia, or nitrogen trifluoride and ammonia.

[0093] Example 5. A method according to Example 3, wherein the ILD layer includes silicon oxide; the CESL includes silicon nitride; the anisotropic etching is a first dry etching performed using tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; the isotropic etching is a second dry etching performed using tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the second dry etching is performed at a greater pressure and a lower bias than the first dry etching.

[0094] Example 6. The method of Example 3, wherein the isotropic etching is performed for a duration in a range of 5 seconds to 60 seconds.

[0095] Example 7. The method of Example 3, wherein performing the isotropic etching widens the opening by 5% to 50%.

[0096] Example 8. The method according to Example 1 also includes: forming a metal-semiconductor alloy region on the upper facet of the epitaxial source / drain region, the source / drain contact contacting the metal-semiconductor alloy region and contacting a subset of the lower facet of the epitaxial source / drain region.

[0097] Example 9. The method of Example 1, wherein the ILD layer physically contacts the epitaxial source / drain regions before etching the openings.

[0098] Example 10. The method of example 1, wherein after forming the source / drain contacts, a void remains beneath the epitaxial source / drain region, the void exposing a portion of the CESL.

[0099] Example 11. A semiconductor device, comprising: an isolation region on a substrate; a contact etch stop layer (CESL) on the isolation region; a first fin extending through the CESL and the isolation region; a second fin extending through the CESL and the isolation region; an epitaxial source / drain region, in which the epitaxial source / drain region is arranged above a first portion of the CESL in the first fin and the second fin, and the first portion of the CESL is laterally arranged between the first fin and the second fin; an interlayer dielectric (ILD) layer on the epitaxial source / drain region and the second portion of the CESL; and a source / drain contact extending through the ILD layer, the source / drain contact contacting the second portion of the CESL and a lower facet of the epitaxial source / drain region.

[0100] Example 12. The semiconductor device of Example 11 further includes: a metal-semiconductor alloy region, wherein the source / drain contact contacts the metal-semiconductor alloy region on an upper facet of the epitaxial source / drain region.

[0101] Example 13. The semiconductor device of Example 11, further comprising: a void beneath the epitaxial source / drain region, the void exposing the first portion of the CESL and exposing a subset of the lower facet of the epitaxial source / drain region.

[0102] Example 14. The semiconductor device of Example 11, wherein an interface of the CESL and the source / drain contacts is parallel to a major surface of the substrate.

[0103] Example 15. The semiconductor device of Example 11, wherein the lower facet of the epitaxial source / drain region is free of the CESL.

[0104] Example 16. The semiconductor device of Example 11, wherein the lower facet of the epitaxial source / drain region is free of the ILD layer.

[0105] Example 17. The semiconductor device of Example 11, wherein the ILD layer comprises silicon oxide and the CESL comprises silicon nitride.

[0106] Example 18. The semiconductor device of Example 11, wherein the first fin and the second fin are each an epitaxial structure disposed on the substrate.

[0107] Example 19. The semiconductor device of Example 11, further comprising: a gate structure on the first fin and the second fin, the gate structure contacting the first portion and the second portion of the CESL.

[0108] Example 20. A semiconductor device comprising: a contact etch stop layer (CESL) on a substrate; a fin extending through the CESL; an epitaxial source / drain region, in which the epitaxial source / drain region extends through the CESL; a metal-semiconductor alloy region contacting an upper facet of the epitaxial source / drain region; a source / drain contact contacting the metal-semiconductor alloy region, a lower facet of the epitaxial source / drain region, and a first surface of the CESL; and an interlayer dielectric (ILD) layer surrounding the source / drain contact, the ILD layer contacting the first surface of the CESL.

Claims

1. A method for manufacturing a semiconductor device, comprising: depositing a contact etch stop layer CESL on the first dielectric layer; depositing a second dielectric layer on the CESL; etching trenches in the second dielectric layer, the CESL, and the first dielectric layer; growing a fin in the groove; removing the second dielectric layer; etching source / drain recesses in the fin, the source / drain recesses extending through the CESL; growing epitaxial source / drain regions in the source / drain recesses; depositing an interlayer dielectric ILD layer on the epitaxial source / drain regions and the CESL; etching an opening through the ILD layer using an isotropic etch that removes a portion of the ILD layer below the epitaxial source / drain region to expose a lower facet of the epitaxial source / drain region and the CESL; as well as Source / drain contacts are formed in the openings, the source / drain contacts extending along the lower facet of the epitaxial source / drain regions.

2. The method according to claim 1, wherein: Etching the opening through the ILD layer includes: performing an anisotropic etch to form the opening, the opening exposing an upper facet of the epitaxial source / drain region after the anisotropic etch, the lower facet of the epitaxial source / drain region remaining covered after the anisotropic etch; and The isotropic etch is performed to enlarge the opening, and after the isotropic etch, the opening exposes the lower facet of the epitaxial source / drain region.

3. The method according to claim 2, wherein: The ILD layer includes silicon oxide; the CESL includes silicon nitride; the anisotropic etching is dry etching performed using tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the isotropic etching is wet etching performed using dilute hydrofluoric acid, hydrogen fluoride and ammonia, or nitrogen trifluoride and ammonia.

4. The method according to claim 2, wherein: The ILD layer includes silicon oxide; the CESL includes silicon nitride; the anisotropic etching is a first dry etching performed using tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; the isotropic etching is a second dry etching performed using tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the second dry etching is performed at a greater pressure and a lower bias than the first dry etching.

5. The method according to claim 2, wherein: The isotropic etching is performed for a duration ranging from 5 seconds to 60 seconds.

6. The method according to claim 2, wherein: The isotropic etching is performed to widen the opening by 5% to 50%.

7. The method according to claim 1, further comprising: A metal-semiconductor alloy region is formed on an upper facet of the epitaxial source / drain region, and the source / drain contact contacts the metal-semiconductor alloy region and contacts a subset of the lower facet of the epitaxial source / drain region.

8. The method according to claim 1, wherein: Prior to etching the openings, the ILD layer physically contacts the epitaxial source / drain regions.

9. The method according to claim 1, wherein: After forming the source / drain contacts, a void remains beneath the epitaxial source / drain regions, the void exposing a portion of the CESL.

10. A semiconductor device comprising: an isolation region, on the substrate; A contact etch stop layer CESL on the isolation region; a first fin extending through the CESL and the isolation region; a second fin extending through the CESL and the isolation region; an epitaxial source / drain region, in the first fin and the second fin, the epitaxial source / drain region being disposed on a first portion of the CESL, the first portion of the CESL being laterally disposed between the first fin and the second fin; an interlayer dielectric ILD layer on the epitaxial source / drain regions and a second portion of the CESL, the second portion of the CESL being disposed between the groups of fins; as well as A source / drain contact extends through the ILD layer, the source / drain contact contacting the second portion of the CESL and a lower facet of the epitaxial source / drain region.

11. The semiconductor device according to claim 10, further comprising: A metal-semiconductor alloy region is provided on an upper facet of the epitaxial source / drain region, and the source / drain contact contacts the metal-semiconductor alloy region.

12. The semiconductor device according to claim 10, further comprising: A void is formed below the epitaxial source / drain region, the void exposing the first portion of the CESL and exposing a subset of the lower facet of the epitaxial source / drain region.

13. The semiconductor device according to claim 10, wherein: An interface of the CESL and the source / drain contacts is parallel to a major surface of the substrate.

14. The semiconductor device according to claim 10, wherein: The lower facet of the epitaxial source / drain region is free of the CESL.

15. The semiconductor device according to claim 10, wherein The lower facet of the epitaxial source / drain region is free of the ILD layer.

16. The semiconductor device according to claim 10, wherein: The ILD layer includes silicon oxide, and the CESL includes silicon nitride.

17. The semiconductor device according to claim 10, wherein: The first fin and the second fin are each an epitaxial structure disposed on the substrate.

18. The semiconductor device according to claim 10, further comprising: A gate structure is provided on the first fin and the second fin, the gate structure contacting the first portion and the second portion of the CESL.

19. A semiconductor device comprising: A contact etch stop layer CESL, on the substrate; a fin extending through the CESL; an epitaxial source / drain region, in the fin, the epitaxial source / drain region extending through the CESL; a metal-semiconductor alloy region contacting an upper facet of the epitaxial source / drain region; a source / drain contact in contact with the metal-semiconductor alloy region, a lower facet of the epitaxial source / drain region, and a first surface of the CESL; an interlayer dielectric ILD layer, surrounding the source / drain contacts, the ILD layer contacting the first surface of the CESL; a gate structure on the sidewalls of the CESL and the fin; as well as A gate spacer is between the gate structure and the epitaxial source / drain region.

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