Light emitting device and display device including the same

Abstract

Disclosed are a light emitting device and a display device including the light emitting device. The light emitting device may include: a plurality of first electrodes and a plurality of second electrodes, which are arranged at positions spaced apart from each other in a first direction; a plurality of light emitting elements, which are electrically connected between mutually adjacent first electrodes and second electrodes among the plurality of first electrodes and the plurality of second electrodes; and a third electrode, which is arranged at a preset position spaced apart from the plurality of first electrodes and the plurality of second electrodes. The third electrode may be electrically separated from the plurality of first electrodes and the plurality of second electrodes.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a light emitting device, and more particularly, to a pixel and a display apparatus including the light emitting device. Background Art

[0002] Recently, a technology for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and manufacturing light-emitting devices using the light-emitting elements has been developed. For example, a technology for manufacturing a plurality of ultra-small light-emitting elements having a small size corresponding to a range from nanometers to micrometers and forming a light source of various light-emitting devices (e.g., pixels of a display device) using the ultra-small light-emitting elements has been developed. Summary of the invention

[0003] Technical issues

[0004] An object of the present disclosure is to provide a light emitting device capable of controlling the alignment density of light emitting elements and a display apparatus including the light emitting device.

[0005] However, the objects of the present disclosure are not limited to the above objects, and various modifications are possible without departing from the spirit and scope of the present disclosure.

[0006] Technical Solution

[0007] A light emitting device according to an embodiment of the present disclosure may include: a plurality of first electrodes and a plurality of second electrodes, which are disposed at positions spaced apart from each other in a first direction; a plurality of light emitting elements, which are electrically coupled between first electrodes and second electrodes adjacent to each other among the plurality of first electrodes and the plurality of second electrodes; and a third electrode, which is disposed at a preset position spaced apart from the first electrode and the second electrode. The third electrode may be electrically separated from the plurality of first electrodes and the plurality of second electrodes.

[0008] In an implementation, the third electrode may be an island-shaped electrode.

[0009] In an embodiment, the first electrode and the second electrode adjacent to each other may form a corresponding electrode pair. The number of light-emitting elements arranged on the first electrode pair closest to the third electrode may be greater than the number of light-emitting elements arranged on the second electrode pair, and the second electrode pair is arranged farther away from the third electrode than the first electrode pair.

[0010] In an embodiment, the density of the light emitting elements may decrease in a direction away from the third electrode with respect to the first direction.

[0011] In an embodiment, one of the plurality of first electrodes may be disposed to face a first side of the third electrode, and another one of the plurality of first electrodes may be disposed to face a second side of the third electrode opposite to the first side of the third electrode.

[0012] In an embodiment, one of the plurality of second electrodes may be disposed to face a first side of the third electrode. Another of the plurality of second electrodes may be disposed to face a second side of the third electrode opposite to the first side of the third electrode.

[0013] In an implementation, a width of the third electrode with respect to the first direction may be greater than a width of the first electrode with respect to the first direction and a width of the second electrode with respect to the first direction.

[0014] In an implementation, the third electrode may include a plurality of conductive patterns sequentially disposed at positions spaced apart from each other in the first direction.

[0015] In an implementation, the first to third electrodes may be formed of the same conductive material and disposed on the same insulating layer.

[0016] A display device according to an embodiment of the present disclosure may include a first pixel disposed in a display area and including an emission area. The first pixel may include: a plurality of first electrodes and a plurality of second electrodes, disposed in the emission area at positions spaced apart from each other in a first direction; a plurality of light-emitting elements, electrically connected between first electrodes and second electrodes adjacent to each other in the plurality of first electrodes and the plurality of second electrodes; a first connecting electrode, coupled to the plurality of first electrodes; a second connecting electrode, coupled to the plurality of second electrodes; and a third electrode, electrically separated from the plurality of first electrodes and the plurality of second electrodes, and disposed at a position spaced apart from the plurality of first electrodes and the plurality of second electrodes.

[0017] In an implementation, the third electrode may be an island-shaped electrode.

[0018] In an embodiment, the first electrode and the second electrode adjacent to each other may form a corresponding electrode pair. The number of light-emitting elements arranged on the first electrode pair closest to the third electrode may be greater than the number of light-emitting elements arranged on the second electrode pair, and the second electrode pair is arranged farther away from the third electrode than the first electrode pair.

[0019] In an embodiment, the density of the light emitting elements may decrease in a direction away from the third electrode with respect to the first direction.

[0020] In an embodiment, the third electrode may be disposed in the emission region. The first electrode and the second electrode may be disposed in a shape symmetrical based on the third electrode.

[0021] In an embodiment, the third electrode may be disposed in the emission region. The number of some of the first electrodes and some of the second electrodes disposed on the first side of the third electrode among the plurality of first electrodes and the plurality of second electrodes is different from the number of the remaining first electrodes and the remaining second electrodes disposed on the second side of the third electrode among the plurality of first electrodes and the plurality of second electrodes.

[0022] In an implementation, the third electrode may be disposed on one side of a non-emission region surrounding the emission region of the first pixel.

[0023] In an implementation, the display device may further include a bank disposed in the non-emission region to surround the first pixel and disposed on the third electrode.

[0024] In an embodiment, the display device may further include a second pixel having the same structure as that of the first pixel and disposed adjacent to the third electrode. The first connection electrode of the first pixel and the first connection electrode of the second pixel may be separated from each other between the first pixel and the second pixel. The second connection electrode of the first pixel and the second connection electrode of the second pixel may be integrally connected to each other.

[0025] In an embodiment, a density at which the light emitting element of each of the first pixel and the second pixel is disposed may increase from a central portion of the corresponding emission region toward the third electrode.

[0026] In an implementation, the first to third electrodes may be formed of the same conductive material and disposed on the same insulating layer.

[0027] Beneficial Effects

[0028] In the light emitting device and the display device including the light emitting device according to the embodiment of the present disclosure, the area where the light emitting elements are densely arranged in the emission area can be easily controlled by controlling the arrangement position of the floating third electrode. Therefore, the design change of the plane shape and size of the pixel can be facilitated.

[0029] Furthermore, as the amount of light and brightness per unit surface area increases, the size of the pixel can be reduced, and high resolution can be easily achieved.

[0030] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications are possible without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a and Figure 1b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0034] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0035] Figure 5a to Figure 5c are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0036] Figure 6 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel forming the light emitting device.

[0037] Figure 7 It is shown Figure 6 A plan view of an example of a first electrode to a third electrode.

[0038] Figures 8a to 8d is shown with Figure 6 FIG. 4 is a cross-sectional view of an example of a cross-section corresponding to line II′ of a light-emitting device.

[0039] Fig. 9 is a plan view showing a light emitting device according to an embodiment of the present disclosure.

[0040] Fig.10 is a plan view showing a display device according to an embodiment of the present disclosure, and shows, for example, an embodiment in which pixels forming the display device are formed.

[0041] Figures 11a to 11c is shown with Fig.10 A cross-sectional view of an example of a cross section corresponding to line II-II' of a display device.

[0042] Fig.12 is a cross-sectional view showing a display device according to an embodiment of the present disclosure, and is a cross-sectional view showing Fig.10 A cross-sectional view of an example of a cross section corresponding to line II-II'.

[0043] Fig.13 is a diagram illustrating an embodiment of a pixel included in a display device according to an embodiment of the present disclosure.

[0044] Fig.14 is a diagram illustrating an embodiment of a pixel included in a display device according to an embodiment of the present disclosure.

[0045] Fig.15 is a plan view showing an example of first to third electrodes included in a light emitting device according to an embodiment of the present disclosure.

[0046] Fig.16 is a plan view showing an example of first to third electrodes included in a light emitting device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used throughout the different drawings to represent the same components, and repeated description of the same components will be omitted.

[0048] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting element LD is illustrated, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0049] refer to Figure 1a and Figure 1b The light emitting element LD according to the embodiment of the present disclosure may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be composed of a stacked body formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 in a longitudinal direction.

[0050] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end with respect to the longitudinal direction.

[0051] In an embodiment, one of the first and second conductive semiconductor layers 11 and 13 may be disposed on a first end of the light emitting element LD, and the other of the first and second conductive semiconductor layers 11 and 13 may be disposed on a second end of the light emitting element LD.

[0052] In an embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type" includes a rod-like shape and a bar-like shape, such as a cylindrical shape and a prismatic shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0053] In an embodiment, the light emitting element LD may have a small size ranging from nanometer level to micrometer level. Each light emitting element LD may have a diameter D and / or a length L ranging from nanometer level to micrometer level. For example, the length L of the light emitting element LD may range from approximately 100 nm to 10 μm, and the aspect ratio of the light emitting element LD may range from approximately 1.2 to approximately 100. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., a display device using a light emitting device using the light emitting element LD as a light source).

[0054] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material for forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0055] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, or may be formed using various other materials.

[0056] If a voltage equal to or greater than a threshold voltage is applied to each of the opposite ends of the light emitting element LD, the light emitting element LD may emit light by coupling of electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD may be controlled based on the aforementioned principle, the light emitting element LD may be used as a light source for various light emitting devices as well as pixels of a display device.

[0057] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer including any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material for forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0058] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12, and may also surround predetermined areas of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting element LD with respect to the longitudinal direction, for example, may expose both base sides of the cylinder (at Figure 1a and Figure 1b , the top surface and the bottom surface of the light emitting element LD), rather than covering the two substrate sides.

[0059] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF may be formed of various well-known insulating materials.

[0060] In an embodiment, the light emitting element LD may further include additional other components as well as the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0061] For example, Figure 2a and Figure 2b As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive semiconductor layer 11 .

[0062] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO, and oxides or alloys thereof may be used alone or in combination with each other. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0063] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround the outer surfaces of the electrode layers 14 and 15. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, for example, at least one region of each of the electrode layers 14 and 15 may be exposed. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0064] If the insulating film INF is provided on the surface of the light emitting element LD (particularly, on the surface of the active layer 12), the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, at least one of the contact electrodes coupled to the opposite ends of the light emitting element LD), etc. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0065] In addition, due to the insulating film INF formed on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on the surface of each light emitting element LD, even when a plurality of light emitting elements LD are disposed adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0066] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, each light emitting element LD may be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed rather than unevenly aggregated in the solution.

[0067] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in a display device, but also in various devices that require a light source. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) may be provided in each pixel region of the display panel to form a light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the field of application of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices (such as lighting devices) that require a light source.

[0068] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (particularly, a display panel PNL provided in the display device) is shown as a usable reference. Figures 1a to 3b The light emitting element LD is described as an example of a means of a light source. For example, a pixel PXL of a display panel PNL may have at least one light emitting element LD.

[0069] For the sake of explanation, Figure 4 The structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0070] refer to Figure 4 , the display panel PNL according to an embodiment of the present disclosure may include a base layer BSL and a plurality of pixels PXL disposed on the base layer BSL. In detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0071] In an embodiment, the display area DA may be disposed in a central area of ​​the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of ​​the display panel PNL so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0072] The base layer BSL may form a base of the display panel PNL. In an embodiment, the base layer BSL may be a rigid or flexible substrate or film, and its material or properties are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not particularly limited.

[0073] In addition, the base layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the base layer BSL may be a transparent, translucent, opaque, or reflective base.

[0074] One area on the base layer BSL may be defined as a display area DA in which the pixels PXL are disposed, and the other area on the base layer BSL may be defined as a non-display area NDA. For example, the base layer BSL may include a display area DA and a non-display area NDA disposed around the display area DA, wherein the display area DA includes a plurality of pixel areas in which corresponding pixels PXL are formed. Various lines and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0075] In an embodiment, the pixels PXL may be distributed and arranged in the display area DA. In an embodiment, the pixels PXL may be arranged in the display area DA in a stripe or PenTile arrangement. However, the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the display area DA in various known arrangements.

[0076] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a power voltage (eg, a first power voltage and a second power voltage), for example, according to Figures 1a to 3b For example, each pixel PXL may include at least one ultra-small light emitting element LD having a small size ranging from nanometer level to micrometer level. For example, each pixel PXL may include a plurality of ultra-small light emitting elements LD connected in parallel to each other between power lines and / or pixel electrodes and forming a light source or light source unit of the corresponding pixel PXL, and each of these ultra-small light emitting elements LD has a rod-like shape.

[0077] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL that can be applied to the display device according to the present disclosure is not limited. For example, each pixel PXL may have the same structure as the structure of a pixel for a passive light-emitting display device or an active light-emitting display device, and the passive light-emitting display device or the active light-emitting display device has various known structures and / or can be operated with various known driving schemes.

[0078] Figure 5a to Figure 5c is a circuit diagram showing a pixel according to an embodiment of the present disclosure, and shows, for example, different embodiments of active pixels forming each light emitting device. Figure 5a to Figure 5c Each pixel PXL shown in FIG. 1 may be in Figure 4 The pixels PXL may have substantially the same or similar structures.

[0079] refer to Figure 5a The pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further include a pixel circuit PXC configured to drive the light source unit LSU.

[0080] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically coupled to each other between a first power source VDD and a second power source VSS. In an embodiment, the light emitting elements LD may be coupled to each other in parallel, but the present disclosure is not limited thereto. For example, in an embodiment, the plurality of light emitting elements LD may be coupled to the first power source VDD and the second power source VSS in a series / parallel combination structure.

[0081] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, at least during the light emitting period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or more.

[0082] although Figure 5a An embodiment is shown in which the light emitting elements LD of the light source unit LSU forming each pixel PXL are connected in parallel to each other in the same direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, in an embodiment, some of the light emitting elements LD may be connected to each other in a first direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, and other light emitting elements LD may be connected to each other in a second direction (e.g., in the reverse direction). Alternatively, in an embodiment, at least one pixel PXL may include only a single light emitting element LD (e.g., a single effective light emitting element LD connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0083] In an embodiment, a first end of the light emitting element LD forming each light source unit LSU may be commonly coupled to the pixel circuit PXC through one electrode of the light source unit LSU (e.g., the first electrode and / or the first contact electrode of each pixel PXL), and may be commonly coupled to the first power source VDD through the pixel circuit PXC and the first power line PL1. A second end of the light emitting element LD may be commonly coupled to the second power source VSS through another electrode of the light source unit LSU (e.g., the second electrode and / or the second contact electrode of each pixel PXL) and the second power line PL2.

[0084] Each light source unit LSU may emit light having brightness corresponding to a driving current supplied thereto through a corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0085] The pixel circuit PXC may be coupled to a scan line (e.g., an i-th scan line Si) and a data line (e.g., a j-th data line Dj) of a corresponding pixel PXL. For example, if the pixel PXL is disposed in an i-th row (i is a natural number) and a j-th column (j is a natural number) of a display area DA, the pixel circuit PXC of the pixel PXL may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0086] The first transistor (also referred to as a "driving transistor") T1 may be coupled between the first power source VDD and the light source unit LSU. A gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0087] The second transistor (also referred to as a "switching transistor") T2 may be coupled between a data line (e.g., the jth data line Dj) and the first node N1. A gate electrode of the second transistor T2 may be coupled to a scan line (e.g., the i-th scan line Si). When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line (e.g., the i-th scan line Si), the second transistor T2 is turned on to electrically couple the first node N1 to the data line (e.g., the j-th data line Dj).

[0088] During each frame period, a data signal of a corresponding frame is supplied to a data line (eg, the j-th data line Dj). The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0089] One electrode of the storage capacitor Cst may be coupled to the first power source VDD, and the other electrode thereof may be coupled to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to a data signal to be supplied to the first node N1 during each frame period.

[0090] Despite Figure 5a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0091] For example, Figure 5b As shown in , both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line (e.g., the j-th data line Dj) into the pixel PXL in each frame period may be a high-level voltage. Similarly, the waveform of the voltage of the data signal for turning on the first transistor T1 may be the same as that for turning on the data line Dj. Figure 5a The waveform of the voltage of the data signal when the first transistor T1 is turned on is opposite. Figure 5b In an embodiment, as the grayscale value to be represented increases, a data signal having a higher voltage may be supplied.

[0092] In addition to the connection positions of some circuit elements and the voltage levels of control signals (eg, scan signals and data signals) that can be changed according to the type of transistor, Figure 5b The pixel PXL shown in FIG. 1 can be configured and operated similarly to Figure 5a The pixels PXL are basically similar. Therefore, the Figure 5b A detailed description of the pixel PXL.

[0093] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. Figure 5c The embodiment shown in FIG. 1 is configured in the same manner as that shown in FIG.

[0094] refer to Figure 5c, the pixel circuit PXC may be coupled not only to the scan line of the corresponding horizontal line (e.g., the i-th scan line Si), but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL disposed in the i-th row of the display area DA may also be coupled to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In an embodiment, the pixel circuit PXC may be coupled not only to the first power supply VDD and the second power supply VSS, but also to a third power supply. For example, the pixel circuit PXC may also be coupled to an initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0095] The first transistor T1 may be coupled between the first power source VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be coupled to the first power source VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 may be coupled to the first electrode of the light source unit LSU (e.g., the first electrode and / or the first contact electrode of the corresponding pixel PXL) via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control the driving current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0096] The second transistor T2 may be coupled between a data line (e.g., the jth data line Dj) and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to a corresponding scan line (e.g., the i-th scan line Si). When a scan signal having a gate-on voltage is supplied from the scan line (e.g., the i-th scan line Si), the second transistor T2 may be turned on to electrically connect the data line (e.g., the j-th data line Dj) to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line (e.g., the j-th data line Dj) may be transmitted to the first transistor T1.

[0097] The third transistor T3 may be coupled between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be coupled to a corresponding scan line (e.g., the i-th scan line Si). When a scan signal having a gate-on voltage is supplied from the scan line (e.g., the i-th scan line Si), the third transistor T3 may be turned on, thereby electrically connecting the first transistor T1 in a diode form.

[0098] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to a previous scan line, for example, the i-1th scan line Si-1. When a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 may be the lowest voltage of the data signal or less.

[0099] The fifth transistor T5 may be coupled between the first power supply VDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage (for example, a high-level voltage) is supplied to the emission control line (for example, the i-th emission control line Ei), and may be turned on in other cases.

[0100] The sixth transistor T6 may be coupled between the first transistor T1 and the light source unit LSU. A gate electrode of the sixth transistor T6 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the emission control line (for example, the i-th emission control line Ei), and may be turned on in other cases.

[0101] The seventh transistor T7 may be coupled between the first electrode of the light source unit LSU (e.g., the first electrode and / or the first contact electrode of the corresponding pixel PXL) and the initialization power supply Vint. The gate electrode of the seventh transistor T7 may be coupled to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When the scan signal of the gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU may be initialized. The control signal for controlling the operation of the seventh transistor T7 may be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 may be coupled to the scan line of the corresponding horizontal line, that is, the i-th scan line Si. In this case, when the scan signal with the gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.

[0102] The storage capacitor Cst may be coupled between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0103] Despite Figure 5c The transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0104] The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 5a to Figure 5c , and each pixel PXL may have various known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the opposite ends of the light-emitting element LD constituting the light source unit LSU may be directly connected to a scan line, a data line, a power line, and / or a control line.

[0105] Figure 6 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel forming the light emitting device. Figure 7 It is shown Figure 6 A plan view of an example of a first electrode to a third electrode.

[0106] In an embodiment, the pixel PXL may be Figure 4 to Figure 5c Any one of the pixels PXL shown in , but the present disclosure is not limited thereto.

[0107] Figure 6 and Figure 7 Only the structure of the display element layer on which the light source unit LSU (or "light emitting device") of each pixel PXL is disposed is shown. Here, the pixel PXL may also selectively include a circuit element for controlling each light source unit LSU (for example, forming a Figure 5a to Figure 5c At least one circuit element of the pixel circuit PXC). In addition, in an embodiment, Figure 6The case where each light source unit LSU is coupled to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (at least one circuit element forming a pixel circuit PXC), and / or a signal line (e.g., a scan line and / or a data line) through a first contact hole CH1 and a second contact hole CH2 is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrodes ET1 and ET1' and the second electrodes ET2 and ET2' may be directly coupled to a predetermined power line and / or a signal line without passing through a contact hole and / or an intermediate line.

[0108] refer to Figure 6 and Figure 7 , the light emitting device included in the pixel PXL etc. may include a predetermined emission area EMA, first electrodes ET1 and ET1', second electrodes ET2 and ET2', third electrodes ET3, and first contact electrodes CE1 and CE1' and second contact electrodes CE2 and CE2' respectively overlapping the first electrodes ET1 and ET1' and the second electrodes ET2 and ET2'. The first electrodes ET1 and ET1' and the second electrodes ET2 and ET2' may be disposed at positions spaced apart from each other in the emission area EMA. Similarly, the first contact electrodes CE1 and CE1' and the second contact electrodes CE2 and CE2' may also be disposed at positions spaced apart from each other in the emission area EMA.

[0109] In addition, the pixel PXL may include a plurality of light emitting elements LD and LD' electrically coupled between adjacent first and second electrodes ET1 and ET1' and ET2 and ET2' and between adjacent first and second contact electrodes CE1 and CE1' and CE2 and CE2'.

[0110] Based on the third electrode ET3, the emission area EMA may include a first sub-area SBA1 and a second sub-area SBA2, the first sub-area SBA1 includes the first electrode ET1 and the second electrode ET2, and the second sub-area SBA2 includes the first electrode ET1' and the second electrode ET2'. In an embodiment, the configuration included in the second sub-area SBA2 may be substantially the same as the configuration included in the first sub-area SBA1. In addition, based on the third electrode ET3, the configuration included in the second sub-area SBA2 may be substantially symmetrical with the configuration included in the first sub-area SBA1. For the sake of explanation, hereinafter, some configurations of the pixel PXL will be described with a focus on the configuration of the first sub-area SBA1.

[0111] The first ends EP1 of at least some of the light emitting elements LD may each be electrically coupled to the first electrode ET1 and the first contact electrode CE1. The second ends EP2 of at least some of the light emitting elements LD may each be electrically coupled to the second electrode ET2 and the second contact electrode CE2. In this way, each of the plurality of light emitting elements LD (also referred to as "effective light emitting elements") electrically coupled between the first electrode ET1 and the second electrode ET2 and between the first contact electrode CE1 and the second contact electrode CE2 (particularly, coupled in a forward direction to emit light in response to a predetermined control signal and / or power supplied to the first electrode ET1 and / or the second electrode ET2) may form a light source of a corresponding pixel PXL. Such effective light emitting elements LD may be aggregated to form a light source unit LSU of a corresponding pixel PXL.

[0112] In addition, reference Figures 8a to 8d The pixel PXL may further selectively include a first bank pattern PW1 and a second bank pattern PW2 disposed to overlap the first electrode ET1 and the second electrode ET2, respectively. In an embodiment, the first bank pattern PW1 and the second bank pattern PW2 may be disposed under the first electrode ET1 and the second electrode ET2, respectively.

[0113] The emission area EMA may be an area in which a light emitting element LD (particularly, an effective light emitting element LD completely coupled between the first electrode ET1 and the second electrode ET2) is disposed, the light emitting element LD forming the light source unit LSU of the pixel PXL. The emission area EMA may be surrounded by a light shielding embankment or a reflective embankment (also referred to as a "pixel defining layer") not shown.

[0114] The first electrode ET1 and the second electrode ET2 may be disposed at positions spaced apart from each other in the first sub-region SBA1 so that at least a predetermined region of the first electrode ET1 and at least a predetermined region of the second electrode ET2 face each other. For example, the first electrode ET1 and the second electrode ET2 may be disposed at positions spaced apart from each other in the first direction DR1. In addition, although Figure 6 It is shown that one first electrode ET1 and one second electrode ET2 are disposed in the first sub-region SBA1 , but this is only for illustration purposes, and a plurality of first electrodes ET1 and a plurality of second electrodes ET2 may be alternately disposed in the first sub-region SBA1 .

[0115] In an embodiment, in the emission area EMA, the first electrode ET1 and the second electrode ET2 may extend in the second direction DR2 and be arranged parallel to each other. The first direction DR1 and the second direction DR2 may be perpendicular to each other, but the present disclosure is not limited thereto. For example, in an embodiment, the first direction DR1 and the second direction DR2 may intersect each other in a diagonal direction.

[0116] In an embodiment, the first electrode ET1 may be coupled to the first connection electrode CNL1 adjacent to the emission area EMA. In an embodiment, the first electrode ET1 and the first connection electrode CNL1 may be integrally coupled to each other, but the present disclosure is not limited thereto. In the case where the first electrode ET1 and the first connection electrode CNL1 are integrally coupled to each other, they may be considered as a single electrode. In an embodiment, the first connection electrode CNL1 may extend in the first direction DR1.

[0117] The first electrode ET1 may be electrically coupled to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line, a data line, or a predetermined control line) through the first connection electrode CNL1 and / or the first contact hole CH1. For example, the first electrode ET1 may be electrically coupled to a predetermined circuit element disposed thereunder through the first connection electrode CNL1 and the first contact hole CH1, and may be electrically coupled to the first line through the circuit element. In an embodiment, the first line may be a first power line PL1 for supplying a first power supply VDD, but the present disclosure is not limited thereto. For example, in an embodiment, the first line may be a signal line through which a predetermined first drive signal (e.g., a scan signal, a data signal, or a predetermined control signal) may be supplied.

[0118] Alternatively, in an embodiment, the first electrode ET1 may be directly coupled to a predetermined power line or signal line without passing through the first connection electrode CNL1, the first contact hole CH1, and / or the circuit element. In this case, the first electrode ET1 may be integrally or non-integrally coupled to the predetermined power line or signal line.

[0119] In an embodiment, the second electrode ET2 may be coupled to the second connection electrode CNL2 adjacent to the emission area EMA. The second electrode ET2 and the second connection electrode CNL2 may be integrally coupled to each other, but the present disclosure is not limited thereto. In the case where the second electrode ET2 and the second connection electrode CNL2 are integrally coupled to each other, they may be considered as a single electrode.

[0120] In an implementation, the second connection electrode CNL2 may extend in the first direction DR1 and be disposed substantially parallel to the first connection electrode CNL1.

[0121] The second electrode ET2 may be electrically coupled to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a second power line PL2) and / or a signal line (e.g., a scan line, a data line, or a predetermined control line) through the second connection electrode CNL2 and / or the second contact hole CH2. For example, the second electrode ET2 may be electrically coupled to a predetermined second line disposed thereunder through the second connection electrode CNL2 and the second contact hole CH2. In an embodiment, the second line may be a second power line PL2 for supplying a second power source VSS, but the present disclosure is not limited thereto. For example, in an embodiment, the second line may be a signal line through which a predetermined second drive signal (e.g., a scan signal, a data signal, or a predetermined control signal) may be supplied.

[0122] Alternatively, in an embodiment, the second electrode ET2 may be directly coupled to a predetermined power line or signal line without passing through the second connection electrode CNL2, the second contact hole CH2 and / or the circuit element. In this case, the second electrode ET2 may be integrally or non-integrally coupled to the predetermined power line or signal line.

[0123] In an embodiment, during a process of forming the pixel PXL (particularly, before the alignment of the light emitting element LD is completed), the corresponding first electrodes ET1 of the pixels PXL disposed in the display area DA may be electrically coupled to each other, and the corresponding second electrodes ET2 may be electrically coupled to each other. At the step of aligning the light emitting element LD, the first electrode ET1 and the second electrode ET2 may be supplied with a first alignment voltage and a second alignment voltage, respectively. In other words, at the step of aligning the light emitting element LD, a predetermined alignment signal may be applied between the first electrode ET1 and the second electrode ET2, so that an electric field may be formed between the first electrode ET1 and the second electrode ET2. The light emitting element LD supplied to each pixel region (particularly, the emission region EMA of each pixel PXL) may be aligned between the first electrode ET1 and the second electrode ET2 by the electric field. After the alignment of the light emitting element LD has been completed, the connection between the first electrodes ET1 and / or the connection between the second electrodes ET2 may be disconnected between the pixels PXL, so that the pixels PXL may be driven individually.

[0124] The third electrode ET3 may not be electrically coupled to the first electrode ET1 and the second electrode ET2. In an embodiment, the third electrode ET3 may be provided in an isolated shape, for example, an island shape (or also referred to as a "floating state" or an "open state"). In other words, the third electrode ET3 may be a dummy electrode through which current does not flow, and is spaced apart from the first electrode ET1 and the second electrode ET2.

[0125] For example, the third electrode ET3 may be disposed in the emission area EMA and separate the first sub-area SBA1 and the second sub-area SBA2 from each other. A light emitting element (not shown) in physical contact with the open third electrode ET3 does not emit light because current does not flow through the light emitting element. Figure 6 It is shown that the third electrode ET3 is not coupled to the light emitting element, but the light emitting element that does not emit light may be substantially disposed on the third electrode ET3. Figure 6 Only the effective light emitting elements LD are shown.

[0126] In an embodiment, the third electrode ET3 may extend in the second direction DR2 and be disposed substantially parallel to the first and second electrodes ET1 and ET2. In an embodiment, the third electrode ET3 may have a shape formed by cutting off a portion of the first or second electrode ET1 or ET2.

[0127] For example, the third electrode ET3 may be formed by the same process as that of the first electrode ET1 or the second electrode ET2. In other words, the third electrode ET3 may be formed by patterning the first and second electrodes ET1 and ET2 so that selected ones of the first and second electrodes ET1 and ET2 float.

[0128] During the process of applying the first alignment voltage and the second alignment voltage for aligning the light emitting element LD, no voltage may be applied to the floating third electrode ET3, so that the third electrode ET3 does not form an electric field. Therefore, the light emitting element LD may move toward other electrodes disposed around the third electrode ET3, rather than being aligned or guided toward the third electrode ET3. Therefore, the arrangement of the light emitting element LD may be concentrated on the electrode pair including the first electrode ET1 and the second electrode ET2 adjacent to the third electrode ET3.

[0129] In an embodiment, the widths WA1, WA2, and WA3 of the first electrode ET1, the second electrode ET2, and the third electrode ET3 relative to the first direction DR1 may be substantially the same as each other. However, this is only for illustrative purposes, and at least some of the widths WA1, WA2, and WA3 of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may be different from each other. For example, the width WA3 of the third electrode ET3 may be greater than the width WA1 of the first electrode ET1 and the width WA2 of the second electrode ET2.

[0130] In an embodiment, the corresponding distances D1, D2, D3 and D4 between adjacent first electrodes ET1, second electrodes ET2 and third electrodes ET3 may be substantially the same as each other. However, this is only for illustrative purposes, and at least some of the distances D1, D2, D3 and D4 between adjacent first electrodes ET1, second electrodes ET2 and third electrodes ET3 may be different from each other.

[0131] The respective widths WA1, WA2, and WA3 of the electrodes and the distances D1, D2, D3, and D4 between the electrodes may be changed in various ways according to a desired alignment density of the light emitting elements LD.

[0132] The first contact electrode CE1 may be disposed above the first electrode ET1 to overlap the first electrode ET1. In an embodiment, the first electrode ET1 and the first contact electrode CE1 may have shapes corresponding to each other.

[0133] In an embodiment, the first contact electrode CE1 may be disposed on a region of the first electrode ET1 and the first ends EP1 of the aligned plurality of light emitting elements LD in the emission region EMA, and electrically coupled to the first end EP1 and the first electrode ET1. The first end EP1 of the light emitting element LD may be electrically coupled to the first electrode ET1 through the first contact electrode CE1. In addition, the first end EP1 of the light emitting element LD may be stably fixed through the first contact electrode CE1, so that the light emitting element LD may be prevented from being removed from the aligned position.

[0134] The second contact electrode CE2 may be disposed above the second electrode ET2 to overlap the second electrode ET2. In an embodiment, the second electrode ET2 and the second contact electrode CE2 may have shapes corresponding to each other.

[0135] In an embodiment, the second contact electrode CE2 may be disposed on at least one region of the second electrode ET2 and the second ends EP2 of the aligned plurality of light emitting elements LD in the emission region EMA, and electrically coupled to the second end EP2 and the second electrode ET2. The second end EP2 of the light emitting element LD may be electrically coupled to the second electrode ET2 through the second contact electrode CE2. In addition, the second end EP2 of the light emitting element LD may be stably fixed through the second contact electrode CE2, so that the light emitting element LD may be prevented from being removed from the aligned position.

[0136] The light emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2. The first end EP1 of the light emitting element LD is electrically coupled to the first electrode ET1, and the second end EP2 of the light emitting element LD is electrically coupled to the second electrode ET2. For example, the first end EP1 of the light emitting element LD may overlap with the first contact electrode CE1, and thus be electrically coupled to the first contact electrode CE1, and may be electrically coupled to the first electrode ET1 through the first contact electrode CE1. Likewise, the second end EP2 of the light emitting element LD may overlap with the second contact electrode CE2, and thus be electrically coupled to the second contact electrode CE2, and may be electrically coupled to the second electrode ET2 through the second contact electrode CE2.

[0137] In an embodiment, each light emitting element LD may be a rod-type light emitting element having a longitudinal direction. In addition, the light emitting element LD may include a first end EP1 disposed at one end of the light emitting element LD with respect to the longitudinal direction and electrically coupled to the first electrode ET1, and a second end EP2 disposed at the other end of the light emitting element LD with respect to the longitudinal direction and electrically coupled to the second electrode ET2. For example, in a region where the first electrode ET1 and the second electrode ET2 are disposed to face each other, each light emitting element LD may be electrically coupled between the first electrode ET1 and the second electrode ET2.

[0138] In an embodiment, each light emitting element LD may be a light emitting element made of a material having an inorganic crystal structure, and the light emitting element has an ultra-small size ranging from nanometer level to micrometer level. For example, each light emitting element LD may be an ultra-small rod-type light emitting element having a diameter D and / or a length L ranging from nanometer level to micrometer level, such as Figures 1a to 3b However, the size of the light emitting element LD may be changed in various ways according to the design conditions of each light emitting device (eg, pixel PXL) and the like.

[0139] In an embodiment, a first end EP1 of a light emitting element (e.g., an effective light emitting element completely coupled between the first electrode ET1 and the second electrode ET2) LD may be electrically coupled to the first electrode ET1 via the first contact electrode CE1. A second end EP2 of the light emitting element LD may be coupled to the second electrode ET2 via the second contact electrode CE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of the light emitting element LD may be in direct contact with the first electrode ET1 and / or the second electrode ET2, and electrically coupled to the first electrode ET1 and / or the second electrode ET2.

[0140] In an embodiment, the light emitting element LD may be prepared in a dispersed form in a predetermined solution, and then supplied to the emission area EMA by an inkjet scheme or the like. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to each emission area EMA. Here, if a predetermined alignment voltage (or alignment signal) is applied to the first electrode ET1 and the second electrode ET2, an electric field may be formed between the first electrode ET1 and the second electrode ET2, whereby the light emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2. After the light emitting element LD has been aligned, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting element LD may be reliably arranged between the first electrode ET1 and the second electrode ET2.

[0141] In the case of conventional technology, the light emitting element LD is aligned in an electrode unit in which a plurality of first electrodes ET1 and a plurality of second electrodes ET2 are arranged, and the light emitting element LD may tend to be concentrated on the periphery of the electrode unit due to interference of the electric field between the electrodes, etc. In order to solve the above-mentioned problem, an insulating dam pattern may be provided on the periphery of the electrode unit, or a coating may be formed to prevent the solution (or paste) including the light emitting element LD from diffusing. However, in the case of providing an insulating dam pattern, the light emitting element LD may be concentrated around the insulating dam pattern. In the case of providing a coating, the complexity of the manufacturing process may increase.

[0142] The light emitting device (or pixel PXL) according to the embodiment of the present disclosure can control the alignment density and alignment position of the light emitting elements LD by using the floating third electrode ET3. For example, the light emitting elements LD can be arranged to be concentrated in the central area of ​​the pixel PXL.

[0143] For example, an electric field close to zero is formed on the floating third electrode ET3. The voltage and electric field distribution may be between the first electrode and the second electrode ( Figure 6 The voltage and electric field change can affect the alignment of the light emitting element LD more significantly. Therefore, compared with the conventional technology, the first electrode and the second electrode ( Figure 6 The number of light emitting elements LD aligned around the top surface (ET1, ET1', ET2 and ET2') can be increased.

[0144] The first contact electrode CE1 and the second contact electrode CE2 may be formed on opposite ends (ie, the first end EP1 and the second end EP2) of the light emitting element LD, respectively. Therefore, the light emitting element LD may be more reliably coupled between the first electrode ET1 and the second electrode ET2.

[0145] If the first end EP1 of the light emitting element LD is electrically coupled to the first power source VDD via the first electrode ET1, the pixel circuit PXC, and / or the first power line PL1, etc., and the second end EP2 of the light emitting element LD is electrically coupled to the second power source VSS via the second electrode ET2 and / or the second power line PL2, etc., at least one light emitting element LD coupled in the forward direction between the first electrode ET1 and the second electrode ET2 may emit light at a brightness corresponding to the driving current supplied from the pixel circuit PXC, etc. Thus, the pixel PXL may emit light.

[0146] As described above, after the light emitting element LD is supplied to each emission area EMA (or while the light emitting element LD is supplied), at the step of aligning the light emitting element LD by applying a predetermined alignment voltage (or alignment signal) between the first electrode ET1 and the second electrode ET2, the arrangement of the third electrode ET3 forming an electric field can increase the first electrode and the second electrode ( Figure 6 The alignment density of the light emitting elements LD around the third electrode ET3 is controlled. Therefore, according to the arrangement position of the third electrode ET3, the density of the light emitting elements LD can be relatively easily controlled according to the position in the pixel PXL. Therefore, the brightness of the pixel PXL can be increased, and the size and shape of the emission area EMA can be easily controlled.

[0147] Figures 8a to 8d is shown with Figure 6 FIG. 4 is a cross-sectional view of an example of a cross-section corresponding to line II′ of a light-emitting device.

[0148] refer to Figures 4 to 8d , a pixel PXL or a display device including a light-emitting device may include a display element layer DPL, and the display element layer DPL includes a plurality of light-emitting elements LD arranged in an emission area EMA of each pixel PXL on a surface of a base layer BSL. In addition, the pixel PXL or the display device including the pixel PXL may further selectively include a pixel circuit layer PCL. For example, the pixel PXL or the display device including the pixel PXL may further include a pixel circuit layer PCL arranged between the base layer BSL and the display element layer DPL.

[0149] In an embodiment, the pixel circuit layer PCL may include at least one circuit element electrically coupled to the light emitting element LD. For example, the pixel circuit layer PCL may include at least one circuit element forming the pixel circuit PXC of each pixel PXL.

[0150] For example, the pixel circuit layer PCL may include a plurality of transistors T and a storage capacitor Cst, which are arranged in each pixel region and form a corresponding pixel circuit PXC, and the pixel circuit layer PCL may also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU. Here, in the case where the pixel circuit PXC is omitted and each light source unit LSU is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted. For the sake of explanation, Figures 8a to 8dOnly one transistor T among the circuit elements and lines provided on the pixel circuit layer PCL is representatively shown. Here, the plane / section structure of the pixel circuit layer PCL may be changed in various ways. The position and section structure of each transistor T may be changed in various ways according to the embodiment. In addition, Figures 8a to 8d The configuration of the transistor T′ is substantially the same as that of the transistor T, and thus the explanation of the transistor T′ overlapping with the explanation of the transistor T will be omitted.

[0151] In addition, the pixel circuit layer PCL may include a plurality of insulating layers disposed between corresponding electrodes and / or lines. In an embodiment, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the base layer BSL. In some embodiments, the pixel circuit layer PCL may also include at least one light shielding pattern (not shown) disposed under at least some of the transistors T.

[0152] The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0153] In an implementation, each transistor T may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes TE1 and TE2. Figures 8a to 8d An embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in at least one transistor T provided in each pixel region may be integrally formed with the corresponding semiconductor layer SCL.

[0154] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0155] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0156] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0157] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor layer SCL, and at least one interlayer insulating layer ILD may be interposed between the first transistor electrode TE1 and the second transistor electrode TE2 and each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on respective different ends of the semiconductor layer SCL, and a gate insulating layer GI and an interlayer insulating layer ILD may be interposed between the first transistor electrode TE1 and the second transistor electrode TE2 and respective different ends of the semiconductor layer SCL. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically coupled to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be coupled to the first region and the second region of the semiconductor layer SCL through respective contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, either one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0158] At least one transistor T provided in the pixel circuit PXC may be coupled to at least one pixel electrode. Figure 5c Any one of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 shown in FIG. 1 (e.g., the drain electrode) can be electrically coupled to the first electrodes ET1 and ET1' of the light emitting device through a contact hole (e.g., the first contact hole CH1) passing through the passivation layer PSV and through a first connection electrode CNL1 disposed above the passivation layer PSV.

[0159] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be arranged on the same layer as the layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, the scan line (e.g., the i-th scan line Si) of each pixel PXL may be arranged on the same layer as the layer of the gate electrode GE. The data line (e.g., the j-th data line Dj) of each pixel PXL may be arranged on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. In addition, the first power line PL1 and / or the second power line PL2 may be arranged on the same layer as the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2.

[0160] In an embodiment, the display element layer DPL may include a light source unit LSU for each of the pixels PXL. For example, the display element layer DPL may include a plurality of first electrodes ET1 and ET1' and a plurality of second electrodes ET2 and ET2' disposed in an emission area EMA of each pixel PXL, a plurality of light emitting elements LD and LD' disposed between adjacent first electrodes ET1 and ET1' and second electrodes ET2 and ET2', and a third electrode ET3 disposed at a preset position between the first electrodes ET1 and ET1' and the second electrodes ET2 and ET2'. In addition, the display element layer DPL may further selectively include first bank patterns PW1 and PW1', second bank patterns PW2 and PW2', and third bank patterns PW3, and first contact electrodes CE1 and CE1' and second contact electrodes CE2 and CE2', the first bank patterns PW1 and PW1', the second bank patterns PW2 and PW2', and the third bank pattern PW3 causing the regions of the first electrodes ET1 and ET1', the second electrodes ET2 and ET2', and the third electrode ET3 to protrude upward, and the first contact electrodes CE1 and CE1' and the second contact electrodes CE2 and CE2' more reliably connect the light emitting elements LD and LD' between the first electrodes ET1 and ET1' and the second electrodes ET2 and ET2'. In addition, the display element layer DPL may further include, for example, at least one conductive layer and / or insulating layer.

[0161] The first electrode ET1', the second electrode ET2', the light emitting element LD', the first contact electrode CE1', the second contact electrode CE2', the first embankment pattern PW1', the second embankment pattern PW2', the first contact portion CNT1' and the second contact portion CNT2' (which are some components of the light emitting device arranged on the right side of the third electrode ET3) may be substantially the same as the first electrode ET1, the second electrode ET2, the light emitting element LD, the first contact electrode CE1, the second contact electrode CE2, the first embankment pattern PW1, the second embankment pattern PW2, the first contact portion CNT1 and the second contact portion CNT2 (which are some components of the light emitting device arranged on the left side of the third electrode ET3), respectively. Therefore, for the sake of explanation, the description of the first electrode ET1, the second electrode ET2, the light emitting element LD, the first contact electrode CE1, the second contact electrode CE2, the first embankment pattern PW1, the second embankment pattern PW2, the first contact portion CNT1 and the second contact portion CNT2 may also be applied in the same manner to the first electrode ET1', the second electrode ET2', the light emitting element LD', the first contact electrode CE1', the second contact electrode CE2', the first embankment pattern PW1', the second embankment pattern PW2', the first contact portion CNT1' and the second contact portion CNT2'.

[0162] In an embodiment, if Figures 8a to 8d As shown in , components of the light emitting device disposed on opposite sides of the third electrode ET3 may form a symmetrical shape.

[0163] In an embodiment, the display element layer DPL may include a first embankment pattern PW1, a second embankment pattern PW2, and a third embankment pattern PW3, a first electrode ET1, a second electrode ET2, and a third electrode ET3, a first insulating layer INS1, a light emitting element LD, an insulating pattern INP, a first contact electrode CE1 and a second contact electrode CE2, and a second insulating layer INS2, which are sequentially arranged and / or formed above the base layer BSL and / or the pixel circuit layer PCL.

[0164] The first bank pattern PW1 and the second bank pattern PW2 may be disposed at positions spaced apart from each other in the emission area EMA of each pixel PXL. The first bank pattern PW1 and the second bank pattern PW2 may protrude from the base layer BSL and / or the pixel circuit layer PCL in a height direction of the base layer BSL. In an embodiment, the first bank pattern PW1 and the second bank pattern PW2 may have substantially the same height, but the present disclosure is not limited thereto.

[0165] In an implementation, a third bank pattern PW3 corresponding to the third electrode ET3 may be further disposed on the passivation layer PSV.

[0166] In an embodiment, the first bank pattern PW1 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and each first electrode ET1. The first bank pattern PW1 may be disposed adjacent to the first end EP1 of the light emitting element LD. For example, one side surface of the first bank pattern PW1 may be positioned adjacent to the first end EP1 of the light emitting element LD and disposed to face the first end EP1.

[0167] In an embodiment, the second bank pattern PW2 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and the second electrode ET2. The second bank pattern PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, one side surface of the second bank pattern PW2 may be positioned adjacent to the second end EP2 of the light emitting element LD and disposed to face the second end EP2.

[0168] In an implementation, the third bank pattern PW3 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and the third electrode ET3. The third bank pattern PW3 may be covered by the third electrode ET3.

[0169] In an embodiment, each of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may have various shapes. Figure 8a and Figure 8c As shown in , the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may have a trapezoidal cross-section whose width gradually decreases upward. In this case, each of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may have an inclined surface on at least one side. In an embodiment, as Figure 8b and Figure 8d As shown in , the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may have a semicircular or semi-elliptical cross-section, the width of which gradually decreases upward. In this case, each of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may have a curved surface on at least one side surface. At least one electrode and / or an insulating layer disposed above the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may have a curved surface in a region corresponding to the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3.

[0170] In other words, the shape of each of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may be changed in various ways without particular limitation. In an embodiment, at least one of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may be omitted or repositioned.

[0171] Each of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may include an insulating material having at least one inorganic material and / or an organic material. For example, the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may include at least one inorganic layer including various known inorganic insulating materials, such as silicon nitride (SiN x ) or silicon oxide (SiO x ). Alternatively, the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may include at least one organic layer and / or a photoresist layer including various known organic insulating materials, or may form a single-layer or multi-layer insulator including a combination of organic / inorganic materials. In an embodiment of the present disclosure, the constituent materials of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may be changed in various ways.

[0172] In an embodiment, each of the first bank pattern PW1 and the second bank pattern PW2 may be used as a reflector. For example, the first bank pattern PW1 and the second bank pattern PW2 together with the first electrode ET1 and the second electrode ET2 disposed on the first bank pattern PW1 and the second bank pattern PW2 may be used as a reflector that guides light emitted from each light emitting element LD in a desired direction, thereby enhancing light efficiency of the pixel PXL.

[0173] The first electrode ET1, the second electrode ET2, and the third electrode ET3 may be disposed over the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3, respectively. The first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 may be disposed at positions spaced apart from each other in each pixel region (particularly, each emission area EMA).

[0174] In an embodiment, the first electrode ET1, the second electrode ET2, the third electrode ET3, etc., which are respectively disposed above the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3, may have shapes corresponding to the corresponding shapes of the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3. For example, the first electrode ET1, the second electrode ET2, and the third electrode ET3 may have inclined surfaces or curved surfaces corresponding to the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3, respectively, and protrude in the height direction of the base layer BSL.

[0175] Each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may include at least one conductive material. For example, each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may include various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or alloys thereof), conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO), etc.), and conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO), etc.). 2 )) and at least one material of a conductive polymer (such as PEDOT), but the present disclosure is not limited thereto. For example, each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may include other conductive materials, such as carbon nanotubes and graphene. In other words, each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may include at least one of various conductive materials to have conductivity, and the constituent material of each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 is not particularly limited. In addition, each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may have the same conductive material or at least one different conductive material.

[0176] In an embodiment, the third electrode ET3 that is not electrically coupled to the first electrode ET1 and the second electrode ET2 may be formed by the same process as that of the first electrode ET1 and the second electrode ET2. Therefore, the third electrode ET3 may include the same material as that of the first electrode ET1 and the second electrode ET2. In addition, the third electrode ET3 may have a shape that is substantially the same as or similar to that of the first electrode ET1 and the second electrode ET2. In addition, the first electrode ET1, the second electrode ET2, and the third electrode ET3 may be formed on the same insulating layer. For example, the first electrode ET1, the second electrode ET2, and the third electrode ET3 may be disposed on the passivation layer PSV and / or respectively disposed on the first bank pattern PW1, the second bank pattern PW2, and the third bank pattern PW3 formed by the same process.

[0177] Therefore, the third electrode ET3 can be formed simultaneously with the first electrode ET1 and the second electrode ET2 through a simple scheme without using an additional material or an additional process for forming the third electrode ET3. Therefore, the cost of designing and manufacturing the third electrode ET3 is not required.

[0178] In an embodiment, each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may have a single-layer or multi-layer structure. For example, each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may include at least one reflective electrode layer. Each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may also selectively include at least one of at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive covering layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0179] In an embodiment, the reflective electrode layer of each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 may be formed of a conductive material having uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or alloys thereof), but the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials.

[0180] Each of the first electrode ET1 and the second electrode ET2 including the reflective electrode layer can enable light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting elements LD to travel in the direction of displaying the image (e.g., in the front direction). In particular, if the first electrode ET1 and the second electrode ET2 respectively have an inclined surface or a curved surface corresponding to the shape of the first bank pattern PW1 and the second bank pattern PW2, and are respectively arranged to face the first end EP1 and the second end EP2 of the light emitting element LD, the light emitted from the first end EP1 and the second end EP2 of each light emitting element LD can be reflected by the first electrode ET1 and the second electrode ET2, and thus more reliably travel in the front direction of the display panel PNL (e.g., in the upward direction of the base layer BSL). As a result, the efficiency of the light emitted from the light emitting element LD can be improved.

[0181] In addition, the transparent electrode layer of each of the first electrode ET1, the second electrode ET2 and the third electrode ET3 may be formed of various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ET1, the second electrode ET2 and the third electrode ET3 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ET1 and the second electrode ET2 are each formed by a multilayer structure including at least a double layer, the voltage drop caused by the signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting element LD.

[0182] In addition, if each of the first electrode ET1, the second electrode ET2, and the third electrode ET3 includes a conductive covering layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ET1, the second electrode ET2, and the third electrode ET3 can be prevented from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive covering layer may be selectively included in the first electrode ET1, the second electrode ET2, and the third electrode ET3, and may be omitted according to the embodiment. In addition, the conductive covering layer may be considered as a component of each of the first electrode ET1, the second electrode ET2, and the third electrode ET3, or as a separate component provided on the first electrode ET1, the second electrode ET2, and the third electrode ET3.

[0183] The first insulating layer INS1 may be disposed on predetermined regions of the first electrode ET1, the second electrode ET2, and the third electrode ET3. For example, the first insulating layer INS1 may be formed to cover predetermined regions of the first electrode ET1, the second electrode ET2, and the third electrode ET3, and may include openings to expose other predetermined regions of the first electrode ET1, the second electrode ET2, and the third electrode ET3. For example, the first insulating layer INS1 may expose the first electrode ET1 in a predetermined first contact portion CNT1 and expose the second electrode ET2 in a predetermined second contact portion CNT2. In some embodiments, the first insulating layer INS1 may be omitted. In this case, the light emitting element LD may be directly disposed on one end of each of the first electrode ET1 and the second electrode ET2 and / or the passivation layer PSV.

[0184] In an embodiment, the first insulating layer INS1 may be first formed to cover the entire surface of the first electrode ET1, the second electrode ET2, and the third electrode ET3. After the light emitting element LD is supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ET1 and the second electrode ET2 in the corresponding predetermined regions (e.g., the corresponding first contact portion CNT1 and the second contact portion CNT2) on the first bank pattern PW1 and the second bank pattern PW2. In an embodiment, the first insulating layer INS1 may be patterned in the form of a separate pattern partially disposed under the light emitting element LD after the supply and alignment of the light emitting element LD have been completed.

[0185] In other words, the first insulating layer INS1 may be interposed between the first and second electrodes ET1 and ET2 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ET1 and ET2. After forming the first, second, and third electrodes ET1, ET2, and ET3, the first insulating layer INS1 may be formed to cover the first, second, and third electrodes ET1, ET2, and ET3, so that the first, second, and third electrodes ET1, ET2, and ET3 may be prevented from being damaged, or metal may be prevented from being deposited in a subsequent process. In addition, the first insulating layer INS1 may stably support each light emitting element LD.

[0186] The first insulating layer INS1 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or organic insulating material. For example, the first insulating layer INS1 may include various organic / inorganic insulating materials, and the various organic / inorganic insulating materials include silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ) etc. The constituent material of the first insulating layer INS1 is not particularly limited.

[0187] A plurality of light emitting elements LD may be supplied to each pixel region (particularly, an emission region EMA of each pixel PXL) in which the first insulating layer INS1 is formed and aligned in the pixel region. For example, a plurality of light emitting elements LD may be supplied to each emission region EMA by an inkjet method or the like, and the light emitting elements LD may be aligned between the first electrode ET1 and the second electrode ET2 with a predetermined directivity by applying a predetermined alignment voltage (or alignment signal) to the first electrode ET1 and the second electrode ET2.

[0188] Here, due to the floating third electrode ET3 , the arrangement of the light emitting element LD may be concentrated between the first electrode ET1 and the second electrode ET2 adjacent to the third electrode ET3 .

[0189] In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first electrodes ET1 and second electrodes ET2 in a horizontal direction so that opposite ends (i.e., first ends EP1 and second ends EP2) of each light emitting element LD with respect to a longitudinal direction thereof overlap with the pair of first electrodes ET1 and second electrodes ET2. In addition, in an embodiment, other some of the light emitting elements LD may be disposed between the pair of first electrodes ET1 and second electrodes ET2 in a diagonal direction. In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first electrodes ET1 and second electrodes ET2 so that at least some of the light emitting elements LD do not overlap with the first electrodes ET1 and second electrodes ET2, and may be coupled to the first electrodes ET1 and second electrodes ET2 through first contact electrodes CE1 and second contact electrodes CE2, respectively.

[0190] The insulating pattern INP may be disposed on a predetermined region of the light emitting element LD. For example, the insulating pattern INP may expose the first end EP1 and the second end EP2 of the light emitting element LD, and may be disposed only partially above a predetermined region of the light emitting element LD, the predetermined region of the light emitting element LD including a corresponding central region of the light emitting element LD. The insulating pattern INP may be formed in an independent pattern in each emission region EMA, but the present disclosure is not limited thereto. The insulating pattern INP may be omitted according to an embodiment. In this case, the opposite ends of the first contact electrode CE1 and the second contact electrode CE2 may be disposed directly on the light emitting element LD.

[0191] The insulating pattern INP may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or an organic insulating material. For example, the insulating pattern INP may include various organic / inorganic insulating materials, and the various organic / inorganic insulating materials include silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ), photoresist (PR) material, etc. The constituent material of the insulating pattern INP is not particularly limited.

[0192] After the alignment of the light emitting element LD has been completed, the insulating pattern INP is formed on the light emitting element LD so that the light emitting element LD can be prevented from being removed from the aligned position. In addition, in the case where there is a space between the first insulating layer INS1 and the light emitting element LD, the space can be filled with the insulating material sucked therein during the process of forming the insulating pattern INP. Therefore, the light emitting element LD can be supported more stably.

[0193] The opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting element LD that are not covered by the insulating pattern INP may be covered by the first contact electrode CE1 and the second contact electrode CE2, respectively. For example, a corresponding end of the first contact electrode CE1 and a corresponding end of the second contact electrode CE2 may be disposed on the first end EP1 and the second end EP2 of the light emitting element LD at positions spaced apart from each other, and the insulating pattern INP is interposed between the corresponding end of the first contact electrode CE1 and the corresponding end of the second contact electrode CE2.

[0194] In an embodiment, the first contact electrode CE1 and the second contact electrode CE2 may be simultaneously formed on the same layer on one surface of the base layer BSL, such as Figure 8a and Figure 8b As shown in . Therefore, the process of manufacturing the pixel PXL and the display device including the pixel PXL can be simplified. For example, compared with the case where the first contact electrode CE1 and the second contact electrode CE2 are formed by corresponding mask processes, the number of mask processes required to form the pixel PXL can be reduced, and the first contact electrode CE1 and the second contact electrode CE2 can be more easily formed.

[0195] In an embodiment, the first contact electrode CE1 and the second contact electrode CE2 may be sequentially formed on different layers on one surface of the base layer BSL, such as Figure 8c and Figure 8d As shown in . An additional third insulating layer INS3 may be disposed between the first contact electrode CE1 and the second contact electrode CE2. In other words, the positions and relative disposition relationship of the first contact electrode CE1 and the second contact electrode CE2 may be changed in various ways.

[0196] In addition, the first contact electrode CE1 and the second contact electrode CE2 may be disposed above the first electrode ET1 and the second electrode ET2 to cover the exposed regions (e.g., the first contact portion CNT1 and the second contact portion CNT2) of the first electrode ET1 and the second electrode ET2. For example, the first contact electrode CE1 and the second contact electrode CE2 may be disposed on at least predetermined regions of the first electrode ET1 and the second electrode ET2 to contact the first electrode ET1 and the second electrode ET2 in the first contact portion CNT1 and the second contact portion CNT2. Therefore, the first contact electrode CE1 and the second contact electrode CE2 may be electrically coupled to the first electrode ET1 and the second electrode ET2, respectively. The first electrode ET1 and the second electrode ET2 may be electrically coupled to the first end EP1 and the second end EP2 of the light emitting element LD, respectively, through the first contact electrode CE1 and the second contact electrode CE2.

[0197] In an embodiment, the first contact electrode CE1 and the second contact electrode CE2 may be formed of various transparent conductive materials. For example, the first contact electrode CE1 and the second contact electrode CE2 may include at least one of various transparent conductive materials (including ITO, IZO and ITZO), and may be substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from the light emitting element LD through the first end EP1 and the second end EP2 may be emitted to the outside of the display device through the first contact electrode CE1 and the second contact electrode CE2.

[0198] The second insulating layer INS2 may be disposed on the first contact electrode CE1 and the second contact electrode CE2. For example, the second insulating layer INS2 may be formed in the display area DA and / or disposed on the entire surface of the base layer BSL on which the first bank pattern PW1 and the second bank pattern PW2, the first electrode ET1 and the second electrode ET2, the light emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2 are formed, so that the second insulating layer INS2 may cover the first bank pattern PW1 and the second bank pattern PW2, the first electrode ET1 and the second electrode ET2, the light emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2.

[0199] In an implementation, the second insulating layer INS2 may be provided to cover the exposed third electrode ET3 .

[0200] The second insulating layer INS2 may include at least one inorganic layer and / or organic layer.

[0201] In an embodiment, the second insulating layer INS2 may include a thin film encapsulation layer having a multi-layer structure, but the present disclosure is not limited thereto. In some embodiments, at least one overcoat layer and / or an encapsulation substrate, etc. may be further disposed over the second insulating layer INS2.

[0202] In an embodiment, the second insulating layer INS2 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or organic insulating material. For example, the second insulating layer INS2 may include various known organic / inorganic insulating materials, including silicon nitride (SiN x ), silicon oxide (SiO x ) etc. The constituent material of the second insulating layer INS2 is not particularly limited.

[0203] Fig. 9 is a plan view showing a light emitting device according to an embodiment of the present disclosure.

[0204] In an embodiment, Fig. 9 Shown according to Figures 6 to 8dThe same reference numerals are used to designate components that are the same as or similar to those of the above-described embodiment, and a detailed description thereof will be omitted.

[0205] refer to Figure 6 and Fig. 9 , the light emitting device may include first and second electrodes ETS1 and ETS2 arranged in a first direction DR1 and a plurality of third electrodes ET31 and ET32 disposed at a preset interval.

[0206] In an embodiment, the first electrode ETS1 may be connected to the first connection electrode (eg, Figure 6 The first electrodes ETS1 may be connected to a predetermined circuit element, a power line and / or a signal line. All of the first electrodes ETS1 may be connected to the same first connection electrode. Alternatively, at least some of the first electrodes ETS1 may be connected to different first connection electrodes.

[0207] The second electrode ETS2 can be connected by a second connecting electrode (eg, Figure 6 CNL2 of the second electrodes ETS2 is connected to a predetermined circuit element, a power line and / or a signal line. All of the second electrodes ETS2 may be connected to the same second connection electrode. Alternatively, at least some of the second electrodes ETS2 may be connected to different second connection electrodes.

[0208] The adjacent first and second electrodes (for example, Figure 6 ET1 and ET2 of FIG. 1 may form an electrode pair. The light emitting element LD may be electrically connected to the electrode pair.

[0209] In an embodiment, the third electrodes ET31 and ET32 may be arranged at regular intervals. Fig. 9 As shown in FIG. 1 , the third electrodes ET31 and ET32 may be disposed with six electrode pairs (ie, six first electrodes and six second electrodes alternately disposed) interposed therebetween. However, this is merely for illustrative purposes, and the intervals at which the third electrodes ET31 and ET32 are disposed are not limited thereto.

[0210] In an embodiment, electrodes having the same polarity may be provided on opposite sides of each of the third electrodes ET31 and ET32. Here, the electrodes having the same polarity may be electrodes supplied with the same alignment voltage at the step of aligning the light emitting element LD. For example, at the step of aligning the light emitting element LD, the first electrodes ETS1 may be commonly supplied with a first alignment voltage. At the step of aligning the light emitting element LD, the second electrodes ETS2 may be commonly supplied with a second alignment voltage different from the first alignment voltage.

[0211] For example, some of the second electrodes ETS2 may be disposed on opposite sides of the first third electrode ET31 and oriented to face the first third electrode ET31. Some of the first electrodes ETS1 may be disposed on opposite sides of the second third electrode ET32 and oriented to face the second third electrode ET32. Since the same voltage is applied to the electrodes disposed on opposite sides of each of the third electrodes ET31 and ET32 when the first alignment voltage and the second alignment voltage are applied at the step of aligning the light emitting element LD, the light emitting element LD adjacent to the third electrodes ET31 and ET32 may move away from the third electrodes ET31 and ET32.

[0212] In addition, the third electrodes ET31 and ET32 to which no voltage is applied may not form an electric field. Therefore, the light emitting element LD may move toward other electrodes disposed around the third electrodes ET31 and ET32, rather than being aligned or guided toward the third electrodes ET31 and ET32. Therefore, the arrangement of the light emitting element LD may be concentrated on the electrode pair adjacent to the third electrode ET3.

[0213] like Fig. 9 As shown in , the number of light emitting elements LD disposed on the first electrode pair may be greater than the number of light emitting elements LD disposed on the second electrode pair, wherein the first electrode pair is the electrode pair closest to each of the third electrodes ET31 and ET32, and the second electrode pair is disposed at a position farther away from each of the third electrodes ET31 and ET32 than the first electrode pair. In addition, the farther away from the third electrodes ET31 and ET32, the smaller the density of the light emitting elements LD disposed on the electrode pair (or the number of the light emitting elements LD) may be.

[0214] In this way, since the floating third electrodes ET31 and ET32 are disposed between the predetermined electrode pairs, the number of light emitting elements LD (or effective light emitting elements LD) around the third electrodes ET31 and ET32 can be increased. Therefore, the emission uniformity and brightness per unit surface area around the third electrodes ET31 and ET32 can be improved.

[0215] In an embodiment, based on Fig. 9 The electrodes shown in FIG. 1 are arranged to define boundaries between pixels so that the emission brightness of the pixels can be controlled.

[0216] In an embodiment, the third electrodes ET31 and ET32 may be formed simultaneously with the first electrodes ETS1 and the second electrodes ETS2 by a patterning process for forming the first electrodes ETS1 and the second electrodes ETS2. For example, the third electrodes ET31 and ET32 may be formed by patterning additional regions so that some of the first electrodes ETS1 and the second electrodes ETS2 are disconnected relative to other elements. In this way, the third electrodes ET31 and ET32 may be formed to be floating and to ensure a predetermined spacing distance between electrodes having the same polarity without increasing manufacturing costs.

[0217] Fig.10 is a plan view showing a display device according to an embodiment of the present disclosure, and shows, for example, an embodiment in which pixels forming the display device are formed.

[0218] In an embodiment, Fig.10 The structure of the pixels PXL1 and PXL2 is shown focusing on the display element layer on which the light emitting elements LD1 and LD2 of the pixels PXL1 and PXL2 are provided.

[0219] refer to Figures 4 to 6 and Fig.10 , the pixels PXL1 and PXL2 may be disposed on a substrate (or Figure 4 In the display area DA on the base layer BSL).

[0220] Each of the first pixel PXL1 and the second pixel PXL2 may include at least one pair of first and second electrodes ET1 and ET2 and an emission area EMA in which at least one light emitting element LD coupled between the first electrode ET1 and the second electrode ET2 is disposed. Fig.10 As shown in FIG. 1 , each of the first pixel PXL1 and the second pixel PXL2 may include three first electrodes ET1 and three second electrodes ET2 .

[0221] In an embodiment, the first pixel PXL1 may include a plurality of first electrodes ET11, ET12, and ET13 and a plurality of second electrodes ET21, ET22, and ET23 disposed at positions spaced apart from each other in the corresponding emission area EMA, and a plurality of first light emitting elements LD1 coupled between the first electrodes ET11, ET12, and ET13 and the second electrodes ET21, ET22, and ET23 adjacent to each other.

[0222] In an embodiment, the second pixel PXL2 may include a plurality of first electrodes ET14, ET15 and ET16 and a plurality of second electrodes ET24, ET25 and ET26 disposed at positions spaced apart from each other in the corresponding emission area EMA, and a plurality of second light emitting elements LD2 connected between the first electrodes ET14, ET15 and ET16 and the second electrodes ET24, ET25 and ET26 adjacent to each other.

[0223] In an embodiment, the first pixel PXL1 may further include a Fig.10 The first connection electrode CNL11 and the second connection electrode CNL2 in the embodiment overlap the bank BNK.

[0224] In an embodiment, the first electrodes ET11, ET12, and ET13 of the first pixel PXL1 may be coupled to the first connection electrode CNL11. For example, the first electrodes ET11, ET12, and ET13 may be integrally coupled to the first connection electrode CNL11. For example, the first electrodes ET11, ET12, and ET13 may be formed by at least one branch branched from the first connection electrode CNL11. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first electrodes ET11, ET12, and ET13 and the first connection electrode CNL11 may be formed separately and electrically coupled to each other through at least one contact hole, a through hole, or the like not shown.

[0225] In an embodiment, the first electrodes ET11, ET12, and ET13 and the first connection electrode CNL11 may extend in different directions. For example, when the first connection electrode CNL11 extends in a first direction DR1, the first electrodes ET11, ET12, and ET13 may extend in a second direction DR2 intersecting the first direction DR1.

[0226] In an embodiment, the second electrodes ET21, ET22, and ET23 may be coupled to the second connection electrode CNL2. For example, the second electrodes ET21, ET22, and ET23 may be integrally coupled to the second connection electrode CNL2. For example, the second electrodes ET21, ET22, and ET23 may be formed by at least one branch branched from the second connection electrode CNL2. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the second electrodes ET21, ET22, and ET23 and the second connection electrode CNL2 may be formed separately and electrically coupled to each other through at least one contact hole, through hole, etc. not shown.

[0227] In an embodiment, the second electrodes ET21, ET22, and ET23 and the second connection electrode CNL2 may extend in different directions. For example, when the second connection electrode CNL2 extends in the first direction DR1, the second electrodes ET21, ET22, and ET23 may extend in the second direction DR2.

[0228] The second pixel PXL2 may further include a Fig.10 The first connection electrode CNL12 and the second connection electrode CNL2 (overlapping with the bank BNK).

[0229] In an embodiment, the first connection electrodes CNL11 and CNL12 of each of the first pixel PXL1 and the second pixel PXL2 may be electrically (and physically) separated from each other between the first pixel PXL1 and the second pixel PXL2. The second connection electrodes CNL2 of the first pixel PXL1 and the second pixel PXL2 may extend integrally. Therefore, the first light emitting element LD1 included in the first pixel PXL1 and the second light emitting element LD2 included in the second pixel PXL2 may emit light, respectively.

[0230] In an embodiment, the first pixel PXL1 and the second pixel PXL2 may have substantially the same or similar structures. Alternatively, the first pixel PXL1 and the second pixel PXL2 may have substantially symmetrical structures based on the third electrode ET3. For the sake of explanation, hereinafter, any one of the first pixel PXL1 and the second pixel PXL2 will be collectively referred to as "pixel PXL", and at least one first light emitting element LD1 or second light emitting element LD2 provided in the pixel PXL will be collectively referred to as "light emitting element LD".

[0231] In an embodiment, the first light emitting element LD1 and the second light emitting element LD2 may emit light of the same color or different colors. For example, all of the first light emitting element LD1 and the second light emitting element LD2 may be formed of a blue light emitting diode that emits blue light. Alternatively, the first light emitting element LD1 and the second light emitting element LD2 may emit one of red light, green light, and blue light. However, this is only for illustrative purposes, and the color of light emitted from the first light emitting element LD1 and the second light emitting element LD2 is not limited thereto.

[0232] The third electrode ET3 may not be electrically coupled to the first electrode ET1 and the second electrode ET2. The third electrode ET3 may be disposed to be spaced apart from the first electrode ET1 and the second electrode ET2. In an embodiment, the third electrode ET3 may be disposed on one side of the first pixel PXL1 in a non-emission region. For example, the third electrode ET3 may be disposed in a non-emission region between the emission region EMA of the first pixel PXL1 and the emission region EMA of the second pixel PXL2.

[0233] The first and second electrodes ET11 , ET12 , and ET13 and ET21 , ET22 , and ET23 of the first pixel PXL1 and the first and second electrodes ET14 , ET15 , and ET16 and ET24 , ET25 , and ET26 of the second pixel PXL2 may form a shape symmetrical based on the third electrode ET3 .

[0234] In an embodiment, the density of the light emitting elements LD of the first pixel PXL1 and the second pixel PXL2 may be increased in a direction from the center of each emission area EMA toward the third electrode ET3. For example, the first light emitting elements LD1 may be concentrated on the right side of the emission area EMA of the first pixel PXL1, and the second light emitting elements LD2 may be concentrated on the left side of the emission area EMA of the second pixel PXL2.

[0235] In an embodiment, the third electrode ET3 may be disposed on the right side of the emission area EMA of the first pixel PXL1 and on the left side of the emission area EMA of the second pixel PXL2. In this case, the light emitting elements LD may be concentrated on the opposite sides of the emission areas EMA of the corresponding pixels PXL. For example, the density of the light emitting elements LD may be the lowest in the central portion of the emission area EMA, and the density of the light emitting elements LD may increase in a direction from the center toward the opposite side.

[0236] Figures 11a to 11c is shown with Fig.10 A cross-sectional view of an example of a cross section corresponding to line II-II' of a display device.

[0237] For convenience, Fig.10 Based on reference Figures 6 to 8d Some components of the display element layer DPL and the pixel circuit layer PCL described in detail schematically illustrate structures of the display element layer DPL and the pixel circuit layer PCL, and a detailed description thereof will be omitted. Figures 11a to 11c Some emission areas and non-emission areas of pixels PXL1 and PXL2 adjacent to each other are shown.

[0238] refer to Figure 4 , Fig.10 and Figures 11a to 11c , the display device may include first electrodes ET11 to ET16 , second electrodes ET21 to ET26 , a third electrode ET3 , light emitting elements LD1 and LD2 , and a bank BNK disposed on a first substrate SUB1 .

[0239] In an embodiment, the first substrate SUB1 may be composed of Figure 4 It can be achieved by the basal layer BSL, etc.

[0240] The third electrode ET3 may be disposed in a non-emission region defining a boundary between the first pixel PXL1 and the second pixel PXL2 . Figures 11a to 11c An electrode pair of first electrodes ET11 and ET14 and second electrodes ET21 and ET24 disposed in the outermost portions of the first pixel PXL1 and the second pixel PXL2 is shown.

[0241] In an embodiment, the light emitting element LD may be directly coupled between the first electrode ET1 and the second electrode ET2 adjacent to each other. Fig.11a As shown in FIG. 1 , there is no bank pattern overlapping each of the first and second electrodes ET11 and ET14 and ET21 and ET24 under the first and second electrodes ET11 and ET14. The third electrode ET3 may be formed by the same process as that of the first and second electrodes ET1 and ET2.

[0242] In an embodiment, if Fig.11b As shown in FIG. 1 , the first bank patterns PW11 and PW14 and the second bank patterns PW21 and PW24 may be disposed respectively under the first electrodes ET11 and ET14 and the second electrodes ET21 and ET24. In the region where the first bank patterns PW11 and PW14 and the second bank patterns PW21 and PW24 are disposed, the first electrodes ET11 and ET14 and the second electrodes ET21 and ET24 may protrude upward. Therefore, light emitted from the opposite ends (or side walls) of the light emitting element LD may be controlled to travel more reliably in the front direction of the display device.

[0243] In addition, if Fig.11c As shown in , a third bank pattern PW3 having a separate pattern structure may also be disposed under the third electrode ET3. For example, when the electrodes ET1, ET2, and ET3 and the bank patterns PW1, PW2, and PW3 are formed at regular intervals, the floating third electrode ET3 may be formed during an existing manufacturing process.

[0244] In an embodiment, the bank BNK covering the third electrode ET3 may be disposed in the non-emission region. The bank BNK may be disposed to surround the pixel PXL. For example, the bank BNK may be formed between the pixels PXL to surround the emission area EMA, so that a pixel defining layer for defining the emission area EMA of each pixel PXL may be formed.

[0245] In an embodiment, the bank BNK may be formed to have a height greater than that of the first bank pattern PW1 and the second bank pattern PW2 (and the third bank pattern PW3). At the step of supplying the light emitting element LD to each emission area EMA, the bank BNK may serve as a dam structure configured to prevent the solution mixed with the light emitting element LD from being sucked into the emission area EMA of the adjacent pixel PXL, or to control the amount of the solution so that a constant amount of the solution is supplied to each emission area EMA.

[0246] According to an embodiment, the bank BNK may have various shapes. In an embodiment, the bank BNK may have a trapezoidal cross-section whose width decreases upward. For example, the bank BNK may have an inclined surface whose width decreases upward in a region connected to the emission area EMA of each pixel PXL. In an embodiment, the bank BNK may have a curved surface whose width decreases upward in a region connected to the emission area EMA of each pixel PXL. In an embodiment, the bank BNK may have a shape whose width decreases upward, and its shape may be changed in various ways.

[0247] In addition, the bank BNK may be formed to prevent light emitted from each emission area EMA from entering the adjacent emission area EMA and causing optical interference. To this end, the bank BNK may be formed to prevent light emitted from the light emitting element LD of each pixel PXL from passing through the bank BNK.

[0248] For example, the bank BNK may be formed of a color bank including a color filter material for blocking light of a predetermined color and / or wavelength emitted from the first light emitting element LD1 and the second light emitting element LD2. In an embodiment, the color bank may include a color pigment (or color dye) having a color different from the color of the light emitted from the first light emitting element LD1 and the second light emitting element LD2. For example, the bank BNK may be formed of at least one color bank layer including a color filter material for blocking light of a predetermined color and / or wavelength emitted from the first light emitting element LD1 and the second light emitting element LD2. Therefore, the bank BNK may be used as a light shielding layer configured to prevent light emitted from the first light emitting element LD1 and the second light emitting element LD2 from leaking into the adjacent emission area EMA.

[0249] In an embodiment, the light emitting elements LD may emit light having the same color. For example, all of the light emitting elements LD may be blue light emitting elements configured to emit blue light. In this case, the bank BNK may include a color filter material configured to block light having a blue wavelength band and allow light having a wavelength band different from the blue wavelength band (e.g., light having a predetermined color and a wavelength band different from the blue wavelength band) to selectively pass through the bank BNK.

[0250] For example, the bank BNK may include a red-based color filter material for allowing light having a wavelength band relatively far from a blue wavelength band in the visible ray region (eg, red light) to selectively pass therethrough. However, the material of the bank BNK is not limited to the foregoing materials.

[0251] For example, all of the light emitting elements LD may emit blue light, and the bank BNK may include a yellow-based color filter material. Alternatively, the bank BNK may include color filter materials of at least two colors. For example, the bank BNK may be formed of an orange bank including a combination of a red pigment and a yellow pigment.

[0252] In this way, if the bank BNK is formed to include a color filter material for blocking light of a predetermined color emitted from the light emitting element LD of each pixel PXL, the bank BNK can be formed without using a black matrix material such as carbon black and also effectively prevent light from leaking between adjacent pixels PXL.

[0253] In an embodiment, a fourth insulating layer (not shown) may be provided on which the first and second electrodes ET1 and ET2, the light emitting element LD, the first contact electrode CE1 (refer to Figure 6 ,For example, Fig.11b and Fig.11c CE11 and CE14 in the reference electrode and the second contact electrode CE2 (reference Figure 6 ,For example, Fig.11b and Fig.11c For example, the fourth insulating layer may be formed on the entire surface of the display area DA to cover the first substrate SUB1 (or Figure 4 The fourth insulating layer may include an upper surface of a base layer BSL on which the first and second electrodes ET1 and ET2, the light emitting element LD, the first and second contact electrodes CE1 and CE2, the bank BNK, etc. are disposed. In an embodiment, the fourth insulating layer may include not only at least one inorganic layer and / or organic layer for protecting components of the display element layer DPL, but also various functional layers, etc.

[0254] Fig.12 is a cross-sectional view showing a display device according to an embodiment of the present disclosure, and is a cross-sectional view showing Fig.10 A cross-sectional view of an example of a cross section corresponding to line II-II'.

[0255] In an embodiment, Fig.12 2 shows a predetermined area in which some pixels PXL are disposed in a display panel PNL formed by bonding an upper panel and a lower panel to each other. Fig.12 Based on Figures 6 to 8d as well as Figures 11a to 11cSome components of the lower panel described in detail in Schematic diagrams illustrate the structure of the lower panel, and a detailed description thereof will be omitted.

[0256] refer to Figure 4 and Fig.12 The display device may include a second substrate SUB2 and a light conversion pattern layer LCP, the second substrate SUB2 being disposed on a surface of the first substrate SUB1 on which the first pixel PXL1 and the second pixel PXL2 are disposed, and the light conversion pattern layer LCP being disposed on a surface of the second substrate SUB2 to face each of the first pixel PXL1 and the second pixel PXL2.

[0257] In an embodiment, the second substrate SUB2 may be disposed over the first substrate SUB1 to cover the display area DA in which at least the pixels PXL are disposed. The second substrate SUB2 may form an upper substrate (eg, an encapsulation substrate or a thin film encapsulation layer) and / or a window assembly of the display panel PNL.

[0258] In an embodiment, the second substrate SUB2 may be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. In addition, the second substrate SUB2 may be formed of the same material as the first substrate SUB1, or may be formed of a material different from that of the first substrate SUB1.

[0259] In an embodiment, the light conversion pattern layer LCP may include a first light conversion pattern layer LCP1 disposed to face the first pixel PXL1 and a second light conversion pattern layer LCP2 disposed to face the second pixel PXL2. In an embodiment, at least some of the first light conversion pattern layer LCP1 and the second light conversion pattern layer LCP2 may include a color conversion layer CCL and / or a color filter CF corresponding to a predetermined color.

[0260] For example, the first light conversion pattern layer LCP1 may include a first color conversion layer CCL1 and a first color filter CF1, the first color conversion layer CCL1 includes first color conversion particles corresponding to a first color, and the first color filter CF1 is configured to allow light of the first color to selectively pass therethrough. Similarly, the second light conversion pattern layer LCP2 may include a second color conversion layer CCL2 and a second color filter CF2, the second color conversion layer CCL2 includes second color conversion particles corresponding to a second color, and the second color filter CF2 is configured to allow light of the second color to selectively pass therethrough.

[0261] In an embodiment of the present disclosure, the first light emitting element LD1 and the second light emitting element LD2 may emit light having the same color or different colors. The color conversion layer CCL may be disposed above at least some of the first pixel PXL1 and the second pixel PXL2. For example, the first color conversion layer CCL1 and the second color conversion layer CCL2 may be disposed on the first pixel PXL1 and the second pixel PXL2, respectively. Although not shown, color conversion layers having different colors corresponding to three or more pixels adjacent to each other may be disposed. Therefore, the display device according to an embodiment of the present disclosure may display a full-color image.

[0262] In an embodiment, the first color conversion layer CCL1 may include first color conversion particles that convert the color of light emitted from the first light emitting element LD1 into light of a first color. For example, in a case where the first light emitting element LD1 is a blue light emitting element configured to emit blue light and the first pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include first quantum dots QD1 that convert the blue light emitted from the first light emitting element LD1 into red light. For example, the first color conversion layer CCL1 may include a plurality of first quantum dots QD1 distributed in a predetermined matrix material such as a transparent resin. The first quantum dots QD1 may absorb blue light and shift the wavelength of the light according to energy conversion, thereby emitting red light having a wavelength ranging from 620 nm to 780 nm. In a case where the first pixel PXL1 is one of pixels having other colors, the first color conversion layer CCL1 may include quantum dots corresponding to the color of the first pixel PXL1.

[0263] In an embodiment, the first color filter CF1 may be disposed between the first color conversion layer CCL1 and the second substrate SUB2, and include a color filter material that allows light of the first color converted by the first color conversion layer CCL1 to selectively pass therethrough. For example, in the case where the first color conversion layer CCL1 includes the first quantum dots QD1, the first color filter CF1 may be a red color filter configured to allow red light to selectively pass therethrough.

[0264] In an embodiment, the second color conversion layer CCL2 may include second color conversion particles that convert the color of light emitted from the second light emitting element LD2 into light of a second color. For example, in the case where the second light emitting element LD2 is a blue light emitting element configured to emit blue light and the second pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include second quantum dots QD2 that convert the blue light emitted from the second light emitting element LD2 into green light. In the case where the second pixel PXL2 is one of the pixels having other colors, the second color conversion layer CCL2 may include quantum dots corresponding to the color of the second pixel PXL2.

[0265] Each of the first quantum dot and the second quantum dot can be a nanoparticle, a nanotube, a nanowire, a nanofiber, for example, in the form of a nanoparticle having a spherical shape, a pyramid shape, a multi-arm shape or a cubic shape, but is not limited thereto. In other words, the shapes of the first quantum dot and the second quantum dot can be changed in various ways.

[0266] In an embodiment, the second color filter CF2 may be disposed between the second color conversion layer CCL2 and the second substrate SUB2, and include a color filter material that allows light of the second color converted by the second color conversion layer CCL2 to selectively pass therethrough. For example, in the case where the second color conversion layer CCL2 includes green quantum dots QD2, the second color filter CF2 may be a green color filter configured to allow green light to selectively pass therethrough.

[0267] In an embodiment, in at least one of the pixels PXL, a light scattering layer may be disposed between the pixel PXL and the color filter CF instead of the color conversion layer CCL.

[0268] In an embodiment, when the light emitting element LD is a blue light emitting element configured to emit blue light and the pixel PXL is a blue pixel, a light scattering layer may be selectively provided to effectively utilize the light emitted from the light emitting element LD. The light scattering layer may include at least one of the light scattering particles. For example, the light scattering layer may include light scattering particles (not shown), such as TiO 2 Or silicon dioxide. For example, the light scattering layer may include a plurality of light scattering particles dispersed in a predetermined matrix material (such as a transparent resin). In the present disclosure, the material of the light scattering particles is not particularly limited, and the light scattering layer may be formed by various known materials.

[0269] In an implementation, the black matrix BM may be disposed between the color filters CF. For example, the black matrix BM may be disposed on the second substrate SUB2 to overlap the bank BNK on the first substrate SUB1. The black matrix BM may correspond to the non-emission area NEMA.

[0270] In the aforementioned embodiment, each pixel PXL using the light emitting element LD for emitting light of the same color and a display device including the pixel PXL can be easily manufactured. Since the color conversion layer CCL is provided on at least some of the pixels PXL, a full-color pixel PXL and a display device including the full-color pixel PXL can be manufactured.

[0271] Fig.13 is a diagram illustrating an embodiment of a pixel included in a display device according to an embodiment of the present disclosure.

[0272] In an embodiment, Fig.13Shown according to Fig.10 The same reference numerals are used to denote components that are the same as or similar to those of the above-described embodiments, and a detailed description thereof will be omitted. In addition to the arrangement of the third electrodes ET31 and ET32 and the position of the emission area EMA defining the pixel PXL, Fig.13 The pixel PXL can be configured with Fig.10 The configurations of the pixels PXL are substantially the same or similar.

[0273] refer to Fig.13 , each of the floating third electrodes ET31 and ET32 may be disposed in the emission area EMA of the corresponding pixel PXL.

[0274] In an embodiment, each pixel PXL may include twelve first electrodes ET1 and twelve second electrodes ET2. Each of the third electrodes ET31 and ET32 may be disposed in a central portion of the corresponding first and second electrodes ET1 and ET2. For example, the first and second electrodes ET1 and ET2 in each pixel PXL may be disposed substantially symmetrically based on each corresponding third electrode ET31 and ET32.

[0275] For example, in the first pixel PXL1, some of the second electrodes ET2 may be respectively disposed to face the third electrode ET31 on opposite sides of the third electrode ET31. In the second pixel PXL2, some of the first electrodes ET1 may be respectively disposed adjacent to the third electrode ET32 on opposite sides of the third electrode ET32.

[0276] During the process of applying the first alignment voltage and the second alignment voltage, the light emitting element LD adjacent to the third electrodes ET31 and ET32 where no electric field is formed may be moved toward other electrodes disposed around the third electrodes ET31 and ET32 and aligned around these other electrodes. In addition, since the electrodes to which the same alignment voltage is applied are disposed on opposite sides of the third electrodes ET31 and ET32, the arrangement of the light emitting element LD may be concentrated on the electrode pair of the first electrode ET1 and the second electrode ET2 adjacent to the third electrodes ET31 and ET32. Therefore, the arrangement and emission of the light emitting element LD may be concentrated in the central region of each of the pixels PXL.

[0277] Fig.14 is a diagram illustrating an embodiment of a pixel included in a display device according to an embodiment of the present disclosure.

[0278] In an embodiment, Fig.14 Shown according to Fig.10 and Fig.13The same reference numerals are used to designate components that are the same as or similar to those of the above-described embodiment, and a detailed description thereof will be omitted.

[0279] refer to Fig.14 , the floating third electrode ET3 may be disposed in the emission area EMA of each pixel PXL. In addition, in the emission area EMA, respective numbers of the first and second electrodes ET1 and ET2 disposed on opposite sides of the third electrode ET3 may be different from each other.

[0280] For example, Fig.14 As shown in, in the emission area EMA, six electrodes may be arranged on the first side (e.g., the left side) of the third electrode ET3, and three electrodes may be arranged on the second side (e.g., the right side) of the third electrode ET3. However, this is only for illustrative purposes, and the position of the third electrode ET3 arranged in the emission area EMA and the number of the first electrode ET1 and the second electrode ET2 are not limited thereto. In addition, at least two third electrodes ET3 may be arranged in the emission area EMA.

[0281] The number of light emitting elements LD concentrated on the electrode pair disposed on the opposite sides of the third electrode ET3 can be maximized. Fig.14 As shown in , in order to concentrate the light emitting element LD on the central portion of the emission area EMA, the third electrode ET3 may be disposed at a position deviated from the central portion of the emission area EMA.

[0282] As described above, by controlling the setting position of the third electrode ET3, the position where the light emitting element LD is concentrated in the emission area EMA of the pixel PXL can be easily controlled. Therefore, the design change of the plane shape and size of the pixel PXL can be promoted. In addition, as the amount of light and brightness per unit surface area increase, the size of the pixel PXL can be reduced, and high resolution can be easily achieved.

[0283] Fig.15 and Fig.16 is a plan view showing an example of first to third electrodes included in a light emitting device according to an embodiment of the present disclosure.

[0284] In an embodiment, Fig.15 and Fig.16 Shown according to Figure 6 and Figure 7 The same reference numerals are used to designate components that are the same as or similar to those of the above-described embodiment, and a detailed description thereof will be omitted.

[0285] refer to Fig.15 and Fig.16, the third electrode ET3 may be disposed at a predetermined position between the alternately arranged first electrodes ET1 and second electrodes ET2.

[0286] In an embodiment, if Fig.15 As shown in , one of the second electrodes ET2 (e.g., ET21) may be disposed to face the first side of the third electrode ET3, and one of the first electrodes ET1 (e.g., ET12) may be disposed to face the second side of the third electrode ET3. No effective light emitting element is disposed and aligned on the third electrode ET3 where no electric field is formed. The light emitting elements may be concentrated on the electrode pair disposed on the opposite sides of the third electrode ET3.

[0287] In this way, different electrodes (e.g., ET21 and ET12) to which different alignment voltages are applied may be disposed on opposite sides of the third electrode ET3 according to the process of forming the electrode pattern. Therefore, a design change of the emission area EMA of the pixel PXL may be easily performed without being limited by the process of patterning the first electrode ET1, the second electrode ET2, and the third electrode ET3.

[0288] like Fig.16 As shown in , the third electrode ET3 may include a plurality of conductive patterns CP1, CP2, and CP3 sequentially disposed at positions spaced apart from each other in the first direction DR1. As the area in which an electric field is not formed between the second electrodes ET21 and ET22 facing the third electrode ET3 increases, the number of light emitting elements aligned on the electrode pair disposed on the opposite side of the third electrode ET3 may further increase. Therefore, the density of the light emitting elements in a narrower area may increase, and the brightness per unit area may increase.

[0289] As described above, in the light emitting device and the display device including the light emitting device according to the embodiment of the present disclosure, by controlling the setting position of the floating third electrode ET3, the area in which the light emitting elements LD are densely arranged in the emission area EMA can be easily controlled. Therefore, the design change of the plane shape and size of the pixel PXL can be facilitated.

[0290] Furthermore, as the amount of light and brightness per unit surface area increase, the size of the pixel PXL can be reduced, and high resolution can be easily achieved.

[0291] The embodiments of the present disclosure are not limited only to display devices, but may be widely applied to other types of devices requiring a light source.

[0292] Although embodiments of the present disclosure have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as claimed in the accompanying claims.

Claims

1. A light emitting device, comprising: a plurality of first electrodes and a plurality of second electrodes, arranged at positions spaced apart from each other in a first direction; a plurality of light emitting elements electrically coupled between mutually adjacent first electrodes and second electrodes among the plurality of first electrodes and the plurality of second electrodes; as well as a third electrode disposed at a preset position spaced apart from the plurality of first electrodes and the plurality of second electrodes; wherein the third electrode is electrically separated from the plurality of first electrodes and the plurality of second electrodes, wherein the first electrode and the second electrode adjacent to each other form a corresponding electrode pair, and The number of light-emitting elements arranged on a first electrode pair that is most adjacent to the third electrode is greater than the number of light-emitting elements arranged on a second electrode pair, and the second electrode pair is arranged to be farther away from the third electrode than the first electrode pair.

2. The light emitting device according to claim 1, wherein: The third electrode is an isolated electrode.

3. The light emitting device according to claim 1, wherein: The density of the light emitting elements decreases in a direction away from the third electrode relative to the first direction.

4. The light emitting device according to claim 1, wherein: One of the plurality of first electrodes is disposed to face the first side of the third electrode, and Another one of the plurality of first electrodes is arranged to face a second side of the third electrode opposite to the first side of the third electrode.

5. The light emitting device according to claim 1, wherein: One of the plurality of second electrodes is disposed to face the first side of the third electrode, and Another one of the plurality of second electrodes is arranged to face a second side of the third electrode opposite to the first side of the third electrode.

6. The light emitting device according to claim 1, wherein: A width of the third electrode relative to the first direction is greater than a width of the first electrode relative to the first direction and a width of the second electrode relative to the first direction.

7. The light emitting device according to claim 1, wherein: The third electrode includes a plurality of conductive patterns sequentially disposed at positions spaced apart from each other in the first direction.

8. The light emitting device according to claim 1, wherein: The first electrode, the second electrode, and the third electrode are formed of the same conductive material and are disposed on the same insulating layer.

9. Display device, including A first pixel is disposed in the display area and includes an emission area, in, The first pixel comprises: a plurality of first electrodes and a plurality of second electrodes disposed in the emission region at positions spaced apart from each other in a first direction; a plurality of light emitting elements electrically coupled between mutually adjacent first electrodes and second electrodes among the plurality of first electrodes and the plurality of second electrodes; a first connecting electrode connected to the plurality of first electrodes; a second connection electrode coupled to the plurality of second electrodes; and a third electrode electrically separated from the plurality of first electrodes and the plurality of second electrodes and disposed at a position spaced apart from the plurality of first electrodes and the plurality of second electrodes, wherein the first electrode and the second electrode adjacent to each other form a corresponding electrode pair, and The number of light-emitting elements arranged on a first electrode pair that is most adjacent to the third electrode is greater than the number of light-emitting elements arranged on a second electrode pair, and the second electrode pair is arranged to be farther away from the third electrode than the first electrode pair.

10. The display device according to claim 9, wherein: The third electrode is an island-shaped isolated electrode.

11. The display device according to claim 9, wherein: The density of the light emitting elements decreases in a direction away from the third electrode relative to the first direction.

12. The display device according to claim 11, wherein: The third electrode is disposed in the emission region, and The first electrode and the second electrode are arranged in a shape symmetrical to the third electrode.

13. The display device according to claim 11, wherein: The third electrode is disposed in the emission region, and In which, the number of some first electrodes and some second electrodes among the multiple first electrodes and the multiple second electrodes arranged on the first side of the third electrode is different from the number of remaining first electrodes and some second electrodes among the multiple first electrodes and the multiple second electrodes arranged on the second side of the third electrode.

14. The display device according to claim 9, wherein: The third electrode is disposed on one side of a non-emission region of the first pixel surrounding the emission region. 15 . The display device according to claim 14 , further comprising a bank provided in the non-emission region to surround the first pixel and provided on the third electrode.

16. The display device according to claim 14, further comprising a second pixel having the same structure as that of the first pixel and disposed adjacent to the third electrode, in, The first connection electrode of the first pixel and the first connection electrode of the second pixel are separated from each other between the first pixel and the second pixel, and Wherein, the second connection electrode of the first pixel and the second connection electrode of the second pixel are integrally connected to each other.

17. The display device according to claim 16, wherein: The light emitting elements of the first pixel and the light emitting elements of the second pixel are arranged at a density that increases from a central portion of a corresponding emission region toward the third electrode.

18. The display device according to claim 9, wherein: The first electrode, the second electrode, and the third electrode are formed of the same conductive material and are disposed on the same insulating layer.

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