Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor devices and methods of manufacturing semiconductor devices. In one example, a semiconductor device includes a substrate including a conductive structure, an electronic component located over a top surface of the substrate and electrically coupled with the conductive structure, a cap structure located over the substrate and located over the electronic component, and a vertical interconnect located in the cap structure, the vertical interconnect extending to a top surface of the cap structure and electrically coupled with the conductive structure. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] Existing semiconductor packages and methods for forming semiconductor packages have shortcomings, such as excessive cost, reduced reliability, relatively low performance, or excessively large package size. Further limitations and disadvantages of this method will become apparent to those skilled in the art by comparing conventional and traditional methods with this disclosure and by referring to the accompanying drawings. Summary of the Invention

[0003] In one of the examples disclosed herein, a semiconductor device includes: a substrate including a conductive structure; an electronic component located on a top surface of the substrate and electrically coupled to the conductive structure; a cover structure located on the substrate and on the electronic component; and a vertical interconnect located in the cover structure, the vertical interconnect extending to a top surface of the cover structure and electrically coupled to the conductive structure.

[0004] The semiconductor device in the example further includes a seal located between the top surface of the substrate and the bottom surface of the cover structure.

[0005] In the semiconductor device described in the example, the cover structure includes a cavity, and the electronic components are located within the cavity.

[0006] In the semiconductor device described in the example, the cover structure includes a cover and a sidewall between the cover and the substrate.

[0007] The semiconductor device in the example further includes a seal located between the cover and the sidewall.

[0008] In the semiconductor device of the example, the vertical interconnect includes a cover vertical interconnect in the cover and a sidewall vertical interconnect in the sidewall, and the sidewall vertical interconnect is electrically coupled to the cover vertical interconnect and the conductive structure.

[0009] The semiconductor device in the example further includes a cover connector that is electrically connected to the vertical interconnect and the conductive structure.

[0010] The semiconductor device in the example further includes an external interconnect located on the top surface of the cover structure and electrically coupled to the vertical interconnect.

[0011] In the semiconductor device described in the example, the cover structure comprises glass.

[0012] In another example disclosed herein, a semiconductor device includes: a substrate assembly; a substrate located on a top surface of the substrate assembly and including a conductive structure; an electronic assembly located on the top surface of the substrate and electrically coupled to the conductive structure; a cover structure located on the substrate and the electronic assembly; and a vertical interconnect located in the substrate assembly and electrically coupled to the conductive structure.

[0013] The semiconductor device in the other example further includes a seal located between the cover structure and the substrate.

[0014] In the semiconductor device of the other example, the cover structure includes a cavity, and the electronic components are located in the cavity.

[0015] In the semiconductor device of the other example, the cover structure includes a cover and a cover sidewall between the cover and the substrate.

[0016] The semiconductor device in the other example further includes a seal located between the cover and the cover sidewall.

[0017] The semiconductor device in the other example further includes an external interconnect that is electrically coupled to the vertical interconnect.

[0018] In the semiconductor device of the other example, the cover structure comprises glass.

[0019] In yet another example disclosed herein, a method for manufacturing a semiconductor device includes: providing a substrate comprising a conductive structure; providing an electronic device on a top surface of the substrate and electrically coupling the electronic device to the conductive structure; providing a seal on the top surface of the substrate; and providing a cover structure on the bottom surface of the substrate and on the electronic device.

[0020] In yet another example of the method, the cover structure includes vertical interconnects, and the method further includes electrically coupling the vertical interconnects to the conductive structure.

[0021] In yet another example of the method, the substrate is located on a base assembly including vertical interconnects, and the method further includes electrically coupling the vertical interconnects to the conductive structure.

[0022] The method in yet another example further includes attaching an external connector to a vertical interconnect in the cover structure or a base assembly coupled to the substrate. Attached Figure Description

[0023] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0024] Figures 2A to 2H A cross-sectional view is shown of an example method for manufacturing an example semiconductor device.

[0025] Figure 3 A cross-sectional view of an example semiconductor device is shown.

[0026] Figures 4A to 4F A cross-sectional view is shown of an example method for manufacturing an example semiconductor device.

[0027] Figure 5 A cross-sectional view of an example semiconductor device is shown.

[0028] Figures 6A to 6I A cross-sectional view is shown of an example method for manufacturing an example semiconductor device.

[0029] Figure 7 A cross-sectional view of an example semiconductor device is shown.

[0030] Figures 8A to 8H A cross-sectional view is shown of an example method for manufacturing an example semiconductor device.

[0031] Figure 9 A cross-sectional view of an example semiconductor device is shown.

[0032] Figures 10A to 10F A cross-sectional view is shown of an example method for manufacturing an example semiconductor device. Detailed Implementation

[0033] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0034] The accompanying drawings illustrate the general construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring this disclosure. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different drawings denote the same elements.

[0035] The term "or" means any one or more items in a list connected by "or". For example, "x or y" means any element in the three-element set {(x),(y),(x,y)}. As another example, "x, y or z" means any element in the seven-element set {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}.

[0036] The terms “comprises,” “comprising,” “includes,” or “including” are “open-ended” terms and specify the presence of the stated feature but do not preclude the presence or addition of one or more other features. Various elements may be described herein using terms such as “first,” “second,” etc., and these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, a first element discussed in this disclosure may be referred to as a second element without departing from the teachings of this disclosure.

[0037] Unless otherwise specified, the term "coupled" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, then element A can be in direct contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0038] In one example, a semiconductor device includes: a substrate including a conductive structure; an electronic component located on a top surface of the substrate and electrically coupled to the conductive structure; a cover structure located on the substrate and on the electronic component; and a vertical interconnect located in the cover structure, the vertical interconnect extending to a top surface of the cover structure and electrically coupled to the conductive structure.

[0039] In another example, a semiconductor device includes: a substrate assembly; a substrate located on a top surface of the substrate assembly and including a conductive structure; an electronic assembly located on the top surface of the substrate and electrically coupled to the conductive structure; a cover structure located on the substrate and the electronic assembly; and a vertical interconnect located in the substrate assembly and electrically coupled to the conductive structure.

[0040] In another example, a method for manufacturing a semiconductor device includes: providing a substrate comprising a conductive structure; providing an electronic device over a top surface of the substrate and electrically coupling the electronic device to the conductive structure; providing a seal over the top surface of the substrate; and providing a cover structure over the bottom surface of the substrate and over the electronic device.

[0041] This disclosure contains other examples. Such examples may be found in the accompanying drawings, claims, or description of this disclosure.

[0042] Figure 1 A cross-sectional view of an example semiconductor device 10 is shown. Figure 1 In the example shown, semiconductor device 10 may include a substrate 11, a substrate assembly 15, an electronic assembly 16, a cover structure 17, a seal 18, and an external connector 19. The seal 18 may be located between the top surface of the substrate 11 and the bottom surface of the cover structure 17. The external connector 19 may connect to a vertical interconnect 172 in the cover structure 17 to connect to a cover connector 173. The vertical interconnect 172 may extend to the top surface of the cover structure 17 and may be electrically coupled to a conductive structure 111 of the substrate 11, for example, via the cover connector 173. The cover structure 17 may include a cover 17A defining a cover cavity 171 and a cover sidewall 17B, wherein the cover 17A covers the top surface of the electronic assembly 16, and the cover sidewall 17B defines the side surfaces of the electronic assembly 16. The electronic assembly 16 may be located within the cover cavity 171 and may be located above the top surface of the substrate 11. The substrate 11 may include a conductive structure 111, a dielectric structure 112, and substrate terminals 1111. In some instances, the first component terminal 151 can electrically connect the base component 15 and the substrate 11. In some instances, the second component terminal 161 can electrically connect the electronic component 16 to the substrate 11 to electrically connect to the conductive structure 111.

[0043] The substrate 11, cover structure 17, and external connector 19 may be referred to as a semiconductor package or encapsulation and may protect the electronic component 16. In some instances, the semiconductor package may provide electrical connection between the external component and the substrate component 15 or the electronic component 16.

[0044] Figures 2A to 2H A cross-sectional view is shown of an example method for manufacturing an example semiconductor device 10. Figure 2A A cross-sectional view is shown at an early stage of the manufacturing process. Figure 2A In the example shown, a substrate 11 may be provided, and the substrate may include a top surface 11a, a bottom surface 11b opposite to the top surface 11a, a conductive structure 111, and a dielectric structure 112. A base assembly 15 may be provided, and the base assembly may be located at the bottom surface 11b of the substrate 11. Although Figure 2A Two base components 15 coupled to the bottom surface 11b of two substrates 11 are shown, but multiple base components 15 and substrates 11 can be arranged to be spaced apart from each other in a row or column direction.

[0045] In some instances, substrate 11 may include, or be referred to as, a multilayer printed circuit board (PCB), a preformed substrate, a coreless substrate, a redistribution layer (RDL) substrate, an interposer, or a lead frame. In some instances, the thickness of substrate 11 may range from approximately 5 micrometers (μm) to approximately 250 μm.

[0046] In some instances, substrate 11 may be a redistribution layer (“RDL”) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, which (a) may be formed layer-by-layer on an electronic device to which the RDL substrate is to be electrically coupled, or (b) may be formed layer-by-layer on a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be fabricated layer-by-layer on a circular wafer as a wafer-level substrate using wafer-level processes, or layer-by-layer on a rectangular or square panel carrier as a panel-level substrate using panel-level processes. The RDL substrate may be formed using an additive stacking process that may include one or more dielectric layers that are alternately stacked with one or more conductive layers defining corresponding conductive redistribution patterns or traces, the conductive redistribution patterns or traces being configured to collectively (a) fan the traces out of the electronic device's footprint, or (b) fan the traces into the electronic device's footprint. Plating processes, such as electroplating or electroless plating processes, may be used to form the conductive patterns. Conductive patterns can include conductive materials, such as copper or other plated metals. The locations of the conductive patterns can be formed using photo-patterning processes, such as photolithography, and photoresist materials used to form a photomask. The dielectric layer of the RDL substrate can be patterned using photo-patterning processes that may include a photomask through which light is exposed to the desired features of the photo-pattern, such as vias in the dielectric layer. The dielectric layer can be made of a photodeterminable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). This dielectric material can be spin-coated or otherwise coated in liquid form, rather than attached as a pre-formed film. To allow for the proper formation of the desired photodeterminable features, this photodeterminable dielectric material may omit structural reinforcing agents or may be filler-free, free of lines, fabrics, or other particles that could interfere with light from the photo-patterning process. In some instances, this filler-free characteristic of filler-free dielectric materials can allow for a reduction in the thickness of the resulting dielectric layer. While the light-defined dielectric material described above can be an organic material, in other instances, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). These one or more inorganic dielectric layers can be formed by growing the inorganic dielectric layer using oxidation or nitridation processes instead of using a light-defined organic dielectric material. Such inorganic dielectric layers may be free of fillers, wires, fabrics, or other different inorganic particles.In some instances, the RDL substrate may omit the permanent core structure or carrier, for example, by including dielectric materials such as bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates. Other substrates in this disclosure may also include RDL substrates.

[0047] In some instances, substrate 11 may be a pre-formed substrate. The pre-formed substrate can be fabricated prior to attachment to an electronic device and may include a dielectric layer situated between respective conductive layers. The conductive layer may include copper and can be formed using an electroplating process. The dielectric layer may be a relatively thick, non-photodefineable layer that can be attached in the form of a pre-formed film rather than a liquid, and may contain a resin with fillers such as wires, fabrics, or other inorganic particles for rigid or structural support. Because the dielectric layer is non-photodefineable, features such as vias or openings can be formed using drilling or lasers. In some instances, the dielectric layer may include a prepreg material or an Ajinomoto build-up film (ABF). The pre-formed substrate may contain a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other instances, the pre-formed substrate may be a coreless substrate omitting a permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier that is removed after the formation of the dielectric and conductive layers and before attachment to an electronic device. The pre-formed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such a pre-formed substrate may be formed using a semi-additive process or a modified semi-additive process. Other substrates in this disclosure may also include pre-formed substrates.

[0048] The substrate 11 may include a conductive structure 111, a dielectric structure 112, and a substrate terminal 1111. The substrate terminal 1111 may be provided as part of the conductive structure 111 exposed on the top surface 11a of the substrate 11. The substrate terminal 1111 may establish or be part of an electrical connection path between the semiconductor device 10 and an external circuit or another semiconductor device. In some instances, the substrate terminal 1111 may include, or be referred to as, a pad, a bar, or a bump.

[0049] In some instances, conductive structure 111 may include one or more conductive layers positioned between one or more dielectric layers of dielectric structure 112. In some instances, conductive structure 111 may include, or be referred to as, one or more conductors, conductive materials, conductive vias, circuit patterns, traces, or wiring patterns. A portion of conductive structure 111 may be exposed on the top or bottom of dielectric structure 112 for electrical connection to substrate assembly 15, electronic assembly 16, or external connector 19. In some instances, conductive structure 111 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0050] In some examples, dielectric structure 112 may have substantially planar top and bottom surfaces. The top and bottom surfaces of dielectric structure 110a may be identical to the top surface 11a and bottom surface 11b of substrate 11, respectively. In some examples, dielectric structure 112 may include, or be referred to as, one or more dielectric layers or core layers. In some examples, dielectric structure 112 may include a core layer. In some examples, dielectric structure 112 may include epoxy resin, phenolic resin, glass epoxy resin, polyimide, polyester, epoxy molding compound, or ceramic. In some examples, the thickness of dielectric structure 112 may range from about 1 μm to about 20 μm. In some examples, dielectric structure 112 may provide structural integrity to support substrate 11 or maintain substrate 11 in a substantially planar state.

[0051] In some instances, the substrate 11 may be formed layer-by-layer on the substrate assembly 15 or may be integral with the substrate assembly. In some instances, the substrate assembly 15 may be attached to a conductive structure 111 exposed on the bottom surface 11b of the substrate 11. In some instances, the substrate assembly 15 may be electrically connected to the conductive structure 111 of the substrate 11 by, for example, mass reflow, thermocompression bonding, or laser-assisted bonding.

[0052] In some instances, substrate component 15 may include, or be referred to as, a semiconductor die, a semiconductor chip, or a semiconductor package. In some instances, substrate component 15 may include active circuitry such as a digital signal processor (DSP), microprocessor, network processor, power management processor, audio processor, radio frequency (RF) circuitry, wireless baseband system-on-chip (SoC) processor, sensor, optical or light sensor, transmitter, wireless, optical, or light transmitter, or application-specific integrated circuit (ASIC). In some instances, substrate component 15 may include a silicon substrate or a glass substrate. In some instances, substrate component 15 may be part of substrate 11 or may include a structural substrate, substrate, or support for substrate 11. In some instances, substrate component 15 may not contain active circuitry. In some instances, substrate component 15 may optionally be omitted. In some instances, the thickness of substrate component 15 may range from approximately 30 μm to approximately 700 μm.

[0053] In some instances, the first component terminal 151 may electrically connect the base component 15 and the substrate 11. In some instances, the first component terminal 151 may comprise aluminum, copper, gold, or silver. In some instances, the first component terminal 151 may comprise, or be referred to as, a pad or bump. The first component terminal 151 may be part of the base component 15 or may be provided on the base component 15 by, for example, sputtering, plating, or evaporation. In some instances, the thickness of the first component terminal 151 may range from approximately 20 μm to approximately 150 μm.

[0054] Figure 2B A cross-sectional view is shown at another stage of the manufacturing process. Figure 2B In the examples shown, electronic components 16 may be provided on the top surface 11a of substrate 11 or may be coupled to the top surface. In some examples, a pick-and-place device (not shown) may pick up electronic components 16 to place them onto a conductive structure 111 exposed on the top surface 11a of substrate 11. In some examples, electronic components 16 may be electrically connected to the conductive structure 111 of substrate 11 by mass reflow, thermal compression, or laser-assisted bonding. In some examples, electronic components 16 may be coupled to substrate 11 on base component 15 as part of a chip-on-chip (CoC) or wafer-on-wafer (COW) process. In one example, substrate 11 may be an RDL substrate formed directly on or as part of base component 15. In another example, base component 15 may include a substrate semiconductor device, die, or chip that has been diced or is still located within a semiconductor wafer. In yet another example, electronic component 16 may include another semiconductor device, die, or chip attached to base component 15 via component terminal 161.

[0055] In some instances, electronic component 16 may include, or be referred to as, a semiconductor die, a semiconductor chip, or a semiconductor package. In some instances, electronic component 16 may include a microelectromechanical system (MEMS) device, a sensor device, a light-emitting diode (LED), or a light detection and ranging (LiDAR) device. In some instances, electronic component 16 may include circuit systems such as a digital signal processor (DSP), a microprocessor, a network processor, a power management processor, an audio processor, radio frequency (RF) circuitry, a wireless baseband system-on-a-chip (SoC) processor, a sensor, an application-specific integrated circuit (ASIC), a power converter, an analog or digital data converter, a switch, an LED, a controller, or a piezoelectric device. In some instances, electronic component 16 may include an RF sensor, a wireless sensor, a light sensor or optical sensor, a transmitter, or a receiver. In some instances, the width of electronic component 16 may range from approximately 1 millimeter (mm) to approximately 20 millimeters (mm).

[0056] In some instances, the second component terminal 161 electrically connects the electronic component 16 to the substrate 11. The second component terminal 161 may include, or be referred to as, a bump, ball, post, rod, wire, solder body, copper body, or solder cap. In some instances, the second component terminal 161 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some instances, the second component terminal 161 may be provided using a ball-drop process, screen printing process, electroplating process, or wire bonding process. The thickness of the second component terminal 161 may range from approximately 20 μm to approximately 50 μm.

[0057] Figure 2C A cross-sectional view is shown at another stage of the manufacturing process. Figure 2C In the examples shown, a cover structure 17 may be provided. In some examples, the cover structure 17 may be referred to as a cavity cover. In some examples, the cover structure 17 may comprise glass, ceramic, or polymer. In some examples, the cover structure 17 may be translucent in allowing the passage, transmission, or reception of light, RF, or other wireless radiation or signals. The cover structure 17 may have a vertical aperture 172a and a bottom surface 17b. The vertical aperture 172a may be provided by using chemical, mechanical, or laser etching, drilling, or ablation. The diameter of the vertical aperture 172a may range from approximately 20 μm to approximately 150 μm.

[0058] Figure 2D A cross-sectional view is shown at another stage of the manufacturing process. Figure 2D In the example shown, the cover vertical interconnect 172 can be provided by filling the vertical hole 172a with metal. In some examples, the cover vertical interconnect 172 may be referred to as a through-glass via (TGV), through-silicon via (TSV), or through-hole. In some examples, the cover vertical interconnect 172 may comprise copper, silver, aluminum, or gold. The diameter of the cover vertical interconnect 172 can range from approximately 20 μm to approximately 150 μm.

[0059] Figure 2E A cross-sectional view is shown at another stage of the manufacturing process. Figure 2EIn the example shown, the cover structure 17 may have a cavity 171 at its bottom surface 17b. The cavity 171 may be formed by etching, routing, or polishing, or it may be formed around a mold. The size of the cavity 171 may be larger than the size of the electronic component 16. The depth of the cavity 171 may be equal to or greater than the height of the electronic component 16. In one example, the depth of the cavity 171 may be from 100 μm to 500 μm. The cavity 171 may be configured to cover the electronic component 16.

[0060] Figure 2F A cross-sectional view is shown at another stage of the manufacturing process. Figure 2F In the example shown, a seal 18 may be provided around the cavity 171 on the bottom surface 17b of the cover structure 17. The seal 18 may be attached to a portion of the bottom surface 17b surrounding the cavity 171. The seal 18 may be referred to as a bottom filler, gasket, adhesive, or engagement ring. In some examples, the seal 18 may comprise glass frit, polymer adhesive, metal, or solder. In some examples, the seal 18 may be dispensed as a paste, film, liquid, or liquid suspension material before, during, or after attachment of the cover structure.

[0061] Figure 2G A cross-sectional view is shown at another stage of the manufacturing process. Figure 2G In the example shown, a cover structure 17 can be provided and attached to a substrate 11. The cover structure 17 can be attached to the substrate 11 via a seal 18. The cover vertical interconnect 172 can be electrically coupled to the conductive structure 111, for example, by connecting the substrate terminals 1111 of the substrate 11 to the cover connector 173. The cover connector 173 may include, or be referred to as, bumps, balls, or posts (such as rods) or wires, solder bodies, copper bodies, or solder caps. In some examples, the cover connector 173 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the cover connector 173 may be provided using a drop ball process, a screen printing process, or an electroplating process. In some instances, the height of the cover connector 173 can be from 20 μm to 50 μm.

[0062] In some instances, the cavity 171 of the cover structure 17 can accommodate the electronic component 16, and a gap may exist between the cover structure 17 and the top or side surface or the electronic component 16. In some instances, the cover structure 17 can be tightly attached to a surface of the substrate 11 by means of a seal 18. The electronic component 16 within the cavity of the cover structure 17 can be enclosed in the cavity environment of the cavity 171, which is protected from or isolated from the external environment.

[0063] Figure 2H A cross-sectional view is shown at another stage of the manufacturing process. Figure 2H In the examples shown, the external connector or interconnect 19 may be located on the top surface of the cover structure 17 and may be electrically coupled or attached to the vertical interconnect 172. In some examples, the external connector 19 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the external connector 19 may be provided by drop ball, screen printing, or electroplating. For example, the external connector 19 may be provided by a reflow process after a conductive material containing solder has been prepared on one side of the vertical interconnect 172 by drop ball. In some examples, the external connector 19 may be referred to as a bump, ball, post, rod, wire, solder body, copper body, or solder cap. In some examples, the thickness of the external connector 19 may range from approximately 20 μm to approximately 50 μm. In some instances, adjacent semiconductor devices 10 can be cut individually, for example, by sawing.

[0064] Figure 3 A cross-sectional view of an example semiconductor device 20 is shown. Figure 3 In the example shown, semiconductor device 20 may include a substrate 11, a base assembly 25, an electronic component 16, a cover structure 27, a seal 18, and an external connector 19. The seal 18 may be located between the cover structure 27 and the substrate 11. The cover structure 27 may include a cavity 171, a cover 17A defining the cavity 171, and a cover sidewall 17B. The electronic component 16 may be located within the cavity 171. The cover sidewall 17B may be located between the cover 17A and the substrate 11. The cover structure 27 may be located over the substrate 11 and the electronic component 16. The cover 17A covers the top surface of the electronic component 16, and the cover sidewall 17B defines the sides of the electronic component 16. In some examples, the seal 18 may be located between the cover sidewall 17B and the substrate 11. The substrate 11 may be located over the top surface of the base assembly 25 and may include a conductive structure 111, a dielectric structure 112, and a substrate terminal 1111. Electronic component 16 may be located on the top surface of substrate 11 and may be electrically coupled to conductive structure 111.

[0065] Semiconductor device 20 and several of its elements may be similar to other semiconductor devices or corresponding elements described herein. For example, semiconductor device 20 and several of its elements may be similar to semiconductor device 10 and its corresponding elements. Semiconductor device 20 may include a substrate assembly 25, which is similar to substrate element 15 and has vertical interconnects 252. Vertical interconnects 252 may be located in substrate assembly 25 and may be electrically coupled to conductive structure 111 of substrate 11. External connectors or interconnects 19 may be electrically coupled to vertical interconnects 252. Semiconductor device 20 may include a cover structure 27, which may be similar to cover structure 17 without the cover vertical interconnects 172. In some instances, cover structure 27 may include the same material as cover structure 17, such as glass.

[0066] The substrate 11, cover structure 27, and external connector 19 may be referred to as a semiconductor package or encapsulation and can protect the electronic component 16. Additionally, the semiconductor package can provide electrical connections between each external component and the substrate component 25 or the electronic component 16.

[0067] Figures 4A to 4F A cross-sectional view is shown of an example method for manufacturing an example semiconductor device 20. Figure 4A A cross-sectional view is shown at an early stage of the manufacturing process. Figure 4A In the example shown, a substrate 11 and a base assembly 25 may be provided. The substrate 11 may be formed on or coupled to the top surface of the base assembly 25. Although Figure 4A Two base components 25 and two substrates 11 are shown, but multiple base components 25 and substrates 11 can be arranged to be spaced apart from each other in a row or column direction.

[0068] The substrate assembly 25 may be similar to the substrate assembly 15 previously described. In some instances, the substrate assembly 25 may include a component vertical interconnect 252. In some instances, the component vertical interconnect 252 may be similar to the cover vertical interconnect 172 previously described and may extend from the top surface to the bottom surface of the substrate assembly 25. In some instances, the component vertical interconnect 252 may include, or be referred to as, a through-glass via (TGV), through-silicon via (TSV), or a through-hole. In some instances, the component vertical interconnect 252 may include copper, silver, aluminum, or gold. The component vertical interconnect 252 may be provided by forming a hole within the substrate assembly 25 using drilling or etching, or laser drilling or laser etching, and filling the hole with a metal or conductive material. In some instances, the diameter of the component vertical interconnect 252 may range from approximately 10 μm to approximately 150 μm.

[0069] Figure 4BA cross-sectional view is shown at another stage of the manufacturing process. Figure 4B In the examples shown, it is possible to use the same as previously discussed. Figure 2B The electronic component 16 is coupled to the top surface 11a of the substrate 11 in a manner similar to that described.

[0070] Figure 4C A cross-sectional view is shown at another stage of the manufacturing process. Figure 4C In the example shown, a cover structure 27 may be provided. Cover structure 27 may be similar to cover structure 17 previously described and may not include cover vertical interconnects 172. Cover structure 27 may have a cavity 171 formed on or in the bottom surface 17b. Cavity 171 may be formed by etching, routing, or polishing, or may be formed around a mold. The size of cavity 171 may be larger than the size of electronic component 16. The depth or width of cavity 171 may be greater than the thickness or width of electronic component 16. In one example, the depth of cavity 171 may be from 100 μm to 500 μm. In one example, cavity 171 may be configured to cover electronic component 16.

[0071] Figure 4D A cross-sectional view is shown at another stage of the manufacturing process. Figure 4D In the example shown, a seal 18 may be attached around the cavity 171 of the cover structure 17. The seal 18 may be attached to the bottom surface 17b of the cover structure 27. The seal 18 may be referred to as a bottom filler, gasket, adhesive, or engagement ring. In some examples, the seal 18 may comprise glass frit, polymer adhesive, metal, or solder. In some examples, the seal 18 may be dispensed as a paste, film, liquid, or liquid suspension material before, during, or after attachment of the cover structure.

[0072] Figure 4E A cross-sectional view is shown at another stage of the manufacturing process. Figure 4E In the example shown, the cover structure 27 can be attached to the substrate 11. The cover structure 27 can be attached to the substrate 11 via a seal 18. In some examples, the cavity 171 of the cover structure 27 can accommodate the electronic component 16, and a gap may exist between the cover structure 27 and the top or side surface of the electronic component 16.

[0073] Figure 4F A cross-sectional view is shown at another stage of the manufacturing process. Figure 4FIn the examples shown, the external connector 19 can be coupled to the base assembly 25. In some examples, the external connector 19 can be electrically coupled or attached to the component vertical interconnect 252 of the base assembly 25. In some examples, the external connector 19 can include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the external connector 19 can be provided by drop ball, screen printing, or electroplating. For example, the external connector 19 can be provided by a reflow process after a conductive material containing solder is prepared on one side of the base assembly 25 by drop ball. In some examples, the external connector 19 can be referred to as a bump, ball, post, rod, wire, solder body, copper body, or solder cap. In some instances, the thickness of the external connector 19 can range from approximately 20 μm to approximately 50 μm. In some instances, adjacent semiconductor devices 20 can be cut individually, for example, by sawing.

[0074] Figure 5 A cross-sectional view of an example semiconductor device 30 is shown. Figure 5 In the example shown, semiconductor device 30 may include a substrate 11, a substrate assembly 15, an electronic assembly 16, a cover structure 37, a seal 18, and an external connector 19. Substrate 11 may include a conductive structure 111, a dielectric structure 112, and substrate terminals 1111.

[0075] Semiconductor device 30 and several of its components may be similar to other semiconductor devices or corresponding components described herein. For example, semiconductor device 30 and several of its components may be similar to semiconductor device 10 and its corresponding components. The cover structure 37 of semiconductor device 30 may be similar to the cover structure 17 of semiconductor device 10 and includes a cover shroud 37A coupled to a cover sidewall 37B to define a cover cavity 171. Cover structure 37 may include a cover vertical interconnect 372A to connect an external connector 19 to a cover connector 373. Cover sidewall 37B may include a vertical interconnect 372B to connect cover connector 373 to cover connector 173, substrate terminal 1111, first component terminal 151, or conductive structure 111 of substrate 11. Seal 38 may be located between sidewall 37B and cover 37A, and seal 38 may be located between sidewall 37B and the top surface of substrate 11. In some instances, the vertical interconnects in the cover structure 17 include a cover vertical interconnect 372A in the cover 37A and a sidewall vertical interconnect 372B in the sidewall 37B. The sidewall vertical interconnect 372A can be electrically connected to the cover vertical interconnect 372A and the conductive structure 111. The external interconnect 19 can be located on the top surface of the cover structure 37 and can be electrically connected to the cover vertical interconnect 372A.

[0076] The substrate 11, cover structure 37, and external connector 19 may be referred to as a semiconductor package or encapsulation and can protect the electronic component 16. Additionally, the semiconductor package can provide electrical connections between each external component and the substrate component 15 or the electronic component 16.

[0077] Figures 6A to 6H A cross-sectional view is shown of an example method for manufacturing an example semiconductor device 30. Figure 6A A cross-sectional view is shown at an early stage of the manufacturing process. Figure 6A In the examples shown, a cover 37A may be provided for the cover structure 37. In some examples, the cover 37A may comprise glass, ceramic, or polymer. In some examples, the cover 37A may be translucent in allowing the passage, transmission, or reception of light, radio frequency (RF) or other wireless radiation or signals. In some examples, the cover 37A may have a vertical aperture 372a. In some examples, the vertical aperture 372a may be formed by chemical, mechanical, or laser etching, drilling, or ablation.

[0078] Figure 6B A cross-sectional view is shown at another stage of the manufacturing process. Figure 6B In the examples shown, a cover vertical interconnect 372A may be provided within a vertical hole 372a. In some examples, the cover vertical interconnect 372A may be similar to the previously described cover vertical interconnect 172. In some examples, the cover vertical interconnect 372A may include, or be referred to as, a through-glass via (TGV) or a through-hole. In some examples, the cover vertical interconnect 372A may include copper, silver, aluminum, or gold. The cover vertical interconnect 372A may be provided by filling the vertical hole 372a with a metal or conductive material.

[0079] Figure 6C A cross-sectional view is shown at another stage of the manufacturing process. Figure 6C In the examples shown, a cover sidewall 37B may be provided for the cover structure 37. In some examples, the cover sidewall 37B may be referred to as an intermediate layer structure, an intermediate cover structure, or a cover cavity structure. In some examples, the cover sidewall 37B may comprise a silicon material, a glass material, a ceramic material, or a polymer material. In some examples, the cover sidewall 37B may have a vertical hole 372b. In some examples, the vertical hole 372b may be formed by chemical, mechanical, or laser etching, drilling, or ablation.

[0080] Figure 6D A cross-sectional view is shown at another stage of the manufacturing process. Figure 6DIn the example shown, a cover vertical interconnect 372B may be provided within a vertical hole 372b. In some examples, the cover vertical interconnect 372B may be similar to the previously described cover vertical interconnect 172. In some examples, the cover vertical interconnect 372B may be referred to as a through-glass via (TGV), through-silicon via (TSV), or through-hole. The cover vertical interconnect 372B may comprise copper, silver, aluminum, or gold. The cover vertical interconnect 372B may be provided by filling the vertical hole 372b with a metal or conductive material.

[0081] Figure 6E A cross-sectional view is shown at another stage of the manufacturing process. Figure 6E In the example shown, a cavity 171 can be formed through the cover sidewall 37B. The cavity 171 can extend from the top surface to the bottom surface of the cover sidewall 37B. In some examples, the cavity 171 can be formed by chemical, mechanical, or laser etching, drilling, or ablation.

[0082] Figure 6F A cross-sectional view is shown at another stage of the manufacturing process. Figure 6F In the example shown, a seal 18 or seal 38 may be attached to the top and bottom surfaces of the cover sidewall 37B around the cavity 171. The seal 18 or seal 38 may be referred to as a bottom filler, gasket, adhesive, or engagement ring. In some examples, the seal 18 or seal 38 may comprise glass frit, polymer adhesive, metal, or solder. In some examples, the seal 18 or seal 38 may be dispensed as a paste, film, liquid, or liquid suspension material before, during, or after attaching the cover structure. The cover connector 173 may be provided to contact the cover vertical interconnect 372B.

[0083] Figure 6G A cross-sectional view is shown at another stage of the manufacturing process. Figure 6G In the example shown, cover 37A can be coupled to cover sidewall 37B to define cover structure 37. Cover 37A and cover sidewall 37B can be coupled together via seal 38 around cavity 171. Cover vertical interconnect 372A of cover 37A and cover vertical interconnect 372B of cover sidewall 37B can be coupled to each other via cover connector 373. Cover connector 173 can be provided below cover sidewall 37B. In some examples, cover connector 373 can be similar to cover connector 173.

[0084] Figure 6H A cross-sectional view is shown at another stage of the manufacturing process. Figure 6H In the examples shown, it is possible to use the same as previously discussed. Figure 2B The electronic component 16 is coupled to the top surface 11a of the substrate 11 in a manner similar to that described.

[0085] Figure 6I A cross-sectional view is shown at another stage of the manufacturing process. Figure 6I In the example shown, the cover structure 37 can be attached to the substrate 11 via the seal 18, the cover vertical interconnect 372B can be electrically coupled to the substrate terminal 1111 of the substrate 11 via the cover connector 173, and can be used in conjunction with the above description regarding Figure 2G-2H The external connector 19 is coupled to the cover vertical interconnect 372A in a manner similar to that described for cover structure 17. The cavity 171 of cover structure 37 may surround electronic component 16. In some instances, adjacent semiconductor device 30 may be slit by sawing, for example, after attaching cover structure 37.

[0086] Figure 7 A cross-sectional view of an example semiconductor device 40 is shown. Figure 7 In the example shown, semiconductor device 40 may include a substrate 11, a substrate assembly 15, an electronic assembly 16, a cover structure 47, a seal 18, and an external connector 19. Substrate 11 may include a conductive structure 111, a dielectric structure 112, and substrate terminals 1111.

[0087] Semiconductor device 40 and several of its components may be similar to other semiconductor devices or corresponding components described herein. For example, semiconductor device 30 and several of its components may be similar to semiconductor device 40 and its corresponding components. The cover structure 47 of semiconductor device 40 may be similar to the cover structure 37 of semiconductor device 30, which includes a cover 37A that contacts the cover sidewall 37B to define a cover cavity 71, and includes a vertical interconnect 172 extending through both the cover 37A and the cover sidewall 37B.

[0088] The substrate 11, cover structure 47, and external connector 19 may be referred to as a semiconductor package or encapsulation and can protect the electronic component 16. Additionally, the semiconductor package can provide electrical connections between each external component and the substrate component 15 or the electronic component 16.

[0089] Figures 8A to 8H A cross-sectional view is shown of an example method for manufacturing an example semiconductor device 40. Figure 8A A cross-sectional view is shown at an early stage of the manufacturing process. Figure 8A In the examples shown, a cover 37A may be provided for the cover structure 47. In some examples, the cover 37A may comprise glass, ceramic, or polymer. In some examples, the cover 37A may be semi-transparent in allowing the passage, transmission, or reception of light, radio frequency (RF), or other wireless radiation or signals.

[0090] Figure 8B A cross-sectional view is shown at another stage of the manufacturing process. Figure 8B In the examples shown, a cover sidewall 37B may be provided for the cover structure 47. In some examples, the cover sidewall 37B may be referred to as an intermediate layer structure, an intermediate cover structure, or a cover cavity structure. In some examples, the cover sidewall 37B may comprise a silicon material, a glass material, a ceramic material, or a polymer material. A cavity 171 may be formed through the cover sidewall 37B, extending from the top surface to the bottom surface of the cover sidewall 37B. In some examples, the cavity 171 may be formed by chemical, mechanical, or laser etching, drilling, or ablation.

[0091] Figure 8C A cross-sectional view is shown at another stage of the manufacturing process. Figure 8C In the examples shown, the cover 37A and the cover sidewall 37B can be coupled together to form or provide a cover structure 47. In some examples, an adhesive can be used to attach the cover 37A and the cover sidewall 37B to each other. Although the cover sidewall 37B is shown as pre-formed separately from the cover 37A and then coupled together, in some examples, the cover sidewall 37B can be molded, grown, plated, or otherwise formed directly on the cover 37A.

[0092] Figure 8D A cross-sectional view is shown at another stage of the manufacturing process. Figure 8D In the examples shown, a vertical hole 172a extending through the cover 37A and the cover sidewall 37B may be provided. In some examples, the vertical hole 172a may be formed within the cover 37A and the cover sidewall 37B by chemical, mechanical, or laser etching, drilling, or ablation.

[0093] Figure 8E A cross-sectional view is shown at another stage of the manufacturing process. Figure 8E In the example shown, the cover vertical interconnect 172 can be provided by filling the vertical hole 372a with metal. In some examples, the cover vertical interconnect 172 may be referred to as a through-glass via (TGV), through-silicon via (TSV), or through-hole. In some examples, the cover vertical interconnect 172 may comprise copper, silver, aluminum, or gold. The diameter of the cover vertical interconnect 172 can range from approximately 20 μm to approximately 150 μm.

[0094] Figure 8F A cross-sectional view is shown at another stage of the manufacturing process. Figure 8FIn the examples shown, a seal 18 may be attached to the bottom surface of the cover sidewall 37B around the cavity 171. In some examples, the seal 18 may be referred to as a bottom filler, gasket, adhesive, or engagement ring. In some examples, the seal 18 may include glass frit, polymer adhesive, metal, or solder. In some examples, a cover connector 173 may be provided on the bottom surface of the cover sidewall 37B. The cover connector 173 may include, or be referred to as, a bump, ball, post (such as a rod), or wire, solder body, copper body, or solder cap. In some examples, the cover connector 173 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some instances, the cover connector 173 can be provided using a drop ball process, a screen printing process, or an electroplating process. In some instances, the height of the cover connector 173 can be from 20 μm to 50 μm.

[0095] Figure 8G A cross-sectional view is shown at another stage of the manufacturing process. Figure 8G In the example shown, the cover structure 47 can be attached to the substrate 11 via the seal 18. The cover vertical interconnect 172 can be electrically coupled to the substrate terminal 1111 of the substrate 11 using the cover connector 173. In some examples, the cavity 171 of the cover structure 47 can surround the electronic component 16.

[0096] Figure 8H A cross-sectional view is shown at another stage of the manufacturing process. Figure 8H In the examples shown, an external connector 19 can be coupled to the cover structure 47. In some examples, the external connector 19 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the external connector 19 may be provided by drop ball, screen printing, or electroplating. In some examples, adjacent semiconductor devices 40 may be individually cut, for example, by sawing after attaching the cover structure 47.

[0097] Figure 9 A cross-sectional view of an example semiconductor device 50 is shown. Figure 7 In the example shown, the semiconductor device 50 may include a substrate 11, a substrate assembly 25, a vertical interconnect 252, an electronic assembly 16, a cover structure 57, a seal 18 and a seal 38, and an external connector 19. The substrate 11 may include a conductive structure 111, a dielectric structure 112, and a substrate terminal 1111.

[0098] Semiconductor device 50 and several of its components may be similar to other semiconductor devices or corresponding components described herein. For example, semiconductor device 50 and several of its components may be similar to semiconductor device 20 and its corresponding components. Semiconductor device 50 may include a cover structure 57, which may be similar to cover structure 27, cover structure 37 or cover structure 47 and has a cover cover 57A coupled to a cover sidewall 57B without vertical interconnect 172. In some instances, such as when the cover sidewall 57B is formed directly on the cover cover 57A, the seal 38 may be omitted.

[0099] The substrate 11, cover structure 57, and external connector 19 may be referred to as a semiconductor package or encapsulation and can protect the electronic component 16. Additionally, the semiconductor package can provide electrical connections between each external component and the substrate component 25 or the electronic component 16.

[0100] Figures 10A to 10F A cross-sectional view is shown of an example method for manufacturing an example semiconductor device 50. Figure 10A A cross-sectional view is shown at an early stage of the manufacturing process. Figure 10A In the examples shown, a cover 57A may be provided for the cover structure 57. In some examples, the cover 57A may comprise glass, ceramic, or polymer. In some examples, the cover 57A may be semi-transparent in allowing the passage, transmission, or reception of light, radio frequency (RF), or other wireless radiation or signals. In some examples, the cover 57A may be similar to those previously described... Figure 6A The cover 37A is described, but the vertical hole 372a can be omitted.

[0101] Figure 10B A cross-sectional view is shown at another stage of the manufacturing process. Figure 10B In the examples shown, a cover sidewall 57B may be provided for the cover structure 57. In some examples, the cover sidewall 57B may be referred to as an intermediate layer structure, an intermediate cover structure, or a cover cavity structure. In some examples, the cover sidewall 57B may comprise a silicon material, a glass material, a ceramic material, or a polymer material. A cavity 171 may be formed through the cover sidewall 57B, and the cavity may extend from the top surface to the bottom surface of the cover sidewall 57B. In some examples, the cavity 171 may be formed by chemical, mechanical, or laser etching, drilling, or ablation.

[0102] Figure 10C A cross-sectional view is shown at another stage of the manufacturing process. Figure 10CIn the example shown, the cover 57A can be coupled to the cover sidewall 57B to define the cover structure 57. The cover 57A and the cover sidewall 57B can be coupled together via a seal 38 around the cavity 171. Although the cover sidewall 57B is shown as pre-formed separately from the cover 57A and then coupled together, in some instances, the cover sidewall 57B can be molded, grown, plated, or otherwise formed directly on the cover 57A.

[0103] Figure 10D A cross-sectional view is shown at another stage of the manufacturing process. Figure 10D In the example shown, a seal 18 may be attached to the bottom surface of the cover sidewall 57B around the cavity 171. In some examples, a seal 18 may be provided on the entire bottom surface of the cover sidewall 57B.

[0104] Figure 10E A cross-sectional view is shown at another stage of the manufacturing process. Figure 10E In the examples shown, substrate 11, base assembly 25, or electronic assembly 16 can be, for example, as described above. Figures 4A to 4B The cover structure 57 is provided as described and can be attached to the substrate 11. The cover structure 57 can be attached to the substrate 11 using a seal 18 or a seal 28. In some instances, the cavity 171 of the cover structure 57 can accommodate the electronic component 16, and a gap may exist between the cover structure 57 and the top or side surface of the electronic component 16.

[0105] Figure 10F A cross-sectional view is shown at another stage of the manufacturing process. Figure 10F In the example shown, the external connector 29 can be coupled to the vertical interconnect 252 of the base assembly 25. In some instances, this coupling can be similar to that described above. Figure 4F The coupling described. In some instances, adjacent semiconductor devices 50 can be cut individually, for example, by sawing.

[0106] This disclosure contains references to certain examples. However, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather encompasses all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device, characterized by comprising: The semiconductor device includes: A substrate, the substrate including a top surface and a bottom surface and a conductive structure, the conductive structure including a horizontal trace located between the top surface and the bottom surface of the substrate; A first electronic component is located above the top surface of the substrate and is electrically coupled to the conductive structure. A cover structure, the cover structure being located on the substrate and on the first electronic component; A vertical interconnect located within the cover structure, extending to the top surface of the cover structure and electrically coupled to the conductive structure; and A substrate assembly that is in contact with the substrate, wherein the substrate assembly includes a top surface and a bottom surface; The substrate is located between the base assembly and the first electronic assembly; The base component includes a second electronic component that is different from the first electronic component; Wherein, the second electronic component of the substrate assembly includes a semiconductor material; and Wherein, the top surface of the substrate assembly facing the first electronic component includes component terminals coupled to the conductive structure; and The cover structure includes glass configured to allow light to pass through it, and the substrate includes at least one of epoxy resin, phenolic resin, polyimide, polyester, or epoxy molding compound.

2. The semiconductor device according to claim 1, wherein It further includes a seal located between the top surface of the substrate and the bottom surface of the cover structure.

3. The semiconductor device according to claim 1, wherein The cover structure includes a cavity, with the first electronic component located within the cavity and the second electronic component located entirely outside the cavity.

4. The semiconductor device according to claim 1, characterized in that: The cover structure includes a cover and a sidewall between the cover and the substrate; The vertical interconnect is coupled to an external connector located on the top surface of the cover; and Most of the top surface of the cover is not covered by metal.

5. The semiconductor device according to claim 4, wherein It further includes a seal located between the cover and the sidewall.

6. The semiconductor device according to claim 4, wherein The vertical interconnect includes a cover vertical interconnect in the cover and a sidewall vertical interconnect in the sidewall, and the sidewall vertical interconnect is electrically coupled to the cover vertical interconnect and the conductive structure.

7. The semiconductor device according to claim 1, wherein Further includes: A cover connector, which is electrically connected to the vertical interconnect and the conductive structure; as well as A seal is provided between the top surface of the substrate and the bottom surface of the cover structure, wherein the cover connector is coupled to the vertical interconnect through an opening in the seal.

8. The semiconductor device according to claim 1, wherein It further includes an external interconnect located on the top surface of the cover structure and electrically coupled to the vertical interconnect.

9. The semiconductor device according to claim 1, wherein The cover structure includes glass.

10. A semiconductor device, characterized by comprising: The semiconductor device includes: Substrate components, including semiconductor materials; A substrate, located above the top surface of the base assembly and including a conductive structure; An electronic component, which is located on the top surface of the substrate and electrically coupled to the conductive structure; A cover structure, the cover structure being situated above the substrate and the electronic components; and A vertical interconnect located in the substrate assembly and electrically coupled to the conductive structure; The cover structure contains a material for transmitting electromagnetic energy; The cover structure includes glass configured to allow light to pass through it, and the substrate includes at least one of epoxy resin, phenolic resin, polyimide, polyester, or epoxy molding compound. The cover structure includes a cover and a cover sidewall located between the cover and the substrate, the cover sidewall being separate from the cover and having its side surface substantially perpendicular to the cover; and The vertical interconnect is located outside the substrate and extends completely through the base assembly, with the bottom surface of the vertical interconnect flush with the bottom surface of the base assembly.

11. The semiconductor device according to claim 10, wherein It further includes a seal located between the cover structure and the substrate.

12. The semiconductor device according to claim 10, wherein The cover structure includes a cavity, and the electronic components are located within the cavity.

13. The semiconductor device according to claim 10, wherein The cover structure includes a cover and a cover sidewall between the cover and the substrate.

14. The semiconductor device according to claim 13, wherein It further includes a seal located between the cover and the sidewall of the cover.

15. The semiconductor device according to claim 10, wherein It further includes an external interconnect that is electrically coupled to the vertical interconnect.

16. The semiconductor device according to claim 10, wherein The cover structure includes glass.

17. A method for manufacturing a semiconductor device, characterized by, The method includes: A substrate assembly including a top surface and a bottom surface is provided, and a substrate including a top surface, a bottom surface and a conductive structure, the conductive structure including a horizontal trace located between the top surface and the bottom surface of the substrate, wherein the substrate is in contact with the substrate assembly; A first electronic component is provided on the top surface of the substrate and the first electronic component is electrically coupled to the conductive structure; A seal is provided on the top surface of the substrate; and A cover structure is provided above the top surface of the substrate and above the first electronic component; The substrate is located between the base assembly and the first electronic assembly; The base component includes a second electronic component that is different from the first electronic component; The second electronic component of the substrate assembly includes a semiconductor material; Wherein, the top surface of the substrate assembly facing the first electronic component includes component terminals coupled to the conductive structure; and The cover structure includes glass configured to allow light to pass through it, and the substrate includes at least one of epoxy resin, phenolic resin, polyimide, polyester, or epoxy molding compound.

18. The method of claim 17, wherein, The cover structure includes vertical interconnects, and the method further includes electrically coupling the vertical interconnects to the conductive structure.

19. The method of claim 17, wherein, The substrate is located on a base assembly including vertical interconnects, and the method further includes electrically coupling the vertical interconnects to the conductive structure.

20. The method of claim 17, wherein, It further includes vertical interconnects for attaching external connectors to the cover structure or to a base assembly coupled to the substrate.

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