Semiconductor device and motor drive system using semiconductor device

Abstract

The present disclosure relates to a semiconductor device and an electrode driving system using the semiconductor device. A gate drive semiconductor device includes an external terminal to which a PWM control signal is supplied, an external terminal that outputs a drive signal to drive a three-phase BLDC motor, an external terminal to which a back electromotive voltage generated by driving the three-phase BLDC motor is supplied, a zero-crossing determination unit that generates an interrupt signal based on the PWM control signal and the back electromotive voltage, the interrupt signal indicating timing at which the back electromotive voltage crosses a midpoint potential of the three-phase BLDC motor, and an external terminal that outputs the interrupt signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-034935, filed on March 2, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device and a motor drive system using the semiconductor device, for example to a semiconductor device suitable for a multiphase sensorless motor, and a motor drive system including the multiphase sensorless motor. Background Technology

[0004] Examples of multiphase sensorless motors (hereinafter also referred to as sensorless motors or simply motors) include brushless DC (BLDC) motors. Patent Document 1 (JP 2019-103369 A1) discloses a technique for detecting the rotational speed of a BLDC motor. As a method for detecting the rotational speed, it typically involves measuring the electrical rotation period by detecting the timing of the intersection of the back electromotive force voltage (BEMF) generated by the rotation of the BLDC motor with the midpoint potential. In this case, appropriately switching the motor drive phase based on the measured rotational period enables control of the BLDC motor's rotational speed. Summary of the Invention

[0005] In recent years, the demand for high-speed rotation of motors used in power tools and other applications has increased. Therefore, it is also necessary to detect the back electromotive force voltage at high speed to measure the rotational cycle, based on the high-speed rotation of the motor.

[0006] Other problems and novel features of the invention will become apparent from the description in this specification and the accompanying drawings.

[0007] The semiconductor device according to the embodiment is as follows.

[0008] That is, the semiconductor device includes: a first external terminal to which a pulse width control signal is supplied; a second external terminal to which a drive signal is output to drive a multiphase sensorless motor; a third external terminal to which a back electromotive force voltage generated by driving the multiphase sensorless motor is supplied; a zero-crossing determination unit to generate an interrupt signal based on the pulse width control signal and the back electromotive force voltage, the interrupt signal indicating the timing of the intersection of the back electromotive force voltage and the midpoint potential of the multiphase sensorless motor; and a fourth external terminal to output the interrupt signal.

[0009] According to an embodiment, a semiconductor device and a motor drive system capable of enabling a multiphase sensorless motor to rotate at high speed can be provided. Attached Figure Description

[0010] Figure 1 This is a block diagram showing the configuration of the motor drive system according to the first embodiment;

[0011] Figure 2A This is a view illustrating the operation of the motor drive system according to the first embodiment;

[0012] Figure 2B This is a view illustrating the operation of the motor drive system according to the first embodiment;

[0013] Figure 3 This is a block diagram illustrating the configuration of the back EMF detection logic according to the first embodiment;

[0014] Figure 4 This is a diagram illustrating the operation of the back EMF detection logic according to the second embodiment;

[0015] Figure 5 This is a block diagram illustrating the configuration of the back EMF detection logic according to the second embodiment;

[0016] Figure 6A This is a diagram used to illustrate the recoil operation;

[0017] Figure 6B This is a diagram used to illustrate the recoil operation;

[0018] Figure 6C This is a diagram used to illustrate the recoil operation;

[0019] Figure 7 This is a waveform diagram showing the operation of the motor drive system according to the third embodiment;

[0020] Figure 8 This is a flowchart illustrating the operation of the motor drive system according to the fourth embodiment; and

[0021] Figure 9 This is a block diagram illustrating the configuration of a motor drive system that has been studied prior to this invention. Detailed Implementation

[0022] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings. Incidentally, this disclosure is merely illustrative, and appropriate modifications that can be readily implemented by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the invention. Furthermore, for illustrative purposes, the drawings may schematically represent the width, thickness, and shape of each portion compared to actual embodiments, but are merely examples and do not limit the interpretation of the invention.

[0023] Furthermore, in each of the figures in this specification and the accompanying drawings, the same elements as those mentioned with respect to the above figures may be represented by the same reference numerals, and their detailed descriptions may be omitted as appropriate.

[0024] (Example of a discussion)

[0025] Prior to this invention, the inventors' discussion examples of this application will be described with reference to the accompanying drawings. Figure 9 This is a block diagram illustrating the configuration of a motor drive system that has been discussed prior to this invention.

[0026] Here, a three-phase BLDC motor is described as an example, assuming it is a sensorless motor. The microprocessor (hereinafter also referred to as the processor) MCU outputs a pulse width control signal (hereinafter also referred to as the PWM control signal) to the gate driver (Gate_Driver) to drive the three-phase BLDC motor. The gate driver (Gate_Driver) supplies a drive signal to the driver (Driver) according to the supplied PWM control signal. The three-phase BLDC motor rotates due to the drive signal from the driver.

[0027] When a three-phase BLDC motor rotates, it generates a back electromotive force voltage. Figure 9 In the motor drive system shown, the back EMF voltage is detected to control the speed of the three-phase BLDC motor. The detection timing for detecting the back EMF voltage will be described next.

[0028] A three-phase BLDC motor includes, for example, a stator formed of magnets and three-phase coils LA to LC attached to a rotor, which is surrounded by the stator. As the rotor rotates, a back electromotive force (EMF) voltage is generated in the coils LA to LC. Further, the back EMF voltage is detected in the phase to be measured at a timing point where the coil of the target phase for detecting the back EMF voltage is placed in a high-impedance state, and at a timing point where a potential difference is applied to the coils of the remaining two phases. Since the timing for applying the potential difference to the coils of the corresponding phases is executed via PWM control, the timing at which the back EMF voltage can be detected is limited.

[0029] Of the voltages HSA to HSC and the midpoint potential COMMON applied to the three-phase coils LA to LC, the voltages HSA to HSC or the midpoint potential COMMON in the phase to be measured is selected by the sensing unit Sense_Block in the gate driver Gate_Driver. The selected voltage, as the selection voltage BAMPO, is supplied to the analog external input terminal ADIN of the processor MCU via the external terminal of the gate driver Gate_Driver, which is a semiconductor device. The voltage of the phase to be measured is the sum of the midpoint potential and the back electromotive force (EMF) voltage, and the value of the back EMF voltage varies according to the speed of the three-phase BLDC motor; therefore, the selection voltage BAMPO is an analog signal. Thus, the processor MCU requires an analog-to-digital (A / D) conversion circuit to perform analog-to-digital (A / D) conversion in order to perform digital processing on the supplied back EMF voltage.

[0030] The processor MCU manages all timing for operating the three-phase BLDC motor and operates the A / D conversion circuit at appropriate timings to perform A / D conversion to the selected voltage BAMPO. Through this conversion, the processor MCU obtains the digital value of the midpoint electromotive force (EMF) COMMON and the digital value of the voltage of the phase to be measured. Comparing these two digital values ​​allows the processor MCU to determine the timing when the back EMF voltage and the midpoint EMF COMMON intersect (zero crossover determination). Furthermore, the processor MCU uses the conversion result of the A / D conversion to calculate the electrical rotation period of the three-phase motor, thereby allowing the PWM control signal to be modified to switch the drive phase of the three-phase BLDC motor at appropriate timing. That is, the processor MCU modifies the PWM control signal based on the calculated electrical rotation period to appropriately switch the phase through which the drive current flows.

[0031] However, as mentioned above, since the back EMF voltage is an analog signal to be processed by the processor, an A / D conversion circuit is required. Furthermore, the zero-crossing determination and the electric rotation period need to be calculated from the A / D conversion result. Performing these calculations requires processing time, which depends on the processor's MCU capabilities, and this processing time introduces delays in switching the drive phases of the three-phase BLDC motor, limiting the upper limit of the three-phase BLDC motor's speed.

[0032] In other words, to determine the zero-crossing of the back EMF voltage, the processor MCU needs to perform many steps, such as A / D conversion and comparison calculations with the midpoint potential, thus requiring processing time to execute these steps. Therefore, when attempting to rotate a three-phase BLDC motor at high speed, the time required for determining the zero-crossing of the back EMF voltage introduces a delay in the processor MCU's control, thereby limiting the motor's speed. In this case, even when using a high-performance processor MCU in a motor drive system, an issue arises regarding the upper limit of the three-phase BLDC motor's speed because a series of processes related to zero-crossing determination are not omitted.

[0033] As a means to address the aforementioned speed-limiting problems, the inventors of this application have configured a portion of the function for estimating motor speed based on back EMF voltage in hardware, and have explored incorporating this hardware into a gate driver (Gate_Driver) which is a semiconductor device. In this configuration, the gate driver generates a midpoint potential or a corresponding virtual midpoint potential, generates a timing signal indicating the timing of the intersection of the back EMF voltage and the virtual midpoint potential, and outputs this timing signal from the gate driver (Gate_Driver) to the processor MCU. This significantly reduces the load on the processor MCU.

[0034] However, the inventors discovered two new problems when attempting to adopt this configuration.

[0035] The first question concerns the timing of detecting the back EMF voltage generated by the motor. As mentioned above, the target phase for detecting the back EMF voltage is the non-energized phase. This requires placing the coil of the target phase in a high-impedance state and the coil of the other phase in a driven state (a state with a potential difference), but the gate driver (Gate_Driver) does not provide information on the timing of detecting the back EMF voltage.

[0036] The second issue concerns the phase used to detect the back EMF voltage. The gate driver (Gate_Driver) does not provide information indicating the location of the motor's rotor. Therefore, it is difficult for the gate driver (Gate_Driver) to identify the target phase for detecting the back EMF voltage.

[0037] (First Embodiment)

[0038] <Configuration of Motor Drive System>

[0039] Figure 1This is a block diagram illustrating the configuration of a motor drive system according to a first embodiment. In the drawing, reference numeral 100 denotes the motor drive system. The motor drive system 100 includes a processor (MCU) 1, a gate drive semiconductor device (Gate_Drive) 2, a driver 3, and a three-phase BLDC motor 4. Here, the three-phase BLDC motor 4 will be described as an example of a multi-phase sensorless motor, but the number of phases, etc., is not limited thereto. Furthermore, in addition to the three-phase BLDC motor 4, the motor drive system 100 can be configured with the processor 1, the gate drive semiconductor device 2, and the driver 3. Further, the processor 1 can also be used with systems other than the motor drive system 100.

[0040] <<Processor 1>>

[0041] Processor 1 has no particular limitations, but it is composed of a semiconductor device. Processor 1 includes multiple circuit blocks, but in Figure 1 Only the circuit blocks necessary for illustration are shown in the figure. In the same figure, reference numeral 5 indicates the processor core that operates according to the program, reference numeral 6 indicates the counter, and reference numeral 7 indicates the A / D conversion circuit. The processor 1 also includes external input / output terminals GPIO_HA to GPIO_HC and GPIO_LA to GPIO_LC, analog external input terminal ADIN, and interrupt external input terminal INTP, all disposed in the semiconductor device.

[0042] When the three-phase BLDC motor 4 is controlled according to the program, the processor core 5 generates PWM control signals HIA to HIC and LIA to LIC, and outputs them to the external input / output terminals GPIO_HA to GPIO_HC and GPIO_LA to GPIO_LC. Incidentally, the PWM control signals HIA to HIC are used to control the upper arm included in the driver 3, which will be described later, and the PWM control signals LIA to LIC are used to control the lower arm included in the driver 3, which will be described later.

[0043] There are no particular limitations on counter 6, but it starts counting in response to the interrupt signal (timing signal) BCMPO from the interrupt external input terminal INTP, and supplies the counted value until the interrupt signal BCMPO is input again to processor core 5. That is, counter 6 supplies the processor core 5 with the time information between interrupt signals BCMPO. As will be described in detail later, processor core 5 determines the time interval between the intersection of the back electromotive force voltage and the midpoint potential COMMON based on the supplied time information, changes the PWM control signals to be generated from HIA to HIC and from LIA to LIC, and switches the speed of the three-phase BLDC motor 4.

[0044] The A / D conversion circuit 7 converts the selection voltage BAMPO from the analog external input terminal ADIN into a digital signal and supplies it to the processor core 5. The A / D conversion circuit 7 will be described later in the fourth embodiment, and therefore further description of it will be omitted.

[0045] <<Gate drive semiconductor device 2, driver 3, and three-phase BLDC motor 4>>

[0046] There are no particular limitations on the gate driving semiconductor device 2, but it is composed of a semiconductor device and includes a control logic unit 8, a sense block 9, and a buffer 10. Furthermore, the gate driving semiconductor device 2 includes a first external terminal to a sixth external terminal disposed on the semiconductor device.

[0047] Here, the first external terminals are input external terminals T1HA to T1HC and T1LA to T1LC, where PWM control signals HIA to HIC and LIA to LIC are supplied from processor 1 to input external terminals T1HA to T1HC and T1LA to T1LC. The second external terminals are output external terminals T2HA, T2LA to T2HC and T2LC, which supply drive signals from gate drive semiconductor device 2 to driver 3. The third external terminal is input external terminals T3A to T3C, where back electromotive force voltage is supplied from driver 3 to input external terminals T3A to T3C. Additionally, the fourth external terminal is output external terminal T4, which supplies interrupt signal BCMPO to processor 1, and the fifth external terminal is output external terminal T5, which supplies selection voltage BAMPO, as an analog signal, to processor 1. Furthermore, the sixth external terminal is the input external terminal T6, and the midpoint potential COMMON is supplied from the three-phase BLDC motor 4 to the input external terminal T6.

[0048] In the PWM control signals HIA to HIC and LIA to LIC output by processor 1, PWM control signals HIA and LIA are PWM control signals corresponding to phase A of the three-phase BLDC motor 4, PWM control signals HIB and LIB are PWM control signals corresponding to phase B of the three-phase BLDC motor 4, and PWM control signals HIC and LIC are PWM control signals corresponding to phase C of the three-phase BLDC motor 4.

[0049] The control logic unit 8 generates internal drive signals ID_A to ID_C based on the PWM control signals HIA to HIC and LIA to LIC supplied to the external terminals T1HA to T1HC and T1LA to T1LC, and supplies the internal drive signals ID_A to ID_C to the buffer 10. That is, the control logic unit 8 generates the internal drive signal ID_A based on the PWM control signals HIA and LIA, the internal drive signal ID_B based on the PWM control signals HIB and LIB, and the internal drive signal ID_C based on the PWM control signals HIC and LIC.

[0050] Buffer 10 includes a unit buffer circuit DHA corresponding to phase A, a unit buffer circuit DHB corresponding to phase B, and a unit buffer circuit DHC corresponding to phase C. Unit buffer circuits DHA to DHC have almost identical configurations. Taking unit buffer circuit DHA as an example, the unit buffer circuit includes two buffers (HS, LS) 19 and 20. Unit buffer circuit DHA corresponds to phase A of the three-phase BLDC motor 4, and buffers 19 and 20 in unit buffer circuit DHA generate drive signals HOA and LOA according to the corresponding internal drive signal ID_A, and supply drive signals HOA and LOA to external terminals T2HA and T2LA, which are the second external terminals. Further, the voltage HSA from the corresponding phase A of the three-phase BLDC motor 4 is supplied to buffer 10 via external terminal T3A, which is the third external terminal. This voltage HSA is output from buffer 10 to sensing unit 9. Since unit buffer circuits DHB and DHC are also identical to unit buffer circuit DHA, their description will be omitted.

[0051] There are no particular restrictions on driver 3, but it is connected in parallel between the power supply voltage VM and the ground voltage GND, and includes three arms ARM_A to ARM_C corresponding to the respective phases of the three-phase BLDC motor 4. Since arms ARM_A to ARM_C have almost identical configurations, arm ARM_A will be described as an example.

[0052] Arm ARM_A includes an upper arm UAM_A and a lower arm DAM_A connected in series between the power supply voltage VM and the ground voltage GND. Each of the upper arm UAM_A and the lower arm DAM_A includes a diode DD connected in the opposite direction to the N-channel MOSFET (Field-Effect Transistor) NM. One end of the coil LA, configured to correspond to phase A, is connected to the connection node nd_A between the upper arm UAM_A and the lower arm DAM_A. Furthermore, a drive signal HOA from the external terminal T2HA is supplied to the gate of the MOSFET NM of the upper arm UAM_A, and a drive signal LOA from the external terminal T2LA is supplied to the gate of the MOSFET NM of the lower arm DAM_A. Further, the connection node nd_A is connected to the external terminal T3A.

[0053] The difference between arm ARM_B and arm ARM_A is that the connection node nd_B is connected to one end of the coil LB configured with the corresponding phase B, and is also connected to external terminals T2HB, T2LB, and T3B. Similarly, the difference between arm ARM_C and arm ARM_A is that the connection node nd_C is connected to one end of the coil LC configured with the corresponding phase C, and is also connected to external terminals T2HC, T2LC, and T3C.

[0054] The three-phase BLDC motor 4 includes the above-mentioned reference. Figure 9 The coils LA to LC correspond to the respective phases described. Here, coil LA corresponds to phase A, coil LB corresponds to phase B, and coil LC corresponds to phase C. As described above, one end of coils LA to LC is connected to connection nodes nd_A to nd_C, respectively, and the other end of each of coils LA to LC is connected to the midpoint CMN. In the first embodiment, the midpoint CMN is connected to the external terminal T6 of the gate drive semiconductor device 2, and the midpoint potential COMMON of the three-phase BLDC motor 4 is supplied from the midpoint CMN to the external terminal T6.

[0055] For example, when the MOSFET NM in driver 3 is turned on (becomes in the on state) according to the PWM control signals HIA to HIC and LIA to LIC, current flows through coils LA and LC, generating a magnetic field, and the rotor (not shown) rotates. At this time, for example, a back electromotive force voltage is generated in coil LB. At this time, a voltage HSB appears at the external terminal T3B, which is obtained by adding the back electromotive force voltage to the midpoint potential COMMON. The voltage HSB is supplied to the sensing unit 9 in the gate drive semiconductor device 2, and the midpoint potential COMMON is also supplied to the sensing unit 9 via the external terminal T6. The comparator circuit 18 detects intersection (zero crossover) by comparing the voltage HSB and the midpoint potential COMMON.

[0056] In the first embodiment, the sensing unit 9 has the function of estimating the rotation period of the three-phase BLDC motor 4. Further, the control logic unit 8 includes back EMF voltage detection control logic (hereinafter also referred to as control logic or back EMF detection logic) 11, for determining the phase to be detected among phases A to C.

[0057] <<<Back EMF Detection Logic and Sensing Unit>>>

[0058] The control logic unit 8 includes back EMF detection logic 11 and a counter 12. Although described in detail later with reference to the accompanying drawings, the back EMF detection logic 11 forms a sampling signal SMPEN and back EMF phase selection signals BDETA to BDETC based on the PWM control signals HIA to HIC and LIA to LIC, and supplies the sampling signal SMPEN and the back EMF phase selection signals BDETA to BDETC to the sensing unit 9. A signal from the comparison circuit described later is supplied to the counter 12. Since the counter 12 is described in the third embodiment, its description will be omitted here.

[0059] The sensing unit 9 includes a back EMF voltage multiplexer 13, sample / hold circuits 15, 16 and 17, a comparator circuit 18 and an amplifier 14.

[0060] Voltages HSA to HSC are supplied from buffer 10 to back EMF voltage multiplexer 13, and back EMF phase selection signals BDETA to BDETC are supplied from back EMF detection logic 11 to back EMF voltage multiplexer 13. Back EMF voltage multiplexer 13 selects and outputs a voltage corresponding to the phase specified by the back EMF phase selection signals BDETA to BDETC from voltages HSA to HSC.

[0061] The sampling signal SMPEN and the voltage selected by the back EMF voltage multiplexer 13 are supplied to the sample / hold circuit 16, and the sampling signal SMPEN and the midpoint potential COMMON are supplied to the sample / hold circuit 17. The sample / hold circuit 16 samples and holds the voltage selected by the back EMF voltage multiplexer 13 in response to changes in the sampling signal SMPEN. Simultaneously, the sample / hold circuit 17 samples and holds the midpoint potential COMMON in response to changes in the sampling signal SMPEN.

[0062] The voltage held by sample / hold circuit 16 and the midpoint potential COMMON held by sample / hold circuit 17 are supplied to comparator circuit 18. Comparator circuit 18 compares the voltage held by sample / hold circuit 16 with the midpoint potential COMMON and outputs the comparison result as an interrupt signal BCMPO to external terminal T4. The signals held by sample / hold circuits 16 and 17 are analog signals, but the interrupt signal BCMPO is converted into a binary digital signal through the above comparison. Furthermore, since the interrupt signal BCMPO changes when the back electromotive force voltage from sample / hold circuit 16 intersects with the midpoint potential COMMON, the interrupt signal BCMPO indicates the timing of the intersection (zero crossing).

[0063] Amplifier 14 amplifies the back-EMF voltage selected by back-EMF voltage multiplexer 13 and supplies this back-EMF voltage to sample / hold circuit 15. The back-EMF voltage held by sample / hold circuit 15 is supplied to external terminal T5 and is supplied to processor 1 as selection voltage BAMPO. Since amplifier 14 and sample / hold circuit 15 are described later in the fourth embodiment, they will not be described further here.

[0064] As mentioned above, although in Figure 1 The circuit blocks used for illustration in other embodiments are also drawn in the diagram, but needless to say, these circuit blocks may not exist in the motor drive system 100 according to the first embodiment.

[0065] When processor 1 changes, for example, the speed of a three-phase BLDC motor 4, it changes the PWM control signals HIA to HIC and LIA to LIC. In this case, processor 1 needs to know the current speed of the three-phase BLDC motor 4 to be controlled. When using back EMF voltage to detect the current speed, the back EMF voltage needs to be detected with appropriate timing and phase. Simultaneously, the PWM control signals HIA to HIC and LIA to LIC supplied from processor 1 to the gate drive semiconductor device 2 include information about the drive phase of the three-phase BLDC motor 4 and about the PWM operation.

[0066] In the first embodiment, the back EMF detection logic 11 extracts the optimal timing for detecting the back EMF voltage and the signal for determining the phase for detecting the back EMF voltage based on information about the drive phase and information about the PWM operations included in the PWM control signals HIA to HIC and LIA to LIC. Figure 1 In this context, the signal indicating the optimal timing for detecting the back EMF voltage corresponds to the sampling signal SMPEN, and the signal for determining the phase for detecting the back EMF voltage corresponds to the back EMF phase selection signals BDETA to BDETC.

[0067] In sensing unit 9, back-EMF voltage multiplexer 13 appropriately selects and switches a voltage corresponding to the phase of the detected back-EMF voltage according to back-EMF phase selection signals BDETA to BDETC. Further, synchronized with PWM control, sample-and-hold circuits 16 and 17 sample and hold the switched voltage and midpoint potential COMMON in response to the sampling signal SMPEN. Comparison circuit 18 compares the midpoint potential COMMON with the selected voltage, generating a detection signal indicating the intersection (zero-crossing) between the voltage and the midpoint potential COMMON, and converts this detection signal into a digital interrupt signal BCMPO. This interrupt signal BCMPO is input to the interrupt external input terminal INTP of processor 1.

[0068] The timing (edge) at which the interrupt signal BCMPO is switched is zero-crossing timing, and the processor 1 counts the time between the edges of the interrupt signal BCMPO that is input to the interrupt external input terminal INTP via the counter 6. Thus, for example, the speed of the three-phase BLDC motor can be determined without using the built-in A / D conversion circuit in the processor 1 to perform arithmetic processing for zero-crossing detection.

[0069] <<<Back EMF Detection Logic 11>>>

[0070] Next, the back EMF detection logic 11 will be described with reference to the accompanying drawings. Figure 2 is a view illustrating the operation of the motor drive system 100 according to the first embodiment. Figure 2A This is a waveform diagram showing the operation of the motor drive system 100. Further, Figure 2B This is a diagram (table) used to illustrate the back EMF detection logic 11.

[0071] exist Figure 2A In the code, BEMF-A to BEMF-C indicate the back electromotive force voltage generated in the corresponding phases A to C of the three-phase BLDC motor 4. Here, BEMF-A indicates the back electromotive force voltage generated in phase A, BEMF-B indicates the back electromotive force voltage generated in phase B, and BEMF-C indicates the back electromotive force voltage generated in phase C.

[0072] In addition, Figure 2AIn this context, codes HSA to HSC indicate the voltages (drive voltage and back electromotive force voltage) appearing in the coils LA, LB, and LC of the corresponding phases A to C. In other words, voltages HSA to HSC are the voltages at connection nodes nd_A to nd_C. Here, voltage HSA indicates the voltage corresponding to the voltage supplied to external terminal T3A (nd_A), voltage HSB indicates the voltage corresponding to the voltage supplied to external terminal T3B (nd_B), and voltage HSC indicates the voltage corresponding to the voltage supplied to external terminal T3C (nd_C).

[0073] exist Figure 2A and 2B In this code, HIA to HIC and LIA to LIC indicate the PWM control signals supplied from processor 1 to the gate drive semiconductor device 2, and control logic unit 8 generates internal drive signals ID_A to ID_C based on the PWM control signals HIA to HIC and LIA to LIC. Further, back EMF detection logic 11 generates sampling signal SMPEN and back EMF phase selection signals BDETA to BDETC based on the PWM control signals HIA to HIC and LIA to LIC.

[0074] Here, the sampling signal SMPEN is a timing signal that indicates the timing for detecting the back electromotive force (EMF) voltage generated by the rotation of the three-phase BLDC motor 4. Further, the back EMF phase selection signals BDETA to BDETC are selection signals used to specify the phase for detecting the back EMF voltage. At the timing indicated by the sampling signal SMPEN, the voltage in the phase specified by the back EMF phase selection signals BDETA to BDETC is compared with the midpoint potential COMMON, and the timing of the intersection of the voltage in the specified phase and the midpoint potential COMMON is detected. This timing is then notified to the processor 1 via the interrupt signal BCMPO. Incidentally, the voltage in the specified phase is obtained by adding the back EMF voltage to the midpoint potential COMMON.

[0075] In the case of a three-phase BLDC motor 4, the conditions for detecting the intersection of the voltage in a specified phase and the midpoint potential in a specified phase can be broadly classified into the following six types. That is, these conditions occur when the back electromotive force voltage BEMF-A of phase A is rising / falling, when the back electromotive force voltage BEMF-B of phase B is rising / falling, and when the back electromotive force voltage BEMF-C of phase C is rising / falling. These six states are... Figure 2BThe table shows: rising detection of phase A (rising edge of A); falling detection of phase C (falling edge of C); rising detection of phase B (rising edge of B); falling detection of phase A (falling edge of A); rising detection of phase C (rising edge of C); and falling detection of phase B (falling edge of B). Further, in Figure 2B The diagram shows the PWM control signals HIA to HIC and LIA to LIC used to generate the six states, as well as the sampling signals SMPEN and back EMF phase selection signals BDETA to BDETC in the six states.

[0076] When reference Figure 2B When explaining, the timing for detecting the back electromotive force voltage is when only one of the PWM control signals HIA to HIC is high, or when only one of the PWM control signals LIA to LIC is high. Figure 2B In the symbol Hi, a high level is indicated by the symbol Lo, and a low level is indicated by the symbol Lo. However, the underlined symbols Hi and Lo indicate the timing of detecting the back electromotive force voltage.

[0077] For example, when describing the timing of the rise detection (rising edge) of phase A, the time periods during which the PWM control signal HIC is high (Hi) and the time periods during which the PWM control signals HIA and HIB are low (Lo) constitute the timing for detecting the back EMF voltage. Incidentally, during this period (rising edge A), in order to connect phase B to ground voltage GND and phase C to power supply voltage VM, the PWM control signal HIC changes from low to high, and the PWM control signal LIC changes from high to low. Therefore, the timing for detecting the back EMF voltage is the period during which the PWM control signal HIC is high. Similarly, the remaining five states also allow the timing for detecting the back EMF voltage to be determined based on the state of the voltage of the PWM control signal supplied from processor 1.

[0078] Furthermore, the phase used for detecting the back EMF voltage can be specified via PWM control signals HIA to HIC and LIA to LIC. No power supply to the target phase is required for back EMF voltage detection. That is, the phases A to C that are not powered by the driver 3 and are in a non-energized state (high impedance state) are identified, making it possible to identify the phase used for detecting the back EMF voltage. In the first embodiment, the upper arms UAM_A to UMA_C and the lower arms DAM_A to DAM_C of the driver 3 are configured to be composed of N-channel MOSFETs NM.

[0079] Therefore, when both PWM control signals HIA and LIA are low, driving phase A becomes de-energized; when both PWM control signals HIB and LIB are low, driving phase B becomes de-energized; and when both PWM control signals HIC and LIC are low, phase C becomes de-energized. Figure 2B In this configuration, the state where both PWM control signals driving the corresponding phase are at a low level is clearly indicated by dots. In this way, the phase used for detecting the back electromotive force voltage can also be identified using the PWM control signals HIA to HIC and LIA to LIC.

[0080] In this way, based on the PWM control signals HIA to HIC and LIA to LIC supplied from processor 1, a sampling signal and a back EMF phase selection signal can be formed. The sampling signal indicates the timing for detecting the back EMF voltage, and the back EMF phase selection signal specifies the phase for detecting the back EMF voltage. Next, an example of back EMF detection logic 11 will be described with reference to the accompanying drawings, which forms a sampling signal SMPEN indicating the timing for detecting the back EMF voltage and back EMF phase selection signals BDETA to BDETC specifying the phase for detecting the back EMF voltage. Figure 3 This is a block diagram illustrating the configuration of the back EMF detection logic according to the first embodiment.

[0081] The back EMF detection logic 11 includes: inverter circuits 50_A to 50_C and 58_A to 58_C; AND circuits 51_A to 51_C, 55 and 56; OR circuits 52, 57_A to 57_C; delay circuits 53, 54; and trigger circuits 59_A to 59_C.

[0082] PWM control signals HIA to HIC are supplied from processor 1 to inverter circuits 50_A to 50_C and AND circuits 51_A to 51_C. Inverter circuits 50_A to 50_C invert the PWM control signals HIA to HIC and output inverted PWM control signals HIA / to HIC / . Taking the PWM control signal HIA as an example, the corresponding PWM control signal HIA and the inverted PWM control signals HIB / and HIC / are supplied to the AND circuit 51_A corresponding to the PWM control signal. Similarly, the corresponding PWM control signal and the inverted PWM control signals of the non-corresponding PWM control signals are supplied to AND circuits 51_B and 51_C. The outputs of AND circuits 51_A to 51_C are supplied to OR circuit 52. The output of OR circuit 52 is supplied to AND circuit 56 via two series-connected delay circuits 53 and 54, and is directly supplied to AND circuit 56. The output of AND circuit 56 is supplied as the sampling signal SMPEN to the sample / hold circuits 16 and 17 in sensing unit 9.

[0083] The output of OR circuit 52 is represented by the following logical formula:

[0084] HIA·HIB / ·HIC / +HIA / ·HIB·HIC / +HIA / ·HIB / ·HIC. Here, the symbol "·" indicates logical multiplication (AND), and "+" indicates logical summation (OR). From this formula, it can be understood that when one of the PWM control signals HIA to HIC goes high, the OR circuit 52 causes the output to go high. The output of the OR circuit 52 can be used as the sampling signal SMPEN, but the first embodiment includes delay circuits 53 and 54 and an AND circuit 56, so that the ringing portion of the motor drive voltage is not used for intersection determination with the midpoint potential COMMON due to the PWM operation, thereby optimizing the sampling signal SMPEN.

[0085] The corresponding PWM control signals HIA, LIA to HIC, and LIC are supplied to OR circuits 57_A to 57_C. The outputs of OR circuits 57_A to 57_C are supplied to the inputs D of the corresponding flip-flop circuits 59_A to 59_C via inverter circuits 58_A to 58_C. Additionally, the outputs of OR circuit 52 and delay circuit 53 are supplied to AND circuit 55. As a result, when the outputs of OR circuit 52 and delay circuit 53 go high, AND circuit 55 generates a pre-sampling signal SMPEN_PRE that changes to a high level. This pre-sampling signal SMPEN_PRE is supplied to the clock terminal CK of flip-flop circuits 59_A to 59_C. Incidentally, the output of OR circuit 52 can be used as the pre-sampling signal SMPEN_PRE. Furthermore, delay circuit 53 and AND circuit 55 can be configured between the output of OR circuit 52 and each of the inputs of flip-flop circuits 59_A to 59_C. Similar to the presampled signal SMPEN_PRE, the back EMF phase selection signals BDETA to BDTC are generated using PWM control signals HIA, HIB, and HIC. However, depending on the circuit configuration and layout, the changes in each inverter circuit of inverter circuits 58_A to 58_C may be slower than the generation of the presampled signal SMPEN_PRE. In this case, erroneous data may be introduced into the flip-flop circuits 59_A to 59_C. By providing the delay circuit 53 and the AND circuit 55 to the output of the OR circuit 52, the output of the presampled signal SMPEN_PRE can also be generated later than the output of the inverter circuits 58_A to 58_C, although the changes in each inverter circuit of inverter circuits 58_A to 58_C are delayed. This prevents erroneous data from being incorrectly introduced into the flip-flop circuits 59_A to 59_C.

[0086] As a result, among the PWM control signals HIA, LIA to HIC and LIC, only the OR circuit supplied with a low-level PWM control signal outputs a low level, causing a high level to be output from the corresponding inverter circuit. Therefore, when the presampled signal SMPEN_PRE changes to a high level, only the flip-flop circuit supplying a high level to input D causes the back EMF phase selection signal to output a high level. For example, when both PWM control signals HIA and LIA are low, the output of inverter circuit 58_A becomes high, and when the presampled signal SMPEN_PRE changes to a high level, flip-flop circuit 59_A receives and maintains the high level from inverter circuit 58_A.

[0087] As a result, the changes in the PWM control signal caused by the PWM operation are eliminated, and the high-level back EMF phase selection signal BDETA continues to be output from the flip-flop circuit 59_A. At this time, the low-level back EMF phase selection signals BDETB and BDETC continue to be output from the remaining flip-flop circuits 59_B and 59_C. That is, the back EMF phase selection signals BDETA to BDETC are output as signals from which the changes caused by the PWM operation have been removed.

[0088] The PWM control signals HIA to HIC and LIA to LIC supplied from processor 1 are signals that combine the drive phase of the three-phase BLDC motor with information about PWM operation. However, according to the first embodiment, the gate drive semiconductor device 2 can extract information for timing the detection of the back EMF voltage and for specifying the phase for detecting the back EMF voltage from the PWM control signals HIA to HIC and LIA to LIC through the back EMF detection logic 11. That is, even if processor 1 does not generate a specific control signal, the gate drive semiconductor device 2 can generate a signal for specifying the timing for detecting the back EMF voltage and a signal for specifying the phase for detecting the back EMF voltage.

[0089] Furthermore, the gate driving semiconductor device 2 generates signals for defining the timing for detecting the back electromotive force voltage and for defining the phase of the back electromotive force voltage. It determines the intersection (zero-crossing determination) of the voltage corresponding to the defined phase and the midpoint potential COMMON in the gate driving semiconductor device 2, thereby enabling the timing of the intersection to be notified to the processor 1 via, for example, an interrupt signal. As a result, the processor does not require an A / D conversion circuit for zero-crossing determination, nor does it need to perform arithmetic processing using that A / D conversion circuit.

[0090] Zero-crossing determination unit (ZCD) Figure 1 This can be considered to be configured by the aforementioned sensing unit 9 and back EMF detection logic 11. In this case, the zero-crossing determination unit ZCD generates an interrupt signal BCMPO based on the PWM control signal and the back EMF voltage. The interrupt signal BCMPO indicates the timing of the intersection of the back EMF voltage with the midpoint potential COMMON of the three-phase BLDC motor 4.

[0091] In addition, such as Figure 3As shown, the back EMF detection logic 11 can be considered to include a timing extraction circuit TDC and a phase detection circuit PDC. In this case, the timing extraction circuit TDC includes: inverter circuits 50_A to 50_C; AND circuits 51_A to 51_C, 56; OR circuit 52; and delay circuits 53, 54, and the timing extraction circuit TDC extracts the timing for detecting the back EMF voltage. Further, the phase detection circuit PDC includes: trigger circuits 59_A to 59_C supplied with a pre-sampling signal SMPEN_PRE; inverter circuits 58_A to 58_C; and AND circuits 57_A to 57_C, and the phase detection circuit PDC extracts the phase for detecting the back EMF voltage based on the PWM control signal.

[0092] According to the first embodiment, the arithmetic processing for zero-crossing determination in processor 1 can be reduced. By reducing this arithmetic processing, the delay time for switching motor drive phases is reduced, and the motor can be controlled to rotate at high speed.

[0093] (Second Embodiment)

[0094] In the second embodiment, a motor drive system is provided that can reduce the direct current in the driver 3 while enabling the motor to rotate at high speed.

[0095] When switching the series connection and configuring the state of the upper and lower arms of driver 3, the upper and lower arms conduct simultaneously at the moment of switching, and a direct current flows between the power supply voltage VM and the ground voltage. (See reference...) Figure 1 As described, for example, when the N-channel MOSFET configured with the upper arm UAM_A and the N-channel MOSFET configured with the lower arm DAM_A switch from the on / off state to the off / on state, the N-channel MOSFET will be temporarily turned on during the switching, and a shoot-through current may flow through these N-channel MOSFETs.

[0096] To prevent shoot-through current flow, in the motor drive system according to the second embodiment, both the N-channel MOSFETs used for configuring the series-connected upper and lower arms are controlled so that the time periods during which both are in the off state are sandwiched in between when switching the N-channel MOSFETs. However, through the inventors' research, it has been found that the method for determining the configuration described in the first embodiment is insufficient when performing this control.

[0097] Next, specific examples of the motor drive system according to the second embodiment will be described with reference to the accompanying drawings. The configuration of the motor drive system according to the second embodiment and... Figure 1The configurations of the motor drive systems shown are similar. The differences between the two are: when switching the state of the upper arm and the lower arm, the driver 3 is controlled to sandwich the time period during which both are turned off; and the back EMF detection logic 11 is structurally changed and becomes back EMF detection logic 11A.

[0098] Figure 4 This is a diagram illustrating the operation of the back electromotive force detection logic according to the second embodiment. Additionally, Figure 5 This is a block diagram illustrating the configuration of the back EMF detection logic according to the second embodiment. Incidentally, the overall configuration of the motor drive system according to the second embodiment is similar to... Figure 1 The configuration shown is the same.

[0099] Figure 4 Similar to Figure 2B The difference between them is that a portion of the PWM control signal supplied to the back EMF detection logic is changed, and the sampling signal SMPEN is also changed.

[0100] The states of the upper and lower arms can be switched based on the PWM control signal. Figure 4 In, for example, when describing the rising detection (rising edge) of phase A as an example, the voltage changes of the PWM control signals HIC and LIC corresponding to phase C cause... Figure 1 The diagram shows the switching of the states of the upper arm UAM_C and the lower arm DAM_C corresponding to phase C. Specifically, in the case of rising phase A, the PWM control signal HIC changes from low to high. At this time, the PWM control signal LIC changes from high to low. As a result, one end of the coil LC corresponding to phase C, which is connected to the ground voltage GND via the lower arm DAM_C, is connected to the power supply voltage VM via the upper arm UAM_C. At this time, as described above, the shoot-through current may flow instantaneously. To prevent this, as... Figure 4 As shown, during voltage switching, each of the PWM control signals HIC and LIC is provided with a time period during which both HIC and LIC simultaneously go low (Lo). This prevents the upper arm UAM_C and the lower arm DAM_C from simultaneously becoming on, and also prevents shoot-through current.

[0101] However, when extracting the timing for detecting the back EMF voltage from the PWM control signal, the back EMF detection logic 11 described in the first embodiment may not be able to extract this timing. For example, in Figure 4In the case of falling edge detection of phase C, if the timing for detecting the back EMF voltage is extracted only through the PWM control signals HIA, HIB, and HIC, then the low-level timing added to prevent shoot-through current flow will also be extracted as the timing for detecting the back EMF voltage. During this low-level timing to prevent shoot-through current flow, the voltages of both phase A and phase B become the supply voltage, and when a zero-crossing of the back EMF voltage is detected at this timing, the midpoint potential COMMON is switched to the supply voltage. Therefore, with... Figure 1 The incorrect determination was caused by the mismatch in the voltage input range of the comparator circuit 18 shown.

[0102] In the second embodiment, note all PWM control signals HIA to HIC and LIA to LIC supplied from processor 1, and the timing of these PWM control signals changing to a predetermined state is set as the timing for detecting the back EMF voltage. That is, the timing for detecting the back EMF voltage is set when only one of the PWM control signals HIA to HIC and only one of the PWM control signals LIA to LIC becomes high. Figure 4 As shown, this allows the low-level timing added to prevent shoot-through current to be eliminated from the timing of detecting the back EMF voltage.

[0103] Next, in the second embodiment, reference will be made to Figure 5 This section describes an example of how the back EMF detection logic 11A generates a sampling signal SMPEN and back EMF phase selection signals BDETA to BDETC.

[0104] Figure 5 Similar to Figure 3 The difference lies in the addition of inverter circuits 60_A to 60_C, AND circuits 61_A to 61_C, 63, and OR circuit 62. The inverter circuits 60_A to 60_C, AND circuits 61_A to 61_C, and OR circuit 62 are interconnected, thus possessing... Figure 3 The inverter circuits 50_A to 50_C, AND circuits 51_A to 51_C, and OR circuit 52 described earlier are configured similarly. However, PWM control signals LIA to LIC are supplied to inverter circuits 60_A to 60_C, and inverter circuits 60_A to 60_C output inverted PWM control signals LIA / to LIC / . Further, the PWM control signals LIA to LIC and the inverted PWM control signals LIA / to LIC / are supplied to AND circuits 61_A to 61_C.

[0105] The outputs of OR circuits 52 and 62 are supplied to AND circuit 63, and the output of AND circuit 63 is supplied to delay circuit 53 and AND circuit 55. That is, in Figure 3 In the OR circuit 52, the output of the OR circuit 52 is supplied to the delay circuit 53 and the AND circuit 55. However, in the back EMF detection logic 11A, the output of the added AND circuit 63 is supplied to the delay circuit 53 and the AND circuit 55.

[0106] The output of AND circuit 63 is represented by the following logical formula: (HIA·HIB / ·HIC / +HIA / ·HIB·HIC / +HIA / ·HIB / ·HIC)·(LIA·LIB / ·LIC / +LIA / ·LIB·LIC / +LIA / ·LIB / ·LIC). From this formula, it can be understood that when only one of the PWM control signals HIA to HIC goes high and only one of the PWM control signals LIA to LIC goes high, AND circuit 63 outputs a high level.

[0107] That is, when only one of the PWM control signals HIA to HIC is turned high and only one of the PWM control signals LIA to LIC is turned high, the sampling signal SMPEN goes high. This timing is for detecting the back electromotive force voltage. Further, similar to... Figure 3 When the pre-sampling signal SMPEN_PRE changes to a high level, the trigger circuits 59_A to 59_C hold and output the back electromotive force phase selection signals BDETA to BDETC.

[0108] The motor drive system according to the second embodiment enables the motor to rotate at high speed while reducing the direct current.

[0109] The timing extraction circuit TDC2 according to the second embodiment can be regarded as an addition of the logic circuit of the timing extraction circuit TDC described in the first embodiment, which excludes the period of maintaining the same potential for phase switching from the timing of detecting the back electromotive force voltage.

[0110] (Third Embodiment)

[0111] During the timing of switching the drive phase of the three-phase BLDC motor 4, the motor coils LA to LC ( Figure 1 A back electromotive force (EMF) voltage is generated during the period in which the back EMF voltage is generated. It is difficult to detect the back EMF voltage during this period. In the third embodiment, a function to avoid the influence of the back EMF voltage is added to the motor drive system described in the first or second embodiment.

[0112] First, the recoil operation used to generate the recoil voltage will be described. Figure 6 is a diagram illustrating the recoil operation. Here, Figure 6A The states of driver 3 and three-phase BLDC motor 4 are shown at the falling edge detection of phase C (falling edge of C). Additionally, Figure 6B It shows in Figure 6A The states of driver 3 and three-phase BLDC motor 4 are shown after the falling detection of phase C and the rising detection of phase B (rising edge of B). Further, Figure 6C The waveform of the recoil voltage generated when the drive phase is switched (in other words, when the detection phase is switched) is shown.

[0113] When a phase C drop-down detection is performed, current flows from phase A to phase B. In this state, as... Figure 6A As shown, the N-channel MOSFET (hereinafter also referred to as the high-side transistor) UNM used to configure the upper arm UAM_A is turned on by the drive signal HOA, and the N-channel MOSFET (hereinafter also referred to as the low-side transistor) DNM used to configure the lower arm DAM_A is turned off by the drive signal LOA. As a result, when the on-resistance of the high-side transistor UNM is Ronh and the drive current flowing through the high-side transistor UNM is Iab, the voltage HSA at the connection node nd_A becomes VM - Ronh * Iab, where VM is the power supply voltage.

[0114] At this time, the low-side transistor DNM, used to configure the lower arm DAM_B, is turned on by the drive signal LOB, and the high-side transistor UNM, used to configure the upper arm UAM_B, is turned off by the drive signal HOB. As a result, when the on-resistance of the low-side transistor DNM is Ron1, the voltage HSB at the connection node nd_B becomes GND + Ron1 * Iab, where GND is the ground voltage. That is, when a drive voltage is applied to the coils LA and LB configuring phases A and B, a drive current Iab flows through coils LA and LB, thereby generating a magnetic field. At this time, no drive voltage is applied to the coil LC configuring phase C to generate a back electromotive force voltage; coil LC is in a high-impedance state, and no drive current flows through coil LC.

[0115] The state of phase C falling detection is changed to the state of phase B rising detection. That is, driver 3 from Figure 6A State switch Figure 6B The state. In Figure 6BIn order to detect the back electromotive force voltage in coil LB of phase B, the low-side transistor DNM of the lower arm DAM_B corresponding to phase B is turned off, and coil LB is switched to a high-impedance state. Further, the low-side transistor DNM of the lower arm corresponding to phase C is switched on, allowing drive current to flow through coils LA and LC.

[0116] However, as described above, even after the low-side transistor DNM of the lower arm DAM_B is turned off and the coil LB is switched to a high-impedance state, the coil LB continues to operate to allow the drive current Iab to flow. As a result, as Figure 6C As shown, the voltage HSB at the connection node nd_B rises and reaches the forward voltage Vf of the power supply voltage VM+ diode (the body diode of the high-side transistor UNM) DD. At this point, using phase B to detect the back EMF voltage will result in an incorrect detection. That is, a recoil voltage KB is generated during the period before the current flowing through coil LB disappears due to the effect of coil LB, and the back EMF voltage cannot be detected using phase B.

[0117] Here, the case of switching from falling detection of phase C to rising detection of phase B is described as an example, but similarly, a recoil voltage KB is generated when switching each phase as shown in Figure 2.

[0118] In the third embodiment, a mask signal is formed such that the back EMF voltage is not detected when the recoil voltage is generated, and the following function is added to the motor drive system of the first or second embodiment: the detection of the back EMF voltage is delayed until the recoil voltage subsides (converges).

[0119] like Figure 1 As shown, in the motor drive system according to the third embodiment, the control logic unit 8 includes a counter 12. As... Figure 1 As shown, the interrupt signal BCMPO is supplied from the comparator circuit 18 to the counter 12, and the counter 12 will output the mask signal MASK (to be displayed later). Figure 7 (As shown in the figure) is supplied to the back EMF detection logic. Counter 12 starts counting by changing the interrupt signal BCMPO, and when only the value corresponding to the predetermined time is counted, counter 12 changes the mask signal MASK and returns its count value to the initial value. Since the back EMF detection logic according to the third embodiment is a modification of the back EMF detection logic 11 and 11A described in the first and second embodiments, for ease of explanation, the back EMF detection logic according to the third embodiment is referred to as reference numeral 11B.

[0120] Using back EMF detection logic 11 as an example, the differences between back EMF detection logics 11 and 11B will be described. Back EMF detection logic 11B has a mask calculation circuit added to back EMF detection logic 11. The sampling signal SMPEN and the mask signal MASK from counter 12 are supplied to the mask calculation circuit, a logical operation is performed between the sampling signal SMPEN and the mask signal MASK, and the signal obtained through the logical operation is output as the sampling signal SMPEN2, which avoids the effects caused by recoil voltage. In a third embodiment, the sampling signal SMPEN2 is supplied to sample / hold circuits 16 and 17 instead of the sampling signal SMPEN.

[0121] Next, the operation of the third embodiment will be described with reference to the accompanying drawings. Figure 7 This is a waveform diagram showing the operation of the motor drive system according to the third embodiment. Because... Figure 7 Similar to Figure 2, the differences between them will be described in detail.

[0122] The difference lies in: Figure 7 Add the mask signal MASK and the sampling signal SMPEN2 to Figure 2.

[0123] In the third embodiment, the mask release time for releasing the sampled signal SMPEN is set using the rotation cycle of the three-phase BLDC motor 4. That is, the previous drive phase switching time is saved as "x [sec]", and the mask release time Tdelay is estimated using this time x. Specifically, the saved drive phase switching time x is divided by the desired variable n (x / n), and the result of this division is defined as the mask release time Tdelay. In the aforementioned counter 12, this mask release time Tdelay is set to a predetermined time. Here, the variable n is a variable used to optimize the mask signal MASK, and is set based on the rotation speed of the three-phase BLDC motor 4, the frequency of the PWM operation, and its duty cycle. Further, the mask release time of the mask signal MASK is initiated by the timing of the drive phase switching. That is, the masking of the mask signal begins in response to a change in the interrupt signal BCMPO output from the comparator circuit 18.

[0124] Counter 12 begins counting by switching the drive phase (a change in the interrupt signal BCMPO). As a result, counter 12 changes the mask signal MASK high and masks the sampled signal SMPEN. Consequently, the sampled signal SMPEN2 supplied to sample / hold circuits 16 and 17 is held low. When counter 12 counts and reaches the mask release time Tdelay, counter 12 sets the mask signal MASK low. As a result, the sampled signal SMPEN is output as sampled signal SMPEN2.

[0125] Therefore, during the period when the recoil voltage KB is generated, the sample / hold circuit 16 does not sample / hold the back EMF voltage from the back EMF voltage multiplexer 13. Furthermore, during this period, the sample / hold circuit 17 also does not sample / hold the midpoint potential COMMON. As a result, erroneous detection of the back EMF voltage due to the recoil voltage can be prevented.

[0126] Incidentally, although there are no particular limitations, in the third embodiment, processor 1 performs the saving of the previous drive phase switching time x and the calculation of the mask release time Tdelay, and processor 1 sets the mask release time Tdelay to counter 12. Of course, the invention is not limited to this, and the gate drive semiconductor device 2 can perform these operations.

[0127] The timing extraction circuit according to the third embodiment is considered to be an addition of logic circuitry to the timing extraction circuit described in the first embodiment, which excludes the period of backlash from the timing of detecting the back electromotive force voltage. In this logic circuitry, a mask signal MASK is formed, and the sampling signal SMPEN is masked to generate a sampling signal SMPEN2.

[0128] (Fourth Embodiment)

[0129] In the operation from the start-up of a three-phase BLDC motor to reaching high-speed rotation, the following method for detecting back EMF voltage is considered suitable: for example, using the A / D conversion circuit built into processor 1 in the low-speed rotation range, and using the configuration described in the first to third embodiments in the high-speed rotation region. The fourth embodiment provides a motor drive system capable of changing the configuration for detecting back EMF voltage according to the rotational speed of the three-phase BLDC motor. In this way, by reducing the conditions (environment) for using the configurations described in the first to third embodiments, a more efficient configuration can be anticipated. For example, when using the configuration described in the third embodiment only in the high-speed rotation region, the size of the gate drive semiconductor device 2 can be reduced. That is, in the third embodiment, a counter 12 needs to be provided in the gate drive semiconductor device 2, but when using the configuration of the third embodiment only in the high-speed rotation region, reducing the number of stages of the counter 12 and reducing the size of the counter 12 makes it possible to reduce the size of the gate drive semiconductor device 2.

[0130] In the fourth embodiment, as Figure 1 As shown, the gate driving semiconductor device 2 includes an amplifier 14, a sample / hold circuit 15, and an external terminal T5. Furthermore, the processor 1 includes an analog external input terminal ADIN and an A / D conversion circuit 7.

[0131] Next, the operation of the motor drive system according to the fourth embodiment will be described with reference to the accompanying drawings. Figure 8 This is a flowchart illustrating the operation of the motor driver according to the fourth embodiment. Here, the case where the three-phase BLDC motor 4 starts from a stopped state and rotates at high speed will be described.

[0132] First, in step S0, the operation is started. Next, in step S1, the phase position of the three-phase BLDC motor is detected (motor position detection).

[0133] In step S2, initial acceleration is performed. That is, the three-phase BLDC motor 4 is initially accelerated under (multiple) conditions optimized for each motor drive system. During this initial acceleration, the back electromotive force voltage is not detected.

[0134] Upon completion of the initial acceleration, in step S3, the processor 1 (A / D conversion circuit 7) confirms the rotational speed of the BLDC motor. In this step, the back-EMF voltage output from the back-EMF voltage multiplexer 13 in the gate drive semiconductor device 2 is amplified by the amplifier 14 and sampled and held by the sample / hold circuit 15. The held analog back-EMF voltage is output to the analog external input terminal ADIN of the processor 1 via the external terminal T5 as the selection voltage BAMPO. The selection voltage BAMPO is converted into a digital signal by the A / D conversion circuit 7 and supplied to the processor core 5. In steps S4 and S5, the processor core 5 confirms the rotational speed of the three-phase BLDC motor 4 based on the supplied back-EMF voltage and performs control according to the confirmed rotational speed. In step S4, the three-phase BLDC motor 4 is driven by PWM operation, and in step S5, the processor 1 (A / D conversion circuit 7) performs zero-crossing determination to determine the rotational speed.

[0135] In step S6, it is determined whether the rotational speed PRM obtained in step S5 has reached the predetermined rotational speed x (rpm). If the rotational speed RPM has not yet reached the predetermined rotational speed x, the process returns to step S4, and the rotational speed is increased through PWM operation.

[0136] When the rotational speed RPM reaches the predetermined speed x, the three-phase BLDC motor 4 is driven by PWM in step S7, and zero-crossing determination is performed by the gate drive semiconductor device 2 in step S8. In this case, as described in the first embodiment, the gate drive semiconductor device 2 compares the back electromotive force voltage and the midpoint potential COMMON, performs zero-crossing determination, and notifies the processor 1 of the determination result as an interrupt signal BCMPO.

[0137] Processor 1 uses the interrupt signal BCMPO to confirm the rotational speed of the three-phase BLDC motor 4. In step S9, it determines whether the confirmed rotational speed RPM has reached the predetermined speed x. If the confirmed rotational speed RPM has reached the predetermined speed x, the process returns to step S7; otherwise, the process returns to step S4.

[0138] In the fourth embodiment, a predetermined speed x is used as a boundary to identify the high-speed rotation region and the low-speed rotation region. That is, the case where the speed of the three-phase BLDC motor 4 is less than the predetermined speed x is defined as the low-speed rotation region, and the case where the speed is greater than the predetermined speed x is defined as the high-speed rotation region. The predetermined speed x can be determined according to the specifications and circuit design of the three-phase BLDC motor and the motor drive system.

[0139] Furthermore, in the fourth embodiment, Figure 8 The flowchart is executed by processor 1, but is of course not limited to this.

[0140] For example, when the back electromotive force voltage is converted into a digital signal using the A / D conversion circuit in the processor, the back electromotive force voltage is sampled, and the voltage between the high-level and low-level voltages obtained through sampling is converted into the value of the digital signal. As the motor speed increases, the number of sampling points decreases, leading to a situation where an accurate digital signal cannot be obtained. If the motor speed is even higher, sampling may not be possible at all, also resulting in a situation where conversion to a digital signal is impossible. To prevent this, a higher sampling frequency is considered; however, a higher sampling frequency can cause increased power consumption or temperature. According to the first to fourth embodiments, zero-crossing determination can be performed without using the A / D conversion circuit at least during high-speed motor rotation, and high-speed rotation can be controlled while suppressing increased power consumption and / or increased temperature.

[0141] Furthermore, according to the first to third embodiments, the A / D conversion circuit for zero-crossing determination becomes unnecessary, thereby enabling, for example, miniaturization of the processor 1. Alternatively, instead of the A / D conversion circuit, another function can be added to the processor 1 to increase added value.

[0142] As described above, although the present invention has been specifically described based on embodiments, the present invention is not limited to the embodiments, and needless to say, various modifications can be made without departing from its spirit. For example, a circuit block is provided between the first external terminals T1HA to T1HC, T1LA to T1LC and the control logic unit 8 for switching the external terminals to programmability, and any external terminal can be able to supply a PWM control signal to the control logic unit 8 as a first external terminal.

Claims

1. A semiconductor device, comprising: A first external terminal is configured to be supplied with a plurality of pulse width control signals, the plurality of pulse width control signals including an upper pulse width control signal for controlling the upper arm of the driver and a lower pulse width control signal for controlling the lower arm of the driver, the driver being used to drive a multiphase sensorless motor; The second external terminal is configured to output a drive signal for driving the multiphase sensorless motor; The third external terminal is configured to be supplied with a back electromotive force voltage, which is generated by driving the multiphase sensorless motor; The circuit system is configured to generate an interrupt signal based on the pulse width control signal and the back electromotive force voltage, the interrupt signal indicating the timing of the intersection of the back electromotive force voltage with the midpoint potential of the multiphase sensorless motor; as well as The fourth external terminal is configured to output the interrupt signal. The circuit system includes a timing extraction circuit configured to extract the timing for detecting the back electromotive force voltage based on the pulse width control signal. The timing extraction circuit includes logic circuitry configured to generate a sampling signal for detecting the back electromotive force (EMF) voltage based on the upper pulse width control signal and the lower pulse width control signal. The timing for detecting the back EMF voltage is enabled only when only one pulse width control signal in the upper pulse width control signal and only one pulse width control signal in the lower pulse width control signal are high. This excludes time periods from the timing for detecting the back EMF voltage during which the pulse width control signals have the same potential for phase switching. The aforementioned time period is a low-level period added to prevent shoot-through current caused by the phase switching.

2. The semiconductor device according to claim 1, The circuit system includes a phase detection circuit configured to extract the phase in which the back electromotive force voltage should be detected based on the pulse width control signal.

3. The semiconductor device according to claim 1, The same potential mentioned therein is a low level.

4. A motor drive system, comprising: Multiphase sensorless motor; The processor is configured to output varying pulse width control signals based on interrupt signals; as well as The semiconductor device according to claim 1.

5. The motor drive system according to claim 4, The circuit system includes a phase detection circuit configured to extract the phase in which the back electromotive force voltage should be detected based on the pulse width control signal.

6. The motor drive system of claim 5 further includes a driver configured to drive the multiphase sensorless motor according to a drive signal output from the semiconductor device.

7. The motor drive system according to claim 4, The processor includes a counter controlled by the interrupt signal, and The time between the interrupt signal and another interrupt signal is measured by the counter, and the pulse width control signal is changed based on the measured time.

8. The motor drive system according to claim 4, The processor mentioned above includes: The counter is configured to be controlled by the interrupt signal; as well as The conversion circuit is configured to convert the back electromotive force voltage into a digital signal, and The processor changes the pulse width control signal based on the time measured by the counter or the digital signal obtained by the conversion circuit.

Images