Apparatus and method for coupling multiple semiconductor devices

Abstract

Disclosed are apparatus and methods for coupling multiple semiconductor devices. The terminals (e.g., die pads) of multiple semiconductor devices can be coupled in a daisy-chain manner by coupling one or more terminals of the semiconductor device to a conductive structure of two conductive bonding pads. The conductive structure may be included in a redistribution layer RDL structure. In some embodiments of the present disclosure, the RDL structure may be "U" shaped. Each end of the "U" shape may be coupled to a corresponding one of the two conductive bonding pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bonding pad of the semiconductor device may be coupled to the conductive bonding pad of other semiconductor devices via a conductor (e.g., a bonding wire). Therefore, the terminals of the semiconductor device may be coupled in a daisy-chain manner via the RDL structure, the conductive bonding pad, and the conductor.

Description

Technical Field

[0001] The present application relates to semiconductors, and in particular to apparatus and methods for coupling multiple semiconductor devices. Background Art

[0002] In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by vertically stacking dies and coupling the dies using through-silicon (or through-substrate) vias (TSVs) and / or wire bonding. Therefore, 3D memory may also be referred to as "stacked memory". Compared to non-3D memory, 3D memory may provide greater memory capacity and / or higher bandwidth with less area increase. Example 3D memory devices include hybrid memory cubes (HMCs), high bandwidth memories (HBMs), and master-slave memories (MSMs), each of which may include multiple dynamic random access memory (DRAM) dies coupled to each other in a stack.

[0003] The memory device can be coupled to an external circuit that provides command signals, address signals, and data signals to the stacked die to access the memory. The stacked die are usually coupled to the external circuit in parallel. Therefore, when providing signals to the stacked die, the external circuit drives the signal against the load of all the die, which may be a large amount of load. The heavy load presented by the stacked die can reduce signal integrity (SI), which may cause data to be incorrectly latched at the receiver, and / or cause increased power consumption. In some applications, reduced SI and increased power may be unacceptable. Summary of the invention

[0004] In one aspect, the present application relates to an apparatus comprising: a plurality of semiconductor devices, the plurality of semiconductor devices including a first semiconductor device, a second semiconductor device, and a third semiconductor device, each of the plurality of semiconductor devices including a die pad coupled to at least one circuit of the corresponding semiconductor device, and further including a redistribution layer structure coupled to the die pad and further coupled to a first bonding pad and a second bonding pad, wherein the second bonding pad of the first semiconductor device is coupled to the first bonding pad of the second semiconductor device, and the second bonding pad of the second semiconductor device is coupled to the first bonding pad of the third semiconductor device.

[0005] On the other hand, the present application relates to a multi-die device, comprising: a substrate comprising a conductive signal line; a stack of semiconductor devices, the stack being attached to the substrate, each of the semiconductor devices in the stack comprising a terminal and a redistribution layer structure coupled to the terminal, and wherein the terminals of the semiconductor devices in the stack are coupled together in a daisy chain through the redistribution layer structure; and a circuit, the circuit being attached to the substrate and coupled to a first semiconductor device in the stack of semiconductor devices through the conductive signal line.

[0006] On the other hand, the present application relates to a device comprising: a memory array configured to store data; a terminal; an input / output circuit configured to receive data from the memory array and provide read data, and to receive write data to be stored in the memory array; a command and address input circuit configured to receive command and address signals; a first bonding pad and a second bonding pad; and a U-shaped conductive structure coupled to the terminal and including a first portion extending between the terminal and the first bonding pad and coupled to the terminal and the first bonding pad, and further including a second portion extending between the terminal and the second bonding pad and coupled to the terminal and the second bonding pad.

[0007] On the other hand, the present application relates to a method comprising: coupling a bonding pad of a first semiconductor device to a first U-shaped conductive structure; coupling a bonding pad of a second semiconductor device to a second U-shaped conductive structure; coupling a bonding pad of a third semiconductor device to a third U-shaped conductive structure; coupling a second portion of the first U-shaped conductive structure to a first portion of the second U-shaped conductive structure; and coupling a second portion of the second U-shaped conductive structure to a first portion of the third U-shaped conductive structure, wherein the first portion of the first U-shaped conductive structure is coupled to a circuit, and wherein the second portion of the third U-shaped conductive structure is coupled to a fourth semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is a diagram illustrating a multi-die device according to an embodiment of the present disclosure.

[0010] Figure 3 is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure.

[0013] Figure 6 is a diagram illustrating an RDL structure coupling a terminal of a semiconductor device to a bonding pad according to an embodiment of the present disclosure.

[0014] Figure 7 is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Disclosed are apparatus and methods for coupling semiconductor devices. The terminals of multiple semiconductor devices can be coupled in a daisy-chain manner by coupling one or more terminals of the semiconductor device to a conductive structure of two conductive bonding pads. The terminal may be a die pad of the semiconductor device. The conductive structure may be included in a redistribution layer RDL structure. In some embodiments of the present disclosure, the RDL structure may be "U" shaped. Each end of the "U" shape may be coupled to a corresponding one of the two conductive bonding pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bonding pad of the semiconductor device may be coupled to the conductive bonding pad of other semiconductor devices via a conductor (such as a bonding wire). Therefore, the terminals of the semiconductor device may be coupled in a daisy-chain manner via the RDL structure, the conductive bonding pad, and the conductor.

[0016] The various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which show specific aspects and embodiments of the present disclosure by way of illustration. The detailed description contains enough details to enable those skilled in the art to practice the embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0017] Figure 1 1 is a block diagram of a semiconductor device 110 according to an embodiment of the present disclosure. For example, in some embodiments, the semiconductor device 110 may be a memory integrated into a single semiconductor chip (e.g., a semiconductor die). Example memories may include volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM), and non-volatile memories such as flash memory, resistive memory, and ferroelectric memory, or any combination thereof.

[0018] The semiconductor device 10 includes a memory cell array 111. The memory cell array 111 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder / driver 112, and the selection of the bit lines BL is performed by a column decoder / driver 113. A sense amplifier 118 is coupled to the corresponding bit line BL and connected to a local I / O line pair LIOT / B. The local IO line pair LIOT / B is connected to the main IO line pair MIOT / B through a transmission gate TG 119 used as a switch.

[0019] The semiconductor device 110 includes a plurality of terminals. In some embodiments of the present disclosure, the terminal may be a die pad. The plurality of terminals include a command and address terminal 121, clock terminals 123 and 123', a data terminal 124, a data strobe terminal 124', and power supply terminals 125 and 126. The data terminal 124 may be coupled to an output buffer of the input / output circuit 117 for a read operation. Alternatively, the data terminal 124 may be coupled to an input buffer of the input / output circuit 117 for write access of the memory in response to a data strobe signal DQS provided at the data strobe terminal 124'.

[0020] The command and address terminal 121 is supplied with a command and address signal CA, which includes a command address and a memory address. The address provided to the command and address terminal 121 is transmitted to the address decoder 132 through the command / address input circuit 131. The address decoder 132 receives the address and supplies the decoded row address to the row decoder / driver 112 and supplies the decoded column address to the column decoder / driver 113. The address decoder 132 also receives the group address and provides the group address signal to the row decoder / driver 112 and / or the column decoder / driver 113. In the self-refresh mode, the self-refresh circuit 138 can provide the row address to the row decoder / driver 112 for a self-refresh operation.

[0021] The command supplied to the command and address terminal 121 is supplied to the command decoder 134 through the command and address input circuit 131. The command decoder 134 decodes the command and supplies the decoded command to the internal control signal generator 137. In response to the decoded command from the command decoder 134, the internal control signal generator 137 may generate various internal command signals. For example, the internal command may include a row command signal for selecting a word line and a column command signal for selecting a bit line, such as a read command or a write command, etc.

[0022] Therefore, when an activation command is issued and a row address is supplied in time with the activation command, and a column address is supplied in time with a read command, read data is read from the memory cell MC specified by the row address and the column address in the memory cell array 111. The read data DQ is output from the data terminal 124 through the read / write amplifier 115 and the input / output circuit 117. Similarly, when an activation command is issued and a row address is supplied in time with the activation command, and a column address is supplied in time with a write command, write data DQ supplied to the data terminal 124 is supplied to the memory cell array 111 through the input / output circuit 117 and the read / write amplifier 115, and the DQ is written into the memory cell MC specified by the row address and the column address.

[0023] The clock terminal 123 is supplied with clock signals CK_t and CK_c, respectively, and the clock terminal 123' is supplied with data clock signals WCK_t and WCK_c. The clock input circuit 135 receives the clock signals CK_t and CK_c and WCK_t and WCK_c, and generates an internal clock signal ICLK. The internal clock signal ICLK may include an internal clock signal based on the clock signals CK_t and CK_c and / or an internal clock signal based on the data clock signals WCK_t and WCK_c. Some or all of the internal clock signal ICLK are supplied to the internal clock and timing generator 136, which generates a phase-controlled internal clock signal LCLK in response. Although not limited to this, the internal clock and timing generator 136 may include a DLL circuit. The phase-controlled internal clock signal LCLK may be supplied to the input and / or output circuit 117 and used for the timing of the input and output of data. The internal clock and timing generator 136 may further generate various other internal clock signals to perform various memory operations.

[0024] Power supply potentials VDD and VSS are supplied to the power supply terminal 125. These power supply potentials VDD and VSS are supplied to the power supply circuit 139. The power supply circuit 139 can generate various internal potentials, such as VPP, VOD, VARY, VPERI, etc. The internal potential VPP is mainly used in the row decoder / driver 112, the internal potentials VOD and VARY are mainly used in the sense amplifier 118 included in the memory cell array 111, and the internal potential VPERI is used in many other circuit blocks. Power supply potentials VDDQ and VSSQ are supplied to the power supply terminal 126. These power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 117. The power supply potentials VDDQ and VSSQ can be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal 125, respectively. However, the power supply potentials VDDQ and VSSQ can be used for the input / output circuit 117 so that the power supply noise generated by the input / output circuit 117 does not propagate to other circuit blocks.

[0025] Figure 2 2 is a diagram showing a multi-die device 200 according to an embodiment of the present disclosure. The multi-die device 200 may include a stack 215 of semiconductor devices 220. The embodiments of the present disclosure are not limited to Figure 2 2 is a diagram showing a specific number of semiconductor devices 220 included in the stack 215. In some embodiments of the present disclosure, each of the semiconductor devices 220 includes Figure 1 A semiconductor device 110 is provided.

[0026] The semiconductor devices 220 can be stacked in a staggered manner, thereby providing a "shingle-stack" configuration for the stack 215. The semiconductor devices 220 can be attached to each other. In some embodiments of the present disclosure, the semiconductor devices 220 are attached to each other by adhesive epoxy. The semiconductor devices 220 are offset from each other to allow the edge areas of the semiconductor devices 220 to be exposed. The exposed edge areas may include bonding pads to which the conductors 225 can be coupled. In some embodiments of the present disclosure, the bonding pads of the edge areas may be conductive pads. The bonding pads may be coupled to the terminals of the corresponding semiconductor devices 220. In some embodiments of the present disclosure, the conductors 225 are bonding wires.

[0027] The stack 215 may be attached to a substrate 230. In some embodiments of the present disclosure, the stack may be attached to the substrate 230 by an adhesive epoxy. The substrate 230 may include conductive signal lines for routing signals along the substrate, for example, to or from the semiconductor device 220. Other circuits may also be attached to the substrate 230 and may also be coupled to the conductive signal lines. Thus, the circuits attached to the substrate 230 may be coupled to the semiconductor device 220, for example, by conductive signal lines of the substrate 230 and conductors coupled to the conductive signal lines and bonding pads of the semiconductor device. Figure 2 200 and coupled to the semiconductor devices in the stack 215. In some embodiments of the present disclosure, the circuit 235 may be a register clock driver (RCD). In such embodiments of the present disclosure, the RCD circuit receives and buffers signals provided to the multi-die device 200 and may provide signals to the semiconductor device 220. Additional or alternative circuits may be included in the multi-die device 200, and / or the circuit 235 may be other circuits without departing from the scope of the present disclosure.

[0028] Figure 3 is a layout diagram of a semiconductor device 310 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device 310 includes Figure 1 In some embodiments of the present disclosure, the semiconductor device 310 includes Figure 2 The semiconductor device 220 in the stack 215 is shown in FIG.

[0029] The semiconductor device 310 may have edges 350a, 350b, 350c, and 350d that define ends of the semiconductor device 310. The edges 350b and 350d may extend along a first direction 357a, and the edges 350a and 350c may extend along a second direction 357b that may be perpendicular to the first direction 357a. The semiconductor device 310 may include a pad formation region 351, a peripheral circuit region 352, and a memory cell array region 353, wherein the memory cell array region includes memory cells, circuits, and signal lines, such as sense amplifier circuits, address decoder circuits, data input / output lines, etc. The peripheral circuit region 352 may include various circuits and signal lines for performing various operations of the semiconductor device 310. For example, the peripheral circuit region 352 may include command and address input circuits, address and command decoders, clock circuits, power supply circuits, and input / output circuits. The peripheral circuit region 352 may also include terminals coupled to various circuits of the semiconductor device (e.g., as previously described for Figure 1 The terminal may be, for example, a die pad of the semiconductor device.

[0030] The pad formation region 351 may include a plurality of bonding pads 354 disposed along the edge 350a. The plurality of bonding pads 354 may be coupled to terminals of the semiconductor device (e.g., a die pad) and represent external terminals of the semiconductor device 310. For example, the plurality of pads 354 may include data terminals, command and address terminals, clock terminals, and / or power terminals.

[0031] The circuits included in the memory cell array region 353 and / or the circuits of the peripheral circuit region 352 may be coupled to one or more bonding pads 354 included in the pad formation region 351. As previously described, various circuits of the semiconductor device 300 may be coupled to terminals (e.g., die pads). The conductive structure may be used to couple the terminal to one or more of the bonding pads 354. Thus, the circuit coupled to the terminal is also coupled to the bonding pad 354. The conductive structure may extend from the location of the terminal included in the memory cell array region 353 and / or the peripheral circuit region 352 to the pad formation region 351. In some embodiments of the present disclosure, the conductive structure may include a conductive redistribution layer (RDL).

[0032] Figure 4 is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the conductive structure may include Figure 1 The semiconductor device 110, Figure 2The semiconductor device 220 of the multi-die device 200, Figure 3 In the semiconductor device 310 and / or any semiconductor device according to the embodiments of the present disclosure. For example, in some embodiments of the present disclosure, the conductive structure may be included in Figure 1-3 in a conductive redistribution layer (RDL) in one or more semiconductor devices in a semiconductor device.

[0033] Conductive structure 430 may couple terminal 440 of the semiconductor device to bonding pad 420. In some embodiments of the present disclosure, terminal 440 may be a die pad. Terminal 440 may be coupled to one or more circuits 445 of the semiconductor device. Thus, bonding pad 420 may be coupled to circuit 445 via conductive structure 430 and terminal 440. In some embodiments of the present disclosure, circuit 445 may be, for example, included in a memory cell array region (e.g., Figure 3 In some embodiments of the present disclosure, the circuit 445 may be, for example, a circuit included in a peripheral circuit region (eg, Figure 3 The circuit 445 may be used to perform various operations of the semiconductor device. In some embodiments of the present disclosure, the circuit 445 may include a command and address input circuit, an address and command decoder, a clock circuit, a power supply circuit, and an input / output circuit, as well as other circuits.

[0034] The bonding pad 420, the conductive structure 430, the terminal 440 and the circuit 445 of the semiconductor device can be formed by a semiconductor structure. The semiconductor structure can include a conductive layer, a conductive via, an insulating intermediate layer, etc. The terminal 440 can be coupled to the circuit 445 by, for example, a metal layer and / or a conductive via. The conductive structure 430 can be placed on one or more insulating intermediate layers. As previously described, the conductive structure 430 can be further coupled to the bonding pad 420. The conductive structure 430 extends from the terminal 440 to the bonding pad 420, so that the bonding pad 420 and the circuit terminal 440 can be coupled together. Therefore, the circuit 445 coupled to the terminal 440 can be accessed from the outside through the bonding pad 420. The bonding pad 420 can be exposed through the opening 425 in the passivation layer 435. In some embodiments of the present disclosure, the passivation layer 435 can be a polyimide material.

[0035] In some embodiments of the present disclosure, the conductive structure 430 may be coupled to a terminal 440 of a semiconductor device (e.g., a die pad of the semiconductor device) to provide a bonding pad 420 for coupling to the terminal 440 at a different location. For example, the terminal 440 may represent a die pad that is typically located in a peripheral circuit region along a central region of the semiconductor device, and the conductive structure 430 may couple the die pad in the central region to a bonding pad 420 located along an edge of the semiconductor device. The bonding pad 420 along the edge may be more conveniently located and provide coupling to the circuit 445 of the semiconductor device, that is, through the conductive structure 430 and the terminal 440.

[0036] Figure 5 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 5 The semiconductor device may include a semiconductor device of a multi-die device (e.g., Figure 2 In some embodiments of the present disclosure, Figure 5 Each of the semiconductor devices may include Figure 1 The semiconductor device 110 may be a memory device.

[0037] The semiconductor devices 510(1)-510(10) are coupled together by conductive structures 520(1)-520(20), which may be included in a redistribution layer (RDL). Figure 5 5. The conductive structure may couple the die pad 515 (e.g., terminal) of the semiconductor device 510 to the bonding pad 525 of the corresponding semiconductor device. The bonding pad 525 of each semiconductor device in the semiconductor device 510 may be coupled together by a corresponding conductor BW(1)-BW(9). In some embodiments of the present disclosure, the conductor BW may be a bonding wire.

[0038] Circuit 540 may be coupled to semiconductor device 510. For example, circuit 540 is coupled to semiconductor device 510(1) via conductive signal line 545 and conductor BW(0), and further coupled to semiconductor device 510(1) via bonding pad 525(1) and conductive structure 520(1), which is coupled to die pad 515 of semiconductor device 510(1). In some embodiments of the present disclosure, circuit 540 may be a register clock driver (RCD) attached to a substrate including conductive signal line 545, and conductor BW(0) may be a bonding wire. For example, in some embodiments of the present disclosure, circuit 540 and conductive signal line 545 may represent circuit 235 and conductive signal line included in substrate 230, and semiconductor device 510(1) may represent Figure 2The semiconductor device 220 in the stack 215 is shown.

[0039] In some embodiments of the present disclosure, two bonding pads 525 and two conductive structures 520 may be coupled to one die pad 515 of a semiconductor device. For example, the die pad 515(1) of the semiconductor device 510(1) is coupled to bonding pads 525(1) and 525(2) through conductive structures 520(1) and 520(2), respectively. Similarly, the die pad 515(2) of the semiconductor device 510(2) is coupled to bonding pads 525(3) and 525(4) through conductive structures 520(3) and 520(4), respectively; the die pad 515(3) of the semiconductor device 510(3) is coupled to bonding pads 525(5) and 525(6), respectively, through conductive structures 520(5) and 520(6), respectively; and so on.

[0040] In some embodiments of the present disclosure, the two conductive structures 520 coupled to the die pad 515 of the semiconductor device 510 may represent a "U"-shaped RDL structure. The U-shaped RDL structure may include two branch portions. Each of the branch portions has a first end coupled to a first end of another branch portion, and each of the branch portions has a second end opposite to the first end. The second end of each branch portion may be coupled to a corresponding bonding pad. The first ends of the branch portions coupled together may represent a closed end of the RDL structure, and the second ends of the two branch portions opposite to the first ends may represent an open end of the RDL structure. For example, referring to Figure 5 , conductive structures 520(1) and 520(2) represent branch portions of the die pad 515 of the semiconductor device 510(1) that are coupled together closest to the RDL structure. The second ends of the branch portions are closest to the bonding pads 525(1) and 525(2). The die pad of the semiconductor device can be coupled to any portion of the RDL structure. In some embodiments of the present disclosure, the die pad of the semiconductor device can be coupled to a closed end of the RDL structure.

[0041] The semiconductor devices 510 may be coupled together in a daisy-chain manner through the RDL structure (e.g., the conductive structure 520), the bonding pads 525, and the conductors BW. For example, the semiconductor devices 510(1)-510(3) may be coupled together in a daisy-chain manner starting from the bonding pad 525(1), as follows: the bonding pad 525(1) is coupled to the die pad 515(1) of the semiconductor device 510(1) through the conductive structure 520(1); the die pad 515(1) is coupled to the bonding pad 525(2) through the conductive structure 520(2); the bonding pad 525(2) is coupled to the bonding pad 525(3) through the conductor BW(1). ); bonding pad 525(3) is coupled to die pad 515(2) of semiconductor device 510(2) via conductive structure 520(3); die pad 515(2) is coupled to bonding pad 525(4) via conductive structure 520(4); bonding pad 525(4) is coupled to bonding pad 525(5) via conductor BW(2); bonding pad 525(5) is coupled to die pad 515(3) of semiconductor device 510(3) via conductive structure 520(5). Similarly, semiconductor devices 510(4)-510(10) are also coupled to each other in a daisy-chain manner and to semiconductor devices 510(1)-510(3).

[0042] Compared to the parallel coupling of semiconductor device 510, daisy-chain coupling can present a lower load to the circuit (e.g., circuit 540 (e.g., RCD)) coupled to semiconductor device 510. For example, with parallel coupling of stacked devices, the load presented to the circuit can include the load of all devices in the stack. In contrast, with daisy-chain (e.g., series) coupling of stacked devices, the load presented to the circuit is generated by the distributed load of the first circuit in the semiconductor die chain and then each subsequent circuit. This electrical distribution results in an effective reduction in the load observed at frequencies higher than the frequency of the parallel configuration. U-turn RDL can be used to implement a true daisy chain. Without using U-turn RDL, there may be long electrical stubs (from bonding pads to die pads) that cause reflections and reduce signal integrity. However, by using U-turn RDL, the "branches" of the RDL no longer form stubs, but rather a series path without parallel segments. Such an arrangement may be beneficial to signal integrity. Therefore, it may be advantageous to have a daisy-chain coupling, such as the daisy-chain coupling provided by one or more embodiments of the present disclosure.

[0043] Figure 5, a semiconductor device 510 having one die pad 515 (e.g., terminal) is shown. However, the semiconductor device 510 may have additional die pads. The additional die pads may also be coupled to the bonding pads, for example, in a daisy-chain manner through a conductive structure, and coupled to the bonding pads through a conductor. In some embodiments of the present disclosure, some of the die pads of each semiconductor device are not coupled to other semiconductor devices in a daisy-chain manner, while other die pads of the semiconductor devices are coupled in a daisy-chain manner. For example, some of the die pads of each semiconductor device may be coupled in parallel to the corresponding die pads of another semiconductor device in the semiconductor device, and some of the die pads of each semiconductor device may be coupled in the form of a daisy chain (e.g., coupled in series) to the corresponding die pads of another semiconductor device in the semiconductor device. In some embodiments of the present disclosure, the data terminals and / or command and address terminals of the semiconductor devices may be coupled in a daisy-chain manner.

[0044] Figure 6 1 is a diagram showing an RDL structure for coupling a terminal of a semiconductor device to a bonding pad according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the RDL structure may include the RDL structure previously described with reference to FIG. Figure 1-5 In any semiconductor device described in the foregoing description, the RDL structure may be included in Figure 3 The semiconductor device 310 is configured to couple the bonding pad 354 to a terminal included in the peripheral circuit region.

[0045] The bonding pads 610(1)-610(6) are coupled to at least one of the die pads 620(1)-620(3) through the RDL structures 630(1)-630(3). For example, at least two bonding pads 610 are coupled to at least one die pad 620 through corresponding RDL structures 630. Figure 6 In the example of the present disclosure, the bonding pads 610(1) and 610(2) are coupled to the die pad 620(1) through the RDL structure 630(1); the bonding pads 610(3) and 610(4) are coupled to the die pad 620(2) through the RDL structure 630(2); and the bonding pads 610(5) and 610(6) are coupled to the die pad 620(3) through the RDL structure 630(3). In some embodiments of the present disclosure, the RDL structure 630 may have a "U" shape that couples two bonding pads 610 to one die pad 620.

[0046] The RDL structure 630(1) may include a first portion 632(1) extending from a bonding pad 610(1) (e.g., a first bonding pad) to a die pad 620(1), and may further include a second portion 634(1) extending from a bonding pad 610(2) (e.g., a second bonding pad) to the die pad 620(1). The portion 632(1) may include a conductive structure, and the portion 634(1) may include a conductive structure. In some embodiments of the present disclosure, each of the conductive structures may be included in the RDL. The first portion 632(1) and the second portion 634(1) are coupled to the die pad 620(1). In some embodiments of the present disclosure, the first portion 632(1) and the second portion 634(1) may be coupled to the die pad 620(1) via a third portion coupled to the first portion 632(1) and the second portion 634(1). For example, in Figure 6 , the third portion 636(1) is coupled to the first portion 632(1) and the second portion 634(1), and is coupled to the die pad 620(1). The third portion 636(3) may be included in the RDL structure 630(1). In some embodiments of the present disclosure, the first portion 632(1) and the second portion 634(1) are coupled to the die pad 620 without the third portion. For example, the first portion and the second portion may be shaped to provide coupling between the first bonding pad and the second bonding pad to the same die pad 620 without the third portion.

[0047] The RDL structures 630(2) and 630(3) may include respective first and second portions as previously described for the RDL structure 630(1), the first and second portions being coupled to respective die pads 620(2) and 620(3). Likewise, in some embodiments of the present disclosure, the RDL structures 630(2) and 630(3) may include respective third portions as previously described for the RDL structure 630(1).

[0048] The RDL structure 630 may be formed of a conductive material of one or more conductive layers. For example, in some embodiments of the present disclosure, the first portion and the second portion of the RDL structure 630 may be formed of the same conductive layer. The third portion may be formed of the same conductive layer. In some embodiments of the present disclosure, one or more portions of the portions of the RDL layer may be formed of a conductive layer different from other portions. The portion itself may be formed of one or more conductive layers. The conductive structure may be formed of a conductive layer located below the bonding pad 610 and above the die pad 620.

[0049] The RDL structure 630 has been provided by way of example, and embodiments of the present disclosure are not limited to Figure 6 specific instance of .

[0050] Figure 7 is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device may be included in a multi-die device (e.g., Figure 2 In a multi-die device 200).

[0051] The bonding pads 731-736 may be included in a pad forming region of a corresponding semiconductor device 710(1)-710(4). The bonding pad pair may be coupled to a corresponding die pad of the semiconductor device. For example, referring to the bonding pads 731(1)-736(1) of the semiconductor device 710(1), the bonding pads 731(1) and 732(1) of the bonding pad pair 721(1) may be coupled to the same die pad of the semiconductor device 710(1). Similarly, the bonding pads 733(1) and 734(1) of the bonding pad pair 722(1) may each be coupled to another die pad of the semiconductor device 710(1), and the bonding pads 735(1) and 736(1) of the bonding pad pair 723(1) may each be coupled to yet another die pad of the semiconductor device 710(1). Bond pad pairs of other semiconductor devices 710 ( 2 )- 710 ( 4 ) may also be coupled to corresponding common die pads.

[0052] The pair of bonding pads may be coupled via a conductive structure extending from respective bonding pads to the same die pad. For example, bonding pads 731(1) and 732(1) may be coupled via a conductive structure extending from respective bonding pads 731(1) and 732(1) to the same die pad. Similarly, bonding pads 733(1) and 734(1) may be coupled via a conductive structure extending from respective bonding pads 733(1) and 734(1) to the same die pad. The conductive structure may be included in the RDL structure. In some embodiments of the present disclosure, a U-shaped RDL structure may be used to couple bonding pads to the same die pad. For example, in some embodiments of the present disclosure, a U-shaped RDL structure may be used to couple bonding pads to the same die pad. Figure 5 In some embodiments of the present disclosure, the conductive structure and RDL structure may be used. Figure 6 Conductive structure and RDL structure.

[0053] The die pads of semiconductor devices 710(1)-710(4) can be coupled together in a daisy-chain manner by coupling the bonding pad pairs to the corresponding die pads. For example, assume that die pad "A" is the die pad of semiconductor device 710(1) coupled to the bonding pad pair 721(1); die pad "B" is the die pad of semiconductor device 710(2) coupled to the bonding pad pair 721(2); die pad "C" is the die pad of semiconductor device 710(3) coupled to the bonding pad pair 721(3); and die pad "D" is the die pad of semiconductor device 710(4) coupled to the bonding pad pair 721(4). Die pad A may be coupled to die pad B by coupling bond pad 732(1) to bond pad 731(2) via conductor BW1(1); die pad B may be coupled to die pad C by coupling bond pad 732(2) to bond pad 731(3) via conductor BW1(2); and die pad C may be coupled to die pad D by coupling bond pad 732(3) to bond pad 731(4) via conductor BW1(3). Thus, die pads A, B, C, and D may be coupled in a daisy-chain manner.

[0054] The daisy chain of die pads A, B, C, and D may be further coupled to a circuit (e.g., an RCD attached to a substrate) via conductor BW1(0). For example, pad 731(1) may be coupled to a conductive signal line via BW1(0), and the conductive signal line may in turn be coupled to a circuit.

[0055] The daisy chain of die pads A, B, C, and D may be further coupled to die pads of other semiconductor devices (e.g., additional semiconductor devices in a multi-die stack) via conductor BW1(4). For example, bonding pad 732(4) may be coupled to a bonding pad of another semiconductor device via BW1(4), and the bonding pad may in turn be coupled to die pads of other semiconductor devices.

[0056] Other die pads of semiconductor devices 710(1)-710(4) may be coupled together in a similar daisy-chain manner. For example, the die pads coupled to the bonding pad pairs 722(1), 722(2), 722(3), and 722(4) may be coupled in a daisy-chain manner as follows: bonding pad 734(1) is coupled to bonding pad 733(2) via conductor BW2(1); bonding pad 734(2) is coupled to bonding pad 733(3) via conductor BW2(2); bonding pad 734(3) is coupled to bonding pad 733(4) via conductor BW2(3). Similarly, the die pads coupled to the bonding pad pairs 723(1), 723(2), 723(3), and 723(4) can be coupled in a daisy-chain manner as follows: bonding pad 736(1) is coupled to bonding pad 735(2) via conductor BW3(1); bonding pad 736(2) is coupled to bonding pad 735(3) via conductor BW3(2); bonding pad 736(3) is coupled to bonding pad 735(4) via conductor BW3(3). Conductors BW2(0) and BW2(4) coupled to bonding pads 733(1) and 734(4), respectively, can be used to couple the daisy-chained die pads to circuits (e.g., RCDs) and other semiconductor devices (e.g., in a multi-die stack). Likewise, conductors BW3(0) and BW3(4), coupled to bond pads 735(1) and 736(4), respectively, may be used to couple daisy-chain die pads to circuits (eg, RCDs) and other semiconductor devices (eg, in a multi-die stack).

[0057] exist Figure 7 In the example of FIG. 7 , six bonding pads 731 - 736 from each of the semiconductor devices 710 ( 1 ) - 710 ( 4 ) are shown. The six bonding pads 731 - 736 are provided by way of example, and each of the semiconductor devices 710 ( 1 ) - 710 ( 4 ) may include a greater or lesser number of bonding pads without departing from the scope of the present disclosure. Additionally, Figure 7 Four semiconductor devices 710(1)-710(4) are shown in FIG. However, a greater or lesser number of semiconductor devices may be coupled together without departing from the scope of the present disclosure.

[0058] Some details have been described to provide a full understanding of the examples of the present disclosure. However, it will be clear to those skilled in the art that the examples of the present disclosure can be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be interpreted as limiting the scope of the present disclosure to these specific examples. In other cases, well-known circuits, control signals, timing protocols and software operations are not shown in detail to avoid unnecessarily obscuring the present disclosure. In addition, terms such as "coupling" and "coupled" mean that two components can be electrically coupled directly or indirectly. Indirect coupling can imply that two components are coupled through one or more intermediate components.

[0059] From the above, it should be understood that although specific embodiments of the present disclosure have been described herein for illustrative purposes, various modifications can be made without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited by any specific embodiments described herein.

Claims

1. A semiconductor device comprising: A plurality of semiconductor devices, the plurality of semiconductor devices comprising a first semiconductor device, a second semiconductor device and a third semiconductor device, each of the plurality of semiconductor devices comprising a die pad coupled to at least one circuit of the corresponding semiconductor device, and further comprising a redistribution layer structure coupled to the die pad and further coupled to a first bonding pad and a second bonding pad, wherein the second bonding pad of the first semiconductor device is coupled to the first bonding pad of the second semiconductor device, and the second bonding pad of the second semiconductor device is coupled to the first bonding pad of the third semiconductor device. 2 . The semiconductor apparatus according to claim 1 , wherein the plurality of semiconductor devices are included in a stack of semiconductor devices.

3. The semiconductor device according to claim 2, wherein the plurality of semiconductor devices are stacked in a staggered manner and an edge region of each of the plurality of semiconductor devices is exposed, wherein corresponding first bonding pads and second bonding pads are positioned at the edge regions of the plurality of semiconductor devices.

4. The semiconductor device according to claim 1, wherein the second bonding pad of the first semiconductor device is coupled to the first bonding pad of the second semiconductor device through a bonding wire, and the second bonding pad of the second semiconductor device is coupled to the first bonding pad of the third semiconductor device through another bonding wire. 5 . The semiconductor apparatus according to claim 1 , wherein the redistribution layer structure of each of the plurality of semiconductor devices has a U-shape.

6. The semiconductor apparatus of claim 1, wherein the redistribution layer structure of each of the plurality of semiconductor devices includes a first portion extending between the die pad and the first bonding pad and further includes a second portion extending between the die pad and the second bonding pad. 7 . The semiconductor apparatus of claim 6 , wherein the redistribution layer structure of each of the plurality of semiconductor devices further comprises a third portion coupled to the first portion and the second portion and further coupled to the die pad.

8. The semiconductor device according to claim 1, further comprising: an external circuit coupled to the first bonding pad of the first semiconductor device; as well as A substrate comprising a conductive signal line, wherein the plurality of semiconductor devices and the external circuit are attached to the substrate, and the external circuit is coupled to the first bonding pad of the first semiconductor device through the conductive signal line. 9 . The semiconductor apparatus according to claim 1 , wherein a corresponding die pad of each of the plurality of semiconductor devices is included in a peripheral circuit region located along a central region of the corresponding semiconductor device. 10 . The semiconductor apparatus of claim 1 , wherein a corresponding die pad of each of the plurality of semiconductor devices is coupled together in a daisy-chain form through the bonding pad and the redistribution layer structure.

11. A multi-die device comprising: a substrate comprising conductive signal lines; a stack of semiconductor devices, the stack attached to the substrate, each of the semiconductor devices in the stack comprising a terminal and a redistribution layer structure coupled to the terminal, wherein the terminals of the semiconductor devices in the stack are coupled together in a daisy-chain manner through the redistribution layer structure, wherein each of the semiconductor devices further comprises a first bonding pad and a second bonding pad, and wherein the first bonding pad is coupled to a first portion of the redistribution layer structure and the second bonding pad is coupled to a second portion of the redistribution layer structure; as well as A circuit is attached to the substrate and coupled to a first semiconductor device in the stack of semiconductor devices through the conductive signal line. 12 . The multi-die device of claim 11 , wherein the first bonding pad and the second bonding pad of each semiconductor device are positioned at an edge region, and the terminals are included in a peripheral circuit region positioned along a central region of the corresponding semiconductor device. 13 . The multi-die device of claim 11 , wherein one of the first bonding pad and the second bonding pad of a semiconductor device in the stack is coupled to one of the first bonding pad and the second bonding pad of another semiconductor device in the stack through a bonding wire.

14. The multi-die device of claim 11, wherein the first portion comprises a first conductive structure formed from a different conductive layer than the first bond pad and the terminal, and wherein the second portion comprises a second conductive structure formed from the same conductive layer.

15. The multi-die device of claim 11, wherein the circuit attached to the substrate comprises a register clock driver (RCD) circuit.

16. The multi-die device of claim 11, wherein the terminals include data terminals or command address terminals.

17. The multi-die arrangement of claim 11, wherein the redistribution layer structure comprises a U-shaped redistribution layer structure.

18. A method for manufacturing a semiconductor, comprising: coupling a bonding pad of the first semiconductor device to the first U-shaped conductive structure; coupling a bonding pad of a second semiconductor device to a second U-shaped conductive structure; coupling a bonding pad of a third semiconductor device to a third U-shaped conductive structure; coupling the second portion of the first U-shaped conductive structure to the first portion of the second U-shaped conductive structure; as well as A second portion of the second U-shaped conductive structure is coupled to a first portion of the third U-shaped conductive structure, wherein the first portion of the first U-shaped conductive structure is coupled to a circuit, and wherein a second portion of the third U-shaped conductive structure is coupled to a fourth semiconductor device.

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