Semiconductor devices, integrated circuits, and systems forming layouts thereof

Abstract

A semiconductor device includes: a plurality of first cell rows extending in a first direction, each first cell row having a first row height; a plurality of second cell rows extending in the first direction, each second cell row having a second row height less than the first row height, wherein the first cell rows and second cell rows are staggered; a first cell disposed in a first row of the first cell rows; and at least one second cell disposed in at least one row of the second cell rows, wherein the at least one second cell is adjacent to the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operating configuration. Embodiments of the invention also relate to integrated circuits and systems for forming their layout.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, integrated circuits, and systems for forming the layout thereof. Background Technology

[0002] Integrated circuits are widely used in various applications, and the demand for faster processing speeds and lower power consumption is increasing. However, gate oxide breakdown has a significant impact on the performance and reliability of integrated circuits. Summary of the Invention

[0003] According to one aspect of the present invention, a semiconductor device is provided, comprising: a plurality of first cell rows extending in a first direction, each of the first cell rows having a first row height; a plurality of second cell rows extending in the first direction, each of the second cell rows having a second row height less than the first row height, wherein the plurality of first cell rows and the plurality of second cell rows are staggered; a first cell disposed in a first row of the plurality of first cell rows; and at least one second cell disposed in at least one row of the plurality of second cell rows, wherein the at least one second cell is adjacent to the first cell in a second direction different from the first direction. The at least one second cell and at least one circuit component included in the first cell have the same operational configuration.

[0004] According to another aspect of the present invention, an integrated circuit is provided, comprising: a first circuit including a plurality of first transistors, each first transistor having a dual-fin active region structure; and a second circuit including at least one second transistor having a single-fin active region structure. The at least one second transistor and at least one of the plurality of first transistors are coupled in parallel to each other and configured to cooperate in response to a first signal at the gate of the at least one second transistor and at least one of the plurality of first transistors.

[0005] According to another aspect of the present invention, a system for forming an integrated circuit layout is provided, comprising: a non-transitory storage medium encoded with an instruction set; and a hardware processor communicatively coupled to the non-transitory storage medium and configured to execute the instruction set, the instruction set being configured to cause the processor to: acquire a plurality of values ​​based on a circuit netlist, each value corresponding to one of a plurality of transistors included in the circuit; compare the plurality of values ​​with a threshold; generate an adjusted netlist of the circuit by adding a plurality of redundant transistors in response to the comparison; and determine one of a plurality of layout configurations of the circuit based on the adjusted netlist, wherein the plurality of layout configurations include a plurality of first cell rows each having a first cell height and a plurality of second cell rows each having a second cell height different from the first cell height. Attached Figure Description

[0006] A better understanding of the various aspects of the invention can be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In practice, the dimensions of the components may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A This is a top view of a portion of a semiconductor device according to some embodiments.

[0008] Figure 1B According to various embodiments Figure 1A A top view of the semiconductor device portion.

[0009] Figure 2 The illustration is based on some embodiments and shows the path along Figure 1A A cross-sectional view of a structure consisting of several unit rows of cross-section lines.

[0010] Figure 3A According to some embodiments, including and Figure 1A The equivalent circuit of the integrated circuit part of the structure corresponding to the semiconductor device in the diagram.

[0011] Figure 3B It is based on some embodiments corresponding to Figure 3A The directed acyclic graph of the equivalent circuit of the integrated circuit portion in the figure.

[0012] Figure 3C Based on some embodiments and Figure 3A The layout diagram of the corresponding integrated circuit part in plan view.

[0013] Figure 3D Based on some embodiments and Figure 3A Another layout diagram of the corresponding integrated circuit part in plan view.

[0014] Figure 4A According to some embodiments, including and Figure 1A The equivalent circuit of the integrated circuit part of the structure corresponding to the semiconductor device in the diagram.

[0015] Figure 4B It is based on some embodiments corresponding to Figure 4A The directed acyclic graph of the equivalent circuit of the integrated circuit portion in the figure.

[0016] Figure 4C Based on some embodiments and Figure 4A The layout diagram of the corresponding integrated circuit part in plan view.

[0017] Figure 5A According to some embodiments, including and Figure 1AThe equivalent circuit of the integrated circuit part of the structure corresponding to the semiconductor device in the diagram.

[0018] Figure 5B It is based on some embodiments corresponding to Figure 5A The directed acyclic graph of the equivalent circuit of the integrated circuit portion in the figure.

[0019] Figure 5C Based on some embodiments and Figure 5A The layout diagram of the corresponding integrated circuit part in plan view.

[0020] Figure 6A According to some embodiments, including and Figure 1A The equivalent circuit of the integrated circuit part of the structure corresponding to the semiconductor device in the diagram.

[0021] Figure 6B It is based on some embodiments corresponding to Figure 6A The directed acyclic graph of the equivalent circuit of the integrated circuit portion in the figure.

[0022] Figure 6C Based on some embodiments and Figure 6A The layout diagram of the corresponding integrated circuit part in plan view.

[0023] Figure 7A According to some embodiments, including and Figure 1A The equivalent circuit of the integrated circuit part of the structure corresponding to the semiconductor device in the diagram.

[0024] Figure 7B It is based on some embodiments corresponding to Figure 7A The directed acyclic graph of the equivalent circuit of the integrated circuit portion in the figure.

[0025] Figure 7C Based on some embodiments and Figure 7A The layout diagram of the corresponding integrated circuit part in plan view.

[0026] Figure 8A According to some embodiments, including and Figure 1A The equivalent circuit of the integrated circuit part of the structure corresponding to the semiconductor device in the diagram.

[0027] Figure 8B It is based on some embodiments corresponding to Figure 8A The directed acyclic graph of the equivalent circuit of the integrated circuit portion in the figure.

[0028] Figure 8C Based on some embodiments and Figure 8A The layout diagram of the corresponding integrated circuit part in plan view.

[0029] Figure 9 This is a flowchart of a method for generating layout design and manufacturing integrated circuits for designing integrated circuit layouts, according to some embodiments of the present invention.

[0030] Figure 10 This is a block diagram of a system for designing integrated circuit layout according to some embodiments of the present invention.

[0031] Figure 11 This is a block diagram of an integrated circuit manufacturing system and an associated integrated circuit manufacturing process according to some embodiments. Detailed Implementation

[0032] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0033] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. Examples used in this specification, including instances of any term discussed herein, are merely illustrative and are in no way intended to limit the scope and meaning of the invention or any exemplary terminology. Similarly, the invention is not limited to the various embodiments given in this specification.

[0034] As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” etc., are understood to be open-ended, meaning including but not limited to.

[0035] Throughout this specification, references to "one embodiment," "embodiment," or "some embodiments" refer to specific features, structures, implementations, or characteristics described in connection with an embodiment that are included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "in an embodiment," or "in some embodiments" used in different places throughout the specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific features, structures, implementations, or characteristics can be combined in any suitable manner.

[0036] Additionally, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship of one element or component to another (or other) element or component as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. The term “and / or” as used herein includes any and all combinations of one or more of the listed related items.

[0037] As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally refer to any approximation of a given value or range, wherein the approximation varies depending on the various fields to which it pertains, and its range is subject to the broadest interpretation understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, the approximation should generally be within 20%, preferably within 10%, and more preferably within 5% of the given value or range. The numerical values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred or imply other approximations.

[0038] Now for reference Figure 1A . Figure 1A This is a top view of a portion of a semiconductor device according to some embodiments. For example... Figure 1A As illustrated illustratively, the semiconductor device 10 includes a plurality of cell rows ROW1-ROW4 and cells CELL1-CELL4. In some embodiments, cells CELL1-CELL4 are implemented by integrated circuits arranged in these cell rows ROW1-ROW4. In some embodiments, each of cells CELL1-CELL4 is implemented as a logic gate circuit, including AND, OR, NAND, multiplexer (MUX), flip-flop, latch, buffer, inverter, combination thereof, or any other type of logic circuit. Figure 1A The number of cell rows ROW1-ROW4 in the semiconductor device 10 is for illustrative purposes. Various numbers of cell rows ROW1-ROW4 are within the scope of the present invention. For example, in some embodiments, the number of cell rows in the semiconductor device 10 is greater than 4.

[0039] For illustration, the cell rows ROW1-ROW4 extend along the x-direction and are parallel to each other. In some embodiments, cell rows ROW1 to ROW4 are arranged along the y-direction, which is generally perpendicular to the x-direction.

[0040] In some embodiments, rows ROW1-ROW4 contain two sets of cell rows based on their row height. For example... Figure 1A As illustrated, each of cell rows ROW1 and ROW3 is configured to have a row height H1, and each of cell rows ROW2 and ROW4 is configured to have a row height H2, where H2 is shorter than H1. Cell rows ROW1 and ROW3 with row height H1 are considered the first group "A" of cell rows ROW1-ROW4, and cell rows ROW2 and ROW4 are considered the second group "B" of cell rows ROW1-ROW4. In some embodiments, as... Figure 1A As shown, the first group A and the second group B of the cell row are interleaved.

[0041] For illustration, in the first group "A", cell row ROW1 with row height H1 includes two active regions 210-220, and in the second group "B", cell row ROW2 with row height H2 includes two active regions 230-240. Similarly, cell row ROW3 includes two active regions 250-260, and cell row ROW4 includes two active regions 270-280. For illustration, active regions 210-280 extend along the x-direction and are separated from each other in the y-direction. The configuration of active regions 210-280 will be combined in the following paragraphs. Figure 2 To elaborate.

[0042] In some embodiments, active regions 210 and 240 have P-type conductivity, while active regions 220 and 230 have N-type conductivity. Active regions 250 and 280 are configured similarly to active regions 210 and 240, and active regions 260 and 270 are configured similarly to active regions 220 and 230. In other words, cell rows ROW1-ROW4 are staggered in a periodic sequence along the y-direction. The configuration of active regions 210-280 is for illustrative purposes. Various embodiments of active regions 210-280 are included within the scope of the invention. For example, in some embodiments, active regions 210, 240, 250, and 280 are N-type, and active regions 220, 230, 260, and 270 are P-type.

[0043] like Figure 1A As illustrated, cell CELL1 includes subcells 110 and 120. Subcells 110 and 120 are adjacent to each other along the y-direction. Subcells 110 and 120 are arranged in cell rows ROW1 and ROW2, respectively. Subcell 110 includes active regions 210-220, and subcell 120 includes active regions 230-240.

[0044] In some embodiments, sub-unit 110 includes logic gates, including AND, OR, NAND, MUX, flip-flops, latches, BUFFs, inverters, or any other type of logic circuitry, and sub-unit 120 includes shaded logic gates. In such embodiments, the shaded logic gates and at least one circuit component included in sub-unit 110 have the same operating configuration. For example, in some embodiments, sub-unit 110 includes a plurality of N-type and P-type transistors. Sub-unit 120 includes a P-type transistor coupled in parallel to a corresponding one of the P-type transistors in sub-unit 110 and an N-type transistor coupled in parallel to a corresponding one of the N-type transistors in sub-unit 110. The P-type transistor in sub-unit 120 and the corresponding one of the P-type transistors in sub-unit 110 are configured to cooperate in response to a first signal at their gates, and the N-type transistor in sub-unit 120 and the corresponding one of the N-type transistors in sub-unit 110 are configured to cooperate in response to a second signal at their gates. In other words, the circuit components in subunit 120 are configured as copies of the corresponding components in subunit 110, thus operating with the same configuration. Details of subunits 110-120 will be provided later. Figures 3A-3D and Figures 7A-7C The discussion will be illustrated with examples.

[0045] As described above, when cell CELL1 is running, subcell 110 is configured as the main logic circuit, and subcell 120 is configured as the shadow logic circuit. In some methods, the semiconductor device includes a shadow logic circuit corresponding to subcell 120, which has transistors and is coupled to the main logic circuit corresponding to subcell 110 to extend cell lifetime. However, due to the rectangular shape of the cell substrate design, in some methods the shadow logic circuit and the main logic circuit are arranged in the same cell row under a single cell row height architecture (SCRHA) and are adjacent to each other in the direction of cell row extension. In this arrangement, the large pin caps result in not only a large area overhead but also poor cell performance.

[0046] Utilizing the hybrid cell row height configuration of this invention, the shadowed logic circuitry in sub-cell 120 is arranged in a lower-height cell row, while the main logic circuitry in sub-cell 110 is arranged in a normal-height cell row. In this embodiment, if a transistor in sub-cell 110 experiences an oxidation failure, for example at the transistor's gate, the corresponding redundant transistor in sub-cell 120 coupled to that transistor in sub-cell 110 can still operate to maintain circuit operation. Therefore, not only is the shadowed logic circuitry in sub-cell 120 improved in reliability, but the hybrid cell row height architecture (MCRHA) configuration described above also has lower area and pin cap overhead compared to some other methods. In other words, the hybrid cell row architecture of this invention offers advantages in terms of smaller core area while largely maintaining the same performance as a single-cell row height architecture.

[0047] Figure 1A The configuration of cell CELL1 is for illustrative purposes. Various embodiments of cell CELL1 are included within the scope of the present invention. For example, in some embodiments discussed in the following paragraphs, the cell corresponding to subcell 120 includes only P-type transistors or N-type transistors.

[0048] Continue to refer to Figure 1A For illustration, the semiconductor device 10 includes a cell CELL2. Instead of including an N-type active region 230 and a P-type active region 240 in the same cell row ROW2, cell CELL2 includes an active region 240 in a portion of cell ROW2 with a height H3, and an active region 270 in a portion of cell ROW4 with a height H3. Cell CELL2 also includes active regions 250-260 in cell row ROW3, ​​which is inserted between cell rows ROW2 and ROW4.

[0049] like Figure 1A As illustrated, cell 2 includes subcell 110 and subcells 130-140. Subcell 110 is inserted between and adjacent to subcells 130 and 140. Subcell 110 is arranged in cell row ROW3. Subcells 130 and 140 are arranged in cell rows ROW2 and ROW4, respectively. In other words, subcells 130-140 are arranged on opposite sides of subcell 110.

[0050] Subunit 110 includes active regions 250-260. Subunit 130 includes active region 240, and subunit 140 includes active region 270. As described above, in some embodiments, active regions 240-250 are P-type, and active regions 260-270 are N-type.

[0051] In some embodiments, sub-unit 130 includes a shadowed logic P-type device, which includes one or more transistors, for example, corresponding to the P-type transistors in sub-unit 110. Sub-unit 140 includes a shadowed logic N-type device, which includes one or more transistors, for example, corresponding to the N-type transistors in sub-unit 110. In other words, compared to unit CELL1, sub-unit 120 is implemented by two sub-units 130-140 arranged on opposite sides of sub-unit 110, with sub-unit 130 including the P-type transistors of sub-unit 120 and sub-unit 140 including the N-type transistors of sub-unit 120. In such embodiments, when unit CELL2 is running, sub-unit 110 is configured as the main logic circuit, and sub-units 130-140 are configured as different shadowed logic circuits.

[0052] Continue to refer to Figure 1A For illustration, semiconductor device 10 includes cell CELL3. Instead of having two sub-cells 130-140, cell CELL3 includes only sub-cell 140, as opposed to cell CELL2. In some embodiments, when cell CELL3 is in operation, sub-cell 110 is configured as a main logic circuit, and sub-cell 140 is configured as a shadow logic circuit with N-type transistors.

[0053] Furthermore, the semiconductor device 10 includes a cell CELL4. Instead of having two sub-cells 130-140, cell CELL4 includes only sub-cell 130, as opposed to cell CELL2. In some embodiments, when cell CELL4 is in operation, sub-cell 110 is configured as a main logic circuit, and sub-cell 130 is configured as a shadow logic circuit with P-type transistors.

[0054] In some embodiments, simulations are performed to identify the most vulnerable transistors, thereby inserting redundant transistors into the shadow logic circuit (i.e., Figure 1A In subcells 120-140, they are coupled to vulnerable transistors. Based on the number of redundant transistors, one of the layout configurations (i.e., cells CELL1-CELL4 or any other suitable layout structure) is determined for the integrated circuit formed on the semiconductor device. The method 900 for identifying transistors and determining the layout configuration will be incorporated in a later paragraph. Figure 9 Detailed discussion.

[0055] Now for reference Figure 1B . Figure 1B According to various embodiments Figure 1A A top view of a portion of the semiconductor device 10. For the embodiment of 1A, for ease of understanding, Figure 1B The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 1BThe cooperative relationship of the components shown.

[0056] For illustration, the semiconductor device 10 also includes cells CELL5-CELL8. In some embodiments, each of cells CELL5-CELL8 is implemented as a logic gate circuit, including AND, OR, NAND, MUX, flip-flops, latches, BUFFs, inverters, combinations thereof, or any other type of logic circuit. In some embodiments, cells CELL5-CELL8 are implemented by assembling some of sub-cells 110-140 and sub-cell 150 along the y-direction. In some embodiments, sub-cells 110 and 150 have the same configuration. In some alternative embodiments, sub-cells 110 and 150 have different configurations.

[0057] Specifically, with Figure 1A Compared to cell CELL2, which has subcell 140, cell CELL5 includes subcell 120 arranged in cell row ROW4. For illustration, subcell 110 is inserted between subcells 120-130. Therefore, in cell CELL5, there are more P-type active regions than N-type active regions to form P-type transistors in the shaded logic circuit.

[0058] Compared to cell CELL5, cell CELL6 includes sub-cells 120 arranged in cell row ROW2 and sub-cells 140 arranged in cell row ROW4, replacing the P-type active regions with more N-type active regions. Therefore, in cell CELL6, there are more N-type active regions than P-type active regions to form N-type transistors in the shadowed logic circuit.

[0059] For illustration, compared to cells CELL5 and CELL6, which have asymmetrical numbers of N-type and P-type active regions in the shadow logic circuit, cell CELL7 includes two sub-cells 120 arranged on opposite sides of sub-cell 110. In such embodiments, relative to Figure 1A Cells CELL1 and CELL7 have double-shaded logic circuitry. Therefore, the reliability of the circuit formed with the configuration of cell CELL7 is increased.

[0060] Figures 1A-1B The configuration shown is for illustrative purposes. Various embodiments are included within the scope of the invention. For example, the semiconductor device 10 also includes a cell having a sub-cell 110 arranged in cell row ROW3 and a sub-cell adjacent to the sub-cell 110 in the y-direction and extending in the x-direction, the width of which is greater than that of the sub-cell. Figure 1A The width of subcell 130 is wide. Therefore, more P-redundant transistors can be formed in the subcell for operation.

[0061] Now for reference Figure 2 . Figure 2 The illustration is based on some embodiments and shows the path along Figure 1A The cross-sectional view of the structure in element row ROW1-ROW2, with section line AA' in the diagram. (Refer to...) Figure 1A The embodiments are provided for ease of understanding. Figure 2 The same elements are indicated by the same reference numerals.

[0062] like Figure 2 As exemplarily shown, the cell row ROW1 with row height H1 in the first group "A" includes active regions 210-220 on the substrate Sub. Active region 210 of cell row ROW1 includes two fin structures 211 and 212, and active region 220 of cell row ROW1 includes two additional fin structures 221 and 222. In other words, each of the active regions 210-220 includes two fin structures, such as 211 and 212, or 221 and 222.

[0063] In some embodiments, fin structures 211 and 212 are n-type fin structures, and fin structures 221 and 222 are p-type fin structures. In some other embodiments, fin structures 211 and 212 are p-type fin structures, and fin structures 221 and 222 are n-type fin structures.

[0064] like Figure 2 As exemplarily shown, the cell row ROW2 with row height H2 in the second group "B" includes two active regions 230-240 on the substrate Sub. The active region 230 of the cell row ROW2 includes a first single-fin structure, and the active region 240 of the cell row ROW2 includes a second single-fin structure. In other words, each of the active regions 230-240 includes a fin structure.

[0065] The fins described above can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby enabling the resulting patterns to have smaller spacing, for example, than patterns obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0066] In some embodiments, such an active region may include one or more fin structures of one or more three-dimensional field-effect transistors (e.g., FinFETs, Gate All-Around (GAA) transistors), or a defined oxide (OD) region of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs). The active region can be used as a source or drain component of the corresponding transistor.

[0067] In some embodiments, the active region 210 of cell row ROW1 includes two fin structures 211 and 212, which together serve as an active region to form an integrated circuit component (e.g., a transistor), such that the equivalent width of the active region of the integrated circuit component disposed on the active region 210 is wider than the equivalent width of another integrated circuit component disposed on the active region 230 including the first single fin structure. In other words, in some embodiments, the performance of the integrated circuit component disposed on cell row ROW1 is better than that of the integrated circuit component disposed on cell row ROW2.

[0068] Now for reference Figures 3A-3B . Figure 3A According to some embodiments, including and Figure 1A The equivalent circuit of a portion of the integrated circuit 30 corresponding to the semiconductor device 10 in the circuit. Figure 3B It is based on some embodiments corresponding to Figure 3A The directed acyclic graph of the equivalent circuit of part of integrated circuit 30 in the figure.

[0069] like Figure 3A As illustrated illustratively, integrated circuit 30 includes a first circuit having transistors M1-M6 and a second circuit having transistors S1-S6. Integrated circuit 30 is coupled between a power supply voltage VDD and ground. In some embodiments, integrated circuit 30 is included in a cell, for example... Figure 1A The first circuit of cell CELL1 includes Figure 1A The second circuit is included in subunit 110 and runs as the main logic circuit. Figure 1A It operates as a shadow logic circuit in subunit 120.

[0070] In some embodiments, transistors M1-M2, M5, S1-S2, and S5 are N-type transistors. Transistors M3-M4, M6, S3-S4, and S6 are P-type transistors.

[0071] Specifically, transistors M1, M4, S1, and S2 include gates for receiving signal A. Transistors M2, M3, S2, and S3 include gates for receiving signal B. Transistors M1-M2, M5, S1-S2, and S5 include a first terminal grounded. Transistors M4, M6, S4, and S6 include a first terminal coupled to the power supply voltage VDD. The second terminal of transistor M4 is coupled to the first terminals of transistors M3 and S3. The second terminal of transistor M3 is coupled to the second terminals of transistor S3, the second terminals of transistors M1-M2, the second transistors of transistors S1-S2, and the gates of transistors M5-M6 and S5-S6. The second terminals of transistors M5-M6 and S5-S6 are coupled together at the output node Z.

[0072] Based on the above discussion, in other words, transistor S1 is coupled in parallel to transistor M1 as a redundant transistor. The relationship between transistors S2-S6 and transistors M2-M6 is similar to the relationship between transistors S1 and M1. Therefore, repeated descriptions are omitted here.

[0073] refer to Figure 3B , Figure 3B The directed acyclic graph shown is based on Figure 3A The netlist of the integrated circuit 30 shown is plotted. For illustration, the vertices labeled "M1-M6" correspond to... Figure 3A Transistors M1-M6 are referred to as vertices M1-M6 for ease of understanding. Vertices labeled "S1-S6" correspond to... Figure 3A Transistors S1-S6 are referred to as vertices S1-S6 for ease of understanding. The vertex labeled "A" corresponds to the pin transmitting signal A and is referred to as vertex A for ease of understanding; the vertex labeled "B" corresponds to the pin transmitting signal B and is referred to as vertex B for ease of understanding. The vertex labeled "Z" corresponds to the pin coupled to the output node and is referred to as vertex Z for ease of understanding. In some embodiments, vertices A and B are independent vertices. Figure 3B The array depicted indicates the output and input relationship between two vertices (i.e., two transistors or pins and transistors).

[0074] like Figure 3BAs shown, vertex A is connected to vertices M1, S1, M4, and S4, indicating that signal A is output to the inputs of transistors M1, S1, M4, and S4. Vertices M4 and S4 are connected to vertices M3 and S3, indicating that the outputs of transistors M4 and S4 are the inputs of transistors M3 and S3. Furthermore, vertices M3 and S3 are connected to vertices M5 and S5, indicating that the outputs of transistors M3 and S3 are the inputs of transistors M5 and S5. Vertices M4 and S4 are connected to vertex Z, indicating that the outputs of transistors M5 and S5 are the inputs of pin Z. In other words, transistors M3-M4 and S3-S4 are involved in the operation of transmitting the power supply voltage VDD to manipulate transistors M5 and S5. Additionally, after being connected to vertex A, vertices M1 and S1 are connected to vertices M6 and S6, indicating that the outputs of transistors M1 and S1 are the inputs of transistors M6 and S6. Vertices M6 and S6 are connected to vertex Z, indicating that the outputs of transistors M6 and S6 are another input of pin Z. In other words, transistors M1 and S1 are included in the operation of transmitting ground voltage levels to manipulate transistors M6 and S6.

[0075] Furthermore, vertex B is connected to vertices M2 and S2, indicating that signal B is output to the inputs of transistors M2 and S2. Vertices M2 and S2 are connected to vertices M6 and S6, indicating that the outputs of transistors M2 and S2 are the inputs of transistors M6 and S6. As mentioned above, vertices M6 and S6 are connected to vertex Z, indicating that the outputs of transistors M6 and S6 are another input to pin Z. In other words, transistors M2 and S2 also include the function of transmitting a ground voltage level to manipulate transistors M6 and S6.

[0076] Continue to refer to Figure 3B SP value A -SP B This represents the probability of a component failure occurring at the pins receiving signals A and B of the integrated circuit 30. In some embodiments, the pins are made free of component failures during the netlisting of the analog integrated circuit 30.

[0077] Values ​​SP1-SP6 indicate the probability of component failure occurring at transistors M1-M6, respectively. In some embodiments, component failure at transistors M1 to M6 includes, for example, gate oxide breakdown. Gate oxide breakdown is defined as the point in time at which a conductive path is formed between the gate and substrate of the transistor. In some cases, the conductive path originates from slow degradation that occurs over time, known as time-dependent dielectric breakdown (TDDB). For example, in a series of events, including, for example, during transistor operation, increased current, increased temperature, thermal damage, more charge traps in the gate oxide, and increased conductivity, gate oxide breakdown is accelerated, leading to transistor failure. Therefore, values ​​SP1-SP6 are obtained based on simulation results of the integrated circuit netlist under certain operating parameters to identify the most vulnerable transistors in the circuit. Accordingly, as previously described, one or more redundant transistors are added to the circuit in case the main transistor fails during operation. The method 900 for identifying transistors and determining appropriate layout configurations will be incorporated in subsequent paragraphs. Figure 9 Detailed discussion.

[0078] Now for reference Figure 3C . Figure 3C Based on some embodiments and Figure 3A The layout diagram of the corresponding integrated circuit 30 in plan view. (Refer to...) Figures 1A-3B The embodiments are provided for ease of understanding. Figure 3C The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 3C The cooperative relationship of the components shown.

[0079] For illustration, integrated circuit 30 includes Figure 1A The layout configuration of cell CELL1, where sub-cells 110 and 120 are adjacent along the y-direction. For example... Figure 3C As shown, the integrated circuit 30 also includes active regions (i.e., oxide diffusion regions OD) 210-240, gates (i.e., polysilicon) 310-370, conductive patterns (i.e., metal-to-device MD) 401-411, conductive lines (i.e., zero metal lines M0) 501-503, 504a-504b, 505-508, 509a-509 and 510-512, conductive traces (i.e., first metal lines M1) 601-604, and vias VG1-VG3, VD1-VD9 and VM1-VM8 in sub-cells 110 and 120. In some embodiments, the active regions 210-240 are arranged in... Figure 2In the first layer on the substrate Sub. Gates 310-370 and conductive patterns 401-411 are arranged in the second layer above the first layer. Conductors 501-503, 504a-504b, 505-508, 509a-509b and 510-512 are arranged in the third layer above the second layer. Conductive portions 601-604 are arranged in the fourth layer above the third layer. Vias VD1-VD9 are arranged between the first and second layers. Vias VG1-VG3 are arranged between the second and third layers. Vias VM1-VM8 are arranged between the third and fourth layers.

[0080] Reference Figure 3A and Figure 3C Active regions 210-220 are configured to form transistors M1-M6, and active regions 230-240 are configured to form transistors S1-S6.

[0081] Conductive pattern 401 corresponds to the second terminal of transistor M3. Conductive pattern 402 corresponds to the first terminal of transistor M3 and the second terminal of transistor M4. Conductive pattern 403 corresponds to the first terminals of transistors M4 and M6. Conductive pattern 404 corresponds to the second terminals of transistors M5 to M6. Conductive pattern 405 corresponds to the first terminals of transistors M2 and S2. Conductive pattern 406 corresponds to the second terminals of transistors M1-M2 and S1-S2. Conductive pattern 407 corresponds to the first terminals of transistors M1, M5, S1, and S5. Conductive pattern 408 corresponds to the second terminal of transistor S3. Conductive pattern 409 corresponds to the first terminal of transistor S3 and the second terminal of transistor S4. Conductive pattern 410 corresponds to the first terminals of transistors S4 and S6. Conductive pattern 411 corresponds to the second terminals of transistors S5-S6.

[0082] Gates 310, 350-360 and 370 are referred to as dummy gates, in which, in some embodiments, a "dummy" gate refers to a gate that is not electrically connected as a metal-oxide-semiconductor (MOS) device and does not function in the circuit.

[0083] The first portion of gate 320 above the active region 210 corresponds to the gate of transistor M3, the second portion of gate 320 above the active region 220 corresponds to the gate of transistor M2, the third portion of gate 320 above the active region 230 corresponds to the gate of transistor S2, and the fourth portion of gate 320 above the active region 240 corresponds to the gate of transistor S3.

[0084] The first portion of gate 330 above active region 210 corresponds to the gate of transistor M4, the second portion of gate 330 above active region 220 corresponds to the gate of transistor M1, the third portion of gate 330 above active region 230 corresponds to the gate of transistor S1, and the fourth portion of gate 330 above active region 240 corresponds to the gate of transistor S4.

[0085] The first portion of gate 340 above the active region 210 corresponds to the gate of transistor M6, the second portion of gate 340 above the active region 220 corresponds to the gate of transistor M5, the third portion of gate 340 above the active region 230 corresponds to the gate of transistor S5, and the fourth portion of gate 340 above the active region 240 corresponds to the gate of transistor S6.

[0086] like Figure 3C As illustrated, active regions 210-240 extend in the x-direction and are separated from each other in the y-direction. As described above, in some embodiments, each of active regions 210-220 includes Figure 2 The two fin-shaped structures 211 and 212, and the active regions 230-240 respectively include the first single fin-shaped structure and the second single fin-shaped structure.

[0087] Gates 310-370 extend in the y-direction and are separated from each other in the x-direction. In addition, gates 320-340 extend through subcells 110 and 120 and through active regions 210-240.

[0088] Conductive patterns 401-411 extend in the y-direction. Conductive patterns 401-403 pass through active region 210. Conductive pattern 404 passes through active region 210-220. Conductive patterns 401-403 pass through active region 220-230. Conductive patterns 408-410 pass through active region 240. Conductive pattern 401 passes through active region 230-240.

[0089] Conductive lines 501-503, 504a-504b, 505-508, 509a-509b, and 510-512 extend in the x-direction and are separated from each other in the y-direction. Conductive line 501 passes through conductive pattern 403 and gates 310-350. Conductive lines 502-503 pass through conductive patterns 401-404 and gates 320-340. Conductive line 504a passes through gate 320, and conductive line 504b passes through conductive pattern 404 and gate 340. Conductive lines 505-507 pass through conductive patterns 405-407 and gates 320-340, and conductive lines 505-506 also pass through conductive pattern 404. Conductive line 508 passes through conductive patterns 405-407 and 411. Conductive line 509a passes through gate 320, and conductive line 509b passes through conductive pattern 411 and gate 340. Conductive line 510 passes through conductive pattern 411 and gates 320-340. Conductive line 511 passes through conductive patterns 408-411 and gates 320-340. Conductive line 512 passes through conductive pattern 410.

[0090] Conductive traces 601-604 extend through sub-units 110-120 in the y-direction and are separated from each other in the x-direction. For illustration, conductive traces 601-602 pass through conductive lines 502-503, 504a, 505-508, 509a, and 510-511, and also through conductive lines 501 and 512. For illustration, conductive traces 603-604 pass through conductive lines 502-503, 504b, 505-508, 509b, and 510-511, and also through conductive lines 501 and 512.

[0091] Via VD2 couples conductive pattern 403 to conductive line 501, and via VD7 couples conductive pattern 410 to conductive line 512. In some embodiments, conductive lines 501 and 512 output power supply voltage VDD to conductive patterns 403 and 410, respectively. Vias VD4 and VD9 couple conductive patterns 405 and 407 to conductive line 507, respectively. In some embodiments, conductive line 507 receives power supply voltage VSS for integrated circuit 30 (i.e., in...). Figure 3A In one embodiment, grounding).

[0092] Furthermore, via VD1 couples conductive pattern 401 to wire 502. Via VM1 couples wire 502 to conductive trace 603. First, via VM4 couples conductive trace 603 to conductive line 506, and via VD3 couples conductive line 506 to conductive pattern 406. Thus, conductive pattern 401 is coupled to conductive pattern 406. In other words, the second terminal of transistor M3 is coupled to the second terminals of transistors M1-M2 and S1-S2. Second, via VM7 couples conductive trace 603 to wire 511, and via VD6 couples wire 511 to conductive pattern 408. Thus, conductive pattern 401 is also coupled to conductive pattern 408. In other words, the second terminal of transistor M3 is coupled to the second terminal of transistor S3. Third, via VM3 couples conductive trace 603 to conductive line 504b, and via VG3 couples conductive line 504b to gate 340. Thus, the conductive pattern 401 is coupled to the gate 340. In other words, the second terminals of transistors M1-M3, the second terminals of transistors S1-S3, and the gates of transistors M5-M6 and S5-S6 are coupled together.

[0093] Via VD5 couples conductive pattern 404 to conductive line 505. Via VM5 couples conductor 505 to conductive trace 604. Via VM8 couples conductive trace 604 to conductive line 509a. Via VD8 couples conductive trace 604 to conductive pattern 411. Thus, conductive pattern 404 is coupled to conductive pattern 411. In other words, the second terminals of transistors M5-M6 and S5-S6 are coupled together.

[0094] In some embodiments, the conductive trace 604 receives Figure 3A The outputs of transistors M5-M6 and S5-S6 at output node Z.

[0095] Via VG1 couples gate 330 to conductive line 510. Via VM6 couples conductive line 510 to conductive trace 602. In some embodiments, conductive trace 602 receives data for gate 330. Figure 3A Signal A. Therefore, the gates of transistors M1, M4, S1, and S4 receive signal A.

[0096] Via VG2 couples gate 320 to conductive line 504a. Via VM1, conductive line 504a, couples to conductive trace 601. In some embodiments, conductive trace 601 receives for gate 320 Figure 3A Signal B. Therefore, the gates of transistors M2, M3, S2, and S3 receive signal B.

[0097] Now for reference Figure 3D . Figure 3D Based on some embodiments and Figure 3AAnother layout diagram of the corresponding integrated circuit 30 in plan view. (Refer to...) Figures 1A-3B The embodiments are provided for ease of understanding. Figure 3D The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 3D The cooperative relationship of the components shown.

[0098] and Figure 3C In comparison, the alternative has Figure 1A The layout configuration of cell CELL1, and integrated circuit 30' also includes Figure 1A The layout configuration of cell CELL2, wherein integrated circuit 30' includes sub-cells 110 and 130-140. For example... Figure 3D As shown, instead of having active regions 210-220, Figure 3D Subunit 110 includes active regions 250-260. Subunit 130 includes active region 240, and subunit 140 includes active region 270. Furthermore, integrated circuit 30' also includes conductive lines 513-514 and vias VG4 and VM9. In some embodiments, conductive lines 513-514 are configured with reference to, for example, conductive lines 510-511. Via VG4 is configured with reference to, for example, conductive lines 510-511. Figure 3C The through-hole VG1 configuration. Through-hole VG9 is referenced for example. Figure 3C The VM6 configuration with through-hole ports.

[0099] In some embodiments, Figure 3C The active region 210-220 and Figure 3D The active zones 250-260 have a similar configuration, and Figure 3D The configuration of subunit 110 is similar to Figure 3C The configuration. Therefore, repeated descriptions are omitted here.

[0100] In some embodiments, Figure 3C The active regions 270 and 230 have similar configurations, and the sub-unit 130 includes features for... Figure 3C The same configuration of the metal wiring in the active area 230. Therefore, Figure 3D The relationship between transistors S1-S2, S5 and the layout structure is similar to Figure 3C The relationship is such that repeated descriptions are omitted here.

[0101] refer to Figure 3A and Figure 3DThe active region 240 is configured to form transistors S3-S4 and S6. Conductive pattern 401 also corresponds to the second terminal of transistor S3. Conductive pattern 402 also corresponds to the first terminal of transistor S3 and the second terminal of transistor S4. Conductive pattern 403 also corresponds to the first terminals of transistors S4 and S6. Conductive pattern 404 also corresponds to the second terminal of transistor S6. As described above, the portion of gate 320 above the active region 240 corresponds to the gate of transistor S3. The fourth portion of gate 330 above the active region 240 corresponds to the gate of transistor S4. The fourth portion of gate 340 above the active region 240 corresponds to the gate of transistor S6.

[0102] For illustration, in subcell 130, gates 320-340 pass through active region 240. Conductive patterns 401-404 also extend from subcell 110 through active region 240. Conductive line 513 passes through gates 320-340. Conductive line 514 passes through conductive patterns 401-404 and gates 320-340. Conductive traces 601-604 also pass through conductive lines 513-514.

[0103] Via VG4 couples gate 330 to conductive line 513. Via VM9 couples conductive line 513 to conductive trace 602. Therefore, Figure 3D The gate of transistor S4 in subunit 130 also receives signal A from conductive trace 602.

[0104] As previously described, conductive patterns 404 are coupled to conductive patterns 411 via vias VD5, VD8, VM5, and VM8, conductive lines 505 and 509b, and conductive trace 604. Therefore, the second terminals of transistors M5-M6 and S5-S6 are coupled together.

[0105] Figures 3A-3D The configuration is for illustrative purposes. Figures 3A-3D Various implementations are within the scope of this invention. For example, in some embodiments, active regions 240-250 are N-type and active regions 260-270 are P-type.

[0106] Now for reference Figures 4A-4B . Figure 4A According to some embodiments, including and Figure 1A The equivalent circuit of a portion of the integrated circuit 40 corresponding to the semiconductor device in the structure. Figure 4B It is based on some embodiments corresponding to Figure 4A The directed acyclic graph of the equivalent circuit of a portion of integrated circuit 40 in the diagram. (Refer to...) Figures 1A-3D The embodiments are provided for ease of understanding. Figures 4A-4BThe same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figures 4A-4B The cooperative relationship of the components shown.

[0107] and Figures 3A-3B In contrast, instead of having P-type transistors and N-type transistors (e.g., transistors S1-S6) as redundant transistors, integrated circuit 40 only includes N-type transistors as redundant transistors, such as transistors S1-S2 and S5.

[0108] Now for reference Figure 4C . Figure 4C Based on some embodiments and Figure 4A The layout diagram of the corresponding integrated circuit 40 in plan view. (Refer to...) Figures 1A-4B The embodiments are provided for ease of understanding. Figure 4C The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 4C The cooperative relationship of the components shown.

[0109] and Figure 3D In comparison, integrated circuit 40 includes Figure 1A The layout structure of cell CELL3, replacing Figure 1A The layout structure of cell CELL2. In other words, the integrated circuit 40 only includes sub-cells 140 with structures corresponding to N-type transistors S1-S2 and S5, instead of sub-cells 130 with structures including P-type transistors S3-S4 and S6.

[0110] Now for reference Figures 5A-5B . Figure 5A According to some embodiments, including and Figure 1A The equivalent circuit of a portion of the integrated circuit 50 corresponding to the semiconductor device in the structure. Figure 5B It is based on some embodiments corresponding to Figure 5A The directed acyclic graph of the equivalent circuit of a portion of integrated circuit 50 in the diagram. (Refer to...) Figures 1A-4C The embodiments are provided for ease of understanding. Figures 5A-5B The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figures 5A-5B The cooperative relationship of the components shown.

[0111] and Figures 3A-3BIn contrast, integrated circuit 50 includes only P-type transistors as redundant transistors, such as transistors S3-S4 and S6, instead of having P-type and N-type transistors (e.g., transistors S1-S6) as redundant transistors.

[0112] Now for reference Figure 5C . Figure 5C Based on some embodiments and Figure 5A The layout diagram of the corresponding integrated circuit 50 in plan view. (Refer to...) Figures 1A-5B The embodiments are provided for ease of understanding. Figure 5C The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 5C The cooperative relationship of the components shown.

[0113] and Figure 3D In comparison, integrated circuit 50 includes Figure 1A The CELL4 cell layout structure replaces Figure 1A The layout structure of cell CELL2. In other words, the integrated circuit 50 only includes sub-cells 130 with structures corresponding to P-type transistors S3-S4 and S6, instead of sub-cells 140 with structures including N-type transistors S1-S2 and S5.

[0114] Now for reference Figures 6A-6B . Figure 6A According to some embodiments, including and Figure 1A The equivalent circuit of a portion of an integrated circuit 60 corresponding to a semiconductor device in the structure. Figure 6B It is based on some embodiments corresponding to Figure 6A The directed acyclic graph of the equivalent circuit of a portion of integrated circuit 60 in the diagram. (Refer to...) Figures 1A-5C The embodiments are provided for ease of understanding. Figures 6A-6B The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figures 6A-6B The cooperative relationship of the components shown.

[0115] and Figures 5A-5B In contrast, integrated circuit 60 includes only a portion of the P-type transistors corresponding to the main logic circuit as redundant transistors, such as transistors S4 and S6, instead of all P-type transistors S3-S4 and S6 having all P-type transistors M3-M4 and M6 corresponding to the main logic circuit.

[0116] Now for reference Figure 6C . Figure 6C Based on some embodiments and Figure 6AThe layout diagram of the corresponding integrated circuit 60 in plan view. (Refer to...) Figures 1A-6B The embodiments are provided for ease of understanding. Figure 6C The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 6C The cooperative relationship of the components shown.

[0117] and Figure 5C In contrast, the layout structure corresponding to transistor S3 is adjusted. Specifically, gate 320 does not extend through subcell 110 to subcell 130. Instead, integrated circuit 60 includes gate 321 extending through active region 240, and gate 321 is electrically isolated from gate 320. Furthermore, conductive pattern 401 also does not extend through subcell 110 to subcell 130. Instead, integrated circuit 60 includes conductive pattern 412 extending through active region 240, and conductive pattern 412 is electrically isolated from conductive pattern 401.

[0118] Now for reference Figures 7A-7B . Figure 7A According to some embodiments, including and Figure 1A The equivalent circuit of a portion of an integrated circuit 70 corresponding to a semiconductor device in the circuit. Figure 7B It is based on some embodiments corresponding to Figure 7A The directed acyclic graph of the equivalent circuit of a portion of integrated circuit 70 in the diagram. (Refer to...) Figures 1A-6C The embodiments are provided for ease of understanding. Figures 7A-7B The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figures 7A-7B The cooperative relationship of the components shown.

[0119] and Figures 6A-6B In contrast, integrated circuit 70 includes N-type and P-type transistors as redundant transistors, such as transistors S2 and S4, instead of transistors S4 and S6 which only have one type.

[0120] Furthermore, in other words, with Figures 3A-3B In contrast, integrated circuit 70 includes a portion of P-type transistors (such as transistor S4) corresponding to the main logic circuit, and a portion of N-type transistors (such as transistor S2) corresponding to the main logic circuit, instead of having all N-type and P-type transistors S1-S6.

[0121] Now for reference Figure 7C . Figure 7C Based on some embodiments and Figure 7AThe layout diagram of the corresponding integrated circuit 70 in plan view. (Refer to...) Figures 1A-7B The embodiments are provided for ease of understanding. Figure 7C The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 7C The cooperative relationship of the components shown.

[0122] and Figure 3D In contrast, the layout structure corresponding to transistors S1, S3, and S5-S6 is adjusted. Specifically, gate 320 does not cross the active region 240. Instead, integrated circuit 70 includes gate 321 that crosses the active region 240, and gate 321 is electrically isolated from gate 320. Gate 330 does not cross the active region 270. Instead, integrated circuit 70 includes gate 331 that crosses the active region 270, and gate 331 is electrically isolated from gate 330. Gate 340 does not cross the active regions 240 and 270. Instead, integrated circuit 70 includes gate 341 that crosses the active region 270 and gate 342 that crosses the active region 240. Gates 341-342 are electrically isolated from gate 340.

[0123] Conductive pattern 404 does not extend into subcell 130. Instead, integrated circuit 70 includes conductive pattern 414 passing through active region 240, and conductive pattern 414 is electrically isolated from conductive pattern 404. Conductive pattern 407 does not extend into subcell 140. Instead, integrated circuit 70 also includes conductive pattern 413 passing through active region 270, and conductive pattern 413 is electrically isolated from conductive pattern 407.

[0124] Furthermore, to illustrate, in Figure 7C In the embodiments, vias VD8 and VM8 configured to couple conductive pattern 411 to conductive pattern 404 are excluded.

[0125] Now for reference Figures 8A-8B . Figure 8A According to some embodiments, including and Figure 1A The equivalent circuit of a portion of an integrated circuit 80 corresponding to a semiconductor device in the circuit. Figure 8B It is based on some embodiments corresponding to Figure 8A The directed acyclic graph of the equivalent circuit of a portion of integrated circuit 80 in the diagram. (Refer to...) Figures 1A-7C The embodiments are provided for ease of understanding. Figures 8A-8B The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figures 8A-8B The cooperative relationship of the components shown.

[0126] and Figures 7A-7B In contrast, integrated circuit 80 includes only one P-type transistor as a redundant transistor, such as transistor S4.

[0127] Now for reference Figure 8C . Figure 8C Based on some embodiments and Figure 8A The layout diagram of the corresponding integrated circuit 80 in plan view. (Refer to...) Figures 1A-8B The embodiments are provided for ease of understanding. Figure 8C The same elements are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here, unless it is necessary to introduce them in conjunction with the reference numerals. Figure 8C The cooperative relationship of the components shown.

[0128] and Figure 7C In contrast, integrated circuit 80 includes sub-unit 130 but does not include sub-unit 140.

[0129] Figures 3A-8C The configuration is for illustrative purposes. Figures 3A-8C Various implementations are within the scope of this invention. For example, in some embodiments, the integrated circuit includes only one N-type transistor as a redundant transistor, such as transistor S2 corresponding to transistor M2, instead of having only one P-type transistor as a redundant transistor.

[0130] Now for reference Figure 9 . Figure 9 This is a flowchart of a method 900 for generating layout design and manufacturing integrated circuits for designing integrated circuit layouts, according to some embodiments of the present invention. It should be understood that, for additional embodiments of this method, [further details may be needed]. Figure 9 Additional operations are provided before, during, and after the processes shown, and some of these operations can be substituted or canceled. The order of operations / processes can be interchanged. The same reference numerals are used to denote the same elements in the various views and illustrative embodiments. Method 900 includes operations 910-960, which are referred to below. Figures 1A-1B Integrated circuit 10 and Figures 3A-8C Integrated circuits 30-80 describe operations 910-960.

[0131] In operation 910, the netlist of integrated circuit 30 is obtained.

[0132] In operation 920, the netlist of integrated circuit 30 is simulated using some operating parameters of integrated circuit 30, and values ​​SP1-SP6 are obtained based on the simulation results, each corresponding to one of transistors M1-M6 included in integrated circuit 30. In some embodiments, integrated circuit 30 includes more than six transistors or fewer than six transistors.

[0133] In operation 930, each of the values ​​SP1-SP6 is compared with the threshold C. crit A comparison is made. In some embodiments, the threshold C is... crit It largely depends on process parameters, such as the thickness of the gate oxide layer. Therefore, the threshold C crit It varies depending on the process and is defined according to the actual application.

[0134] In some embodiments, the values ​​SP3-SP4 and SP6 of the P-type transistor are compared with the threshold C. crit Compare the values ​​of N-type transistors SP1-SP2 and SP5 with the value (1-C). crit (Compare)

[0135] In operation 940, based on comparison, when the value corresponding to the P-type transistor is less than the threshold C... crit At that time, the corresponding redundant P-type transistors are added to the netlist of integrated circuit 30 to generate an adjusted netlist. For example, in Figures 3A-3B In this embodiment, the values ​​SP3-SP4 and SP6 are both equal to 0.2, which is less than the threshold C. crit 0.3. Therefore, as Figure 3B As shown, transistors S3-S4 and S6 are added to the netlist. Similarly, when values ​​SP1-SP2 and SP5 are all equal to 0.2, it is less than the value 0.7 (i.e., 1 minus C). crit Therefore, as Figure 3B As shown, transistors S1-S2 and S5 are added to the netlist.

[0136] In operation 950, the circuit layout configuration is determined based on the number of N-type transistors and the number of P-type transistors configured as redundant transistors. In other words, the layout configuration with redundant transistors varies according to the adjusted netlist. For example, in Figures 4A-4C In this embodiment, instead of adding P-type transistors as redundant transistors, three N-type transistors are added. Therefore, reference will be made to, for example... Figure 1A The layout configuration of cell CELL3 is assigned to integrated circuit 40.

[0137] exist Figures 5A-6C and Figures 8A-8C In this embodiment, instead of adding an N-type transistor as a redundant transistor, one or more P-type transistors are added. Therefore, reference will be made to, for example... Figure 1A The layout configuration of the cell CELL4 is assigned to integrated circuits 50, 60 and 80.

[0138] In some embodiments, at least one of the N-type transistors and at least one of the P-type transistors are added as redundant transistors. One of the plurality of layout configurations of the circuit is determined based on the resistor and capacitor values ​​of the wiring. Method 900 also includes the operation of determining one of the layout configurations of the circuit based on the resistor and capacitor values ​​of the wiring. For example, in some embodiments, for an integrated circuit, a layout configuration is determined as shown by... Figure 1A The layout configuration shown for cell CELL1, for example Figure 3C The integrated circuit 30 is processed to have small resistor and capacitor values ​​for the back-to-end process (BEOL) and larger resistor and capacitor values ​​for the intermediate process (MEOL) compared to the BEOL. In an alternative embodiment, the integrated circuit is determined as follows: Figure 1A The layout configuration shown for cell CELL2, for example Figure 3D The integrated circuit 30 is configured to have large resistor and capacitor values ​​for BEOL and smaller resistor and capacitor values ​​for MEOL compared to BEOL.

[0139] In some embodiments, an integrated circuit manufacturing process is generally considered to include a front-end process (FEOL) portion, an intermediate process (MEOL or MOL) portion, and a back-end process (BEOL) portion. FEOL is the first part of integrated circuit manufacturing, in which individual active devices are patterned on a semiconductor wafer. The FEOL process includes: selecting the type of semiconductor wafer to use; chemically and mechanically planarizing and cleaning the wafer; shallow trench isolation (STI); forming wells, forming gate modules, and generating source and drain electrodes. FEOL does not include the deposition of metal interconnect layers. The MEOL process follows the FEOL process and includes gate contact formation and under-bump metallization (UBM) processes. BEOL is the final part of the integrated circuit manufacturing process, in which individual devices (transistors, capacitors, resistors, etc.) are interconnected through vias and conductive traces (e.g., metal lines). BEOL typically begins with the deposition of the first metal layer, including contacts, an insulating layer (dielectric), metal surfaces, and bonding sites for chip-to-package connections. In some embodiments, ten or more metal layers are added in the BEOL portion.

[0140] In some embodiments, method 900 includes assigning one of the layout configurations of reference cells CELL5-CELL8 to an integrated circuit to add one or more redundant transistors of a specific conductivity type. In some embodiments, the assignment operation is related to the number of N-type transistors and the number of P-type transistors configured as redundant transistors.

[0141] In operation 960, the layout of the integrated circuit is generated, for example... Figures 3C-3D , Figure 4C , Figure 5C , Figure 6C , Figure 7C and Figure 8C .

[0142] Now for reference Figure 10 . Figure 10 This is a block diagram of an electronic design automation (EDA) system 1000 for designing integrated circuit layout designs according to some embodiments of the present invention. The EDA system 1000 is configured to implement... Figure 9 The information disclosed in China and combined with Figures 1A-8C One or more operations of method 900 are further explained. In some embodiments, EDA system 1000 includes an APR system.

[0143] In some embodiments, the EDA system 1000 is a general-purpose computing device including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. Among other uses, the storage medium 1004 is encoded with (i.e., storing) computer program code (instructions) 1006 (i.e., an executable instruction set). Execution of the instructions 1006 by the hardware processor 1002 represents (at least partially) an EDA tool that implements, for example, part or all of method 900.

[0144] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 and manufacturing tool 1016 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, thereby enabling processor 1002 and computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable storage medium 1004 to enable EDA system 1000 to perform some or all of the described process / or method. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0145] In one or more embodiments, the computer-readable storage medium 1004 is an electronic system, magnetic system, optical system, electromagnetic system, infrared system, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes optical disc read-only memory (CD-ROM), optical disc read / write memory (CD-R / W), and / or digital video optical disc (DVD).

[0146] In one or more embodiments, the storage medium 1004 storing computer program code 1006 is configured to enable EDA system 1000 (where such execution represents (at least partially) EDA tools) to perform some or all of the described process and / or method. In one or more embodiments, the storage medium 1004 also stores some or all of the information that helps perform the described process and / or method. In one or more embodiments, the storage medium 1004 stores an integrated circuit (IC) layout diagram 1020 of standard cells, including such standard cells disclosed herein, for example, those included above referenced. Figures 1A-11 The cells in the integrated circuits 100 and / or 700 discussed.

[0147] EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0148] EDA system 1000 also includes a network interface 1012 coupled to processor 1002. Network interface 1012 allows EDA system 1000 to communicate with network 1014, which connects to one or more other computer systems. Network interface 1012 includes a wireless network interface such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1064. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more systems 1000.

[0149] The EDA system 1000 also includes a manufacturing tool 1016 coupled to the processor 1002. The manufacturing tool 1016 is configured to manufacture integrated circuits, such as those based on design documents processed by the processor 1002. Figures 1A-8C The integrated circuits shown are 10, 30, 30', 40-80.

[0150] EDA system 1000 is configured to receive information via I / O interface 1010. The information received via I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1002. The information is transmitted to processor 1002 via bus 1008. EDA system 1000 is also configured to receive information related to the user interface (UI) via I / O interface 1010. This information is stored in computer-readable medium 1004 as design specification 1022.

[0151] In some embodiments, part or all of the described process and / or method is executed as a standalone software application executed by a processor. In some embodiments, part or all of the described process and / or method is executed as a software application as part of an additional software application. In some embodiments, part or all of the described process and / or method is executed as a plug-in to a software application. In some embodiments, part or all of the described process and / or method is executed as a software application as part of an EDA tool. In some embodiments, part or all of the described process and / or method is executed as a software application used by the EDA system 1000. In some embodiments, a suitable layout generation tool is used to generate a layout diagram including standard cells.

[0152] In some embodiments, these processes are implemented as program functions stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), and semiconductor memories (e.g., ROMs, RAMs, and memory cards).

[0153] Figure 11 This is a block diagram of an IC manufacturing system 1100 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 1100 is used to manufacture at least one of the following two: (A) one or more semiconductor masks, or (B) at least one component in a semiconductor integrated circuit layer.

[0154] exist Figure 11In this IC manufacturing system 1100, entities such as design room 1120, mask room 1130, and IC fabrication plant (“fab”) 1150 interact with each other in the design, R&D, and production cycles and / or services related to the manufacture of IC devices 1160. The entities in the IC manufacturing system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, a single entity owns two or more of the design room 1120, mask room 1130, and IC fab 1150. In some embodiments, two or more of the design room 1120, mask room 1130, and IC fab 1150 share common equipment and use common resources.

[0155] Design studio (or design team) 1120 generates IC design layout 1122. IC design layout 1122 includes designs for IC device 1160 (e.g., ...). Figures 1A-8C The various geometric patterns of the integrated circuits 10, 30, 30', 40-80 shown are, for example... Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and / or Figure 8A The IC layout design depicted herein. The geometric pattern corresponds to the pattern of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1160 to be manufactured. The various layers are combined to form various IC components. For example, a portion of the IC design layout 1122 includes various IC components to be formed on a semiconductor substrate (such as a silicon wafer), such as active regions for interlayer interconnects, gate electrodes, source and drain electrodes, conductive portions or vias, and various metal layers disposed on the semiconductor substrate. The design room 1120 performs appropriate design processes to form the IC design layout 1122. The design processes include one or more of logic design, physical design, or placement and routing. The IC design layout 1122 exists in one or more data files containing geometric pattern information. For example, the IC design layout 1122 may be represented in GDSII file format or DFII file format.

[0156] Mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. Mask chamber 1130 fabricates one or more masks 1145 using an IC design layout 1122 for fabricating various layers of an IC device 1160 according to the IC design layout 1122. Mask chamber 1130 performs mask data preparation 1132, where the IC design layout 1122 is translated into a representative data file (“RDF”). Mask data preparation 1132 provides the RDF to mask fabrication 1144. Mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1145 or a semiconductor wafer 1153. The IC design layout 1122 is manipulated by mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1150. Figure 11 In this diagram, data preparation 1132 and mask manufacturing 1144 are shown as distinct elements. In some embodiments, data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0157] In some embodiments, data preparation 1132 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image distortions, such as those that may be caused by diffraction, interference, and other process effects. OPC adjusts the IC design layout diagram 1122. In some embodiments, data preparation 1132 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary patterning, phase-shift masks, and other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, where ILT treats OPC as a reverse imaging problem.

[0158] In some embodiments, data preparation 1132 includes a mask rule checker (MRC) that checks an IC design layout 1122 that has undergone processes in the OPC and has a set of mask generation rules. This set of mask generation rules includes certain geometric constraints and / or connectivity constraints to ensure sufficient space, taking into account variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1144, which can undo portions of the modifications performed by the OPC to conform to the mask generation rules.

[0159] In some embodiments, data preparation 1132 includes a lithography process check (LPC), an LPC simulation performed by an IC fab 1150 to manufacture an IC device 1160. The LPC simulates this process based on an IC design layout 1122 to generate a simulated manufactured device, such as IC device 1160. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), and other suitable factors, or combinations thereof. In some embodiments, after the simulated manufactured device is generated by the LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0160] It should be understood that, for clarity, the foregoing description of data preparation 1132 has been simplified. In some embodiments, data preparation 1132 includes additional features, such as logical operations (LOPs), to modify the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0161] Following data preparation 1132 and during mask fabrication 1144, a mask 1145 or a set of masks 1145 is fabricated based on the IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, an electron beam (e-beam) or multiple e-beams are used to pattern the mask (photomask or intermediate mask) 1145 based on the modified IC design layout 1122. Various techniques can be used to form the mask 1145. In some embodiments, a binary technique is used to form the mask 1145. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (such as ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in opaque regions of the binary mask. In another example, mask 1145 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1145, various components in a pattern formed on the phase-shifting mask are configured to have suitable phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be attenuated PSM or alternating PSM. One or more masks generated by mask fabrication 1144 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0162] IC fab 1150 includes wafer fabrication 1152. IC fab 1150 is an IC manufacturing enterprise, including one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 1150 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end process (BEOL) manufacturing) for IC product interconnection and packaging, and a third manufacturing facility can provide other services for the foundry enterprise.

[0163] IC fab 1150 uses mask 1145, fabricated in mask chamber 1130, to fabricate IC device 1160. Therefore, IC fab 1150 uses IC design layout 1122 at least indirectly to fabricate IC device 1160. In some embodiments, IC fab 1150 uses mask 1145 to fabricate semiconductor wafer 1153 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric components, and multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0164] As described above, the integrated circuit and method of the present invention utilize the advantages of a hybrid row architecture to reduce the shadow cell area, duration and power consumption by half while extending the lifespan of the cell TDDB.

[0165] In some embodiments, an integrated circuit is disclosed, including a semiconductor device. The semiconductor device includes: a plurality of first cell rows extending in a first direction, each first cell row having a first row height; a plurality of second cell rows extending in the first direction, each second cell row having a second row height less than the first row height, wherein the first cell rows and second cell rows are staggered; first cells disposed in a first row of the first cell rows; and at least one second cell disposed in at least one row of the second cell rows, wherein the at least one second cell is adjacent to the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operating configuration. In some embodiments, at least one row of the second cell rows includes: a first row including a first active region of type P conductivity; and a second row including a second active region of type N conductivity; wherein the first row and the second row of the second cell rows are disposed on opposite sides of the first row of the first cell rows. In some embodiments, the first cell includes a plurality of first active regions, and at least one second cell includes a plurality of second active regions; wherein the semiconductor device further includes: at least one gate extending in the second direction and passing through the first and second active regions. In some embodiments, at least one second unit includes: a first active region and a second active region extending in a first direction, wherein the first active region and the second active region have different conductivity types; and at least one conductive pattern extending in a second direction; wherein the first active region is arranged closer to the first unit adjacent to the at least one second unit compared to the second active region; wherein the at least one conductive pattern passes through the first active region. In some embodiments, the at least one conductive pattern is configured as a terminal of a first transistor included in the first unit and a terminal of a second transistor included in at least one second unit; wherein the first transistor and the second transistor are configured to receive a signal at their gate terminals and have first terminals coupled to each other and second terminals coupled to each other. In some embodiments, at least one second unit includes a first active region, and the first unit includes a second active region; wherein the integrated circuit further includes: at least one conductive pattern extending in the second direction and intersecting the first active region and the second active region. In some embodiments, the semiconductor also includes a third unit configured as identical to the at least one second unit, wherein the third unit is arranged in a first row of the second unit rows; wherein at least one row of the first row and the second unit rows is arranged on opposite sides of the first row of the first unit rows. In some embodiments, at least one second unit includes a first unit and a second unit, the first unit including a first active region of a first type, and the second unit including a second active region of a second type different from the first type; wherein the first unit and the second unit of at least one second unit are arranged on opposite sides of the first unit.In some embodiments, the semiconductor further includes a third unit different from the first unit and at least one second unit, wherein at least one second unit is arranged to be inserted between the first unit and the third unit; wherein the first unit, at least one second unit and the third unit are configured to cooperate as a logic circuit.

[0166] An integrated circuit including an integrated circuit is also disclosed. An integrated circuit includes: a first circuit including a plurality of first transistors, each first transistor having a double-fin active region structure; and a second circuit including at least one second transistor having a single-fin active region structure; wherein the at least one second transistor and at least one of the first transistors are coupled in parallel to each other and configured to cooperate in response to a first signal at the gate of the at least one second transistor and at least one of the first transistors. In some embodiments, the at least one second transistor includes a plurality of second transistors; wherein each of the first transistors is coupled in parallel to a corresponding one of the second transistors, and each of the first transistors and the corresponding one of the second transistors are configured to receive the same signal at their gates. In some embodiments, the at least one second transistor and the at least one first transistor have the same conductivity type. In some embodiments, the at least one second transistor and the at least one first transistor share a gate structure configured as their gates and a plurality of conductive patterns configured as their coupling terminals; wherein the gate structure and the conductive patterns pass through the single-fin active region structure and the double-fin active region structure in a layout diagram. In some embodiments, the first circuit operates faster than the second circuit. In some embodiments, a first circuit is arranged in a first cell row having a first row height, and a second circuit is arranged in a second cell row having a second row height different from the first row height; wherein the first cell row and the second cell row are adjacent to each other in the layout diagram.

[0167] A system is also disclosed, comprising: a non-transitory storage medium encoded with an instruction set; and a hardware processor communicatively coupled to the non-transitory storage medium and configured to execute the instruction set, the instruction set being configured to cause the processor to: acquire a plurality of values ​​based on a circuit's netlist, each value corresponding to one of a plurality of transistors included in the circuit; compare the values ​​with a threshold; generate an adjusted netlist of the circuit by adding a plurality of redundant transistors in response to the comparison; and determine one of a plurality of layout configurations of the circuit based on the adjusted netlist, wherein the layout configuration includes a plurality of first cell rows, each having a first cell height, and a plurality of second cell rows, each having a second cell height different from the first cell height. In some embodiments, the redundant transistors include a plurality of first redundant transistors of a first type and a plurality of second redundant transistors of a second type different from the first type; wherein the instruction set is further configured to cause the processor to: determine one of the layout configurations based on the number of first redundant transistors and the number of second redundant transistors. In some embodiments, the layout configuration includes: a first layout configuration, wherein at least one of the first redundant transistors and at least one of the second redundant transistors are arranged in the second cell rows; a second layout configuration, wherein at least one of the first redundant transistors is arranged in a first row of the second cell rows; and a third layout configuration, wherein at least one of the second redundant transistors is arranged in a second row of the second cell rows. In some embodiments, the redundant transistors include a plurality of first redundant transistors of a first type and a plurality of second redundant transistors of a second type, different from the first type; wherein the layout configuration includes a first layout configuration in which at least one of the first redundant transistors and at least one of the second redundant transistors are arranged in different rows in a second cell row. In some embodiments, the instruction set is configured to enable the processor to determine one of the layout configurations of the circuitry based on the resistor and capacitor values ​​of the wiring.

[0168] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A system for forming an integrated circuit layout, comprising: Non-transient storage media with encoded instruction sets; as well as A hardware processor, communicatively coupled to the non-transient storage medium and configured to execute the instruction set, the instruction set being configured to cause the processor to: A circuit-based netlist acquires multiple values, each corresponding to one of a plurality of transistors included in the circuit; Compare the plurality of values ​​with a threshold; In response to the comparison, an adjusted netlist for the circuit is generated by adding multiple redundant transistors; as well as Based on the adjusted netlist, one of a plurality of layout configurations for the circuit is determined, wherein the plurality of layout configurations includes a plurality of first cell rows, each having a first cell height, and a plurality of second cell rows, each having a second cell height different from the first cell height.

2. The system according to claim 1, wherein, The plurality of redundant transistors includes a plurality of first redundant transistors of a first type and a plurality of second redundant transistors of a second type different from the first type; The instruction set is configured to further enable the processor to: One of the layout configurations is determined based on the number of the plurality of first redundant transistors and the number of the plurality of second redundant transistors.

3. The system according to claim 2, wherein, The plurality of layout configurations include: A first layout configuration, wherein at least one of the plurality of first redundant transistors and at least one of the plurality of second redundant transistors are arranged in the plurality of second cell rows; A second layout configuration, wherein at least one of the plurality of first redundant transistors is arranged in the first row of the plurality of second cell rows; and A third layout configuration, wherein at least one of the plurality of second redundant transistors is arranged in the second row of the plurality of second cell rows.

4. The system according to claim 1, wherein, The plurality of redundant transistors includes a plurality of first redundant transistors of a first type and a plurality of second redundant transistors of a second type different from the first type; The plurality of layout configurations include a first layout configuration in which at least one of the plurality of first redundant transistors and at least one of the plurality of second redundant transistors are arranged in different rows of the plurality of second cell rows.

5. The system according to claim 4, wherein, The instruction set is also configured to enable the processor to: One of the plurality of layout configurations of the circuit is determined based on the resistor and capacitor values ​​of the wiring.

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