Display Devices

Abstract

A display device includes: a substrate including a display area and a peripheral area, a thin film transistor arranged on the substrate, a first metal wiring layer electrically connected to the thin film transistor, an inorganic protective layer on the first metal wiring layer, a patterned first organic film layer located on the inorganic protective layer and overlapping with the first metal wiring layer in a plan view, a second metal wiring layer on the first organic film layer, and a second organic film layer on the second metal wiring layer, wherein the first organic film layer is patterned to be arranged at a position where the first metal wiring layer and the second metal wiring layer overlap each other in a plan view instead of being arranged on the entire display area, and the second organic film layer is arranged on the entire display area.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0028625 filed on March 6, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Art

[0003] Generally, a display device has a configuration including various stacked layers. For example, an organic light emitting display device includes an organic light emitting device. The organic light emitting device includes a pixel electrode, an intermediate layer including an organic light emitting layer, and a counter electrode. In addition, a circuit unit for driving the organic light emitting device also has a configuration including a plurality of stacked wiring layers, and an insulating layer for preventing a short circuit between the plurality of wiring layers may be placed between the plurality of wiring layers. The insulating layer may include an inorganic substance or an organic substance. Summary of the invention

[0004] In the insulating layer including organic matter, since the gas generated from the organic matter may not be completely discharged during the manufacturing process of the display device and may partially remain in the insulating layer, degassing may occur from the insulating layer including organic matter during the use of the display device. In addition, when the display device is used outdoors for a long time, the insulating layer including organic matter may begin to decompose due to sunlight, and gas may be generated during the decomposition process. As described above, when gas is generated from the insulating layer including organic matter, the organic light-emitting layer deteriorates due to the generated gas, and defects such as pixel shrinkage are generated, and thus, the reliability of the display device is reduced. One or more embodiments include a display device capable of minimizing degassing from the insulating layer including organic matter and a manufacturing method thereof.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0006] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area; a thin film transistor arranged on the substrate; a first metal wiring layer electrically connected to the thin film transistor; an inorganic protective layer on the first metal wiring layer; a patterned first organic film layer located on the inorganic protective layer and overlapping with the first metal wiring layer in a plan view; a second metal wiring layer on the first organic film layer; and a second organic film layer on the second metal wiring layer, wherein the first organic film layer is patterned to be arranged at a position where the first metal wiring layer and the second metal wiring layer overlap each other in a plan view, rather than being arranged on the entire display area, and the second organic film layer is arranged on the entire display area.

[0007] In an embodiment, the first metal wiring layer may include a plurality of wirings spaced apart from each other, and the second organic film layer may contact an upper surface of the inorganic protective layer between the plurality of wirings.

[0008] In an embodiment, the second organic film layer may have a concave shape at a position contacting the upper surface of the inorganic protective layer.

[0009] In an embodiment, the display device may further include a light emitting device electrically connected to the thin film transistor, wherein the light emitting device may include a pixel electrode, a common electrode, and an intermediate layer having an emission layer between the pixel electrode and the common electrode, and the pixel electrode is located on the second organic film layer, and the first organic film layer may be arranged at a position overlapping with the pixel electrode.

[0010] In an embodiment, the display device may further include an encapsulation layer on the common electrode and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

[0011] In an embodiment, the thin film transistor may include a semiconductor layer and a gate electrode, the first metal wiring layer may include a scan line electrically connected to the gate electrode, and the scan line may be located in a layer different from a layer where the gate electrode is located.

[0012] In an embodiment, the display device may further include a first insulating layer between the semiconductor layer and the gate electrode, and a second insulating layer and an interlayer insulating layer on the gate electrode, wherein the scan line may be located on the interlayer insulating layer.

[0013] In an embodiment, the display device may further include an upper electrode disposed between the second insulating layer and the interlayer insulating layer at a position overlapping the gate electrode in a plan view.

[0014] In an embodiment, the second metal wiring layer may include wirings directly on the inorganic protection layer exposed by the patterned first organic film layer.

[0015] In an embodiment, the second metal wiring layer may include a data line and a driving voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a plan view of a display device according to an embodiment;

[0018] Figure 2 is an equivalent circuit diagram of a pixel circuit included in a display device according to an embodiment;

[0019] Figure 3 is a layout diagram showing positions of a plurality of thin film transistors and capacitors included in a pixel circuit according to an embodiment;

[0020] Figures 4 to 8 For each layer Figure 3 A layout diagram of the configuration of a plurality of thin film transistors and capacitors; and

[0021] Fig. 9 yes Figure 1 A cross-sectional view of a cross section of a portion of a display device. DETAILED DESCRIPTION

[0022] Now will be referred to in detail embodiment, the example of these embodiments is illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiment can have different forms and should not be construed as being limited to the description stated herein. Therefore, the following only describes the embodiment by reference to the accompanying drawings to explain the various aspects of this specification. The terms used herein are only for the purpose of describing a specific embodiment, and are not intended to be limited. As used herein, the singular forms "one" and "the (described)" are intended to include plural forms, unless the context clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the association. Throughout the disclosure, the statement "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or their variants.

[0023] It will be understood that, although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms.

[0024] An expression used in the singular includes the expression in the plural unless it has an obviously different meaning in the context.

[0025] It will be further understood that the terms “comprises” and / or “comprising” as used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0026] It will be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, it may be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0027] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments according to the present invention are not limited thereto.

[0028] When a certain embodiment can be implemented differently, a specific process can be performed in an order different from the described order. For example, two processes described in succession can be performed substantially at the same time, or in an order opposite to the described order.

[0029] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to represent the same elements.

[0030] Figure 1 is a plan view of a display device according to an embodiment.

[0031] refer to Figure 1 , the display device 10 may include a display area DA and a peripheral area PA located outside the display area DA. The display device 10 may provide an image by an array of a plurality of pixels PX arranged in a two-dimensional manner in the display area DA. The peripheral area PA is an area where no image is provided, and may completely or partially surround the display area DA. A driver for providing an electrical signal or power to the pixel PX may be provided in the peripheral area PA. In the peripheral area PA, a pad area may be provided as an area to which an electronic device or a printed circuit board may be electrically connected.

[0032] Hereinafter, although the display device 10 is described as including an organic light emitting diode OLED as a display element, the display device 10 according to the present disclosure of the present invention is not limited thereto. As another embodiment, the display device 10 may be a light emitting display device (an inorganic light emitting display or an inorganic electroluminescent ("EL") display device) including an inorganic substance such as a micro light emitting diode ("LED"), or may be a display device such as a quantum dot light emitting display. For example, the light emitting layer of the display element provided in the display device 10 may include an organic substance, an inorganic substance, a quantum dot, an organic substance and a quantum dot, or an inorganic substance and a quantum dot.

[0033] Figure 2 is an equivalent circuit diagram of a pixel circuit included in a display device according to an embodiment.

[0034] refer to Figure 2 , the display device 10 includes a pixel circuit PC, the pixel circuit PC includes signal lines 121, 131, 132, 133 and 151, a plurality of thin film transistors T1 to T7 connected to the signal lines, a storage capacitor Cap, a first initialization voltage line 122 and a second initialization voltage line 123, and a driving voltage line 152. In addition, the display device 10 may include an organic light emitting diode OLED as a light emitting device, and the organic light emitting diode OLED emits light by receiving a driving voltage through the pixel circuit PC.

[0035] Figure 2The diagram shows a case where signal lines 121, 131, 132, 133 and 151, a first initialization voltage line 122 and a second initialization voltage line 123, and a driving voltage line 152 are provided for each pixel circuit PC. However, the present disclosure according to the present invention is not limited thereto. As another embodiment, at least one of the signal lines 121, 131, 132, 133 and 151, the first initialization voltage line 122 and / or the second initialization voltage line 123 may be shared by adjacent pixel circuits PC.

[0036] The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor. Figure 2 As shown in , the thin film transistors may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an action control thin film transistor T5, a light emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0037] The signal lines include a scan line 131 transmitting a scan signal Sn, a previous scan line 132 transmitting a previous scan signal Sn-1 to a first initialization thin film transistor T4, a subsequent scan line 133 transmitting a subsequent scan signal Sn+1 to a second initialization thin film transistor T7, a light emission control line 121 transmitting a light emission control signal En to an action control thin film transistor T5 and a light emission control thin film transistor T6, and a data line 151 crossing the scan line 131 and transmitting a data signal Dm. The driving voltage line 152 may transmit a driving voltage ELVDD to the driving thin film transistor T1, and the first initialization voltage line 122 and the second initialization voltage line 123 may transmit an initialization voltage Vint for initializing the driving thin film transistor T1 and a pixel electrode of the organic light emitting diode OLED.

[0038] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the electrode (e.g., the lower electrode Cap1) of the storage capacitor Cap, one of the source electrode and the drain electrode of the driving thin film transistor T1 is connected to the driving voltage line 152 via the action control thin film transistor T5, and the other of the source electrode and the drain electrode of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the light emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies the driving current Id to the organic light emitting diode OLED.

[0039] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line 131, one of the source electrode and the drain electrode of the switching thin film transistor T2 is connected to the data line 151, and the other of the source electrode and the drain electrode of the switching thin film transistor T2 is connected to the driving voltage line 152 via the action control thin film transistor T5, and is connected to the driving thin film transistor T1. The switching thin film transistor T2 is turned on in response to the scan signal Sn received through the scan line 131, and performs a switching operation for transmitting the data signal Dm transmitted to the data line DL to the driving thin film transistor T1.

[0040] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line 131, one of the source electrode and the drain electrode of the compensation thin film transistor T3 is connected to the pixel electrode of the organic light emitting diode OLED via the light emitting control thin film transistor T6, and is connected to the driving thin film transistor T1, and the other of the source electrode and the drain electrode of the compensation thin film transistor T3 is connected to the electrode of the storage capacitor Cap (for example, the lower electrode Cap1), the first initialization thin film transistor T4 and the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn received through the scan line 131, and the driving gate electrode G1 of the driving thin film transistor T1 is electrically connected to one of the source electrode and the drain electrode of the driving thin film transistor T1 (for example, the drain electrode), so that the driving thin film transistor T1 is diode-connected.

[0041] A first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line 132, one of the source electrode and the drain electrode of the first initialization thin film transistor T4 is connected to the first initialization voltage line 122, and the other of the source electrode and the drain electrode of the first initialization thin film transistor T4 is connected to the electrode of the storage capacitor Cap (e.g., the lower electrode Cap1), the compensation thin film transistor T3, and the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 received through the previous scan line 132, and initializes the voltage of the driving gate electrode G1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0042] The action control gate electrode G5 of the action control thin film transistor T5 is connected to the light emitting control line 121, one of the source electrode and the drain electrode of the action control thin film transistor T5 is connected to the driving voltage line 152, and the other of the source electrode and the drain electrode of the action control thin film transistor T5 is connected to the driving thin film transistor T1 and the switching thin film transistor T2.

[0043] The light emitting control gate electrode G6 of the light emitting control thin film transistor T6 is connected to the light emitting control line 121, one of the source electrode and the drain electrode of the light emitting control thin film transistor T6 is connected to the driving thin film transistor T1 and the compensation thin film transistor T3, and the other of the source electrode and the drain electrode of the light emitting control thin film transistor T6 is electrically connected to the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0044] The action control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line 121 , so that the driving voltage ELVDD is transmitted to the organic light emitting diode OLED and the driving current Id flows through the organic light emitting diode OLED.

[0045] The second initialization gate electrode G7 of the second initialization thin film transistor T7 may be connected to a subsequent scan line 133 connected to another pixel PX disposed in a subsequent row of the current pixel PX. In addition, one of the source electrode and the drain electrode of the second initialization thin film transistor T7 is connected to the pixel electrode of the light emission control thin film transistor T6 and the organic light emitting diode OLED, and the other of the source electrode and the drain electrode of the second initialization thin film transistor T7 is connected to the second initialization voltage line 123.

[0046] In an embodiment, the scan line 131 and the subsequent scan line 133 are electrically connected to each other (not shown), and the scan signal Sn and the subsequent scan signal Sn+1 applied to the scan line 131 and the subsequent scan line 133 may be the same. Therefore, the second initialization thin film transistor T7 may be turned on according to the scan signal Sn received through the subsequent scan line 133 to initialize the pixel electrode of the organic light emitting diode OLED.

[0047] As another example, the first initialization thin film transistor T4 and the second initialization thin film transistor T7 may be connected together to the previous scan line 132 .

[0048] The other electrode (e.g., upper electrode Cap2) of the storage capacitor Cap is connected to the driving voltage line 152, and the counter electrode of the organic light emitting diode OLED is connected to the line supplying the common voltage ELVSS. Therefore, the organic light emitting diode OLED can emit light by receiving the driving current Id from the driving thin film transistor T1, and thus display an image.

[0049] Figure 2 The pixel circuit PC is shown to include seven thin film transistors and one storage capacitor Cap, but the present disclosure according to the present invention is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously changed according to the design of the pixel circuit PC.

[0050] Figure 3 is a layout diagram showing positions of a plurality of thin film transistors and capacitors included in a pixel circuit according to an embodiment, Figures 4 to 8 For each layer Figure 3 A layout diagram of a configuration of a plurality of thin film transistors and capacitors, and Fig. 9 yes Figure 1 A cross-sectional view of a cross section of a portion of a display device.

[0051] In the following, we will refer to Figures 3 to 9 Describe in more detail ( Figure 3 ) Structure of the pixel circuit PC. Fig. 9 To illustrate ( Figure 1 ) shows the structure of the device 10, rather than showing ( Figure 1 ) shows a cross section at a specific location of the device 10. For example, Fig. 9 In the layout diagram ( FIG. 1 ), the pixel electrode 310 and the switch thin film transistor T2 are illustrated as not being directly connected to each other in the vertical direction, but being electrically connected to each other through the first metal wiring layer CM1 and the second metal wiring layer CM2. Figures 3 to 8 ), the pixel electrode 310 and the switching thin film transistor T2 may not overlap in the vertical direction.

[0052] like Figure 3 The arrangement diagram shown in is a layout diagram of one pixel circuit, and pixel circuits having the same / similar configuration may be arranged above, below, left, and right of the one pixel circuit. Figures 4 to 8 Each of shows the arrangement of wiring or semiconductor layers in the same layer, and insulating layers etc. may be arranged in Figures 4 to 8 Between the hierarchical structures shown in .

[0053] refer to Figures 3 to 9 The display device may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an action control thin film transistor T5, a light emitting control thin film transistor T6, a second initialization thin film transistor T7, a storage capacitor Cap and an organic light emitting device (not shown).

[0054] The driving semiconductor layer A1 of the driving thin film transistor T1, the switching semiconductor layer A2 of the switching thin film transistor T2, the compensation semiconductor layer A3 of the compensation thin film transistor T3, the first initialization semiconductor layer A4 of the first initialization thin film transistor T4, the action control semiconductor layer A5 of the action control thin film transistor T5, the light emitting control semiconductor layer A6 of the light emitting control thin film transistor T6, and the second initialization semiconductor layer A7 of the second initialization thin film transistor T7 are arranged on the substrate 100 and may include the same material.

[0055] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer including the above-mentioned polymer resin and an inorganic layer (not shown).

[0056] The buffer layer 110 may be further disposed on the substrate 100. The buffer layer 110 may include an inorganic insulating material. For example, the buffer layer 110 may include silicon oxynitride (SiON), silicon oxide (SiO x ) and silicon nitride (SiN x ) is a single layer or multiple layers of at least one of ).

[0057] The semiconductor layers A1 to A7 may include polycrystalline silicon or amorphous silicon. Alternatively, the semiconductor layers A1 to A7 may include an oxide semiconductor material including an oxide of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and zinc (Zn). In addition, the semiconductor layers A1 to A7 are connected to each other and can be bent into various shapes.

[0058] Each of the semiconductor layers A1 to A7 may include a channel region and a source region and a drain region on both sides of the channel region, respectively. For example, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region may correspond to a source electrode and a drain electrode of a thin film transistor, respectively. Hereinafter, for convenience, the terms "source region" and "drain region" are used instead of a source electrode and a drain electrode.

[0059] The first insulating layer 120 is located on the semiconductor layers A1 to A7. The first insulating layer 120 may be a layer including SiON, SiO x and SiN x A single layer or multiple layers of at least one of the above.

[0060] On the first insulating layer 120, as Figure 5As shown in FIG. 1 , a driving gate electrode G1 of a driving thin film transistor T1, a switching gate electrode G2 of a switching thin film transistor T2, a compensation gate electrode G3 of a compensation thin film transistor T3, a first initialization gate electrode G4 of a first initialization thin film transistor T4, an action control gate electrode G5 of an action control thin film transistor T5, a light emission control gate electrode G6 of a light emission control thin film transistor T6, and a second initialization gate electrode G7 of a second initialization thin film transistor T7 may be provided. The gate electrodes G1 to G7 include molybdenum (Mo), titanium (Ti), etc., and may be formed as a single layer or multiple layers.

[0061] The gate electrodes G1 to G7 may be positioned to overlap the semiconductor layers A1 to A7, respectively. Fig. 9 As shown in , the driving thin film transistor T1 includes a driving semiconductor layer A1 and a driving gate electrode G1 at a position overlapping with the driving semiconductor layer A1, and the switching thin film transistor T2 includes a switching semiconductor layer A2 and a switching gate electrode G2 at a position overlapping with the switching semiconductor layer A2. In this case, the driving semiconductor layer A1 may include a driving channel region C1 overlapping with the driving gate electrode G1, and a driving source region S1 and a driving drain region D1 on both sides of the driving channel region C1, and the switching semiconductor layer A2 may include a switching channel region C2 overlapping with the switching gate electrode G2, and a switching source region S2 and a switching drain region D2 on both sides of the switching channel region C2. This structure may also be the same in the compensation thin film transistor T3, the first initialization thin film transistor T4, the action control thin film transistor T5, the light emission control thin film transistor T6, and the second initialization thin film transistor T7.

[0062] like Figure 4 As shown in , the driving semiconductor layer A1 may be formed by bending, and the storage capacitor Cap may be arranged on the driving thin film transistor T1 to overlap with the driving thin film transistor T1. The driving semiconductor layer A1 has a curved shape and may be longer than each of the other semiconductor layers A2 to A7. For example, the driving semiconductor layer A1 may have a shape such as an omega shape or a letter "S" that is bent multiple times to form a long channel length in a narrow space. Since the driving semiconductor layer A1 is longer, the driving range of the gate voltage applied to the driving gate electrode G1 becomes wider, so that the grayscale of the light emitted from the organic light emitting diode OLED can be more accurately controlled and the display quality can be improved.

[0063] One end of the driving semiconductor layer A1 of the driving thin film transistor T1 is connected to the switching semiconductor layer A2 and the action control semiconductor layer A5 , and the other end of the driving semiconductor layer A1 may be connected to the compensation semiconductor layer A3 and the light emission control semiconductor layer A6 .

[0064] The second insulating layer 130 is located on the gate electrodes G1 to G7 and Figure 5 , Figure 6 and Fig. 9 As shown in , the storage capacitor Cap may include a lower electrode Cap1 and an upper electrode Cap2, wherein the second insulating layer 130 is between the lower electrode Cap1 and the upper electrode Cap2. Here, the driving gate electrode G1 may also serve as the lower electrode Cap1. That is, the driving gate electrode G1 may be formed integrally with the lower electrode Cap1. ( Fig. 9 The second insulating layer 130 of FIG. 1 serves as a dielectric of the storage capacitor Cap, and the storage capacitance may be determined by charges stored in the storage capacitor Cap and a voltage between the electrodes Cap1 and Cap2.

[0065] The lower electrode Cap1 may be an island-shaped electrode, and may include the same material as the switch gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the action control gate electrode G5, the light emission control gate electrode G6, or the second initialization gate electrode G7. The lower electrode Cap1 may be arranged in the same layer as the switch gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the action control gate electrode G5, the light emission control gate electrode G6, or the second initialization gate electrode G7.

[0066] The upper electrode Cap2 may be on the second insulating layer 130. The upper electrode Cap2 is disposed to overlap the entire lower electrode Cap1 in a plan view, and may define a storage opening SOP (see Figure 6 ). The storage opening SOP is provided to overlap with the lower electrode Cap1. The storage opening SOP may have a shape of a single closed curve that passes through the upper electrode Cap2. A single closed curve refers to a closed figure that has the same starting point and end point when a point is drawn on a straight line or a curve (such as a polygon or a circle). The upper electrode Cap2 is connected to the driving voltage line 152 through a contact hole to receive the driving voltage ELVDD ( Figure 2 ).

[0067] The interlayer insulating layer 140 is on the upper electrode Cap2. The interlayer insulating layer 140 may be made of SiON, SiO x and SiN x A single layer or multiple layers of at least one of the above.

[0068] On the interlayer insulating layer 140, as Figure 7 and Fig. 9 As shown in FIG. 1 , a scan line 131, a previous scan line 132, a subsequent scan line 133, a horizontal driving voltage line 134, a node connection line 135, a connection electrode 136, and an intermediate connection layer 137 may be positioned. As described above, wirings separated from each other on the interlayer insulating layer 140 are referred to as a first metal wiring layer CM1. For example, the first metal wiring layer CM1 may include a scan line 131, a previous scan line 132, and an intermediate connection layer 137.

[0069] Each of the scan line 131, the previous scan line 132, and the subsequent scan line 133 is disposed on a different layer from the gate electrodes G1 to G7 of the thin film transistors T1 to T7, and may have a resistance smaller than each resistance of the gate electrodes G1 to G7. That is, the resistivity value of the scan line 131 may be smaller than each resistivity value of the gate electrodes G1 to G7. By doing so, an RC delay phenomenon caused by application of a scan signal may be prevented or minimized.

[0070] For example, the scan line 131, the previous scan line 132, and the subsequent scan line 133 may include a conductive material including Al, copper (Cu), Ti, or Mo, etc., and may be a single layer or a multilayer. For example, the scan line 131, the previous scan line 132, and the subsequent scan line 133 may be formed of a multilayer structure of Ti / Al / Ti or include a multilayer structure of Ti / Al / Ti.

[0071] The scan line 131 can be electrically connected to the gate connection line 124 through the first contact hole CNT1 (see Figure 3 ). Similarly, since the previous scan line 132 and the subsequent scan line 133 are disposed on a layer different from the layer of the gate electrodes G1 to G7 connected thereto, the scan line 131, the previous scan line 132, and the subsequent scan line 133 may be connected to the gate electrodes G1 to G7 through the contact holes.

[0072] The horizontal driving voltage line 134 may extend in the first direction DR1. The horizontal driving voltage line 134 may be connected to the driving voltage line 152 extending in the second direction DR2 through a contact hole. Therefore, the horizontal driving voltage line 134 and the driving voltage line 152 may form a mesh structure. The horizontal driving voltage line 134 may be connected to one of the source electrode and the drain electrode of the action control thin film transistor T5 and the storage capacitor Cap through a contact hole, and thus the action control thin film transistor T5 and the upper electrode Cap2 may receive ( Figure 2 ) driving voltage ELVDD.

[0073] One end of the node connection line 135 is connected to the lower electrode Cap1 through the second contact hole CNT2. The other end of the node connection line 135 may be connected to the compensation semiconductor layer A3 and the first initialization semiconductor layer A4 through the third contact hole CNT3.

[0074] The connection electrode 136 may connect the switching semiconductor layer A2 to the data line 151. One end of the connection electrode 136 may be connected to the switching semiconductor layer A2 through a contact hole, and the other end may be connected to the data line 151 through a contact hole. The connection electrode 136 may be arranged to bypass the area where the switching gate electrode G2 is disposed so as not to overlap with the switching gate electrode G2 in a plane.

[0075] The intermediate connection layer 137 can be connected to the light emitting control semiconductor layer A6 and ( Figure 8 The intermediate connection layer 137 may be electrically connected to the pixel electrode 310 of the organic light emitting device through the auxiliary connection layer 153, as described later below.

[0076] The inorganic protective layer PVX may be disposed on the first metal wiring layer CM1. The inorganic protective layer PVX may be SiN x and SiO x Single or multiple layers. Figure 1 During a manufacturing process of the display device 10 , the inorganic protective layer PVX may prevent the first metal wiring layer CM1 from being damaged during the patterning process of the pixel electrode 310 by preventing the first metal wiring layer CM1 from being exposed to an etchant used when patterning the pixel electrode 310 .

[0077] The first organic film layer 141 may be on the inorganic protective layer PVX. The first organic film layer 141 may include a general polymer such as benzocyclobutene ("BCB"), polyimide ("PI"), hexamethyldisiloxane ("HMDSO"), polymethylmethacrylate ("PMMA"), and polystyrene ("PS"), a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, or a mixture thereof.

[0078] The first organic film layer 141 is not formed on ( Figure 1 Instead of being patterned and formed on only some portions of the substrate 100, such as Fig. 9 As shown in FIG. 1 , the first organic film layer 141 is formed on ( Figure 1 When the first organic film layer 141 is partially formed on the substrate 100, the volume of the first organic film layer 141 is reduced compared to the entire display area DA. Therefore, degassing of organic matter is reduced, and defects such as pixel shrinkage caused by degassing can be prevented and / or reduced. In addition, even when ( Figure 1 When the display device 10 is exposed to sunlight for a long time, the amount of organic matter that may be decomposed by sunlight can also be reduced, and thus, the display device 10 can be improved. Figure 1) displays the reliability of the device 10.

[0079] The data line 151, the driving voltage line 152, and the auxiliary connection layer 153 may be located on the first organic film layer 141, or on the inorganic protective layer PVX exposed between the regions in the patterned first organic film layer 141. In this way, the wiring located on the first organic film layer 141 or on the inorganic protective layer PVX exposed between the regions in the patterned first organic film layer 141 is referred to as the second metal wiring layer CM2. For example, the second metal wiring layer CM2 may include the data line 151, the driving voltage line 152, and the auxiliary connection layer 153 (see Figure 3 ).

[0080] When the first metal wiring layer CM1 and the second metal wiring layer CM2 overlap, the first organic film layer 141 covers the first metal wiring layer CM1 overlapping with the second metal wiring layer CM2. As an example, the data line 151 and the driving voltage line 152 may be arranged on the scan line 131 and may extend in a second direction DR2 intersecting the first direction DR1, wherein the first organic film layer 141 is between the data line 151 and the driving voltage line 152 and the scan line 131. In this case, the first organic film layer 141 may be patterned and arranged at least in an area where the data line 151 overlaps with the scan line 131 and an area where the driving voltage line 152 overlaps with the scan line 131. Therefore, the distance between the first metal wiring layer CM1 and the second metal wiring layer CM2 may be extended to minimize the occurrence of parasitic capacitance. That is, according to the method included in Figure 7 The first organic film layer 141 may be arranged to cover the types of wirings in the first metal wiring layer CM1 shown in FIG. As another example, in order to control the volume of the first organic film layer 141, the first organic film layer 141 may be positioned to overlap some of the wirings included in the first metal wiring layer CM1. As an example, the first organic film layer 141 may be arranged to extend to overlap with scan lines such as the scan line 131, the previous scan line 132, and the subsequent scan line 133, and the horizontal drive voltage line 134.

[0081] The auxiliary connection layer 153 may be connected to the intermediate connection layer 137 through a fifth contact hole CNT5 defined in the first organic film layer 141 .

[0082] The second organic film layer 142 is disposed on the second metal wiring layer CM2, and the pixel electrode 310 may be on the second organic film layer 142. The second organic film layer 142 may include a general polymer such as BCB, PI, HMDSO, PMMA, and PS, a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, or a mixture thereof.

[0083] Different from the first organic film layer 141, the second organic film layer 142 is arranged at ( Figure 1 ) above the entire display area DA. In the area where the inorganic protective layer PVX is exposed and defined by the patterned first organic film layer 141, the second organic film layer 142 directly contacts the inorganic protective layer PVX. That is, between the wirings included in the first metal wiring layer CM1, the second organic film layer 142 contacts the upper surface of the inorganic protective layer PVX, and may have a concave shape (in a top view) at the portion in contact with the upper surface of the inorganic protective layer PVX. In other words, in a position where the first organic film layer 141 is not arranged, the second organic film layer 142 may have a curved shape. Therefore, in order to allow the pixel electrode 310 to be arranged on a flat portion, the first organic film layer 141 may be arranged at a position overlapping with the pixel electrode 310 in a plan view. That is, the first metal wiring layer CM1 may not be arranged below the first organic film layer 141 overlapping with the pixel electrode 310.

[0084] The pixel defining layer 150 may be disposed on the second organic film layer 142 to define an opening for exposing the center of the pixel electrode 310, while the edge of the pixel electrode 310 is covered by the pixel defining layer 150. The pixel defining layer 150 may include an organic insulating material such as PI, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by spin coating.

[0085] The intermediate layer 320 including the emission layer is located in the opening in the pixel defining layer 150. The intermediate layer 320 may include a low molecular weight material or a polymer material. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a single or composite structure by stacking a hole injection layer ("HIL"), a hole transport layer ("HTL"), an emission layer ("EML"), an electron transport layer ("ETL"), and an electron injection layer ("EIL") . The intermediate layer 320 may include various organic substances such as copper phthalocyanine ("CuPc"), N, N'-di(1-naphthyl)-N, N'-biphenyl-benzidine ("NPB"), and tri-8-hydroxyquinoline aluminum ("Alq 3 ”). These layers in the intermediate layer 320 can be formed by a vacuum deposition method.

[0086] When the intermediate layer 320 includes a polymer material, the intermediate layer 320 may have a structure including an HTL and an EML. The HTL may include poly(ethylenedioxythiophene), and the EML may include polymer materials such as polyphenylene vinylene ("PPV") and polyfluorene. However, the intermediate layer 320 according to the present invention is not limited thereto, and may have various structures in another embodiment. For example, at least one of the layers constituting the intermediate layer 320 may be integrally formed above the plurality of pixel electrodes 310. Alternatively, the intermediate layer 320 may include a layer patterned to correspond to each of the plurality of pixel electrodes 310.

[0087] In addition, the common electrode 330 may be disposed at ( Figure 1 ) display area DA, and can be set to cover ( Figure 1 That is, for a plurality of light emitting devices 300, the common electrode 330 may be integrally formed.

[0088] The encapsulation layer 400 for protecting the light emitting device 300 from external moisture or oxygen may be on the common electrode 330. The encapsulation layer 400 has a thickness extending not only to the area where the light emitting device 300 is located ( Figure 1 The display area DA extends to ( Figure 1 () outside the display area DA Figure 1 The encapsulation layer 400 may have a multi-layer structure. For example, Fig. 9 As shown in FIG, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430, which are sequentially stacked.

[0089] The first inorganic encapsulating layer 410 covers the common electrode 330 and may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0090] The organic encapsulation layer 420 covers the first inorganic encapsulation layer 410 and has a sufficient thickness and is Figure 1 The organic encapsulation layer 420 may be substantially flat over the entire display area DA. The organic encapsulation layer 420 may include at least one selected from the group consisting of polyethylene terephthalate ("PET"), polyethylene naphthalate ("PEN"), polycarbonate ("PC"), PI, polyether sulfone ("PES"), polyoxymethylene ("POM"), polyarylate ("PAR"), and HMDSO.

[0091] The second inorganic encapsulating layer 430 covers the organic encapsulating layer 420 and may include silicon oxide, silicon nitride and / or silicon oxynitride. The second inorganic encapsulating layer 430 extends outside the organic encapsulating layer 420 to contact the first inorganic encapsulating layer 410 so that the organic encapsulating layer 420 may not be exposed to the outside.

[0092] In this way, since the encapsulation layer 400 has a multi-layer structure including the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430, even if a crack occurs in the encapsulation layer 400, the crack may not be connected to each other between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. In this way, the entry of external moisture or oxygen can be prevented or minimized ( Figure 1 ) shows the formation of a permeation path in area DA.

[0093] According to an embodiment of the present disclosure, degassing of organic matter can be minimized by reducing the volume of organic matter in the display device. Therefore, even if the display device is exposed to sunlight for a long time, the decomposition of organic matter caused by sunlight can be prevented or minimized, thereby improving the reliability of the display device.

[0094] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: A substrate including a display area and a peripheral area; A thin film transistor disposed on the substrate; a first metal wiring layer electrically connected to the thin film transistor; an inorganic protective layer on the first metal wiring layer; a patterned first organic film layer located on the inorganic protective layer and overlapping the first metal wiring layer in plan view; a second metal wiring layer on the first organic film layer; as well as a second organic film layer on the second metal wiring layer, wherein the first organic film layer is patterned to be disposed at a position where the first metal wiring layer and the second metal wiring layer overlap each other in the plan view, rather than being disposed over the entire display area, The second organic film layer is disposed on the entire display area, and A portion of the second organic film layer contacts an upper surface of the inorganic protective layer.

2. The display device according to claim 1, wherein: The first metal wiring layer includes a plurality of wirings separated from each other.

3. The display device according to claim 2, wherein: The second organic film layer has a concave shape at a position in contact with the upper surface of the inorganic protective layer.

4. The display device according to claim 1, further comprising: a light emitting device electrically connected to the thin film transistor, The light emitting device comprises a pixel electrode, a common electrode and an intermediate layer having an emission layer between the pixel electrode and the common electrode. The pixel electrode is located on the second organic film layer, and The first organic film layer is disposed at a position overlapping with the pixel electrode.

5. The display device according to claim 4, further comprising: An encapsulation layer is located on the common electrode and includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

6. The display device according to claim 1, wherein: The thin film transistor includes a semiconductor layer and a gate electrode. The first metal wiring layer includes a scan line electrically connected to the gate electrode, and The scan line is located in a layer different from a layer where the gate electrode is located.

7. The display device according to claim 6, further comprising: a first insulating layer between the semiconductor layer and the gate electrode and a second insulating layer and an interlayer insulating layer on the gate electrode, The scanning line is located on the interlayer insulating layer. 8 . The display device according to claim 7 , further comprising an upper electrode provided between the second insulating layer and the interlayer insulating layer at a position overlapping the gate electrode in the plan view.

9. The display device according to claim 1, wherein: The second metal wiring layer includes wirings directly on the inorganic protective layer exposed by the patterned first organic film layer.

10. The display device according to claim 1, wherein: The second metal wiring layer includes a data line and a driving voltage line.

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