Switched capacitor analog-to-digital converter and method of operation thereof

Abstract

A switched capacitor analog-to-digital converter (ADC) and a method of operating a switched capacitor ADC are disclosed. The switched capacitor ADC includes a main digital-to-analog converter (DAC) circuit, a comparator coupled to the main DAC circuit and configured to determine whether an input to the comparator exceeds a predetermined threshold, and a supplemental DAC circuit coupled to the main DAC circuit, wherein the switched capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring an offset of the switched capacitor ADC, the supplemental DAC circuit is configured to shift a voltage at an output of the main DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring a full-scale gain error of the switched capacitor ADC, the supplemental DAC circuit is configured to shift the voltage at the output of the main DAC circuit by a second value having a second polarity opposite the first polarity.

Description

Technical Field

[0001] The present invention generally relates to analog-to-digital converters (ADCs), and in certain embodiments, to ADCs having a built-in supplemental digital-to-analog converter (DAC) that shifts the DC conversion curve to facilitate the measurement of the ADC's offset and gain error (e.g., full-scale gain error). Background Technology

[0002] Analog-to-digital converters (ADCs) are widely used in electronic systems to convert analog signals, such as voltage or current, into digital signals for processing in digital systems. Various types of ADCs can be used, such as direct-conversion ADCs, successive approximation ADCs (SAR ADCs), sigma-delta ADCs, etc.

[0003] After manufacturing, the ADC is tested to verify its functionality and whether its parameters are within target specifications. Automated Test Equipment (ATE) is typically used to test ADC devices to reduce testing time. For low-cost ADC devices, testing time is a major factor determining the device's manufacturing cost. To test high-precision ADCs, current ADC testing processes typically require high-precision test equipment and long test / computation times. Summary of the Invention

[0004] According to an embodiment of the present invention, a switched-capacitor analog-to-digital converter (ADC) includes: a primary digital-to-analog converter (DAC) circuit having an output; a comparator having an input coupled to the output of the primary DAC circuit, the comparator being configured to determine whether the input to the comparator exceeds a predetermined threshold; and a supplementary DAC circuit coupled to the primary DAC circuit, wherein the switched-capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring the offset of the switched-capacitor ADC with a zero-voltage input, the supplementary DAC circuit is configured to shift the voltage at the output of the primary DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring the full-scale gain error of the switched-capacitor ADC with a full-scale input voltage, the supplementary DAC circuit is configured to shift the voltage at the output of the primary DAC circuit by a second value having a second polarity opposite to the first polarity.

[0005] According to an embodiment of the present invention, a switched-capacitor analog-to-digital converter (ADC) includes: a primary digital-to-analog converter (DAC) circuit having an output; a comparator coupled to the output of the primary DAC circuit; and a supplementary DAC circuit. The supplementary DAC circuit includes: at least one supplementary capacitor, wherein a first terminal of the at least one supplementary capacitor is coupled to the output of the primary DAC circuit; a first switch coupled between a second terminal of the at least one supplementary capacitor and a first reference voltage terminal of the switched-capacitor ADC; and a second switch coupled between the second terminal of the at least one supplementary capacitor and a second reference voltage terminal of the switched-capacitor ADC.

[0006] According to an embodiment of the present invention, a method of operating a switched-capacitor analog-to-digital converter (ADC) includes at least one of the following: shifting the DC conversion curve of the switched-capacitor ADC by a predetermined value along a first direction during a period when the offset of the switched-capacitor ADC is measured with zero input voltage; and shifting the DC conversion curve of the switched-capacitor ADC by a predetermined value along a second direction opposite to the first direction during a period when the full-scale gain error of the switched-capacitor ADC is measured with a full-scale voltage input. Attached Figure Description

[0007] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 Three DC conversion curves are shown in the implementation scheme;

[0009] Figure 2A This is a block diagram of the ADC in the implementation method;

[0010] Figure 2B It is in the implementation method Figure 2A Detailed block diagram of the ADC in the diagram;

[0011] Figure 3A and Figure 3B The embodiments are shown respectively. Figure 2B The sampling and conversion phases of the ADC in normal operating mode;

[0012] Figure 4A and Figure 4B The embodiments are shown respectively. Figure 2B The ADC's modified zero-crossing mode sampling and conversion phases;

[0013] Figure 5A and Figure 5B The embodiments are shown respectively. Figure 2B The modification of the ADC involves the sampling and conversion stages of the full-scale mode;

[0014] Figure 6 A reconfigurable capacitor is shown in the embodiment; and

[0015] Figure 7 A flowchart illustrating the method for operating the ADC device in this embodiment is shown. Detailed Implementation

[0016] The implementation and use of the currently disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of particular ways of implementing and using the invention and do not limit the scope of the invention.

[0017] The invention will be described in a specific context relative to an exemplary embodiment, namely an ADC with built-in supplementary DAC circuitry that shifts the DC conversion curve up and down, respectively, to facilitate simple and rapid measurement of the ADC's offset and full-scale gain error.

[0018] In an embodiment of the invention, the ADC includes: a main DAC circuit, a comparator coupled to the output of the main DAC circuit, and a supplementary DAC circuit coupled to the main DAC circuit. In normal operating mode, the supplementary DAC circuit is disabled. During the measurement of the ADC's offset with a zero-voltage input, the supplementary DAC circuit is activated to shift the ADC's DC conversion curve upward by a predetermined value, thereby providing margin for both negative and positive offsets to be measured with a zero-voltage input. During the measurement of the ADC's full-scale gain error with a full-scale input, the supplementary DAC circuit is activated to shift the ADC's DC conversion curve downward by a predetermined value, thereby providing margin for both negative and positive offsets to be measured with a full-scale input voltage.

[0019] Linear ramp testing is commonly used to measure the full-scale gain error and offset of an ADC (also known as an ADC device). In linear ramp testing, an automated test equipment (ATE) is used to generate a high-precision ramp signal. Typically, additional hardware is mounted on the ATE to provide an accurate analog source to generate the high-precision ramp signal. The ramp signal is applied to the input of the ADC, and the digital result from the ADC is stored in a histogram. Mathematical post-processing of the histogram can provide various ADC parameters such as integral nonlinearity (INL), differential nonlinearity (DNL), full-scale gain error, and offset.

[0020] While an ideal ramp signal is a linear signal (e.g., a sloping line), in practice, a ramp signal generated by a test device can be a step function (e.g., a step along a sloping line), where each step has a height below the LSB (e.g., a voltage level). Throughout this discussion, when used to represent voltage levels, LSB refers to the analog voltage level corresponding to the LSB of the ADC output. For example, for a 12-bit ADC and a full-scale input voltage V... AREF (For example, to generate a full-scale ADC output voltage of 4095), the LSB voltage can be calculated as Varef / 4096.

[0021] Due to non-ideal ramp signals (e.g., step functions), linear ramp testing requires several transitions for each ramp step to achieve noise suppression, resulting in longer test times. For example, for a 10-bit ADC with a step size of 1 / 4 LSB, if each step involves 30 transitions, 1024 x 4 x 30 transitions would be required, which not only results in long measurement times but also necessitates high-precision analog source instruments on the ATE (Automatic Test Equipment). This disclosure discloses an ADC that allows for simple and rapid measurement of the ADC's full-scale gain error and offset without the need for high-precision test equipment. Details are discussed below.

[0022] Figure 1 Three DC conversion curves from the implementation method are shown. Figure 1 Curve 20 in the figure shows an ideal DC conversion curve, illustrating the ideal relationship between the ADC's input analog voltage (in LSB volts) and its output. The ADC's output is a multi-bit digital output (e.g., a 12-bit output for a 12-bit ADC), also referred to as the ADC output code or ADC output code. Figure 1 As shown, curve 20 is a linear line that means an input voltage of zero will result in an ADC output code of zero, an input voltage of 1 LSB volt will result in an ADC output code of 1, and so on.

[0023] An ADC's offset (also known as offset error) and full-scale gain error can be measured as zero-crossing and full-scale (FS) points, respectively. To measure ADC offset, a zero-volt input voltage (e.g., electrical ground) is applied to the ADC input; the ADC output (e.g., a non-zero value) is the ADC offset. To measure ADC full-scale gain error, a positive reference voltage (e.g., a full-scale input voltage such as a positive supply voltage) is applied to the ADC input; the difference between the ADC output and the full-scale ADC output code (e.g., the maximum ADC output) is the ADC full-scale gain error. However, for a zero-volt input, if the offset is negative, ADC underflow occurs. Similarly, with a full-scale input voltage, if the offset is positive, ADC overflow occurs. Calculations of full-scale gain error and offset based on measurements that cause ADC underflow or overflow may be inaccurate.

[0024] For the reasons described above, without this disclosure, the ADC testing process might have to extrapolate to obtain the ADC's offset and full-scale gain error. For example, the ADC testing process might measure the ADC output at many different input voltage levels between zero-volt and full-scale inputs and use these measurements to plot a local DC conversion curve (e.g., a curve without data points at zero-volt and full-scale inputs). The local DC conversion curve is then extrapolated (e.g., by linear extrapolation) to obtain estimates of the ADC's offset and full-scale gain error.

[0025] This disclosure enables the direct measurement of ADC offset (or full-scale gain error) via a single measurement at zero-volt input (or full-scale input voltage). Specifically, when measuring ADC offset, an upward shift of the ADC's DC conversion curve is introduced to shift the zero-crossing point along the y-axis (see [link to documentation]). Figure 1 The curve 10 in the figure can be a point with both positive and negative offsets. In other words, an artificial offset is introduced to allow measurements to be taken within a window near zero input voltage. Figure 1 Curve 10 in the diagram illustrates an example of a modified DC conversion curve for the ADC. For offset measurements, the DC conversion curve is shifted upwards, for example, by +16. In other words, sampling a zero-volt input voltage (e.g., electrically ground) will result in an ideal +16 volt ADC output code. The deviation of the ADC output relative to the code (e.g., +16) directly gives the ADC's offset. In the discussion herein, the aforementioned offset measurement mode (e.g., the DC conversion curve with a shift) may also be referred to as a modified zero-crossing mode or a modified zero-crossing operating mode.

[0026] Similarly, to measure the full-scale gain error of the ADC, the DC conversion curve is shifted downwards to have a negative zero-crossing point along the y-axis (see [link to relevant documentation]). Figure 1 (Curve 30 in the text). Figure 1 Curve 30 in the diagram illustrates an example of a down-shifted DC conversion curve, where the DC conversion curve is shifted down, for example, by +16. For example, using a down-shifted DC conversion curve, an ideal 12-bit ADC would convert a reference voltage (e.g., the full-scale input voltage) into an ADC output code of 4079. The deviation of the ADC output from this code (e.g., 4079) directly gives the full-scale gain error. Those skilled in the art will readily understand that the shift value of 16 in the above discussion is used as a non-limiting example of the amount of shift in a DC conversion curve. Other suitable values ​​are also possible and are fully intended to be included within the scope of this disclosure. In the discussion herein, the above-described full-scale gain error measurement mode (e.g., with a shifted DC conversion curve) may also be referred to as a modified over-full-scale mode or a modified over-full-scale operating mode.

[0027] Figure 2A This is a block diagram of the ADC 100 in the implementation. The ADC 100 is configured to shift the DC conversion curve up and down to measure the ADC offset and full-scale gain error, respectively. Figure 2B It is in the implementation method Figure 2A Detailed diagram of the ADC 100. (Refer to...) Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B This section discusses the various operating modes of the ADC 100. For simplicity, in... Figure 2B Not all features of the ADC 100 are shown in the diagram.

[0028] Reference Figure 2AADC 100 is a switched-capacitor ADC and includes ADC circuitry 104 (e.g., a successive approximation register (SAR) circuit), comparator 101, main digital-to-analog converter (DAC) circuitry 150, and supplementary DAC circuitry 140. Main DAC circuitry 150 is electrically coupled to supplementary DAC 140. Comparator 101 has an input coupled to output 125 of main DAC circuitry 150 and an output coupled to ADC circuitry 104. Comparator 101 is configured to determine whether an input to comparator 101 exceeds a threshold voltage of comparator 101. ADC circuitry 104 can control the operation of main DAC circuitry 150 via signal path 113. ADC 100 can be configured to operate in either a first mode or a second mode. In the first mode, used for measuring the offset of ADC 100 with a zero-voltage input, supplementary DAC circuit 140 is configured to shift the voltage at output 125 of main DAC circuit 150 by a first value of a first polarity. In the second mode, used for measuring the full-scale gain error of ADC 100 with a full-scale input voltage, supplementary DAC circuit 150 is configured to shift the voltage at output 125 of main DAC circuit 150 by a second value of a second polarity opposite to the first polarity. Details of ADC 100 are discussed below.

[0029] Now refer to Figure 2B It is the implementation method Figure 2A A detailed block diagram of ADC 100 is provided. In the illustrated embodiment, ADC 100 is a switched-capacitor ADC. Figure 2B In the examples, a successive approximation (SAR) ADC is used as an example of a switched capacitor ADC, but it should be understood that a switched capacitor ADC can be other types of ADCs, such as a flash ADC, a pipelined ADC, or a tracking ADC. Figure 2B Using a SAR ADC as a non-limiting example, those skilled in the art, upon reading this disclosure, will be able to readily apply the principles disclosed herein to other types of ADCs.

[0030] exist Figure 2B In this circuit, ADC 100 includes a successive approximation register (SAR) circuit 104, a comparator 101, a main digital-to-analog converter (DAC) circuit 150, and a supplementary DAC circuit 140. The supplementary DAC circuit 140 and the main DAC circuit 150 are respectively located in... Figure 2B Above and below the dashed line 130 in the diagram. For ease of discussion and without loss of generality, the following discussion uses ADC 100 as an example of a 12-bit ADC. Those skilled in the art, upon reading this disclosure, will be able to readily apply the principles disclosed herein to ADCs with any number of output bits.

[0031] exist Figure 2B In this circuit, SAR circuit 104 includes a successive approximation register (SAR) 103, a switch control circuit 106, and a logic circuit 105 (e.g., a state machine). SAR 103 stores the ADC output code at the completion of analog-to-digital conversion and intermediate ADC output codes during the successive approximation process. Logic circuit 105 generates a series of ADC output codes based on the output of comparator 101, which are sequentially stored in SAR 103 during the successive approximation process. Logic circuit 105 can control the operation of SAR 103 via signal path 111. Switch control circuit 106 generates control signals (e.g., on signal path 108) configured to control various switches of ADC 100 (e.g., ...). Figure 2B The switches in the pair SC1A / SC1B, ..., SC1A / SC1B are excluded. 11 A / SC 12 The state (e.g., open or closed) of the switch other than B. In some embodiments, the switch control circuit 106 may be implemented as part of the logic circuit 105. Each bit of the ADC output code stored in SAR 103 is used to control the state (e.g., open or closed) of the corresponding pair of switches during the successive approximation process, which will be discussed in detail below. Figure 2B Further shown are a master latch signal (e.g., a clock signal) 109 and a steering signal 107, wherein the steering signal 107 can send the contents of SAR 103 to the master DAC circuit 150.

[0032] The main DAC circuit 150 includes capacitors C1, C2, ... and C N An array of , where N is the number of bits in the ADC output code. Figure 2B In the example, a 12-bit ADC is used, so N = 12, and capacitors C1, C2, ... and C N It is binary weighted (also known as binary encoding). Here, binary weighting refers to the capacitor C. n The capacitance is 2 n-1 ×C, where n = 1, 2, ..., N, and C is a predetermined capacitance value. For a 12-bit ADC, capacitors C1, C2, ..., C... 12 The capacitors have the following capacitances: C1 = C, C2 = 2 × C, ..., C 12 =2 11 xC. Binary-encoded capacitors are used as such Figure 2B The capacitors C1, C2, ... and C in N Non-limiting examples. Other suitable capacitors, such as redundancy-coded or thermometer-coded capacitors, can also be used as capacitors C1, C2, ... and C. NAs will readily apparent to those skilled in the art, the following discussion uses a binary-coded capacitor as an example.

[0033] like Figure 2B As shown, each capacitor C in the array of binary weighted capacitors n The first terminal (e.g., Figure 2B The right-hand terminal of the binary weighted capacitor array is coupled to the output node 125 (also referred to as the output) of the main DAC circuit 150. Each capacitor C in the array of binary weighted capacitors... n The second terminal (e.g., Figure 2B The left terminal of the circuit is coupled to a pair of switches SC. nA and SC nB Where n = 1, 2, ..., N. For ease of description, switch SC nA and SC nB The pair can be referred to as a paired switch. As will be discussed in more detail below, in different operating phases of the ADC 100 (e.g., the sampling phase or the conversion phase), the switch SC... nA and SC nB Each of them can be open or closed to connect each capacitor C. n Electrically coupled to the input voltage terminal Vin and the first reference voltage terminal V AREF Or the second reference voltage terminal V AGND In the illustrated embodiment, the first reference voltage terminal V AREF Configured to connect to the full-scale input voltage, the second reference voltage terminal V AGND It is configured to be connected to electrical ground. In some implementations, the first reference voltage terminal V AREF It is configured to be connected to a positive reference voltage, and the second reference voltage terminal V AGND It is configured to be connected to a negative reference voltage. During the conversion phase of ADC operation, each pair of switches (e.g., via signal path 113 coupled to input 114 of main DAC circuit 150) is controlled by the corresponding bit in the ADC code stored in SAR 103, details of which are discussed below.

[0034] like Figure 2B As shown, each switch SC nA The first terminal (e.g., Figure 2B The right-side terminal of the circuit is electrically coupled to capacitor Cn, n = 1, 2, ..., N, and each switch SC nA The second terminal (e.g., Figure 2B The left terminal of the circuit is electrically coupled to node 121, which is electrically coupled to switch S. 1A And switch S2. Depends on switch S. 1ABased on the state of S2 (e.g., open or closed), node 121 can be connected to the input voltage terminal V at different operating stages. IN Or the first reference voltage terminal V AREF .

[0035] Still refer to Figure 2B Each switch SC nB The first terminal (e.g., Figure 2B The right-side terminal is electrically coupled to capacitor C. n And each switch SC nB Second terminal (e.g., Figure 2B The left terminal of the circuit is electrically coupled to node 123, which is electrically connected to switch S. 1B And switch S3. Depends on switch S. 1B Based on the state of S3 (e.g., open or closed), node 123 can be connected to the input voltage terminal V at different operating stages. IN Or the second reference voltage terminal V AGND .

[0036] The main DAC circuit 150 also includes a switch S4. Switch S4 is closed during the sampling phase of ADC 100 operation and open during the conversion phase of ADC 100 operation. The first terminal (e.g., Figure 2B The lower terminal of the middle terminal is electrically coupled to the output terminal 125, and the second terminal (e.g., Figure 2B The upper terminal of the middle is electrically coupled to the low bias voltage terminal V. cm Low bias voltage terminal V cm It is configured to be coupled to a low bias voltage, which is selected to set comparator 101 to appropriate bias conditions. The bias voltage can be selected, for example, based on the supply voltage of comparator 101 and the type of transistor used. In some embodiments, a common voltage is generated to be used as the bias voltage.

[0037] The supplementary DAC circuit 140 includes a supplementary capacitor CS and a switch S. 5A and S 5B A pair of switches. Depends on switch S. 5A and S 5B In different operating phases (e.g., open or closed), the supplementary capacitor CS can be connected to the first reference voltage terminal V. AREF Or the second reference voltage terminal V AGNDIn the illustrated embodiment, the capacitance of the supplementary capacitor CS determines the amount of upward or downward shift of the DC conversion curves 10 and 30. To shift the DC conversion curve upward (or downward) by M, the capacitance of the supplementary capacitor CS is chosen to be M×C. For example, for an upward or downward shift of 16 in the DC conversion curve, the capacitance of the supplementary capacitor CS is chosen to be 16C. Although the supplementary capacitor CS in Figure 2B The block diagram shows a single capacitor, but for implementation in the circuit, the supplementary capacitor CS can be implemented as multiple capacitors (see reference below for example). Figure 6 (Discussion). In some implementations, the supplementary DAC circuit 140 includes more than one capacitor.

[0038] The supplementary DAC circuit 140 is constructed from capacitors of the same type as those in the main DAC circuit 150, and therefore can achieve the same accuracy as the main DAC circuit 150. This supplementary DAC circuit 140 is very small (e.g., a single capacitor and a few switches) and can also be used for other purposes during measurement, such as window tracking of DC signals.

[0039] Comparator 101 is coupled between the output 125 of the main DAC circuit 150 and the SAR circuit 104. In the illustrated embodiment, comparator 101 compares the voltage at the output 125 of the main DAC circuit with a threshold voltage of comparator 101, where the threshold voltage may be a trip point of comparator 101 set during the sampling phase of operation of ADC 100. During the conversion phase of operation, the output of comparator 101 is sent to SAR circuit 104, which, as discussed below, determines whether the current ADC bit should be set to zero or one based on the output of comparator 101.

[0040] The following reference Figure 3A and Figure 3B Let's discuss the operation of ADC 100 in normal mode (also known as normal operating mode). In normal mode, ADC 100 is configured to convert the input voltage terminal V... IN The analog input voltage is converted (or measured) into a digital output code (e.g., a 12-bit ADC output). See reference... Figure 4A , Figure 4B , Figure 5A and Figure 5B Other operating modes are discussed (e.g., for measuring offset and full-scale gain error).

[0041] Figure 3A and Figure 3B The sampling and conversion phases of the ADC 100 in the implementation embodiment during normal operation are shown respectively. During normal operation, switch S... 5AKeep it off, and switch S 5B Keep it closed, thereby grounding the supplementary capacitor CS and disabling the supplementary DAC circuit 140. Note that in the illustrated embodiment, when the supplementary DAC circuit 140 is disabled in normal mode, its function is bypassed, and switch S is closed in normal mode. 5A and S 5B No switching occurs, but the supplementary DAC circuit 140 remains connected to the main DAC circuit 150. Those skilled in the art will readily understand that during operation, the switched-capacitor ADC (e.g., a successive approximation ADC) functions in two phases: first, the sampling phase, and then the conversion phase. Details of the different phases are discussed below.

[0042] Figure 3A The sampling phase of the ADC 100 in normal operating mode in this embodiment is shown. Figure 3A During the sampling phase, switches S4 and S 1A S 1B SC 1A SC 1B SC 2A SC 2B , ..., SC 12A and SC 12B When closed, switches S2 and S3 are open. As a result, the binary weighted capacitors (e.g., C1, C2, ..., C...)... 12 The array is coupled to the input voltage V. IN They are charged, and each capacitor now holds a charge equal to its capacitance multiplied by the input voltage V. IN Subtract the low bias voltage V cm .

[0043] Next, in Figure 3B In the middle, ADC 100 enters the conversion stage, where SAR circuit 104 searches for each bit of the ADC output code during successive approximation. During the conversion stage, switches S4 and S... 1A and S 1B The circuit is open, while switches S2 and S3 are closed. Paired switches (e.g., SC) 1A SC 1B SC 2A SC 2B ..., SC 12A and SC 12B The state of the array (e.g., open or closed) is controlled by the ADC output code stored in the SAR 103 during successive approximation. Note that each capacitor in the array of binary weighted capacitors corresponds to a corresponding bit in the ADC output code, with the smallest capacitor C1 corresponding to the LSB of the ADC output code, and the largest capacitor (e.g., C...). 12This corresponds to the MSB of the ADC output code. Figure 3B The state of the switch during the test of the MSB bit is shown.

[0044] During the conversion phase, firstly, SAR circuit 104 determines the MSB bit (e.g., bit 12). This is done by closing switch SC. 12A And disconnect switch SC 12B The MSB capacitor (e.g., C12) is coupled to the first reference voltage V. AREF (For example, full-scale input voltage). By disconnecting switch SC nA and closed switch SC nB The other capacitors (C1, C2, ..., C11) in the binary weighted capacitor array are coupled to the second reference voltage V. AGND (For example, electrically), where n = 1, 2, ..., 11. Note that switch S4 is open during the switching phase.

[0045] Due to the binary weighting of the array of binary-weighted capacitors, the MSB capacitor C12 forms a 1:1 charge distributor with the rest of the array. Therefore, the input voltage to comparator 101 (e.g., the voltage at the output 125 of the main DAC circuit) and (V... AREF / 2)-V IN Proportional. In other words, the main DAC circuit 150 generates a voltage at output 125 that is proportional to the first voltage (e.g., V). AREF / 2) and input voltage V IN The voltage difference is proportional to the voltage, where the first voltage corresponds to the voltage of the current ADC output code (e.g., 100...0 in binary format) stored in SAR 103. If V IN If the value is greater than VREF / 2, comparator 101 outputs zero, and SAR circuit 104 sets the MSB of the ADC output code to bit 1; otherwise, SAR circuit 104 sets the MSB of the ADC output code to bit 0. Once the MSB bit is determined, switch SC... 12A and SC 12B It is set accordingly. For example, for the MSB with digital bit 1, switch SC... 12A Close, and switch SC 12B Disconnect. For MSB with digital bit 0, switch SC 12A and SC 12B The state is flipped to the opposite state.

[0046] After determining the MSB bit, SAR circuit 104 determines the next bit (e.g., bit 11), performing similar processing on the MSB bit. Each capacitor in the array of binary weighted capacitors is tested in the same manner until the comparator input voltage converges to zero, or at least as close to zero as possible for a given DAC resolution. The ADC output code stored in SAR 103 after the LSB is determined as the final ADC output code.

[0047] Figure 4A and Figure 4B The sampling and conversion phases of the modified zero-crossing mode of the ADC 100 in the embodiment are shown respectively. The modified zero-crossing mode is used to measure the offset of the ADC 100, and therefore can also be called the offset measurement mode.

[0048] Figure 4A The modified zero-crossing mode sampling phase of the ADC 100 is shown. Figure 3A During the sampling phase of the normal working mode, Figure 4A The main DAC circuit 150 operates in the same manner as the main DAC circuit. The supplementary DAC circuit 140 is now activated. Specifically, switch S... 5A Close, and switch S 5B Disconnecting the capacitor CS, thereby coupling the supplementary capacitor CS to the first reference voltage V. AREF (For example, the full-scale input voltage). As a result, the supplementary capacitor CS is charged during the sampling phase.

[0049] Next, in Figure 4B In the middle, the ADC 100 enters the conversion phase of the modified zero-crossing mode of the ADC 100. Figure 4B The main DAC circuit in the middle is connected with Figure 3B The main DAC circuit operates in the same way during the normal operating mode transition phase. Figure 4B During the transition phase, switch S 5A Disconnect, and switch S 5B The circuit is closed. As a result, the supplementary capacitor CS injects charge into the capacitors C1, C2, ..., C11 of the binary weighted capacitor array. As a result, the voltage at the output of the capacitor is shifted (e.g., reduced), which effectively shifts the DC conversion curve upward. The amount of voltage shift is determined by the capacitance of the supplementary capacitor CS. As mentioned above, if the capacitance of the supplementary capacitor CS is, for example, 16C (which is the capacitance of capacitor C5), the DC conversion curve is shifted upward by 16. The target shift amount in the DC conversion curve is achieved by changing the capacitance of the supplementary capacitor CS.

[0050] Figure 5A and Figure 5BThe sampling and conversion phases of the modified full-scale overrange mode of the ADC 100 in this embodiment are shown respectively. The modified full-scale overrange mode is used to measure the full-scale gain error of the ADC 100, and therefore can also be called the full-scale gain error measurement mode. The modified full-scale overrange mode and the modified zero-crossing mode can be collectively referred to as the test modes of the ADC 100.

[0051] Figure 5A The sampling phase of the modified full-scale mode of the ADC 100 is shown. Figure 5A The main DAC circuit in the middle is connected with Figure 3A The main DAC circuit operates in the same manner as during the sampling phase of normal operation mode. The supplementary DAC circuit is now activated. Specifically, switch S5A is open and switch S5B is closed, thereby coupling the supplementary capacitor CS to the second reference voltage VAGND (e.g., electrical ground) during the sampling phase.

[0052] Next, in Figure 5B In the middle, the ADC 100 enters the conversion stage of the modified full-scale mode of the ADC 100. Figure 5B The main DAC circuit in the middle is connected with Figure 3B The main DAC circuit operates in the same way during the normal operating mode transition phase. Figure 5B During the conversion phase, switch S5A is closed and switch S5B is open. As a result, the supplementary capacitor CS is coupled in parallel with the MSB capacitor C12 (during the testing of the MSB capacitor C12), causing a redistribution of charge in the capacitors of the array. Consequently, the voltage at the output 125 of the main DAC circuit is shifted (e.g., increased), which effectively shifts the DC conversion curve downward. The amount of voltage shift is determined by the capacitance of the supplementary capacitor CS. As mentioned above, if the capacitance of the supplementary capacitor CS is, for example, 16C (which is the capacitance of capacitor C5), the DC conversion curve shifts downward by 16. The target shift in the DC conversion curve is achieved by changing the capacitance of the supplementary capacitor CS.

[0053] Figure 6 A capacitor 200 is shown in the embodiment. The capacitor 200 includes multiple capacitors, such as C, with different capacitance values. A C B and C C and the switch S connected to the capacitor A S B and S C By changing switch S A S B and S CThe state (e.g., open or closed) can change the equivalent capacitance of capacitor 200 between terminals 201 and 203 to different values. Therefore, capacitor 200 is an adjustable capacitor or a reconfigurable capacitor. Capacitor 200 can be used as... Figure 2B The supplementary capacitor CS will allow the shift in the DC conversion curve to be adjusted or reconfigured. Figure 6 The number of capacitors described is merely a non-limiting example; other numbers are possible and are intended to be included within the scope of this disclosure.

[0054] Figure 7 A flowchart illustrating the method for operating a successive approximation ADC device in this embodiment is shown. It should be understood that... Figure 7 The illustrated implementation methods are merely examples of many possible implementation methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, or repetitions may be made. Figure 7 The steps shown.

[0055] Reference Figure 7 In step 1001, during the measurement of the offset of the switched capacitor ADC with a zero voltage input, the DC conversion curve of the switched capacitor ADC is shifted by a predetermined value along a first direction. In step 1002, during the measurement of the full-scale gain error of the switched capacitor ADC with a full-scale voltage input, the DC conversion curve of the switched capacitor ADC is shifted by a predetermined value along a second direction opposite to the first direction.

[0056] The implementation offers various advantages. For example, the disclosed ADC with built-in supplemental DAC circuitry allows for direct measurement of the ADC offset (or full-scale gain error) in a single measurement, providing a simple and rapid measurement not available with previous methods. Furthermore, since the electrical ground voltage and full-scale reference voltage are readily available on the board to which the ADC device is attached, a high-precision analog voltage source is not required to perform offset and full-scale gain error measurements. This simplifies test setup and requirements, and reduces test costs. The ability to rapidly measure ADC offset and full-scale gain error using on-board voltage (e.g., on the board without requiring an additional high-precision analog source for testing) provides a quick way to identify ADC devices that are not functioning in the field (e.g., damaged), enabling rapid repair or replacement. Moreover, the disclosed structure and method, according to the discharge method disclosed in U.S. Patent No. 9,787,291B1, can be used with a simple ATE to measure the integral nonlinearity (INL) and differential nonlinearity (DNL) of a high-precision ADC.

[0057] Exemplary embodiments of the invention are summarized herein. Other embodiments may be understood from the entire specification and claims herein.

[0058] Example 1. In one embodiment, a switched-capacitor analog-to-digital converter (ADC) includes: a primary digital-to-analog converter (DAC) circuit having an output; a comparator having an input coupled to the output of the primary DAC circuit, the comparator being configured to determine whether an input to the comparator exceeds a predetermined threshold; and a supplementary DAC circuit coupled to the primary DAC circuit, wherein the switched-capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring the offset of the switched-capacitor ADC with a zero-voltage input, the supplementary DAC circuit is configured to shift a voltage at the output of the primary DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring the full-scale gain error of the switched-capacitor ADC with a full-scale input voltage, the supplementary DAC circuit is configured to shift a voltage at the output of the primary DAC circuit by a second value having a second polarity opposite to the first polarity.

[0059] Example 2. A switched-capacitor ADC according to Example 1, wherein the supplementary DAC circuit is configured to be disabled in normal operating mode for measuring the input voltage of the switched-capacitor ADC.

[0060] Example 3. A switched capacitor ADC based on Example 1, wherein the magnitude of the first value is the same as the magnitude of the second value.

[0061] Example 4. A switched-capacitor ADC according to Example 1, wherein the supplementary DAC circuit includes at least one supplementary capacitor.

[0062] Example 5. A switched capacitor ADC according to Example 4, wherein the main DAC circuit includes at least one capacitor, and wherein the capacitance of at least one supplementary capacitor is equal to the capacitance of at least one capacitor of the main DAC circuit.

[0063] Example 6. A switched capacitor ADC according to Example 4, wherein the capacitance of at least one supplementary capacitor is reconfigurable.

[0064] Example 7. A switched capacitor ADC according to Example 4, wherein a first terminal of at least one supplementary capacitor is coupled to the output of the main DAC circuit, and a second terminal of at least one supplementary capacitor is coupled to a first node, wherein the switched capacitor ADC further includes: a first switch between the first node and a first reference voltage input terminal of the switched capacitor ADC; and a second switch between the first node and a second reference voltage input terminal of the switched capacitor ADC.

[0065] Example 8. The switched capacitor ADC according to Example 7, wherein a first reference voltage input terminal is configured to be coupled to a positive reference voltage of the switched capacitor ADC, and a second reference voltage input terminal is configured to be coupled to an electrical ground voltage or to a negative reference voltage of the switched capacitor ADC.

[0066] Example 9. A switched capacitor ADC according to Example 7, wherein during normal operation mode in which the input voltage of the switched capacitor ADC is converted into an output code, a first switch is configured to remain open and a second switch is configured to remain closed.

[0067] Example 10. A switched-capacitor ADC according to Example 1, wherein the switched-capacitor ADC is a successive approximation ADC, wherein the main DAC circuit includes an array of capacitors, wherein each capacitor corresponds to a corresponding bit in the output code of the successive approximation ADC, and wherein the nth capacitor in the array of capacitors is 2. (n-1) ×C, where n=1,2,...,N, where N is the total number of bits in the output code of the successive approximation ADC, and C is a predetermined capacitance value.

[0068] Example 11. A switched capacitor ADC according to Example 1, wherein the switched capacitor ADC is configured to determine at least one of the offset or full-scale gain error of the switched capacitor ADC based on a first reference voltage received at a first reference voltage input terminal and a second reference voltage received at a second reference voltage input terminal.

[0069] Example 12. A switched capacitor ADC according to Example 1, wherein the switched capacitor ADC is configured to determine at least one of offset or full-scale gain error during at least one of a test mode or a normal operation mode.

[0070] Example 13. A switched-capacitor analog-to-digital converter (ADC) includes: a primary digital-to-analog converter (DAC) circuit having an output; a comparator coupled to the output of the primary DAC circuit; and a supplementary DAC circuit. The supplementary DAC circuit includes: at least one supplementary capacitor, wherein a first terminal of the at least one supplementary capacitor is coupled to the output of the primary DAC circuit; a first switch coupled between a second terminal of the at least one supplementary capacitor and a first reference voltage terminal of the switched-capacitor ADC; and a second switch coupled between the second terminal of the at least one supplementary capacitor and a second reference voltage terminal of the switched-capacitor ADC.

[0071] Example 14. A switched capacitor ADC according to Example 13, wherein a first reference voltage terminal is configured to be coupled to a positive reference voltage of the switched capacitor ADC, and a second reference voltage terminal is configured to be coupled to an electrical ground voltage or to a negative reference voltage of the switched capacitor ADC.

[0072] Example 15. A switched-capacitor ADC according to Example 13, wherein the switched-capacitor ADC is a successive approximation ADC, wherein the main DAC circuit includes: an array of capacitors, wherein a first terminal of each capacitor in the array of capacitors is coupled to the output of the main DAC circuit, wherein a second terminal of each capacitor in the array of capacitors is configured to be coupled to an input voltage terminal of the successive approximation ADC, a first reference voltage terminal of the successive approximation ADC, or a second reference voltage terminal of the successive approximation ADC at different stages of operation of the successive approximation ADC; and an array of paired switches, wherein each pair of switches in the array of paired switches includes a first switch and a second switch, the first terminal of the first switch of the paired switch and the first terminal of the second switch of the paired switch are coupled to the second terminal of a corresponding capacitor in the array of capacitors, the second terminal of the first switch of the paired switch is coupled to a first node, and the second terminal of the second switch of the paired switch is coupled to a second node.

[0073] Example 16. The switched capacitor ADC of Example 15, wherein the main DAC circuit further includes: a third switch coupled between the first node and the input voltage terminal; a fourth switch coupled between the second node and the input voltage terminal; a fifth switch coupled between the first node and the first reference voltage terminal; and a sixth switch coupled between the second node and the second reference voltage terminal.

[0074] Example 17. The switched capacitor ADC according to Example 16, wherein the main DAC circuit further includes a seventh switch coupled between the output of the main DAC circuit and the low bias voltage terminal of the switched capacitor ADC.

[0075] Example 18. A method of operating a switched-capacitor analog-to-digital converter (ADC), the method comprising at least one of: shifting the DC conversion curve of the switched-capacitor ADC by a predetermined value along a first direction during a period of measuring the offset of the switched-capacitor ADC with a zero-voltage input; and shifting the DC conversion curve of the switched-capacitor ADC by a predetermined value along a second direction opposite to the first direction during a period of measuring the full-scale gain error of the switched-capacitor ADC with a full-scale voltage input.

[0076] Example 19. According to the method of Example 18, wherein shifting the DC conversion curve along the first direction includes: during the sampling phase of the switched-capacitor ADC: connecting a first terminal of the array of capacitors of the main digital-to-analog converter (DAC) circuit of the switched-capacitor ADC to an input voltage terminal and connecting a second terminal of the array of capacitors to a low bias voltage terminal; and connecting a first terminal of a supplementary capacitor of the supplementary DAC circuit of the switched-capacitor ADC to a first reference voltage terminal and connecting a second terminal of the supplementary capacitor to a low bias voltage terminal; and during the conversion phase of the switched-capacitor ADC: based on a corresponding bit in the ADC output code generated by the switched-capacitor register (SAR) circuit of the switched-capacitor ADC, connecting the first terminal of the array of capacitors to the first reference voltage terminal or to an electrical ground terminal, and connecting the second terminal of the array of capacitors to the input of a comparator of the switched-capacitor ADC, the comparator being coupled between the array of capacitors and the SAR circuit; and connecting a first terminal of the supplementary capacitor to an electrical ground terminal and connecting a second terminal of the supplementary capacitor to the input of the comparator.

[0077] Example 20. According to the method of Example 19, wherein shifting the DC conversion curve in the second direction includes: during the sampling phase of the switched capacitor ADC: connecting a first end of the capacitor array to the input voltage terminal and connecting a second end of the capacitor array to the low bias voltage terminal; and connecting a first end of a supplementary capacitor to the electrical ground terminal and connecting a second end of the supplementary capacitor to the low bias voltage terminal; and during the conversion phase of the switched capacitor ADC: based on the corresponding bit in the ADC output code generated by the SAR circuit, connecting the first end of the capacitor array to a first reference voltage terminal or to the electrical ground terminal, and connecting the second end of the capacitor array to the input of the comparator; and connecting a first end of the supplementary capacitor to the first reference voltage terminal and connecting the second end of the supplementary capacitor to the input of the comparator.

[0078] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations thereof will be apparent to those skilled in the art from the specification, exemplary embodiments, and other embodiments of the invention. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A switched capacitor analog-to-digital converter, comprising: The main digital-to-analog converter circuit has an output terminal; A supplementary digital-to-analog converter circuit coupled to the main digital-to-analog converter circuit, the supplementary digital-to-analog converter circuit including at least one supplementary capacitor, the first terminal of the at least one supplementary capacitor being coupled to the output terminal of the main digital-to-analog converter circuit; and First reference voltage input terminal and second reference voltage input terminal; The switched capacitor analog-to-digital converter is configured to operate in at least one of a first mode and a second mode, wherein: In the first mode for measuring the offset of the switched capacitor analog-to-digital converter with zero voltage input, the second terminal of the at least one supplementary capacitor is coupled to the first reference voltage input terminal, and the supplementary digital-to-analog converter circuit is configured to shift the voltage at the output of the main digital-to-analog converter circuit by a first value of a first polarity using the charge in the at least one supplementary capacitor. In the second mode used to measure the full-scale gain error of the switched capacitor analog-to-digital converter with a full-scale input voltage, the second terminal of the at least one supplementary capacitor is coupled to the second reference voltage input terminal, and the supplementary digital-to-analog converter circuit is configured to use the charge in the at least one supplementary capacitor to shift the voltage at the output of the main digital-to-analog converter circuit to a second value with a second polarity opposite to the first polarity.

2. The switched capacitor analog-to-digital converter according to claim 1, wherein, The supplementary digital-to-analog converter circuit is configured to be disabled in normal operating mode for measuring the input voltage of the switched capacitor analog-to-digital converter.

3. The switched capacitor analog-to-digital converter according to claim 1, wherein, The first value is the same as the second value.

4. The switched capacitor analog-to-digital converter according to claim 1, wherein, The main digital-to-analog converter circuit includes at least one capacitor, wherein the capacitance of the at least one supplementary capacitor is equal to the capacitance of the at least one capacitor of the main digital-to-analog converter circuit.

5. The switched capacitor analog-to-digital converter according to claim 1, wherein, The capacitance of the at least one supplementary capacitor is reconfigurable.

6. The switched capacitor analog-to-digital converter according to claim 1, wherein, The switched capacitor analog-to-digital converter also includes: A first switch between the second terminal of the at least one supplementary capacitor and the first reference voltage input terminal; and A second switch between the second terminal of the at least one supplementary capacitor and the second reference voltage input terminal.

7. The switched capacitor analog-to-digital converter according to claim 6, wherein, The first reference voltage input terminal is configured to be coupled to the positive reference voltage of the switched capacitor analog-to-digital converter, and the second reference voltage input terminal is configured to be coupled to electrical ground voltage or to the negative reference voltage of the switched capacitor analog-to-digital converter.

8. The switched capacitor analog-to-digital converter according to claim 1, wherein, The switched capacitor analog-to-digital converter (ADC) is a successive approximation ADC. The main ADC circuit includes a capacitor array, where each capacitor corresponds to a specific bit in the output code of the successive approximation ADC. The capacitance Cn of the nth capacitor in the capacitor array is 2. (n-1) ×C, where n=1,2,...,N, where N is the total number of bits in the output code of the successive approximation analog-to-digital converter, and C is a predetermined capacitance value.

9. The switched capacitor analog-to-digital converter according to claim 6 or 7, wherein, The switched capacitor analog-to-digital converter is configured to determine at least one of the offset and full-scale gain error of the switched capacitor analog-to-digital converter based on a first reference voltage received at the first reference voltage input terminal and a second reference voltage received at the second reference voltage input terminal.

10. The switched capacitor analog-to-digital converter according to claim 1, wherein, The switched capacitor analog-to-digital converter is configured to determine at least one of the offset and the full-scale gain error during at least one of a test mode and a normal operating mode.

11. A switched capacitor analog-to-digital converter, comprising: The main digital-to-analog converter circuit has an output terminal; A supplementary digital-to-analog converter (DAC) circuit coupled to the main DAC circuit, the supplementary DAC circuit including at least one supplementary capacitor, the first terminal of the at least one supplementary capacitor being coupled to the output terminal of the main DAC circuit; and First reference voltage input terminal and second reference voltage input terminal The supplementary digital-to-analog converter circuit is configured as follows: During the measurement of the offset of the switched capacitor analog-to-digital converter (ADC) with zero voltage input, the DC-DC conversion curve of the ADC is shifted by a predetermined value along a first direction using the charge in the at least one supplementary capacitor, wherein the second terminal of the at least one supplementary capacitor is coupled to the first reference voltage input terminal, and During the measurement of the full-scale gain error of the switched capacitor analog-to-digital converter with a full-scale voltage input, the DC conversion curve of the switched capacitor analog-to-digital converter is shifted by a predetermined value in a second direction opposite to the first direction using the charge in the at least one supplementary capacitor, wherein the second terminal of the at least one supplementary capacitor is coupled to the second reference voltage input terminal.

12. A switched capacitor analog-to-digital converter, comprising: The main digital-to-analog converter circuit has an output terminal; as well as The supplementary digital-to-analog converter circuit includes: At least one supplementary capacitor, wherein the first terminal of the at least one supplementary capacitor is coupled to the output of the main digital-to-analog converter circuit; A first switch, coupled between a second terminal of the at least one supplementary capacitor and a first reference voltage terminal of the switched capacitor analog-to-digital converter; and A second switch is coupled between the second terminal of the at least one supplementary capacitor and the second reference voltage terminal of the switched capacitor analog-to-digital converter. The supplementary digital-to-analog converter circuit is configured as follows: In a first mode for measuring the offset of the switched capacitor analog-to-digital converter with zero voltage input, the voltage at the output of the main analog-to-digital converter circuit is shifted by a first value of a first polarity using the charge in the at least one supplementary capacitor, wherein the second terminal of the at least one supplementary capacitor is coupled to the first reference voltage terminal by turning on the first switch, and In a second mode for measuring the full-scale gain error of the switched capacitor analog-to-digital converter with a full-scale input voltage, the voltage at the output of the main digital-to-analog converter circuit is shifted by the charge in the at least one supplementary capacitor to a second value with a second polarity opposite to the first polarity, wherein the second terminal of the at least one supplementary capacitor is coupled to the second reference voltage terminal by turning on the second switch.

13. The switched capacitor analog-to-digital converter according to claim 12, wherein, The first reference voltage terminal is configured to be coupled to the positive reference voltage of the switched capacitor analog-to-digital converter, and the second reference voltage terminal is configured to be coupled to electrical ground voltage or to the negative reference voltage of the switched capacitor analog-to-digital converter.

14. The switched capacitor analog-to-digital converter according to claim 12, wherein, The switched capacitor analog-to-digital converter is a successive approximation analog-to-digital converter, wherein the main digital-to-analog converter circuit includes: A capacitor array, wherein a first terminal of each capacitor in the capacitor array is coupled to the output of the main digital-to-analog converter circuit, and wherein a second terminal of each capacitor in the capacitor array is configured to be coupled to an input voltage terminal of the successive approximation analog-to-digital converter, a first reference voltage terminal of the successive approximation analog-to-digital converter, or a second reference voltage terminal of the successive approximation analog-to-digital converter at different stages of operation of the successive approximation analog-to-digital converter; and An array of paired switches, wherein each pair of switches in the array of paired switches includes a first switch and a second switch, a first terminal of the first switch and a first terminal of the second switch are coupled to a second terminal of a corresponding capacitor in the capacitor array, the second terminal of the first switch is coupled to a first node, and the second terminal of the second switch is coupled to a second node.

15. The switched capacitor analog-to-digital converter according to claim 14, wherein, The main digital-to-analog converter circuit also includes: A third switch is coupled between the first node and the input voltage terminal; A fourth switch is coupled between the second node and the input voltage terminal; A fifth switch, coupled between the first node and the first reference voltage terminal; and A sixth switch is coupled between the second node and the second reference voltage terminal.

16. The switched capacitor analog-to-digital converter according to claim 15, wherein, The main digital-to-analog converter circuit also includes a seventh switch, which is coupled between the output terminal of the main digital-to-analog converter circuit and the low bias voltage terminal of the switched capacitor analog-to-digital converter.

17. A method of operating a switched-capacitor analog-to-digital converter according to any one of claims 1 to 16, the method comprising at least one of the following operations: During the measurement of the offset of the switched capacitor analog-to-digital converter with zero voltage input, the DC-DC conversion curve of the switched capacitor analog-to-digital converter is shifted by a predetermined value along a first direction; and During the measurement of the full-scale gain error of the switched capacitor analog-to-digital converter with a full-scale voltage input, the DC conversion curve of the switched capacitor analog-to-digital converter is shifted by the predetermined value along a second direction opposite to the first direction.

18. The method according to claim 17, wherein, Shifting the DC conversion curve along the first direction includes: During the sampling phase of the switched capacitor analog-to-digital converter: The first terminal of the capacitor array in the main digital-to-analog converter circuit of the switched capacitor analog-to-digital converter is connected to the input voltage terminal, and the second terminal of the capacitor array is connected to the low bias voltage terminal. The first terminal of the supplementary capacitor in the supplementary digital-to-analog converter circuit of the switched capacitor analog-to-digital converter is connected to the first reference voltage terminal, and the second terminal of the supplementary capacitor is connected to the low bias voltage terminal; and During the conversion phase of the switched capacitor analog-to-digital converter: Based on the corresponding bits in the analog-to-digital converter output code generated by the successive approximation register circuit of the switched-capacitor analog-to-digital converter, a first terminal of the capacitor array is connected to the first reference voltage terminal or to the electrical ground terminal, and a second terminal of the capacitor array is connected to the input of the comparator of the switched-capacitor analog-to-digital converter, the comparator being coupled between the capacitor array and the successive approximation register circuit. Connect the first terminal of the supplementary capacitor to the electrical ground terminal, and connect the second terminal of the supplementary capacitor to the input terminal of the comparator.

19. The method according to claim 18, wherein, Shifting the DC conversion curve along the second direction includes: During the sampling phase of the switched capacitor analog-to-digital converter: Connect the first terminal of the capacitor array to the input voltage terminal, and connect the second terminal of the capacitor array to the low bias voltage terminal. Connect the first terminal of the supplementary capacitor to the electrical ground terminal, and connect the second terminal of the supplementary capacitor to the low bias voltage terminal; and During the conversion phase of the switched capacitor analog-to-digital converter: Based on the corresponding bits in the analog-to-digital converter output code generated by the successive approximation register circuit, the first terminal of the capacitor array is connected to the first reference voltage terminal or the electrical ground terminal, and the second terminal of the capacitor array is connected to the input terminal of the comparator. The first terminal of the supplementary capacitor is connected to the first reference voltage terminal, and the second terminal of the supplementary capacitor is connected to the input terminal of the comparator.

Images