Interconnect structures, semiconductor structures, and methods of forming the same

Abstract

Structures and methods for reducing electromigration are provided. An interconnect structure according to the present invention includes a conductive feature embedded in a dielectric layer, a capping barrier disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier and the dielectric layer. The adhesion layer has a crystallinity between about 40% and about 70%. Embodiments of the present application also relate to interconnect structures, semiconductor structures, and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to interconnect structures, semiconductor structures, and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each with smaller and more complex circuitry than the previous one. Throughout IC development, functional density (the number of interconnect devices per chip area) has generally increased, while its geometry (the smallest component or line that can be manufactured using a manufacturing process) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, scaling down also increases the complexity of handling and manufacturing ICs.

[0003] For example, to prevent degradation of conductive components due to contact with adjacent dielectric layers, the conductive component can be lined with a barrier layer and covered with a covering barrier layer. While existing interconnect structures are generally sufficient for their intended purpose, they are not satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of this application provide an interconnect structure including: a conductive component embedded in a dielectric layer; a cover barrier layer disposed above the conductive component and the dielectric layer; and an adhesive layer sandwiched between the cover barrier layer and the dielectric layer, wherein the adhesive layer has a crystallinity between about 40% and about 70%.

[0005] Other embodiments of this application provide a semiconductor structure including: a contact component located in a dielectric layer, the contact component including: a metal filling layer, a barrier layer disposed between the metal filling layer and the dielectric layer, and a conductive capping layer disposed above the metal filling layer and the barrier layer; a capping barrier layer disposed above the conductive capping layer and the dielectric layer; and an adhesive layer sandwiched between the capping barrier layer and the dielectric layer, wherein the capping barrier layer includes aluminum nitride or boron nitride.

[0006] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a workpiece including a dielectric layer and conductive components embedded in the dielectric layer; forming an adhesive layer on a top surface of the dielectric layer; and depositing a cover barrier layer over the adhesive layer, wherein the cover barrier layer comprises aluminum nitride or boron nitride. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart is shown of a method for forming an interconnect structure or a partial interconnect structure according to one or more aspects of the present invention.

[0009] Figure 2A , Figure 2B , Figure 3 , Figures 4A to 7A and Figures 4B to 7B It shows the experience of one or more aspects of the invention. Figure 1 The method includes partial cross-sectional views of the workpiece at each operational stage. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to cover values ​​within a reasonable range that takes into account the inherent deviations that arise during the manufacturing process, as understood by those skilled in the art. For example, a numerical value or range encompasses a reasonable range including the described value, such as within + / -10% of the described value, based on known manufacturing tolerances related to manufacturing parts having characteristics associated with that value. For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, with manufacturing tolerances known to those skilled in the art related to the deposition of such a material layer being + / -15%. Additionally, reference numerals and / or characters may be repeated in various examples of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] The present invention generally relates to the reduction or elimination of electromigration, and more specifically, to the deposition of an adhesive layer to improve the adhesion of a covering barrier layer.

[0014] The IC manufacturing industry has researched various conductive materials to improve the performance of interconnect structures. For example, aluminum, due to its ease of integration with IC manufacturing processes and improved conductivity compared to doped polysilicon, was once the mainstream conductive material for constructing interconnect structures. However, because aluminum is prone to electromigration and its conductivity is inferior to copper, it was forced to withdraw from the mainstream and was gradually replaced by copper. However, integrating copper with IC manufacturing processes presents numerous difficulties. While copper is less susceptible to electromigration, it cannot be completely eliminated. Electromigration refers to the migration of materials due to the flow of current. Moving electrons in the current flow are scattered by metal ions in the crystal lattice, and their momentum may be transferred to the metal ions. This momentum transfer from electrons to metal ions generates a momentum transfer force. When this momentum transfer force is greater than the activation energy of the conductor, it may cause metal ion diffusion in the direction of electron movement, i.e., electromigration.

[0015] Electromigration is non-uniform, caused by various factors such as different activation energy levels, stress distribution, material variations, shape changes, and temperature gradients. For example, conductive materials may have different activation energies in different regions, leading to varying electromigration rates. In this regard, aluminum has a lower activation energy along grain boundaries, so its electromigration primarily occurs at these boundaries. Copper has a lower activation energy on its surface, so its electromigration mainly occurs at the surface or surface edges. In conductive components, metal atoms migrating along different diffusion paths can cause metal consumption or accumulation. Consumption manifests as voids or vacancies, while accumulation manifests as whiskers or hillocks. Void growth can trigger a positive feedback loop, leading to accelerated defect formation. In this positive feedback loop, voids induce current crowding, increasing the local current density around the void. This increased local current density generates Joule heating, which lowers the activation energy, further accelerating material diffusion.

[0016] For example, damascene or dual damascene processes can be used to fabricate copper conductive components. A typical damascene process uses photolithography and etching processes to form openings (via openings or trenches) in a dielectric layer. Copper is then deposited in the openings, and a planarization process is performed to remove excess copper, leaving the copper conductive component in the opening. In an exemplary dual damascene process, trenches are formed in a dielectric layer, and via openings are formed in another dielectric layer beneath that dielectric layer, with both the trenches and via openings filled with copper. Allowing copper to contact with silicon or silicon oxide can have negative effects. For example, copper may diffuse into silicon, reducing the semiconductor properties of silicon and resulting in the formation of copper silicide with lower conductivity. Oxygen in silicon oxide and copper in the copper conductive layer may diffuse into each other, reducing the conductivity of the copper conductive layer. To prevent copper from contacting silicon and silicon oxide, a barrier layer or gasket can be applied to seal the copper conductive component. As mentioned above, since copper has the lowest activation energy at the surface, poor adhesion between the barrier layer or gasket and the copper creates a surface that triggers accelerated electromigration processes, affecting device performance and lifetime. Taking a copper conductive component in a dielectric layer as an example, if the overlay barrier layer formed above the copper conductive component and the dielectric layer does not adhere well to them, it may increase the surface area on the copper conductive component. Around such a surface, voids and hillocks may grow faster, and positive feedback loops will accelerate their formation, leading to via-hole bonding defects (VBD), time-delayed dielectric breakdown (TDDB), and resistive conductance (RC) delays. Here, VBD refers to defects at the interface between the contact via and the contact component. TDDB refers to dielectric degradation due to copper diffusion. RC delay refers to the increased resistance and / or conductance due to the formation of voids or hillocks.

[0017] As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). Multi-gate devices generally refer to devices with a gate structure or portion thereof disposed on more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance, low-leakage applications. FinFETs have raised channels covered by gates on more than one side (e.g., the gate covers the top and sidewalls of a semiconductor material "fin" extending from the substrate). MBC transistors have a gate structure that can extend partially or entirely around the channel region, allowing access to the channel region from two or more sides. Because the gate structure of an MBC transistor surrounds the channel region, it is also referred to as a gate-all-around (SGT) transistor or a gate-all-around (GAA) transistor. The channel region of an MBC transistor can be formed from nanowires, nanosheets, or other nanostructures; therefore, MBC transistors can also be called nanowire transistors or nanosheet transistors. The introduction of multi-gate devices further increases the package density of the source / drain contacts, gate contacts, and the interconnects connected to them. This increased package density requires smaller interconnects, and smaller interconnects lead to increased current density. Since the increased current density leads to increased electromigration rates, it becomes increasingly important to implement processes and device structures that prevent electromigration.

[0018] This invention provides structures and methods for improving the adhesion between a capping barrier layer and an amorphous dielectric layer surrounding a conductive component. According to the process of the invention, an adhesive layer is selectively deposited on the dielectric layer, and may include an annealing process to increase the crystallinity of the adhesive layer. Due to the compositional similarity and / or small lattice mismatch between the adhesive layer and the capping barrier layer, the adhesion between the capping barrier layer and the dielectric layer is improved. By improving the adhesion between the capping barrier layer and the dielectric layer, the adhesion between the capping barrier layer and the conductive component is also improved, and VBD, TDDB, and RC delay caused by electromigration are reduced.

[0019] The various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1A flowchart illustrating a method 100 for forming an interconnect structure or partial interconnect structure from a workpiece according to one or more aspects of the invention is shown. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and / or after method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following are partial cross-sectional views of the workpiece 200 at different manufacturing stages according to embodiments of method 100 (e.g., Figure 2A , Figure 2B , Figure 3 , Figures 4A to 7A and Figures 4B to 7B (As shown). To avoid ambiguity, throughout the figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. It should be noted that since workpiece 200 can be manufactured into a semiconductor device, workpiece 200 may also be referred to as semiconductor device 200, depending on the context.

[0020] refer to Figure 1 , Figure 2A and Figure 2B Method 100 includes a frame 102 for receiving a workpiece 200. The workpiece 200 includes a device substrate 10, a dielectric layer 202 located above the device substrate 10, and conductive components 204 disposed in the dielectric layer 202. Although not explicitly shown, the device substrate 10 may include a semiconductor substrate, a front-end process (FEOL) structure fabricated on the semiconductor substrate, and a middle-end process (MEOL) structure coupled to the FEOL structure. The semiconductor substrate may be a silicon (Si) substrate. In some other embodiments, the semiconductor substrate may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Exemplary group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The semiconductor substrate may also include an insulating layer, such as a silicon oxide layer, to construct a silicon-on-insulator (SOI) structure.

[0021] IC manufacturing processes are typically divided into three levels: front-end (FEOL), mid-end (MEOL), and back-end (BEOL). The FEOL level generally includes manufacturing processes related to the fabrication of IC devices such as transistors. For example, FEOL processes may include forming active regions, isolation components, gate structures, and source / drain components. The MEOL level typically includes processes related to the fabrication of contacts for conductive components (or conductive regions) to the IC device, such as contacts for gate structures and / or source / drain components. The BEOL level typically includes processes related to the fabrication of interconnect structures (also known as multilayer interconnect (MLI) structures) that interconnect IC components fabricated in the FEOL and MEOL processes. Here, the FEOL structure may include transistors, diodes, and other passive devices fabricated along with transistors. Transistors may include multi-gate transistors. The MEOL structure may include source / drain contacts coupled to the source / drain components of the FEOL structure, or gate contacts coupled to the gate structure of the FEOL structure. Figure 2A or Figure 2B The interconnect structure 20 shown is manufactured at the BEOL level and is a BEOL structure.

[0022] In an exemplary process for forming device substrate 10, a semiconductor substrate is first received. In the case where the FEOL structure includes an MBC transistor, a stack of first and second semiconductor layers is epitaxially deposited on the semiconductor substrate. The first and second semiconductor layers may contain different compositions. For example, the first semiconductor layer may include silicon, and the second semiconductor layer may include silicon-germanium. The first and second semiconductor layers are interleaved. A fin structure is formed by patterning the semiconductor substrate, or by patterning the semiconductor substrate and the stack. In the case where the FEOL structure includes a FinFET, the fin structure is formed by patterning the semiconductor substrate. In some embodiments, a post-gate process or a gate replacement process may be employed, and a dummy gate stack is formed over the channel region of the fin structure. The dummy gate stack may include a dummy dielectric layer formed of silicon oxide and a dummy electrode layer formed of polysilicon. After the formation of the dummy gate stack, one or more gate spacer layers are deposited over the dummy gate stack. The dummy gate stack is used to mask the channel region, causing the source / drain regions of the fin structure to be recessed. When the FEOL structure includes a FinFET, source / drain components are epitaxially formed over the recessed source / drain regions. When the FEOL structure includes an MBC transistor, the second semiconductor layer is selectively and partially recessed to form an internal spacer trench, and dielectric internal spacers are formed within the internal spacer trench. After forming the internal spacers, source / drain components are epitaxially formed from the semiconductor substrate and the sidewalls of the first semiconductor layer. Depending on the conductivity type of the FEOL structure, the source / drain components may be n-type doped with an agent such as phosphorus or silicon-germanium doped with an agent such as boron.

[0023] After forming the source / drain components, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer are sequentially deposited over the source / drain components. Following the deposition of the CESL and ILD layers, a planarization process is performed to expose the dummy gate stack. When the FEOL structure includes a FinFET, the dummy gate stack is replaced by a functional gate structure comprising an interface layer, a gate dielectric layer above the interface layer, one or more work function layers, and a metal fill layer. When the FEOL structure includes an MBC transistor, the dummy gate stack is selectively removed to expose a first semiconductor layer and a second semiconductor layer in the channel region. The exposed second semiconductor layer is selectively removed to release the first semiconductor layer as a channel component. The channel components are vertically stacked and extend between the source / drain components. After forming the gate structure, additional etch stop layers (ESL) and ILD layers are deposited over the gate structure and the source / drain components. MEOL structures, such as gate contacts and source / drain contacts, are then formed to extend through the ESL and ILD layers.

[0024] like Figure 2A and Figure 2BAs shown, the conductive component 204 in the dielectric layer 202 can represent the conductive component of the interconnect structure 20. The interconnect structure 20 includes a layer of conductive component 204, and other conductive layers located above or below the conductive component 204. The interconnect structure 20 interconnects multiple devices in the FEOL structure via the MEOL structure and couples the FEOL structure to an external circuit. In some embodiments, to reduce parasitic capacitance, the dielectric layer 202 may be formed of a low-k (LK) dielectric material or an ultra-low-k (ELK) dielectric material. Here, a low-k (LK) dielectric material refers to a dielectric material with a dielectric constant less than or equal to the dielectric constant of silicon oxide (about 3.9). An ultra-low-k (ELK) dielectric material refers to a dielectric material with a dielectric constant less than that of a low-k dielectric material. In some embodiments, dielectric layer 202 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide (such as boron-doped phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)) and / or other suitable dielectric materials. Dielectric layer 202 may be deposited using spin coating or chemical vapor deposition (CVD). Due to its composition and manufacturing process, dielectric layer 202 is amorphous and does not have long-range or short-range crystallinity. In some embodiments, conductive component 204 may include copper (Cu) and may be deposited using physical vapor deposition (PVD), electroless plating, electroplating, metal-organic CVD (MOCVD), or suitable methods. In some embodiments, conductive component 204 includes copper (Cu) and manganese (Mn). In these embodiments, manganese in conductive component 204 may diffuse to the top surface of conductive component 204 to form a manganese-rich region, thereby reducing electromigration. In one embodiment, the conductive component 204 is disposed above the source / drain components of the transistor in the device substrate 10.

[0025] exist Figure 2A and Figure 2B In some embodiments shown, the workpiece 200 further includes a barrier layer 206 disposed between the dielectric layer 202 and the conductive member 204. Because the barrier layer 206 lining the surface of the opening for the conductive member 204, the barrier layer 206 can also be referred to as a gasket 206. Figure 2A In some embodiments shown, the barrier layer 206 is conductive and may comprise titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, ruthenium, nickel nitride, tungsten nitride, copper nitride, manganese nitride, or cobalt nitride. In these embodiments, the barrier layer 206 may be present on the bottom surface and only moderately increases the contact resistance. Figure 2BIn some alternative embodiments shown, the barrier layer 206 is anisotropically recessed to remove the barrier layer 206 on the bottom surface, thereby reducing contact resistance. In still some embodiments, the barrier layer 206 has multiple layers, including an outer metal nitride layer for connecting the dielectric layer 202 and an inner metal layer for connecting the conductive component 204. The conductive component 204 can adhere better to the inner metal layer than the outer metal nitride layer, and the dielectric layer 202 can adhere better to the outer metal nitride layer than the inner metal layer; therefore, the multilayer arrangement of the barrier layer 206 can improve the adhesion between the conductive component 204 and the dielectric layer 202. An exemplary outer metal nitride layer can be formed of titanium nitride or tantalum nitride, and an exemplary inner metal layer can be formed of titanium or tantalum. Furthermore, in these embodiments, the outer metal nitride layer and the inner metal layer are conductive, and the multilayer barrier layer 206 can have a similar Figure 2A The structure. In some embodiments where low resistance is desired, the multilayer barrier layer 206 can be anisotropically recessed to remove the multilayer barrier layer 206 on the bottom surface, thereby allowing the conductive component 204 to directly contact the MEOL structure in the device substrate 10 or the conductive component below it, such as... Figure 2B As shown.

[0026] The barrier layer 206 can be deposited using atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), or other suitable methods. The barrier layer 206 serves not only to prevent oxygen from diffusing from the dielectric layer 202 to the conductive component 204, but also to prevent metal atoms from diffusing from the conductive component 204 to the dielectric layer 202. To form... Figure 2A or Figure 2B The workpiece 200 shown is planarized to remove excess barrier layer material and conductive component material from the dielectric layer 202. In some embodiments, planarization can be performed using a chemical mechanical polishing (CMP) process. It should be noted that, for simplicity, the device substrate 10 is... Figure 3 and Figures 4A to 7A It is shown only by dashed lines, and in Figures 4B to 7B , Figure 1 and Figure 3 The middle part is omitted.

[0027] refer to Figure 3 and Figure 1Method 100 may optionally include block 104, selectively depositing a conductive capping layer 208 over the conductive component 204. The conductive capping layer 208 may also be referred to as a metal cap 208 or conductive cap layer 208, and is formed of a different metal than that forming the conductive component 204. In embodiments where the conductive component 204 is formed of copper, the conductive capping layer 208 may include titanium, tantalum, molybdenum, nickel, cobalt, ruthenium, or other refractory metals. In the depicted embodiments, the conductive capping layer 208 includes cobalt. In some embodiments, an organometallic precursor having both metal ions and coordinating ligands is used to selectively deposit the conductive capping layer 208 on the conductive component 204. An exemplary cobalt organometallic precursor may be cobalt dicarbonylcyclopentadiene ((C5H5)Co(CO)2. Figure 4A As shown, due to the selective nature of its formation, the conductive capping layer 208 is deposited only on the conductive component 204 and is not present on the surface of the dielectric layer 202. In addition to acting as a diffusion barrier, the conductive capping layer 208 can also repair damage to the conductive component 204 caused during the planarization process. For convenience, the conductive capping layer 208, the conductive component, and the barrier layer 206 can be collectively referred to as the contact component 205.

[0028] refer to Figure 4B , Figure 4A and Figure 4A Method 100 includes block 106, wherein a first adhesive layer 210 is deposited over dielectric layer 202. Figure 4A In some embodiments shown, the first adhesive layer 210 comprises silicon nitride and can be formed by treating the workpiece 200 with a nitrogen-containing plasma, such as ammonia plasma or nitrogen plasma. In these embodiments, the nitrogen-containing plasma can be inductively coupled plasma (ICP) or transformer-coupled plasma (TCP) with energy levels between about 400 watts (W) and about 600 W. The nitrogen-containing plasma is allowed to react with the surface of the workpiece 200 at a process temperature of about 320°C to about 500°C. Figure 4B In the illustrated case, due to the presence of hydroxyl groups, the nitrogen-containing plasma can selectively react or adhere to the top surface of the dielectric layer 202, while the surfaces of the barrier layer 206, conductive component 204, or conductive capping layer 208 (if already formed) are relatively inert to the nitrogen-containing plasma at the aforementioned energy levels and process temperatures due to the lack of hydroxyl groups. In some embodiments, the nitrogen-containing plasma can be generated in situ within the process cavity where the workpiece 200 is located, or generated ex-situ via a remote plasma source, and then transported to the process cavity. Figure 4B In the embodiment shown, the thickness of the first adhesive layer 210 can be between approximately 1.5 angstroms. Peace Treaty Between. Since hydroxyl groups are absent on the surfaces of the barrier layer 206, the conductive component 204, or the optional conductive cover layer 208 (if formed), the first adhesive layer 210 will be selectively formed on the top surface of the dielectric layer 202. That is, the first adhesive layer 210 is absent on the surfaces of the barrier layer 206, the conductive component 204, and the optional conductive cover layer 208.

[0029] exist Figure 1 In some alternative embodiments shown, the first adhesive layer 210 may be formed using atomic layer deposition (ALD) and may include silicon nitride, silicon oxide, silicon carbide, silicon, titanium oxide, chromium oxide, or aluminum oxide. Figure 5A In the alternative embodiments shown, the deposition of the first adhesive layer 210 is not selective, but conformally deposited over the top surface of the conductive layer 202, the barrier layer 206, the conductive component 204, and the optional conductive capping layer 208 (if formed). ALD deposition of the first adhesive layer 210 can be performed at a temperature of approximately 150°C to approximately 350°C and a process pressure of approximately 2500 mTorr to 3500 mTorr. In these alternative embodiments, the thickness of the first adhesive layer 210 can be between approximately Peace Treaty between.

[0030] refer to Figure 5B , Figure 4A and Figure 4B Method 100 includes block 108, wherein the workpiece 200 is annealed in annealing process 300 to at least partially crystallize the first adhesive layer 210, thereby forming the second adhesive layer 2100. Since the dielectric layer 202 is amorphous, the first adhesive layer 210 formed at block 106 also lacks a long-range or short-range order and is amorphous. As described above, the first adhesive layer 210 may include... Figure 4A The silicon nitride in the illustrated embodiment, or Figure 4B The illustrated embodiments use silicon nitride, silicon oxide, silicon carbide, silicon, titanium oxide, chromium oxide, or aluminum oxide. In block 108, annealing process 300 is used to increase the structural order (i.e., crystallinity) of the first adhesive layer 210 to between about 40% and about 70%. In some embodiments, annealing process 300 may employ rapid thermal annealing (RTA), laser peaking annealing, rapid annealing, or furnace annealing, and may include annealing temperatures between about 800°C and about 1000°C. Annealing process 300 causes... Figure 4B or Figure 5B The first adhesive layer 210 partially crystallizes and short-range order is introduced into the first adhesive layer 210. Selective formation in the first adhesive layer 210... Figure 4B When applied to the dielectric layer 202 shown, the annealing process 300 can convert the amorphous silicon nitride in the first adhesive layer 210 into... Figure 5BThe second adhesive layer 2100 is shown to contain localized β-silicon nitride (β-Si3N4) regions. Silicon nitride can be a stable form of α-silicon nitride (α-Si3N4) or β-silicon nitride (β-Si3N4), both of which have a hexagonal structure. At the high temperature of annealing process 300, β-silicon nitride is more stable than α-silicon nitride; therefore, β-silicon nitride is the dominant component of the second adhesive layer 2100. Because the second adhesive layer 2100 includes locally hexagonal β-silicon nitride, it exhibits a short-range hexagonal structure. Crystallinity can be measured using X-ray diffraction or differential scanning calorimetry (DSC).

[0031] Similarly, in Figure 1 In the alternative embodiments shown, when the first adhesive layer 210 is deposited using the ALD method, the annealing process 300 can partially crystallize the first adhesive layer 210 and introduce short-range order. For example, when the first adhesive layer 210 is formed of silicon oxide, the annealing process 300 can convert low-crystallinity silicon oxide into locally hexagonal silicon oxide regions. When the first adhesive layer 210 is formed of silicon carbide, the annealing process 300 can convert low-crystallinity silicon carbide into locally hexagonal silicon carbide regions. When the first adhesive layer 210 is formed of silicon, the annealing process 300 can convert low-crystallinity silicon into locally diamond cubic silicon regions. When the first adhesive layer 210 is formed of titanium oxide, the annealing process 300 can convert low-crystallinity titanium oxide into locally tetragonal titanium oxide regions. When the first adhesive layer 210 is formed of chromium oxide, the annealing process 300 can convert low-crystallinity chromium oxide into locally hexagonal chromium oxide. When the first adhesive layer 210 is formed of alumina, the annealing process 300 can convert low-crystallinity alumina into locally hexagonal alumina. Figure 6A As shown, the annealing process 300 increases the structural order (i.e., crystallinity) of the first adhesive layer 210 to form a second adhesive layer 2100 with a crystallinity between approximately 40% and approximately 70%. This range of crystallinity is important. On the one hand, it has been observed that when the crystallinity is less than 40%, the improvement in adhesion due to reduced lattice mismatch is likely to be unsatisfactory. On the other hand, while high crystallinity improves adhesion, increasing the crystallinity to above 70% may require excessively long annealing times or excessively high annealing temperatures, potentially leading to higher manufacturing costs and / or introducing defects. Exemplary defects may include damage to conductive components and metal gate structures.

[0032] refer to Figure 6B , Figure 6A and Figure 6BMethod 100 includes block 110, wherein a dielectric capping layer 212 is deposited over a conductive capping layer 208 and a second adhesive layer 2100. In some embodiments, the dielectric capping layer 212 comprises aluminum nitride and can be deposited using atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD). Exemplary ALD processes include the use of an aluminum-containing precursor such as trimethylaluminum (TMA) and a nitrogen-containing precursor such as ammonia (NH3). In an exemplary ALD process, a workpiece 200 is heated to a temperature between about 300°C and about 400°C, and an optional aluminum-containing precursor and a nitrogen-containing precursor are provided to the workpiece 200. After allowing one precursor to contact the workpiece 200, an inert purging gas, such as argon (Ar), helium (He), or nitrogen (N2), is used to purge the reaction chamber. In some embodiments, an inert gas plasma can be generated by a plasma generator to enhance or accelerate the ALD process. In those embodiments, the above process may be referred to as a plasma-enhanced atomic layer deposition (PEALD) process. In some cases, a thickness between about Peace Treaty A dielectric capping layer 212 is formed between the layers. The dielectric capping layer 212, formed using an ALD or PEALD process, may include at least a short-range hexagonal wurtzite crystal structure. In some alternative embodiments, the dielectric capping layer 212 may include boron nitride, which may be deposited using an ALD or PEALD process. The boron nitride may also have a hexagonal or wurtzite crystal structure.

[0033] like Figure 1 As shown, when the second adhesive layer is selectively formed above the dielectric layer 202, the dielectric capping layer 212 is spaced apart from the dielectric layer by the second adhesive layer 2100, but directly contacts the barrier layer 206 (when the conductive capping layer 208 is not formed), the conductive component 204 (when the conductive capping layer 208 is not formed), or the conductive capping layer 208 (if formed). Figure 7A As shown, when the second adhesive layer is conformally formed over the workpiece 200, the dielectric capping layer 212 is spaced apart from the barrier layer 206 (when the conductive capping layer 208 is not formed), the conductive component 204 (when the conductive capping layer 208 is not formed), or the conductive capping layer 208 (if formed) by the second adhesive layer 2100. The dielectric capping layer 212 can also be referred to as the cover barrier layer 212.

[0034] According to the present invention, the second adhesive layer 2100 improves the adhesion between the dielectric capping layer 212 and the dielectric layer 202. Experimental results show that, due to the reduction in lattice mismatch between the second adhesive layer 2100 and the dielectric capping layer 212, the dielectric capping layer 212 adheres better to the second adhesive layer 2100 than to the dielectric layer 202. It has been observed that this improved adhesion reduces electromigration. In this regard, localized crystalline regions in the second adhesive layer 2100 can reduce the lattice mismatch with the dielectric capping layer 212. For example, when the dielectric capping layer 212 is formed of aluminum nitride, the dielectric capping layer comprises hexagonal fibrous wurtzite-type aluminum nitride with a lattice constant of (a) 3.110. When the second adhesive layer 2100 is formed of aluminum nitride, the second adhesive layer comprises hexagonal β-silicon nitride with a lattice constant of (a) 7.608. Although a lattice mismatch of approximately 59% (i.e., (7.608 - 3.110) / 7.608) still exists between hexagonal wurtzite aluminum nitride and hexagonal β-silicon nitride, this represents an improvement of approximately 41% compared to the 100% lattice mismatch between crystalline aluminum nitride and amorphous dielectric layer 202. Similarly, in embodiments where dielectric capping layer 212 is formed of boron nitride, both the first adhesive layer 210 and the second adhesive layer 2100 improve the adhesion between dielectric capping layer 212 and dielectric layer 202. The lattice constant (a) of hexagonal boron nitride is approximately 2.504, and its lattice mismatch with β-silicon nitride is approximately 67% (i.e., (7.608 - 2.504) / 7.608), representing an improvement of approximately 33% compared to the 100% lattice mismatch between crystalline boron nitride and amorphous dielectric layer 202.

[0035] When the first adhesive layer 210 comprises silicon oxide, silicon carbide, silicon, titanium oxide, chromium oxide, or aluminum oxide (in optional embodiments), the second adhesive layer 2100 can also improve adhesion to the dielectric capping layer 212 due to reduced lattice mismatch. In these optional embodiments, the second adhesive layer 2100 may comprise hexagonal silicon oxide, hexagonal silicon carbide, diamond cubic silicon, tetragonal titanium oxide, hexagonal chromium oxide, or hexagonal aluminum oxide. The lattice constant (a) of hexagonal silicon oxide is 4.991. The lattice constant (a) of hexagonal silicon carbide is 3.073. The lattice constant (a) of diamond cubic silicon is 5.431. The lattice constant (a) of tetragonal titanium oxide is 4.58. The lattice constant (a) of hexagonal chromium oxide is 4.961. The lattice constant (a) of hexagonal aluminum oxide is 4.785. Although there is a lattice mismatch between these crystal forms and hexagonal fibrous zinc nitride (or hexagonal boron nitride), the degree of lattice mismatch is less than the 100% lattice mismatch between crystalline aluminum nitride (or crystalline boron nitride) and amorphous dielectric layer 202.

[0036] refer to Figure 7B , Figure 7A and Figure 7BMethod 100 includes block 112, in which a further process is performed. This further process may include depositing an intermetallic dielectric (IMD) layer 214 over the workpiece 200. In some embodiments, the IMD layer 214 and the dielectric layer 202 may include similar compositions and may be formed using similar processes. In these embodiments, the IMD layer 214 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)) and / or other suitable dielectric materials. Spin coating or chemical vapor deposition (CVD) may be used to deposit the IMD layer 214. Although not explicitly shown, other contact elements coupled to the conductive component 204 may be formed in the IMD layer 214. For example, in Figure 7B In the illustrated embodiment, an opening can be formed through the IMD layer 214 and the dielectric capping layer 212 to expose the conductive component 204 or the conductive capping layer 208 (if formed). Here, the dielectric capping layer 212 acts as an etch stop layer (ESL) because the etching of the opening is slowed down at the dielectric capping layer 212. Barrier layers and metal fill layers similar to those described above can be deposited in the opening. Excess material can be removed from the top surface of the IMD layer 214 using a planarization process to provide a flat top surface. ​ In the illustrated embodiment, an opening may be formed through the IMD layer 214, the dielectric capping layer 212, and the second adhesive layer 2100 to expose the conductive component 204 or the conductive capping layer 208 (if formed). ​ In the embodiments shown, the dielectric capping layer 212 and the second adhesive layer 2100 serve as etch stop layers (ESL). The remaining processes are similar and will not be repeated here.

[0037] As described above, electromigration is positively correlated with current density, while current density is negatively correlated with the size of the conductive components. Although the process of the present invention could be repeated layer by layer on interconnect structure 20 to improve adhesion and reduce electromigration, this may not be necessary. The conductive components in interconnect structure 20 are located far from the device substrate 10 and can therefore have a large size. When the size of the conductive components is large enough, the risk of electromigration is small enough that the first adhesive layer 210 (or the second adhesive layer 2100) is no longer needed. Therefore, depending on the size of the conductive components in interconnect structure 20, the first adhesive layer 210 (or the second adhesive layer 2100) of this disclosure may not be implemented throughout interconnect structure 20.

[0038] In an exemplary aspect, the present invention relates to an interconnect structure. This interconnect structure includes a conductive component embedded in a dielectric layer, a cover barrier layer disposed above the conductive component and the dielectric layer, and an adhesive layer sandwiched between the cover barrier layer and the dielectric layer. The adhesive layer has a crystallinity between about 40% and about 70%.

[0039] In some embodiments, the dielectric layer comprises amorphous silicon oxide. In some embodiments, the cover barrier layer comprises aluminum nitride. In some embodiments, an adhesive layer is disposed above the conductive component. In some cases, the adhesive layer comprises β-silicon nitride. In some embodiments, the adhesive layer comprises hexagonal silicon oxide, hexagonal silicon carbide, diamond cubic silicon, tetragonal titanium oxide, hexagonal chromium oxide, or hexagonal aluminum oxide. In some embodiments, the interconnect structure may further include a conductive cover layer disposed between the conductive component and the cover barrier layer.

[0040] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes a contact component located in a dielectric layer. The contact component includes a metal filler layer, a barrier layer disposed between the metal filler layer and the dielectric layer, and a conductive capping layer disposed above the metal filler layer and the barrier layer. The semiconductor structure also includes a capping barrier layer disposed above the conductive capping layer and the dielectric layer, and an adhesive layer sandwiched between the capping barrier layer and the dielectric layer. The capping barrier layer includes aluminum nitride or boron nitride.

[0041] In some embodiments, the dielectric layer comprises amorphous silicon oxide. In some embodiments, the conductive capping layer comprises cobalt. In some embodiments, the adhesive layer comprises β-silicon nitride, hexagonal silicon oxide, hexagonal silicon carbide, diamond cubic silicon, tetragonal titanium oxide, hexagonal chromium oxide, or hexagonal aluminum oxide. In some cases, the adhesive layer comprises a crystallinity between about 40% and about 70%. In some embodiments, the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, ruthenium, nickel nitride, tungsten nitride, copper nitride, manganese nitride, or cobalt nitride.

[0042] In another exemplary aspect, the invention relates to a method. The method includes receiving a workpiece including a dielectric layer and conductive components embedded in the dielectric layer, forming an adhesive layer on a top surface of the dielectric layer, and depositing a cover barrier layer over the adhesive layer. The cover barrier layer includes aluminum nitride or boron nitride.

[0043] In some embodiments, the dielectric layer comprises amorphous silicon oxide, and the conductive component comprises copper and manganese. In some embodiments, the method may further include annealing the workpiece after forming the adhesive layer to increase the crystallinity of the adhesive layer. In some cases, depositing the cover barrier layer includes using atomic layer deposition (ALD). In some embodiments, the adhesive layer comprises silicon nitride, silicon oxide, silicon carbide, silicon, titanium oxide, chromium oxide, or aluminum oxide. In some embodiments, the method may further include selectively depositing a cobalt layer over the conductive component before forming the adhesive layer. In some cases, the adhesive layer is not present on the top surface of the cobalt layer after forming the adhesive layer.

[0044] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An interconnection structure, comprising: Conductive components are embedded in the dielectric layer; A barrier layer is disposed above the conductive component and the dielectric layer and covers the conductive component; as well as An adhesive layer, sandwiched between the cover barrier layer and the dielectric layer, Wherein, the dielectric layer is an amorphous dielectric layer, the covering barrier layer is a crystalline covering barrier layer, the adhesive layer is partially crystalline and includes a crystallinity between 40% and 70%, and the lattice mismatch between the covering barrier layer and the adhesive layer is lower than the lattice mismatch between the covering barrier layer and the dielectric layer.

2. The interconnection structure according to claim 1, wherein, The dielectric layer comprises amorphous silicon oxide.

3. The interconnection structure according to claim 1, wherein, The covering barrier layer comprises aluminum nitride.

4. The interconnection structure according to claim 1, wherein, The adhesive layer is disposed above the conductive component.

5. The interconnection structure according to claim 1, wherein, The adhesive layer comprises β-silicon nitride.

6. The interconnection structure according to claim 1, wherein, The adhesive layer includes hexagonal silicon oxide, hexagonal silicon carbide, diamond cubic silicon, tetragonal titanium oxide, hexagonal chromium oxide, or hexagonal aluminum oxide.

7. The interconnection structure according to claim 1, further comprising: A conductive cover layer is disposed between the conductive component and the cover barrier layer.

8. A semiconductor structure, comprising: Contact components, located in the dielectric layer, include: Metal filler layer A barrier layer is disposed between the metal filler layer and the dielectric layer, and A conductive capping layer is located above the metal filler layer and the barrier layer; A barrier layer is disposed above the conductive cover layer and the dielectric layer and covers the conductive cover layer; and An adhesive layer, sandwiched between the cover barrier layer and the dielectric layer, Wherein, the dielectric layer is an amorphous dielectric layer, the covering barrier layer is a crystalline covering barrier layer and includes crystalline aluminum nitride or crystalline boron nitride, the adhesive layer is partially crystalline, and the lattice mismatch between the covering barrier layer and the adhesive layer is lower than the lattice mismatch between the covering barrier layer and the dielectric layer.

9. The semiconductor structure according to claim 8, wherein, The dielectric layer comprises amorphous silicon oxide.

10. The semiconductor structure according to claim 8, wherein, The conductive coating layer includes cobalt.

11. The semiconductor structure according to claim 8, wherein, The covering barrier layer comprises crystalline aluminum nitride.

12. The semiconductor structure according to claim 11, wherein, The adhesive layer has a crystallinity between 40% and 70%.

13. The semiconductor structure according to claim 8, wherein, The barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, ruthenium, nickel nitride, tungsten nitride, copper nitride, manganese nitride, or cobalt nitride.

14. A method for forming a semiconductor structure, comprising: Receive a workpiece, the workpiece comprising a dielectric layer and conductive components embedded in the dielectric layer, wherein the dielectric layer is an amorphous dielectric layer; An adhesive layer is formed on the top surface of the dielectric layer; After the adhesive layer is formed, the workpiece is annealed to partially crystallize the adhesive layer and increase the crystallinity of the adhesive layer; as well as A cover barrier layer is deposited over the adhesive layer and the conductive component, wherein the cover barrier layer covers the conductive component, wherein the cover barrier layer is a crystalline cover barrier layer and comprises crystalline aluminum nitride or crystalline boron nitride, and the lattice mismatch between the cover barrier layer and the adhesive layer is lower than the lattice mismatch between the cover barrier layer and the dielectric layer.

15. The method according to claim 14, wherein, The dielectric layer comprises amorphous silicon oxide, and the conductive components comprise copper and manganese.

16. The method of claim 14, wherein, The partially crystalline adhesive layer has a crystallinity between 40% and 70%.

17. The method of claim 14, wherein, Depositing the overlay barrier layer includes using atomic layer deposition (ALD).

18. The method according to claim 14, wherein, The adhesive layer includes silicon nitride, silicon oxide, silicon carbide, silicon, titanium oxide, chromium oxide, or aluminum oxide.

19. The method of claim 14, further comprising: Before forming the adhesive layer, a cobalt layer is selectively deposited over the conductive component.

20. The method according to claim 19, in, After the adhesive layer is formed, it is not present on the top surface of the cobalt layer.

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