Solid-state imaging devices and electronic devices

Abstract

The present technology relates to a solid-state imaging element and an electronic device capable of suppressing degradation of the photoelectric conversion characteristics of a photoelectric conversion unit. The solid-state imaging element is provided with a pixel, and the pixel includes: a photoelectric conversion unit formed outside a semiconductor substrate; a charge holding unit for holding a signal charge generated in the photoelectric conversion unit and directly connected to the photoelectric conversion unit; a reset transistor for resetting the potential of the charge holding unit; a capacitance switching transistor connected to the charge holding unit and used to switch the capacitance of the charge holding unit; and an additional capacitance element connected to the capacitance switching transistor. For example, the present technology can be applied to a solid-state imaging element.

Description

[0001] This application is a divisional application of a patent application with application number 201680006416.1, filed on January 15, 2016, and with the invention name “Solid-state imaging device and electronic device”. Technical Field

[0002] The present technology relates to a solid-state imaging device and an electronic device, and in particular, to a solid-state imaging device and an electronic device capable of suppressing degradation of photoelectric conversion characteristics of a photoelectric conversion unit. Background Art

[0003] In recent years, as a technology for discontinuously changing the characteristics of an image sensor, a structure in which a photoelectric conversion unit is arranged outside a semiconductor substrate has been proposed. For example, Patent Documents 1-3 disclose a structure in which a photoelectric conversion unit is arranged on the upper part of a semiconductor substrate and a photoelectric conversion signal is accumulated in the semiconductor substrate. This structure can greatly change the photoelectric conversion characteristics determined by the conventional semiconductor substrate material, and enables the sensor technology to be applied to fields such as the far infrared field that are usually difficult to achieve with silicon (Si) image sensors.

[0004] In addition, in the pixel arrangement in which red filters, blue filters, and green filters are arranged in a planar manner, which is currently widely used in image sensors, color separation is performed by absorbing light of a specific wavelength in units of pixels. Therefore, for example, in the color filter of a red pixel, light with blue and green wavelengths is absorbed and lost.

[0005] As a solution, a stacked solid-state imaging device is proposed in Patent Document 1, in which photoelectric conversion regions for photoelectrically converting red, blue, and green light are stacked in the same pixel space, for example. This structure can suppress sensitivity degradation caused by light absorption by the color filter. In addition, this structure does not require interpolation processing, and it can be expected that no false color influence will occur.

[0006] The structure in which the photoelectric conversion unit is arranged outside the semiconductor substrate requires that the photoelectric conversion unit and the semiconductor substrate be electrically connected. Since the photoelectric conversion unit and the semiconductor substrate are connected using metal, the signal charge generated in the photoelectric conversion unit cannot be completely transferred to the charge holding unit via the transfer gate. Therefore, as disclosed in Patent Document 1, the structure generally adopts a structure in which the photoelectric conversion unit and the charge holding unit are directly connected.

[0007] However, for the photoelectric conversion unit of this structure, the photoelectric conversion and sensitivity of the photoelectric conversion unit will be degraded. In order to improve the degradation of the sensitivity of the photoelectric conversion unit, an effective solution is to increase the capacitance of the charge holding unit and reduce the voltage change relative to the signal charge. However, when the capacitance of the charge holding unit is increased, the signal amplification rate of the charge holding unit is reduced, and therefore, the S / N ratio of the solid-state imaging device will be reduced.

[0008] Therefore, Patent Document 4 proposes a method for controlling the capacitance of a charge holding unit according to the amount of signal charge. Specifically, the capacitance of the charge holding unit is controlled so that, under low illumination where a high S / N ratio is required, the capacitance of the charge holding unit is reduced, and under high illumination where a large amount of signal charge needs to be retained, the capacitance of the charge holding unit is increased by using a capacitance adding unit.

[0009] However, with this configuration, in order to reduce the capacitance of the charge holding unit at low illumination requiring a high S / N ratio, the capacitance adding unit needs to be depleted. Therefore, a depletion region is connected to the charge holding unit, and leakage characteristics deteriorate at low illumination.

[0010] In addition, in Patent Document 5, a transistor (Tr) for adding capacitance is arranged between a floating diffusion (FD) unit and a reset Tr, thereby controlling a signal amplification ratio.

[0011] Reference List

[0012] Patent Literature

[0013] Patent Document 1: Japanese Patent Application Laid-Open No. 2007-329161

[0014] Patent Document 2: Japanese Patent Application Laid-Open No. 2010-278086

[0015] Patent Document 3: Japanese Patent Application Laid-Open No. 2011-138927

[0016] Patent Document 4: Japanese Patent Application Laid-Open No. 2013-89869

[0017] Patent Document 5: Japanese Patent Application Laid-Open No. 2010-124418 Summary of the invention

[0018] Technical issues

[0019] However, in the configuration of Patent Document 5, since the readout Tr is arranged between the photoelectric conversion unit and the signal amplification unit, the capacitance of the portion between the photoelectric conversion unit and the readout Tr cannot be controlled. Therefore, the voltage of the photoelectric conversion unit changes according to the amount of signal charge, and the photoelectric conversion efficiency also changes.

[0020] The present invention has been made in view of the above circumstances, and is intended to suppress degradation of the photoelectric conversion characteristics of a photoelectric conversion unit.

[0021] Technical Solution

[0022] A solid-state imaging device according to a first aspect of the present technology includes a pixel having: a photoelectric conversion unit formed outside a semiconductor substrate; a charge holding unit for holding a signal charge generated by the photoelectric conversion unit and directly connected to the photoelectric conversion unit; a reset transistor for resetting the potential of the charge holding unit; a capacitance switching transistor connected to the charge holding unit and for switching the capacitance of the charge holding unit; and an additional capacitance element connected to the capacitance switching transistor.

[0023] The electronic device of the second aspect of the present technology includes: a solid-state imaging device, the solid-state imaging device includes a pixel, the pixel has: a photoelectric conversion unit, the photoelectric conversion unit is formed outside the semiconductor substrate; a charge holding unit, the charge holding unit is used to hold the signal charge generated by the photoelectric conversion unit, and the charge holding unit is directly connected to the photoelectric conversion unit; a reset transistor, the reset transistor is used to reset the potential of the charge holding unit; a capacitance switching transistor, the capacitance switching transistor is connected to the charge holding unit and is used to switch the capacitance of the charge holding unit; and an additional capacitance element, the additional capacitance element is connected to the capacitance switching transistor.

[0024] According to the first and second aspects of the present technology, a signal charge generated in a photoelectric conversion unit formed outside a semiconductor substrate is held in a charge holding unit, and the potential of the charge holding unit is reset by a reset transistor. The capacitance of the charge holding unit is switched by a capacitance switching transistor connected to the charge holding unit, and an additional capacitance element is connected to the capacitance switching transistor.

[0025] The solid-state imaging device and the electronic device may be independent devices, and may also be a module incorporated in other devices.

[0026] Beneficial Effects

[0027] According to the first and second aspects of the present technology, degradation of the photoelectric conversion characteristics of the photoelectric conversion unit can be suppressed.

[0028] Note that the effects described herein are not limited, and any effects described in the present technology can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a diagram showing an equivalent circuit of a basic pixel.

[0030] Figure 2 is a diagram showing a cross-sectional structure of a basic pixel.

[0031] Figure 3 It is a diagram for explaining a problem caused in a basic pixel.

[0032] Figure 4 It is a diagram for explaining a problem caused in a basic pixel.

[0033] Figure 5 is a diagram showing an equivalent circuit of a pixel according to the first embodiment.

[0034] Figure 6 is a diagram showing a cross-sectional structure of a pixel according to the first embodiment.

[0035] Figure 7 is a diagram for explaining how to drive the pixel according to the first embodiment.

[0036] Figure 8 is a diagram showing an equivalent circuit of a pixel according to the second embodiment.

[0037] Fig. 9 is a diagram showing a cross-sectional structure of a pixel according to the second embodiment.

[0038] Fig.10 is a diagram for explaining how to drive pixels according to the second embodiment.

[0039] Fig.11 It is a diagram for explaining the difference between the first embodiment and the second embodiment.

[0040] Fig.12 It is a diagram for explaining the difference between the first embodiment and the second embodiment.

[0041] Fig.13 is a diagram showing an equivalent circuit of a pixel according to the third embodiment.

[0042] Fig.14 is a diagram showing a cross-sectional structure of a pixel according to the third embodiment.

[0043] Fig.15 is a diagram for explaining the difference between the second embodiment and the third embodiment.

[0044] Fig.16 is a diagram for explaining the difference between the second embodiment and the third embodiment.

[0045] Fig.17is a diagram showing an equivalent circuit of a pixel according to the fourth embodiment.

[0046] Fig.18 is a diagram showing a cross-sectional structure of a pixel according to a fourth embodiment.

[0047] Fig.19 is a diagram for explaining the difference between the third embodiment and the fourth embodiment.

[0048] Fig. 20 is a diagram for explaining the difference between the third embodiment and the fourth embodiment.

[0049] Fig.21 is a diagram showing an equivalent circuit of a pixel according to the fifth embodiment.

[0050] Fig. 22 is a diagram showing a cross-sectional structure of a pixel according to a fifth embodiment.

[0051] Fig.23 is a diagram showing a schematic configuration of a solid-state imaging device to which the present technology is applied.

[0052] Fig.24 : is a block diagram showing an exemplary configuration of a photographing device as an electronic device to which the present technology is applied. DETAILED DESCRIPTION

[0053] A mode for implementing the present technology (hereinafter referred to as an embodiment) will be described below. Note that the description will be given in the following order.

[0054] 1. Basic pixel description

[0055] 2. First Embodiment (Exemplary Configuration in Which a Reset Transistor and a Capacitance Switching Transistor are Connected in Parallel)

[0056] 3. Second Embodiment (Exemplary Configuration in Which a Reset Transistor and a Capacitance Switching Transistor are Connected in Series)

[0057] 4. Third Embodiment (Exemplary Configuration Where Signal Charges Are Holes)

[0058] 5. Fourth Embodiment (Exemplary Configuration in Which the Gate Portion of the Additional Capacitance Element is Connected to the Charge Retention Unit)

[0059] 6. Fifth Embodiment (Exemplary Configuration Having Photoelectric Conversion Film and Photodiode)

[0060] 7. Schematic Configuration Example of Solid-State Imaging Device

[0061] 8. Exemplary Applications of Electronic Devices

[0062] 1. Basic pixel description

[0063] To help understanding of the present technology, first, a pixel of a solid-state imaging device (hereinafter referred to as a basic pixel) as a basic configuration to which the present technology is applied will be described.

[0064] Equivalent circuit of a basic pixel

[0065] Figure 1 An equivalent circuit of a basic pixel is shown.

[0066] Figure 1 The basic pixel 1 shown has a photoelectric conversion unit 11 , a charge holding unit 12 , a reset transistor 13 , an amplification transistor (output transistor) 14 , and a selection transistor 15 .

[0067] The photoelectric conversion unit 11 generates and accumulates charge (signal charge) according to the amount of received light. One end of the photoelectric conversion unit 11 is grounded, and the other end thereof is connected to the charge holding unit 12, the source of the reset transistor 13, and the gate of the amplifier transistor 14. Figure 1 In the structure, the signal charge is electrons.

[0068] The charge holding unit 12 holds the charge read from the photoelectric conversion unit 11. Figure 2 As shown, the charge holding unit 12 is connected to one end of the photoelectric conversion unit 11, the source of the reset transistor 13, and the gate of the amplifier transistor 14, so that the charge is actually held in all the above devices.

[0069] When the reset transistor 13 is turned on by the reset signal RST supplied to the gate thereof, the charge accumulated in the charge holding unit 12 is discharged to the drain (power supply voltage VDD) of the reset transistor 13 , and the reset transistor 13 resets the potential of the charge holding unit 12 .

[0070] The gate of the amplifier transistor 14 is connected to the charge holding unit 12, the drain thereof is connected to the power supply voltage VDD, and the source thereof is connected to the drain of the selection transistor 15. The amplifier transistor 14 outputs a pixel signal according to the potential of the charge holding unit 12. That is, the amplifier transistor 14 and a load MOS (not shown) constitute a source follower circuit, which serves as a constant current source connected via a column signal line 16 for transmitting a pixel signal output from the basic pixel 1, and a pixel signal at a level based on the charge accumulated in the charge holding unit 12 is output from the amplifier transistor 14 to an AD conversion unit (not shown) via the selection transistor 15. The load MOS is provided, for example, in an AD conversion unit provided in units of columns of a plurality of basic pixels 1 arranged two-dimensionally.

[0071] The drain of the selection transistor 15 is connected to the source of the amplifier transistor 14, and the source thereof is connected to a column signal line 16 for transmitting a pixel signal of each basic pixel 1 arranged in a column direction (vertical direction). When a basic pixel 1 is selected by a selection signal SEL supplied to the gate of the selection transistor 15, the selection transistor 15 is turned on, thereby outputting the pixel signal of the basic pixel 1 to the AD conversion unit via the column signal line 16.

[0072] Cross-sectional structure of a basic pixel

[0073] Figure 2 is a diagram showing a cross-sectional structure of a basic pixel.

[0074] In the basic pixel 1 , the reset transistor 13 , the amplifying transistor 14 , and the selecting transistor 15 are formed on one interface (upper surface in the figure) of a P-type semiconductor substrate (P-well) 21 .

[0075] Specifically, the reset transistor 13 is composed of a gate portion 13GT on a P-type semiconductor substrate 21 and n-type diffusion layers 22 and 23 in the P-type semiconductor substrate 21, the amplification transistor 14 is composed of a gate portion 14GT on the P-type semiconductor substrate 21 and n-type diffusion layers 23 and 24 in the P-type semiconductor substrate 21, and the selection transistor 15 is composed of a gate portion 15GT on the P-type semiconductor substrate 21 and n-type diffusion layers 24 and 25 in the P-type semiconductor substrate 21. For example, the gate portions 13GT, 14GT, and 15GT are made of polycrystalline silicon.

[0076] The n-type diffusion layer 22 functions as a source of the reset transistor 13 and a charge holding unit 12, and is connected to a lower electrode 29B of a photoelectric conversion unit 11 and a gate portion 14GT of an amplifier transistor 14 to be described later via a metal wiring 26. Therefore, the lower electrode 29B in the photoelectric conversion unit 11 and the gate portion 14GT of the amplifier transistor 14 connected via the metal wiring 26 jointly function as the charge holding unit 12 in which electric charge is held. For example, the metal wiring 26 is made of tungsten (W), aluminum (Al), copper (Cu), or the like.

[0077] The n-type diffusion layer 23 functions as a drain of the reset transistor 13 and a drain of the amplification transistor 14 , and is supplied with a power supply voltage VDD.

[0078] The n-type diffusion layer 24 functions as a source of the amplification transistor 14 and a drain of the selection transistor 15. The n-type diffusion layer 25 functions as a source of the selection transistor 15 and is connected to the column signal line 16.

[0079] The photoelectric conversion unit 11 is formed above each pixel transistor (the reset transistor 13 , the amplification transistor 14 , and the selection transistor 15 ) in the P-type semiconductor substrate 21 via the insulating layer 27 .

[0080] The photoelectric conversion unit 11 is formed in such a way that the photoelectric conversion film 28 is sandwiched between the upper electrode 29A and the lower electrode 29B. The photoelectric conversion film 28 can be an organic photoelectric conversion film, CIGS (Cu, In, Ga, Se compound), CIS (Cu, In, Se compound), chalcopyrite semiconductor, compound semiconductor such as GaAs, etc. The upper electrode 29A is made of a transparent electrode film such as an indium tin oxide (ITO) film or an indium zinc oxide film. The lower electrode 29B is made of an electrode film of tungsten (W), aluminum (Al), copper (Cu), etc. The upper electrode 29A is formed in common for all pixels, while the lower electrode 29B is formed in units of pixels. The upper electrode 29A is grounded (GND).

[0081] The color filter 31 and the on-chip lens 32 are formed on the upper electrode 29A via the protective film (insulating film) 30. For example, the color filter 31 arranges red (Red), green (Green) and blue (Blue) in a Bayer arrangement in units of pixels. Therefore, the photoelectric conversion film 28 can perform photoelectric conversion on any red light, green light or blue light that passes through the color filter 31.

[0082] The basic pixel 1 is formed in the above-mentioned cross-sectional structure.

[0083] Basic pixel problem

[0084] Will refer to Figure 3 and Figure 4 A problem caused in the basic pixel 1 will be described.

[0085] Figure 3 The operation of the photoelectric conversion unit 11, the charge holding unit 12, and the reset transistor 13 related to holding the charge in the basic pixel 1 is shown by comparing the flow of current (electrons) and the gate of the transistor to a water flow and a water gate, respectively. Figure 3 In the figure, the on / off state of the gate of the transistor is represented by the top / bottom of the gray water gate. The gray water gate moves up or down, thereby controlling the shaded (diagonal) water flow (current). In the figure, the vertical height represents the voltage, and the lower the gray water gate or the shaded part, the higher the voltage.

[0086] Figure 3 A in the middle shows the state before the photoelectric conversion unit 11 receives light.

[0087] Before receiving light, the reset transistor 13 is turned on to reset the potential of the charge holding unit 12 to VDD. Next, the upper electrode 29A of the photoelectric conversion unit 11 is grounded (GND), so the potential difference between the upper electrode 29A and the lower electrode 29B in the photoelectric conversion unit 11 is VDD.

[0088] When signal charge is generated and accumulated due to photoelectric conversion during light reception, such as Figure 3 As shown in B, the voltage of the charge holding unit 12 holding the photoelectric conversion signal changes, and the voltage applied to the photoelectric conversion unit 11 decreases. Therefore, the photoelectric conversion film 28 is not applied with a sufficient voltage to extract the generated signal, and the sensitivity of the photoelectric conversion unit 11 deteriorates.

[0089] In order to improve the problem of sensitivity degradation, an effective solution is to increase the capacitance of the charge holding unit 12 and reduce the voltage change relative to the signal charge. However, when the capacitance of the charge holding unit 12 is increased, the signal amplification rate of the charge holding unit 12 is reduced, and therefore, the S / N ratio of the solid-state imaging device is reduced.

[0090] Therefore, as disclosed in the background art of patent document 4, as a method for preventing the S / N ratio of a solid-state imaging device from being reduced, there is a method for controlling the capacitance of a charge holding unit 12 according to the amount of signal charge. That is, the method involves controlling the capacitance of the charge holding unit 12 so that the capacitance of the charge holding unit 12 is reduced under low illumination that requires a high S / N ratio, and the capacitance of the charge holding unit 12 is increased under high illumination that requires a large amount of signal charge to be retained. Such capacitance control can be achieved by providing a charge holding unit 12 with, for example, a capacitance adding device. However, with this configuration, in order to reduce the capacitance of the charge holding unit 12 under low illumination that requires a high S / N ratio, the capacitance adding unit needs to be depleted. Therefore, there is a problem that the depletion region is connected to the charge holding unit and the leakage characteristics deteriorate under low illumination.

[0091] In addition, for example, according to the background section of Patent Document 5, a capacitance adding transistor (Tr) is disposed between the FD unit and the reset Tr, thereby controlling the signal amplification factor.

[0092] Figure 4 Similar to Figure 3 The water flow pattern shown is a diagram showing the structure of the charge retention portion of the pixel disclosed in Patent Document 5.

[0093] Regarding the structure of the pixel disclosed in Patent Document 5, Figure 4 As shown in FIG. 1A, since the readout Tr (TG) 42 is arranged between the photoelectric conversion unit 11 and the signal amplification unit 41, the capacitance of the portion between the photoelectric conversion unit 11 and the readout Tr 42 cannot be controlled. Figure 4As shown in B, when signal charge is generated and accumulated due to photoelectric conversion, the voltage applied to the photoelectric conversion unit 11 decreases. Therefore, the structure of the pixel disclosed in Patent Document 5 cannot solve the following problems: the voltage of the photoelectric conversion unit 11 changes according to the amount of signal charge, and the photoelectric conversion characteristics (photoelectric conversion efficiency) also change.

[0094] Therefore, a pixel structure that suppresses degradation of the photoelectric conversion characteristics (photoelectric conversion efficiency) and suppresses degradation of the image quality will be described below in comparison with the basic pixel 1.

[0095] Note that components corresponding to those in the above-described basic pixel 1 are denoted by the same reference numerals, and description thereof is omitted as necessary in each embodiment to be described later.

[0096] 2. First embodiment

[0097] Will refer to Figures 5 to 7 A first embodiment of a pixel to which the present technology is applied will be described.

[0098] Figure 5 An equivalent circuit of the pixel 51A according to the first embodiment is shown.

[0099] Figure 5 The illustrated pixel 51A has a photoelectric conversion unit 11 , a charge holding unit 12 , a reset transistor 13 , an amplification transistor 14 , a selection transistor 15 , a capacitance switching transistor 61 , and an additional capacitance element 62 .

[0100] That is to say, except Figure 1 In addition to the components of the basic pixel 1 shown, the pixel 51A is newly provided with a capacitance switching transistor 61 and an additional capacitance element 62. The source of the capacitance switching transistor 61 is connected to the charge holding unit 12, and the drain thereof is connected to one end of the additional capacitance element 62. A connection node 63 indicates a connection point between the capacitance switching transistor 61 and the additional capacitance element 62. The other end of the additional capacitance element 62 is connected to the power supply voltage VDD.

[0101] The capacitance switching transistor 61 switches the capacitance of the charge holding unit 12 by connecting or separating the additional capacitance element 62 from the charge holding unit 12 in response to a switching control signal CapSEL supplied to the gate of the capacitance switching transistor 61 .

[0102] Figure 6 2 is a diagram showing a cross-sectional structure of a pixel 51A.

[0103] In such Figure 6In the cross-sectional structure of the pixel 51A shown in the figure, a gate portion 61GT and an n-type diffusion layer 71 of the capacitance switching transistor 61 are newly added due to the addition of the capacitance switching transistor 61. In addition, a gate portion 62GT of the additional capacitance element 62 is newly added due to the addition of the additional capacitance element 62. The additional capacitance element 62 is composed of a MOS capacitor, which is formed by the n-type diffusion layer 71 and the gate portion 62GT.

[0104] In addition, according to the first embodiment, Figure 2 The n-type diffusion layer 22 serving as the source of the reset transistor 13 is used as the source of the capacitance switching transistor 61. The n-type diffusion layer 71 is used as the drain of the capacitance switching transistor 61 and one end of the additional capacitance element 62.

[0105] First Drive

[0106] The following will refer to Figure 7 How to drive the pixel 51A according to the first embodiment (first drive) is described.

[0107] The pixel 51A first detects the signal level (reset signal level) of the state before signal accumulation, accumulates the signal charge, and then reads the accumulated signal charge, thereby performing a correlated double sampling (CDS) process, thereby finding the difference between the reset signal level before accumulation and the signal level (accumulated signal level) after accumulation. The CDS process can eliminate pixel-specific fixed pattern noise such as kTC noise, or can eliminate the threshold variation of the amplifier transistor 14.

[0108] Figure 7 A timing chart of signals respectively supplied to the gate of the selection transistor 15 , the gate of the reset transistor 13 , and the gate of the capacitance switching transistor 61 in order to perform CDS processing by the pixel 51A is shown.

[0109] Figure 7 A shows how to drive in a case where the capacitance of the charge holding unit 12 is increased for more signal charges (hereinafter, referred to as high capacitance selection), Figure 7 B shows how to drive in a case where the capacitance of the charge holding unit 12 is reduced to increase the gain for less signal charge (hereinafter, referred to as low capacitance selection). In the control circuit 405 or the signal processing circuit 406 ( Fig.24 ) under the control of Figure 7 A high capacitance setting or Figure 7 The low capacitance in B is set, thereby driving pixel 51A.

[0110] In high capacitance selection, before starting to drive each pixel 51A, the gate portion 61GT of the capacitance switching transistor 61 is supplied with a high (Hi) switching control signal CapSEL, and the capacitance switching transistor 61 is turned on. In high capacitance selection, the capacitance switching transistor 61 is always set to be turned on.

[0111] Then, at time t1 , when the selection transistor 15 is turned off and the reset transistor 13 is turned off, the selection signal SEL enters a high level, and the selection transistor 15 is turned on.

[0112] Then, while the selection transistor 15 is turned on, the reset transistor 13 is turned on at time t2, and the reset transistor 13 is turned off at time t3, so that the voltage of the charge holding unit 12 is reset to the power supply voltage VDD in the initial state. In addition, since the capacitance switching transistor 61 is turned on, the additional capacitance element 62 connected to the charge holding unit 12 via the capacitance switching transistor 61 is also reset at the same time.

[0113] Thereafter, at time t4, the selection transistor 15 is turned off and then starts accumulating signal charges.

[0114] After the accumulation of the signal charge is completed, the selection transistor 15 is turned on at time t5 , thereby outputting the signal charge accumulated in the charge holding unit 12 to a memory or the like in the AD conversion unit via the column signal line 16 .

[0115] After the reading of the accumulated signal charge is completed, the selection transistor 15 is turned off at time t6.

[0116] On the other hand, when the low capacitance is selected, before each pixel 51A is driven to start, the gate portion 61GT of the capacitance switching transistor 61 is supplied with a low (Lo) switching control signal CapSEL, and the capacitance switching transistor 61 is turned off. When the low capacitance is selected, the capacitance switching transistor 61 is always set to be turned off. The driving except the capacitance switching transistor 61 is the same as when the high capacitance is selected.

[0117] That is, at time t11 , when the selection transistor 15 is turned off and the reset transistor 13 is turned off, the selection signal SEL enters a high level (Hi), and the selection transistor 15 is turned on.

[0118] Then, while the selection transistor 15 is turned on, the reset transistor 13 is turned on at time t12, and the reset transistor 13 is turned off at time t13, so that the voltage of the charge holding unit 12 is reset to the initial state. Since the capacitance switching transistor 61 is turned off, the additional capacitance element 62 is separated from the charge holding unit 12.

[0119] Thereafter, at time t14, the selection transistor 15 is turned off and then starts accumulating signal charges.

[0120] After the accumulation of the signal charge is completed, the selection transistor 15 is turned on at time t15 , thereby outputting the signal charge accumulated in the charge holding unit 12 to a memory or the like in the AD conversion unit via the column signal line 16 .

[0121] After the reading of the accumulated signal charge is completed, the selection transistor 15 is turned off at time t16.

[0122] Effects of the First Embodiment

[0123] According to the first embodiment described above, the capacitance of the charge holding unit 12 connected to the photoelectric conversion unit 11 is controlled according to the amount of signal charge, thereby controlling the voltage amplitude of the charge holding unit 12. That is, in the case where there is a large amount of signal charge, the capacitance switching transistor 61 is turned on to increase the capacitance of the charge holding unit 12, thereby suppressing an increase in the voltage of the charge holding unit 12 and suppressing a decrease in the applied voltage of the photoelectric conversion unit 11. Thus, it is possible to suppress degradation of the photoelectric conversion efficiency of the photoelectric conversion unit 11.

[0124] According to the first embodiment, the capacitance switching transistor 61 as a switch is inserted between the additional capacitance element 62 and the charge holding unit 12. Thus, when the charge holding unit 12 is used with a low capacitance, leakage current generated in the additional capacitance element 62 can be prevented from mixing into the charge holding unit 12.

[0125] Therefore, degradation of the photoelectric conversion characteristics (photoelectric conversion efficiency) can be suppressed, and degradation of the image quality of the solid-state imaging device can be suppressed.

[0126] 3. Second embodiment

[0127] The following will refer to Figures 8 to 12 A second embodiment of a pixel to which the present technology is applied will be described.

[0128] Figure 8 : shows an equivalent circuit of a pixel 51B according to the second embodiment, Fig. 9 A cross-sectional structure of a pixel 51B according to the second embodiment is shown.

[0129] The first embodiment described above is constructed in such a way that the reset transistor 13 and the capacitance switching transistor 61 are connected in parallel. Figure 8 As shown, the capacitance switching transistor 61 is inserted between the reset transistor 13 and the charge holding unit 12, and the reset transistor 13 and the capacitance switching transistor 61 are connected in series.

[0130] More specifically, the source of the capacitance switching transistor 61 is connected to the charge holding unit 12, and the drain thereof is connected to the source of the reset transistor 13 and one end of the additional capacitance element 62. The connection node 64 is a connection point of the reset transistor 13, the capacitance switching transistor 61 and the additional capacitance element 62.

[0131] exist Fig. 9 In the cross-sectional structure of the pixel 51B shown, an n-type diffusion layer 72 serving as the source of the reset transistor 13 and the drain of the capacitance switching transistor 61 is newly added. The n-type diffusion layer 72 is connected to the n-type diffusion layer 71 at one end of the additional capacitance element 62 in the substrate, or is connected thereto via a metal wiring 73 provided in the insulating layer 27. Thus, the n-type diffusion layer 71 of the additional capacitance element 62 is connected to the charge holding unit 12 via the capacitance switching transistor 61.

[0132] Second drive

[0133] The following will refer to Fig.10 The timing chart of FIG. 1 illustrates how to drive the pixel 51B according to the second embodiment (second drive).

[0134] Fig.10 How to drive when high capacitance is selected shown in A is the same as how to drive when high capacitance is selected according to the first embodiment, so the description thereof will be omitted.

[0135] On the other hand, when the low capacitance is selected, the reset transistor 13 is always turned on, and the capacitance switching transistor 61 operates as the reset transistor 13 instead.

[0136] Specifically, after the selection transistor 15 is turned on at time t31, the capacitance switching transistor 61 is turned on at time t32 and turned off at time t33. Thus, the voltage of the charge holding unit 12 is reset to the initial state.

[0137] Thereafter, at time t34, the selection transistor 15 is turned off and then starts accumulating signal charges.

[0138] After the accumulation of the signal charge is completed, the selection transistor 15 is turned on at time t35 , thereby outputting the signal charge accumulated in the charge holding unit 12 to a memory or the like in the AD conversion unit via the column signal line 16 .

[0139] After the reading of the accumulated signal charge is completed, the selection transistor 15 is turned off at time t36.

[0140] Effects of the Second Embodiment

[0141] The following will refer to Fig.11 and Fig.12The difference between the first embodiment and the second embodiment will be described.

[0142] In the pixel 51A according to the first embodiment, when the low capacitance is selected, the connection node 63 ( Figure 5 ) is a floating node.

[0143] Fig.11 The state of the pixel 51A according to the first embodiment when the low capacitance is selected is shown.

[0144] Generally, there is a parasitic capacitance between the connection node 63 and the charge holding unit 12, and there is a concern that when the reset signal level is read and the accumulated signal level is read after the signal charge is accumulated, the potential of the connection node 63 changes, and the potential of the charge holding unit 12 changes due to coupling, which causes noise of the signal charge. In addition, since the connection node 63 is connected to the charge holding unit 12 via the capacitance switching transistor 61, there is a concern that a leakage current occurring during the accumulation of the signal charge is mixed into the charge holding unit 12.

[0145] On the contrary, Fig.12 The state of the pixel 51B according to the second embodiment when the low capacitance is selected is shown.

[0146] As described above, in the pixel 51B, the capacitance switching transistor 61 is inserted between the reset transistor 13 and the charge holding unit 12, and when the low capacitance is selected, the reset transistor 13 is always controlled to be turned on. Fig.12 As shown, the connection node 64 ( Figure 8 ) is fixed to the power supply voltage VDD, thereby suppressing the potential change of the charge holding unit 12 caused by coupling. In addition, all the leakage current appearing at the connection node 64 is discharged to the drain of the reset transistor 13, thereby suppressing the leakage current from mixing into the charge holding unit 12.

[0147] Therefore, the structure of the pixel 51B according to the second embodiment can suppress the potential change of the charge holding unit 12 due to coupling when the low capacitance is selected, and suppress the leakage current that occurs in the first embodiment from mixing into the charge holding unit 12. Therefore, in addition to the effects of the first embodiment described above, according to the second embodiment, it is possible to further suppress the degradation of the image quality of the solid-state imaging device.

[0148] 4. Third embodiment

[0149] The following will refer to Figures 13 to 16 A third embodiment of a pixel to which the present technology is applied will be described.

[0150] Fig.13 : shows an equivalent circuit of a pixel 51C according to the third embodiment, Fig.14 A cross-sectional structure of a pixel 51C according to the third embodiment is shown.

[0151] The first and second embodiments described above use electrons as signal charges, but the third embodiment differs from the first and second embodiments in that holes are used as signal charges.

[0152] Since holes are employed as signal charges, the power supply voltage VDD is applied to the upper electrode 29A at one end of the photoelectric conversion unit 11. In addition, the reset transistor 13 is connected to GND instead of the power supply voltage VDD.

[0153] In the second embodiment Fig. 9 In the embodiment, the n-type diffusion layer 23 in the P-type semiconductor substrate 21 is shared by the reset transistor 13 and the amplifier transistor 14. However, according to the third embodiment, Fig.14 As shown, n-type diffusion layer 23A of reset transistor 13 and n-type diffusion layer 23B of amplifier transistor 14 are formed separately. Then, n-type diffusion layer 23A of reset transistor 13 is connected to ground GND, and n-type diffusion layer 23B of amplifier transistor 14 is connected to power supply voltage VDD.

[0154] The other components according to the third embodiment are similar to those according to the above-described second embodiment, and how to drive the pixels is similar to the reference pixel. Fig.10 The second drive described is similar, so its description is omitted.

[0155] Effects of the Third Embodiment

[0156] The following will refer to Fig.15 and Fig.16 The difference between the second embodiment and the third embodiment will be described.

[0157] Fig.15 The state of the second embodiment is shown when a high capacitance is selected.

[0158] When the high capacitance is selected, the potential at the bottom of the gate portion 61GT of the capacitance switching transistor 61 changes according to the amount of signal charge. When the charge holding unit 12 is reset by the power supply voltage VDD, the bottom of the gate portion 61GT of the capacitance switching transistor 61 has fewer electrons immediately after the reset and is in a weak inversion state, such as Fig.15 Then, as the charge accumulates, the state changes to an inverted state, as shown in Fig.15As shown in B. Therefore, the capacitance at the bottom of the gate portion 61GT of the capacitance switching transistor 61 changes, and the QV conversion efficiency changes according to the signal charge. This phenomenon deteriorates the linear characteristics of the solid-state imaging device. By the way, although the second embodiment is used here for explanation, a similar phenomenon can also be caused according to the first embodiment.

[0159] Fig.16 The state of the third embodiment is shown when a high capacitance is selected.

[0160] According to the third embodiment, it is assumed that the reset potential of the charge holding unit 12 is GND. In addition, the signal charges are holes. Therefore, according to the third embodiment, Fig.16 As shown in A in FIG. 1 , the bottom of the gate portion 61GT of the capacitance switching transistor 61 in the strong inversion state is used, and as Fig.16 As shown in B, the bottom of the gate portion 61GT of the capacitance switching transistor 61 gradually changes to an inverted state. Therefore, depletion of the gate portion 61GT of the capacitance switching transistor 61 can be suppressed during signal charge accumulation, and broken linearity caused by capacitance change can be suppressed.

[0161] In addition, the charge holding unit 12 is reset to the same GND potential as the P-type semiconductor substrate (P well) 21, thereby suppressing the potential difference between the charge holding unit 12 and the P-type semiconductor substrate 21 under low illumination and suppressing noise under low illumination.

[0162] Therefore, in addition to the effects of the above-mentioned first and second embodiments, the structure of the pixel 51C according to the third embodiment can also suppress the linear collapse caused by the change of capacitance, and can suppress the noise in the charge retention unit 12 at low illumination, thereby further suppressing the image quality degradation of the solid-state imaging device.

[0163] 5. Fourth embodiment

[0164] The following will refer to Figures 17 to 20 A fourth embodiment of a pixel to which the present technology is applied will be described.

[0165] Fig.17 : shows an equivalent circuit of a pixel 51D according to the fourth embodiment, Fig.18 A cross-sectional structure of a pixel 51D according to the fourth embodiment is shown.

[0166] Fig.17 The equivalent circuit of the pixel 51D shown is different from that of the third embodiment described above in that the node of the additional capacitance element 62 located on the side opposite to the connection node 64 closer to the reset transistor 13 is not connected to the power supply voltage VDD but to the ground GND.

[0167] exist Fig.18 In the cross-sectional structure of the pixel 51D shown, the gate portion 62GT of the additional capacitance element 62 as a MOS capacitor is connected to the n-type diffusion layer 72 of the capacitance switching transistor 61 via the metal wiring 81 provided in the insulating layer 27, and the gate portion 62GT of the additional capacitance element 62 is connected to the charge holding unit 12 via the capacitance switching transistor 61. The n-type diffusion layer 71 of the additional capacitance element 62 is grounded GND. Other aspects are similar to those of the third embodiment described above.

[0168] Effects of the Fourth Embodiment

[0169] The following will refer to Fig.19 and Fig. 20 The difference between the third embodiment and the fourth embodiment will be described.

[0170] Fig.19 The state of the third embodiment is shown when a high capacitance is selected.

[0171] The saturation charge amount of the charge holding unit 12 is determined by the capacitance of the charge holding unit 12 when the high capacitance is selected and the range of voltage available to the charge holding unit 12. To increase the saturation charge amount, high capacitance needs to be added to the charge holding unit 12.

[0172] In the pixel 51C according to the third embodiment, the additional capacitance element 62 is constituted by a MOS capacitor, such as Fig.14 As shown, the n-type diffusion layer 71 as a node of the additional capacitance element 62 closer to the P-type semiconductor substrate 21 is connected to the charge holding unit 12 .

[0173] The node of the additional capacitance element 62 closer to the P-type semiconductor substrate 21 has a pn junction and generates leakage current. Therefore, this configuration has a problem that when the area of ​​the additional capacitance element 62 is increased to increase the saturation charge amount, the leakage current flowing into the charge holding unit 12 increases.

[0174] In addition, similar to the third embodiment, there is also a concern about increased leakage current in the first and second embodiments. Incidentally, according to the third embodiment, when a high capacitance is selected, increased leakage current occurs under high illumination, whereas according to the first and second embodiments, increased leakage current occurs under low illumination because the signal charge is electrons.

[0175] In contrast, Fig. 20 The state of the fourth embodiment is shown when a high capacitance is selected.

[0176] In the pixel 51D according to the fourth embodiment, the gate portion 62GT of the additional capacitance element 62 constituted by a MOS capacitor is connected to the charge holding unit 12. Therefore, even if leakage current is generated in the n-type diffusion layer 71 of the MOS capacitor as a pn junction, the leakage current flows to GND, whereby the leakage current of the charge holding unit 12 can be suppressed when the area of ​​the additional capacitance element 62 is increased.

[0177] In addition, in the pixel 51D of the fourth embodiment, the gate portion 62GT of the additional capacitance element 62 is at the GND potential under low illumination. Therefore, the n-type diffusion layer 71 of the additional capacitance element 62 closer to the P-type semiconductor substrate 21 is assumed to be at the GND potential. Thus, the bottom of the gate portion 62GT of the additional capacitance element 62 can be suppressed from being depleted, and the reduction in the capacitance of the additional capacitance element 62 can be suppressed. Therefore, the change in the QV conversion efficiency with respect to the signal charge amount can be suppressed.

[0178] Therefore, in addition to the effects of the first to third embodiments, the structure of the pixel 51D according to the fourth embodiment can suppress leakage current in the charge holding unit 12 when the capacitance is increased, and can achieve an increase in the dynamic range of the solid-state imaging device and suppression of noise. Therefore, it is possible to further suppress the degradation of the image quality of the solid-state imaging device.

[0179] 6. Fifth embodiment

[0180] The following will refer to Figure 21 to Figure 22 A fifth embodiment of a pixel to which the present technology is applied will be described.

[0181] Fig.21 : shows an equivalent circuit of a pixel 51E according to the fifth embodiment, Fig. 22 A cross-sectional structure of a pixel 51E according to the fifth embodiment is shown.

[0182] like Fig.21 As shown, the equivalent circuit of the pixel 51E is composed of a pixel circuit 101G for green light as the first wavelength light and a pixel circuit 101RB for red light as the second wavelength light and blue light as the third wavelength light.

[0183] The structure of the green light pixel circuit 101G is Fig.17 The configuration of the pixel 51D according to the fourth embodiment shown is the same.

[0184] That is, the pixel circuit 101G has a photoelectric conversion unit 111G, a charge holding unit 112G, a reset transistor 113G, an amplification transistor 114G, a selection transistor 115G, a capacitance switching transistor 161G, and an additional capacitance element 162G.

[0185] The photoelectric conversion unit 111G, the charge holding unit 112G, the reset transistor 113G, the amplifying transistor 114G, the selection transistor 115G, the capacitance switching transistor 161G, and the additional capacitance element 162G in the pixel circuit 101G correspond to Fig.17 The photoelectric conversion unit 11, the charge holding unit 12, the reset transistor 13, the amplification transistor 14, the selection transistor 15, the capacitance switching transistor 61 and the additional capacitance element 62 in the pixel 51D shown.

[0186] On the other hand, in the pixel circuit 101RB for red light and blue light, a photoelectric conversion unit and a transfer transistor are provided for red light and blue light, respectively, and other components are shared by red light and blue light.

[0187] More specifically, the pixel circuit 101RB has a photoelectric conversion unit 111R, a photoelectric conversion unit 111B, a transfer transistor 191R, a transfer transistor 191B, a charge holding unit 112RB, a reset transistor 113RB, an amplification transistor 114RB, a selection transistor 115RB, a capacitance switching transistor 161RB, and an additional capacitance element 162RB.

[0188] The photoelectric conversion unit 111R accumulates charges obtained by receiving red light and photoelectrically converting it. The photoelectric conversion unit 111B accumulates charges obtained by receiving blue light and photoelectrically converting it.

[0189] When the transfer signal TG(R) supplied to the gate of the transfer transistor 191R is turned on, the transfer transistor 191R transfers the signal charge generated in the photoelectric conversion unit 111R to the charge holding unit 112RB as the FD unit. When the transfer signal TG(B) supplied to the gate of the transfer transistor 191B is turned on, the transfer transistor 191B transfers the signal charge generated in the photoelectric conversion unit 111B to the charge holding unit 112RB as the FD unit.

[0190] The charge holding unit 112RB holds the signal charge transferred from the photoelectric conversion unit 111R or 111B.

[0191] When the reset signal RST(RB) supplied to the gate of the reset transistor 113RB is turned on, the reset transistor 113RB resets the potentials of the charge holding unit 112RB and the additional capacitance element 162RB.

[0192] The gate of the amplifier transistor 114RB is connected to the charge holding unit 112RB, the drain thereof is connected to the power supply voltage VDD, and the source thereof is connected to the drain of the selection transistor 115RB. The amplifier transistor 114RB outputs a pixel signal according to the potential of the charge holding unit 112RB.

[0193] The drain of the selection transistor 115RB is connected to the source of the amplifier transistor 114RB, and the source of the selection transistor 115RB is connected to the column signal line 16. When the selection signal SEL (RB) supplied to the gate of the selection transistor 115RB selects the pixel circuit 101RB, the selection transistor 115RB is turned on and outputs a pixel signal corresponding to the red light or the blue light received by the pixel 51E to the AD conversion unit via the column signal line 16.

[0194] The drain of the capacitance switching transistor 161RB is connected to the source of the reset transistor 113RB and one end of the additional capacitance element 162RB, and the source of the capacitance switching transistor 161RB is connected to the charge holding unit 112RB. The power supply voltage VDD is applied to the other end of the additional capacitance element 162RB not connected to the reset transistor 113RB.

[0195] Fig. 22 A cross-sectional structure of a pixel 51E according to the fifth embodiment is shown.

[0196] In the pixel 51E, the photoelectric conversion unit 111G is formed on the light incident surface of the P-type semiconductor substrate 21 through the protective film (insulating film) 201. The photoelectric conversion unit 111G is constructed in such a way that the photoelectric conversion film 202 is clamped between the upper electrode 203A and the lower electrode 203B. The material of the photoelectric conversion film 202 adopts a material that can photoelectrically convert green light and transmit red light and blue light. The organic photoelectric conversion film for photoelectrically converting green wavelength light can adopt organic photoelectric conversion materials including rhodamine-based pigments, merocyanine-based pigments, quinacridone, etc. For example, the upper electrode 203A and the lower electrode 203B are made of a transparent electrode film such as an indium tin oxide (ITO) film or an indium zinc oxide film.

[0197] In addition, when the photoelectric conversion film 202 is an organic photoelectric conversion film for photoelectrically converting red wavelength light, for example, an organic photoelectric conversion material containing a phthalocyanine-based pigment can be used. In addition, when the photoelectric conversion film 202 is an organic photoelectric conversion film for photoelectrically converting blue wavelength light, for example, an organic photoelectric conversion material containing a coumarin-based pigment, tris-8-hydroxyquinoline aluminum (Alq3, tris-8-hydroxyquinoline Al), a merocyanine pigment, etc. can be used. The on-chip lens 32 is formed on the photoelectric conversion unit 111G.

[0198] Two n-type semiconductor regions 204 and 205 are formed in a stacked manner in the depth direction in the P-type semiconductor substrate 21, and the photodiodes PD1 and PD2 are formed by two PN junctions. Due to the difference in light absorption coefficient, the photodiode PD1 performs photoelectric conversion on blue light, and the photodiode PD2 performs photoelectric conversion on red light. Parts of the two n-type semiconductor regions 204 and 205 are formed to reach the bottom of the P-type semiconductor substrate 21.

[0199] The pixel transistor in the pixel 51E is formed at the lower surface of the P-type semiconductor substrate 21 opposite to the surface where the photoelectric conversion unit 111G and the like are formed.

[0200] Specifically, the green light reset transistor 113G is composed of a gate portion 113GT on a P-type semiconductor substrate 21 and n-type diffusion layers 223A and 272 in the P-type semiconductor substrate 21, and the amplifier transistor 114G is composed of a gate portion 114GT on a P-type semiconductor substrate 21 and n-type diffusion layers 223B and 224 in the P-type semiconductor substrate 21.

[0201] In addition, the selection transistor 115G is composed of a gate portion 115GT on the P-type semiconductor substrate 21 and n-type diffusion layers 224 and 225 in the P-type semiconductor substrate 21. The n-type diffusion layer 224 is shared by the amplification transistor 114G and the selection transistor 115G.

[0202] The capacitance switching transistor 161G is composed of a gate portion 161GT on a P-type semiconductor substrate 21 and n-type diffusion layers 272 and 222 in the P-type semiconductor substrate 21, and the additional capacitance element 162G constructed as a MOS capacitor is composed of a gate portion 162GT on the P-type semiconductor substrate 21 and an n-type diffusion layer 271 in the P-type semiconductor substrate 21.

[0203] The gate portion 162GT of the additional capacitance element 162G in the MOS capacitor is connected to the n-type diffusion layer 272 of the capacitance switching transistor 161G via a metal wiring 281 provided in the insulating layer 237 , and the n-type diffusion layer 271 of the additional capacitance element 162G is connected to the ground GND.

[0204] Assume that the signal charges generated by receiving green light are holes, and the upper electrode 203A of the photoelectric conversion film 202 is supplied with the power supply voltage VDD. The lower electrode 203B of the photoelectric conversion film 202 is connected to the n-type diffusion layer 222 at one end of the source / drain of the capacitance switching transistor 161G and the gate portion 114GT of the amplifying transistor 114G via the metal wiring conductor 227, and the structure as a whole is the charge holding unit 112G. In addition, in the P-type semiconductor substrate 21, the wiring conductor 227 is covered with an insulating film 228 such as SiO2 or SiN so that the wiring conductor 227 is insulated.

[0205] In addition, the blue light transfer transistor 191B is composed of a gate portion 191BGT on a P-type semiconductor substrate 21, an n-type semiconductor region 204 in the P-type semiconductor substrate 21, and an n-type diffusion layer 231, and the red light transfer transistor 191R is composed of a gate portion 191RGT on a P-type semiconductor substrate 21, an n-type semiconductor region 205 in the P-type semiconductor substrate 21, and an n-type diffusion layer 231.

[0206] In addition, the reset transistor 113RB is composed of a gate portion 113RBGT on the P-type semiconductor substrate 21 and n-type diffusion layers 234 and 235 in the P-type semiconductor substrate 21, and the amplifier transistor 114RB is composed of a gate portion 114RBGT on the P-type semiconductor substrate 21 and n-type diffusion layers 235 and 236 in the P-type semiconductor substrate 21. The n-type diffusion layer 235 is applied with a power supply voltage VDD and is shared by the reset transistor 113RB and the amplifier transistor 114RB.

[0207] The selection transistor 115RB is composed of a gate portion 115RBGT on the P-type semiconductor substrate 21 and n-type diffusion layers 236 and 225 in the P-type semiconductor substrate 21. The n-type diffusion layer 225 is shared by the selection transistor 115G and the selection transistor 115RB.

[0208] The capacitance switching transistor 161RB is composed of a gate portion 161RBGT on a P-type semiconductor substrate 21 and n-type diffusion layers 233 and 234 in the P-type semiconductor substrate 21, and the additional capacitance element 162RB constructed as a MOS capacitor is composed of a gate portion 162RBGT on the P-type semiconductor substrate 21 and an n-type diffusion layer 232 in the P-type semiconductor substrate 21.

[0209] The gate portion 162RBGT of the additional capacitance element 162RB in the MOS capacitor is connected to the n-type diffusion layer 234 of the capacitance switching transistor 161RB via the metal wiring 282 provided in the insulating layer 237 , and the n-type diffusion layer 232 of the additional capacitance element 62RB is connected to the power supply voltage VDD.

[0210] The n-type diffusion layer 231 shared by the blue light transfer transistor 191B and the red light transfer transistor 191R is an FD unit, and is connected to the n-type diffusion layer 233 at one side of the capacitance switching transistor 161RB and the gate portion 114RBGT of the amplifier transistor 114RB, and the entire structure is a charge holding unit 112RB.

[0211] The surface of the P-type semiconductor substrate 21 where the pixel transistor is formed is covered with an insulating film 237 .

[0212] In addition, due to the limitation of the diagram, although Fig. 22 Although the plurality of n-type diffusion layers shared as the source or drain of the pixel transistor are shown to be connected via metal wiring, it is a matter of course that a pixel may be formed of a single n-type diffusion layer.

[0213] Regarding the structure of the pixel 51E according to the fifth embodiment, the configuration of the pixel circuit 101G for green light is the same as that of Fig.17 The illustrated pixel 51D according to the fourth embodiment has the same configuration, and therefore the charge holding unit 112G for holding the green light signal can obtain effects similar to those of the fourth embodiment described above.

[0214] That is, the capacitance of the charge holding unit 112G connected to the photoelectric conversion unit 111G is controlled according to the amount of signal charge, thereby controlling the voltage amplitude of the charge holding unit 112G. That is, when there is a large amount of signal charge, the capacitance of the charge holding unit 112G increases, thereby suppressing the increase in the voltage of the charge holding unit 12G and suppressing the decrease in the voltage applied to the photoelectric conversion unit 111G. Thus, it is possible to suppress the degradation of the photoelectric conversion efficiency of the photoelectric conversion unit 111G.

[0215] Furthermore, a capacitance switching transistor 161G as a switch is inserted between the additional capacitance element 162G and the charge retention unit 112G. This prevents leakage current generated in the additional capacitance element 162G from mixing into the charge retention unit 112G when the charge retention unit 112G is used at a low capacitance.

[0216] Therefore, it is possible to suppress degradation of the photoelectric conversion characteristics (photoelectric conversion efficiency) and to suppress degradation of the image quality of the solid-state imaging device.

[0217] In addition, as referenced Fig.12As described above, when the low capacitance is selected, the reset transistor 13 is controlled to be always on, so that when the low capacitance is selected, the potential change of the charge holding unit 112G due to coupling and the leakage current mixing into the charge holding unit 112G can be suppressed.

[0218] In addition, as referenced Fig.16 As described, the charge holding unit 112G is reset to the same GND potential as the P-type semiconductor substrate 21, and the bottom of the gate portion 61GT of the capacitance switching transistor 161G is used from a strong inversion state, thereby suppressing linear collapse caused by capacitance changes and suppressing noise of the charge holding unit 112G under low illumination.

[0219] In addition, even if leakage current occurs in the n-type diffusion layer 271 of the additional capacitance element 162G, the leakage current will flow to GND, so the leakage current in the charge retention unit 112G can be suppressed when the capacitance is increased, and the dynamic range of the solid-state imaging device can be increased and noise can be suppressed.

[0220] Due to the above-mentioned effects, it is possible to further suppress the degradation of the image quality of the solid-state imaging device.

[0221] In addition, regarding the structure of the pixel 51E according to the fifth embodiment, in addition to the charge holding unit 112G for green light, a charge holding unit 112RB for holding the signals of red light and blue light that are photoelectrically converted is also provided, and the capacitance of the charge holding unit 112RB can be controlled independently of the green signal by using a capacitance switching transistor 161RB and an additional capacitance element 162RB.

[0222] Thus, the gains of R, G, and B can be controlled differently according to the color of the subject. For example, when shooting a green object, the capacitance value of the green light charge holding unit 112G is increased, thereby suppressing the amplification rate of the green signal; when reading the red (Red) signal and the blue (Blue) signal, the capacitance value of the red and blue light charge holding unit 112RB is reduced, thereby setting the signal amplification rate to a high value. Therefore, for different subjects, the S / N ratio of the shooting signal can be improved while suppressing the sensitivity degradation of the photoelectric conversion unit.

[0223] In addition, for Fig. 22 In the pixel structure shown, a photoelectric conversion unit (photoelectric conversion unit 111G) for photoelectrically converting one color of light is formed outside a P-type semiconductor substrate 21, and a photoelectric conversion unit (photodiodes PD1 and PD2 formed by two PN junctions) for photoelectrically converting two colors of light is formed in the P-type semiconductor substrate 21.

[0224] However, it is also possible to configure that a photoelectric conversion unit for photoelectrically converting two colors of light is formed outside the P-type semiconductor substrate 21, and a photoelectric conversion unit for photoelectrically converting one color of light (a photodiode PD formed by a PN junction) is formed in the P-type semiconductor substrate 21. In this case, the photoelectric conversion film 202 includes two layers of films, for example, a photoelectric conversion film for photoelectrically converting green light and a photoelectric conversion film for photoelectrically converting blue light. Alternatively, a structure in which the photoelectric conversion film 202 is sandwiched between the upper electrode 203A and the lower electrode 203B can be stacked.

[0225] 7. Exemplary Schematic Configuration of Solid-State Imaging Device

[0226] Fig.23 The pixels of the solid-state imaging device shown can adopt the above-mentioned pixels 51A to 51E. That is, Fig.23 : is a schematic configuration showing a solid-state imaging device to which the present technology is applied.

[0227] Fig.23 The solid-state imaging device 301 is configured to include: a pixel array section 303 in which pixels 302 are arranged in a two-dimensional matrix shape, and a peripheral circuit unit surrounding the pixel array section is provided on a semiconductor substrate 312 using, for example, silicon (Si) as a semiconductor. The peripheral circuit unit includes a vertical drive circuit 304, a column signal processing circuit 305, a horizontal drive circuit 306, an output circuit 307, a control circuit 308, and the like.

[0228] The pixel 302 adopts any configuration of the above-described pixels 51A to 51E.

[0229] The control circuit 308 receives input clocks and data for indicating an operation mode and the like, and outputs data such as internal information of the solid-state imaging device 301. That is, the control circuit 308 generates a clock signal or a control signal as an operation reference of the vertical drive circuit 304, the column signal processing circuit 305, and the horizontal drive circuit 306 based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock. Then, the control circuit 308 outputs the generated clock signal or the control signal to the vertical drive circuit 304, the column signal processing circuit 305, the horizontal drive circuit 306, and the like.

[0230] The vertical drive circuit 304 is composed of, for example, a shift register, and selects a predetermined pixel drive wiring 310, supplies a pulse for driving the pixel 302 to the selected pixel drive wiring 310, and drives the pixel 302 in row units. That is, the vertical drive circuit 304 sequentially selects and scans the pixels 302 in the pixel array section 303 in the vertical direction in row units, and supplies a pixel signal based on a signal charge generated according to the amount of light received in the photoelectric conversion unit in each pixel 302 to the column signal processing circuit 305 via a vertical signal line 309.

[0231] The vertical drive circuit 304 controls the above-mentioned reset signals RST, RST(G) and RST(RB); selection signals SEL, SEL(B) and SEL(RB); switching control signals CapSEL, CapSEL(G) and CapSEL(RB) and transmission signals TG(R), TG(B), etc. via the pixel drive wiring 310.

[0232] For example, each of the column signal processing circuits 305 is arranged for each column of the pixels 302, and performs signal processing such as noise removal on a pixel column basis for signals output from one row of pixels 302. For example, the column signal processing circuit 305 performs signal processing such as CDS or AD conversion to remove pixel-specific fixed pattern noise.

[0233] The horizontal drive circuit 306 is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses, sequentially selects the column signal processing circuits 305 , and outputs a pixel signal from each column signal processing circuit 305 to a horizontal signal line 311 .

[0234] The output circuit 307 performs signal processing on the signals sequentially supplied from each column signal processing circuit 305 via the horizontal signal line 311, and outputs the processed signals. For example, the output circuit 307 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The I / O port 313 exchanges signals with the outside.

[0235] The solid-state imaging device 301 configured as above is a CMOS image sensor of a column AD system in which a column signal processing circuit 5 for performing CDS processing and AD conversion processing is arranged for each pixel column.

[0236] The pixel 302 in the solid-state imaging device 301 can adopt any structure of the pixels 51A to 51E, and therefore, it is possible to suppress degradation of the photoelectric conversion characteristics (photoelectric conversion efficiency) and suppress degradation of the image quality of the solid-state imaging device.

[0237] 8. Exemplary Applications of Electronic Devices

[0238] The present technology is not limited to application to solid-state imaging devices. That is, the present technology can be applied to all electronic devices that use solid-state imaging devices for image acquisition units (photoelectric conversion units), including shooting devices such as digital cameras or video cameras, portable terminal devices with shooting functions, and copiers that use solid-state imaging devices as image reading units. The solid-state imaging device can be formed as a single chip, or it can be a module with a shooting function in which a shooting unit and a signal processing unit or an optical system are collectively packaged.

[0239] Fig.24 : is a block diagram showing an exemplary configuration of a photographing device as an electronic device to which the present technology is applied.

[0240] Fig.24 The illustrated photographing apparatus 401 includes an optical system 402 , a shutter device 403 , a solid-state imaging device 404 , a control circuit 405 , a signal processing circuit 406 , a monitor 407 , and a memory 408 , and is capable of photographing still images and moving images.

[0241] The optical system 402 is composed of one or more lenses, guides light (incident light) from a subject to the solid-state imaging device 404 , and forms an image on a light receiving surface of the solid-state imaging device 404 .

[0242] The shutter device 403 is arranged between the optical system 402 and the solid-state imaging device 404 , and controls a light irradiation period and a light shielding period of the solid-state imaging device 404 under the control of the control circuit 405 .

[0243] The solid-state imaging device 404 is composed of the above-mentioned solid-state imaging device 301 (that is, a solid-state imaging device in which degradation of the photoelectric conversion characteristics is suppressed and degradation of the image quality is suppressed). The solid-state imaging device 404 accumulates signal charges for a period of time according to the imaging light imaged on the light receiving surface through the optical system 402 and the shutter device 403. In response to the drive signal (timing signal) supplied from the control circuit 405, the signal charge accumulated in the solid-state imaging device 404 is transmitted. The solid-state imaging device 404 can be constructed as a single single chip, and can be constructed as a part of a camera module packaged together with the optical system 402 or the signal processing circuit 406.

[0244] The control circuit 405 is composed of, for example, a central processing unit (CPU) and outputs a drive signal for controlling the transfer operation of the solid-state imaging device 404 and the shutter operation of the shutter device 403 , thereby driving the solid-state imaging device 404 and the shutter device 403 .

[0245] The user (operator) gives instructions through an operation unit (not shown) so that the camera 401 can select operation under high capacitance setting or operation under low capacitance setting. The control circuit 405 instructs the solid-state imaging device 404 to adopt high capacitance setting or low capacitance setting according to the setting information specified by the user.

[0246] In addition, the control circuit 405 can obtain the brightness of the subject in the captured image from the signal processing circuit 406, can (automatically) select the high capacitance setting or the low capacitance setting for capturing the next frame, and can instruct the solid-state imaging device 404. The solid-state imaging device 404 controls the capacitance switching transistor 61, 161G, or 161RB of each pixel 302 (pixel 51) based on the instruction from the control circuit 405.

[0247] The signal processing circuit 406 is constituted by, for example, a digital signal processor (DSP) or the like, and performs various signal processing on the pixel signal output from the solid-state imaging device 404. An image (image data) obtained by the signal processing performed by the signal processing circuit 406 is supplied to the monitor 407 and displayed thereon, or supplied to the memory 408 and stored (recorded) therein.

[0248] As described above, the solid-state imaging device 404 adopts the solid-state imaging device having the structure of the pixel 51 according to each of the above-described embodiments, thereby suppressing the degradation of the photoelectric conversion characteristics and suppressing the degradation of the image quality. Therefore, even in the imaging device 401 such as a video camera, a digital camera, or a camera module for a mobile device such as a mobile phone, higher image quality can be achieved.

[0249] The embodiments of the present technology are not limited to the above-described embodiments, and various changes may be made without departing from the scope of the present technology.

[0250] For example, a P-type or N-type semiconductor region on a semiconductor substrate may be composed of semiconductor regions of opposite conductivity types.

[0251] In addition, the present technology is not limited to solid-state imaging devices for detecting the distribution of the amount of incident visible light and capturing it as an image. The present technology is applicable to all solid-state imaging devices (physical quantity distribution detection devices), such as solid-state imaging devices for capturing the distribution of the amount of incident infrared rays, X-rays or particles as an image, and fingerprint detection sensors in a broad sense for detecting the distribution of other physical quantities (such as pressure or electrostatic capacitance) and capturing it as an image.

[0252] The above embodiments may be combined in whole or in part. For example, although the green light pixel circuit 101G according to the fifth embodiment has the same Fig.17The pixel 51D of the fourth embodiment shown in FIG. 1 has the same configuration as that of the pixel 51D of the fourth embodiment, but other than that, any configuration of the pixels 51A to 51C according to the first to third embodiments may be adopted.

[0253] In addition, the present technology is not limited to solid-state imaging devices, and can be applied to all semiconductor devices having other semiconductor integrated circuits.

[0254] Furthermore, the effects described in the specification are merely exemplary and not restrictive, and effects other than the effects described in the specification may be obtained.

[0255] Furthermore, the present technology can adopt the following configurations. (1)

[0257] A solid-state imaging device, comprising a pixel, wherein the pixel has:

[0258] a photoelectric conversion unit formed outside the semiconductor substrate;

[0259] a charge holding unit for holding a signal charge generated by the photoelectric conversion unit and directly connected to the photoelectric conversion unit;

[0260] a reset transistor, the reset transistor being used to reset the potential of the charge holding unit;

[0261] a capacitance switching transistor connected to the charge holding unit and used for switching the capacitance of the charge holding unit; and

[0262] An additional capacitance element is connected to the capacitance switching transistor. (2)

[0264] The solid-state imaging device according to (1),

[0265] The capacitance switching transistor is connected between the reset transistor and the charge holding unit. (3)

[0267] The solid-state imaging device according to (2),

[0268] When the capacitance of the charge holding unit is switched to a low capacitance by the capacitance switching transistor, the reset transistor is controlled to be always turned on. (4)

[0270] The solid-state imaging device according to (2),

[0271] The reset transistor resets the potential of the charge holding unit to the same potential as that of the semiconductor substrate. (5)

[0273] The solid-state imaging device according to (4),

[0274] The reset transistor resets the potential of the charge holding unit to GND. (6)

[0276] The solid-state imaging device according to any one of (1) to (5),

[0277] Wherein, the additional capacitance element is composed of a MOS capacitor. (7)

[0279] The solid-state imaging device according to (6),

[0280] Wherein, a gate portion of the MOS capacitor is connected to the charge holding unit. (8)

[0282] The solid-state imaging device according to (6),

[0283] The MOS capacitor is connected to the charge holding unit through a diffusion layer in the semiconductor substrate. (9)

[0285] The solid-state imaging device according to any one of (1) to (3), (6) and (8),

[0286] The reset transistor resets the potential of the charge holding unit to a power supply voltage. (10)

[0288] The solid-state imaging device according to any one of (1) to (9),

[0289] Wherein, the capacitance switching transistor and the reset transistor are connected in series. (11)

[0291] The solid-state imaging device according to (1),

[0292] Wherein, the capacitance switching transistor and the reset transistor are connected in parallel. (12)

[0294] The solid-state imaging device according to any one of (1) to (11),

[0295] The photoelectric conversion unit is constructed in such a way that a photoelectric conversion film is sandwiched between an upper electrode and a lower electrode. (13)

[0297] The solid-state imaging device according to any one of (1) to (12),

[0298] The pixel further includes a different photoelectric conversion unit located above or below the photoelectric conversion unit. (14)

[0300] The solid-state imaging device according to (13),

[0301] Wherein, the different photoelectric conversion units are photodiodes formed on the semiconductor substrate. (15)

[0303] The solid-state imaging device according to (1),

[0304] The signal charges generated by the photoelectric conversion unit are holes. (16)

[0306] The solid-state imaging device according to (1),

[0307] The signal charges generated by the photoelectric conversion unit are electrons. (17)

[0309] An electronic device including a solid-state imaging device, the solid-state imaging device including a pixel, the pixel having:

[0310] a photoelectric conversion unit formed outside the semiconductor substrate;

[0311] a charge holding unit for holding a signal charge generated by the photoelectric conversion unit and directly connected to the photoelectric conversion unit;

[0312] a reset transistor, the reset transistor being used to reset the potential of the charge holding unit; a capacitance switching transistor, the capacitance switching transistor being connected to the charge holding unit and being used to switch the capacitance of the charge holding unit; and

[0313] An additional capacitance element is connected to the capacitance switching transistor. (18)

[0315] The electronic device according to (17), further comprising:

[0316] A control circuit outputs a control signal for controlling the capacitance switching transistor. (19)

[0318] The electronic device according to (18),

[0319] The control circuit outputs a control signal for controlling the capacitance switching transistor based on an image captured by the solid-state imaging device. (20)

[0321] The electronic device according to (18) or (19),

[0322] The control circuit outputs a control signal for controlling the capacitance switching transistor based on setting information specified by a user.

[0323] Reference numerals list

[0324] 11 Photoelectric conversion unit

[0325] 12 Charge retention unit

[0326] 13 Reset transistor

[0327] 21 P-type semiconductor substrate

[0328] 28 Photoelectric conversion film

[0329] 29A Upper electrode

[0330] 29B Lower electrode

[0331] 51(51A to 51E) pixels

[0332] 61 Capacitor Switching Transistor

[0333] 62 Additional capacitance element

[0334] 101G, 101RB pixel circuit

[0335] 111B, 111G, 111R Photoelectric conversion unit

[0336] 112G, 112RB Charge Retention Unit

[0337] 113G, 113RB reset transistor

[0338] 161G, 161RB Capacitor Switching Transistors

[0339] 162G, 162RB additional capacitance element

[0340] 301 Solid-state imaging device

[0341] 302 pixels

[0342] 401 Filming Device

[0343] 404 Solid-state imaging device

[0344] 405 Control Circuit

[0345] 406 Signal Processing Circuit

Claims

1. A solid-state imaging device, comprising a pixel, wherein the pixel has: a photoelectric conversion unit formed outside the semiconductor substrate; a charge holding unit for holding a signal charge generated by the photoelectric conversion unit and directly connected to the photoelectric conversion unit; a reset transistor, the reset transistor being used to reset the potential of the charge holding unit; a capacitance switching transistor, the capacitance switching transistor being connected to the charge holding unit and used for switching the capacitance of the charge holding unit; an additional capacitance element, the additional capacitance element being connected to the capacitance switching transistor; as well as a photodiode formed in the semiconductor substrate, Wherein, in the cross-sectional view, the capacitance switching transistor is located in a region below the photodiode.

2. The solid-state imaging device according to claim 1, in, The capacitance switching transistor is connected between the reset transistor and the charge holding unit.

3. The solid-state imaging device according to claim 2, in, When the capacitance of the charge holding unit is switched to a low capacitance by the capacitance switching transistor, the reset transistor is controlled to be always turned on.

4. The solid-state imaging device according to claim 2, in, The reset transistor resets the potential of the charge holding unit to the same potential as that of the semiconductor substrate.

5. The solid-state imaging device according to claim 4, in, The reset transistor resets the potential of the charge holding unit to GND.

6. The solid-state imaging device according to claim 1, in, The additional capacitance element is formed by a MOS capacitor.

7. The solid-state imaging device according to claim 6, in, A gate portion of the MOS capacitor is connected to the charge holding unit.

8. The solid-state imaging device according to claim 6, in, The MOS capacitor is connected to the charge holding unit at a diffusion layer in the semiconductor substrate.

9. The solid-state imaging device according to any one of claims 1 to 3, 6 and 8, in, The reset transistor resets the potential of the charge holding unit to a power supply voltage.

10. The solid-state imaging device according to any one of claims 1 to 8, in, The capacitance switching transistor and the reset transistor are connected in series.

11. The solid-state imaging device according to claim 1 or 6, in, The capacitance switching transistor and the reset transistor are connected in parallel.

12. The solid-state imaging device according to any one of claims 1 to 8, in, The photoelectric conversion unit is configured in such a manner that a photoelectric conversion film is sandwiched between an upper electrode and a lower electrode.

13. The solid-state imaging device according to any one of claims 1 to 8, in, The pixel further includes a different photoelectric conversion unit located above or below the photoelectric conversion unit.

14. The solid-state imaging device according to claim 1, in, The signal charges generated by the photoelectric conversion unit are holes.

15. The solid-state imaging device according to claim 1, in, The signal charges generated by the photoelectric conversion unit are electrons. 16 . An electronic device comprising a solid-state imaging device, the solid-state imaging device being the solid-state imaging device according to claim 1 .

17. The electronic device according to claim 16, further comprising: A control circuit outputs a control signal for controlling the capacitance switching transistor.

18. The electronic device according to claim 17, in, The control circuit outputs a control signal for controlling the capacitance switching transistor based on an image captured by the solid-state imaging device.

19. The electronic device according to claim 17, in, The control circuit outputs a control signal for controlling the capacitance switching transistor based on setting information designated by a user.

Images