Display device

Abstract

A display device includes: a substrate; a display element layer disposed on the substrate and including a driving electrode; an insulating layer disposed on the display element layer and defining an effective display area and a peripheral area adjacent to the effective display area; an input sensing layer disposed on the insulating layer and including a sensing electrode overlapping the effective display area and generating a parasitic capacitance with the driving electrode and a compensation electrode overlapping the peripheral area; and a sensing control circuit electrically connected to the sensing electrode and the compensation electrode via an output node, wherein each sensing control circuit utilizes the capacitance of a first offset capacitor generated by the compensation electrode to cancel the capacitance of the parasitic capacitor input through the output node.

Description

Technical Field

[0001] This invention relates to a display device with improved touch performance. Background Technology

[0002] Various display devices are being developed for use in multimedia devices such as televisions, mobile phones, tablets, navigation devices, and game consoles. The display device may include a display module that displays images and senses external input, as well as a window. The display module may include a display panel that displays images and an input sensing layer that senses external input.

[0003] Recently, capacitive input sensing layers have been widely used. Capacitive sensing determines whether a touch has occurred by utilizing the change in capacitance between sensing electrodes when an object such as a finger touches the surface. Because this type of sensing relies on the capacitance between the touching object and the sensing electrodes of the input sensing layer, achieving stable output under various noise conditions is crucial. Summary of the Invention

[0004] The purpose of this invention is to provide a display device with improved touch performance.

[0005] A display device according to an embodiment for achieving the objectives of the present invention includes: a substrate; a display element layer disposed on the substrate and including a driving electrode; an insulating layer disposed on the display element layer and defining an effective display area and a peripheral area adjacent to the effective display area; an input sensing layer disposed on the insulating layer and including a sensing electrode overlapping the effective display area and generating a parasitic capacitance with the driving electrode and a compensation electrode overlapping the peripheral area; and a sensing control circuit electrically connected to the sensing electrode and the compensation electrode via an output node, wherein each sensing control circuit utilizes the capacitance of a first offset capacitor generated by the compensation electrode to cancel the capacitance of the parasitic capacitor input through the output node.

[0006] According to an embodiment of the present invention, the compensation electrode includes a first compensation electrode and a second compensation electrode disposed on different layers to generate the first offset capacitor.

[0007] According to an embodiment of the present invention, the input sensing layer includes: a first insulating layer disposed on the insulating layer; a first conductive layer disposed on the same layer as the first compensation electrode, i.e., on the first insulating layer; a second insulating layer disposed on the first conductive layer; and a second conductive layer overlapping the first compensation electrode and disposed on the same layer as the second compensation electrode, i.e., on the second insulating layer.

[0008] According to an embodiment of the present invention, the sensing electrode includes a first sensing electrode and a second sensing electrode that is spaced apart from the first sensing electrode on a plane and mutually compliant with the first sensing electrode. The sensing control circuit outputs a detection signal and a compensation signal that is phase-reversed with the detection signal to the first sensing electrode and the first compensation electrode, respectively.

[0009] According to an embodiment of the present invention, the sensing control circuit includes: a voltage conversion unit that senses a sensing signal output from the second sensing electrode to the output node and an offset sensing signal output from the second compensation electrode to the output node and outputs a detection voltage; and an offset control unit that includes a second offset capacitor connected to the output node.

[0010] According to an embodiment of the present invention, the capacitance of the second offset capacitor is less than the capacitance of the first offset capacitor.

[0011] According to an embodiment of the present invention, the second offset capacitor includes: a third compensation electrode for receiving an offset signal corresponding to the compensation signal; and a fourth compensation electrode connected to the output node.

[0012] According to an embodiment of the present invention, the offset control unit further includes a switch configured between the third compensation electrode and the output node.

[0013] According to an embodiment of the present invention, the second offset capacitor includes a plurality of auxiliary capacitors electrically connected to the output node and connected in parallel with each other.

[0014] According to an embodiment of the present invention, the capacitance of each of the auxiliary capacitors is less than the capacitance of the first offset capacitor.

[0015] A display device according to an embodiment of the present invention may include: a substrate defining an effective display area and a peripheral area adjacent to the effective display area; a circuit element layer disposed on the substrate and including a constant current circuit; a display element layer disposed on the circuit element layer and including a driving electrode; an input sensing layer disposed on the display element layer and including a sensing electrode overlapping the effective display area and generating a parasitic capacitance with the driving electrode; and a sensing control circuit electrically connected to the sensing electrode and the constant current circuit, wherein the sensing control circuit controls the constant current circuit to eliminate at least a portion of the component caused by the capacitance of the parasitic capacitor from the signal input from the sensing electrode.

[0016] Alternatively, the constant current circuit may be configured on the surrounding area.

[0017] The constant current circuit may include a first transistor, the first transistor including a first gate, a first source and a first drain, and the sensing control circuit including a first terminal electrically connected to the first gate, a second terminal electrically connected to the first source and a third terminal electrically connected to the first drain.

[0018] Alternatively, the second terminal may provide the signal to the constant current circuit.

[0019] Alternatively, the sensing control circuit may provide a control voltage to the first terminal to control the on / off state of the first transistor.

[0020] Alternatively, the control voltage may be provided in pulse width modulation mode.

[0021] Alternatively, the sensing control circuit may further include a ground electrode, and the third terminal is electrically connected to the ground electrode.

[0022] Alternatively, the display element layer may also include a power line supplied with power voltage, and the third terminal is electrically connected to the power line.

[0023] Alternatively, the constant current circuit may further include a second transistor, the second transistor including a second gate, a second source and a second drain, and the sensing control circuit may further include a fourth terminal electrically connected to the second gate.

[0024] Alternatively, the second source may be electrically connected to the second terminal, and the second drain may be electrically connected to the third terminal.

[0025] Alternatively, the sensing control circuit may provide a control voltage to the fourth terminal to control the on / off state of the second transistor.

[0026] (Invention Effects)

[0027] According to an embodiment of the present invention, the parasitic capacitor between the display panel and the sensing electrode can have a capacitance corresponding to the capacitance of the sensing capacitor between the external input and the sensing electrode. The sensing control circuit according to the present invention can subtract the capacitance of the parasitic capacitor using the offset capacitor generated by the compensation electrode.

[0028] In particular, the input sensing layer may include sensing electrodes and compensation electrodes forming an offset capacitor. Therefore, corresponding to the capacitance change of the parasitic capacitor based on the temperature changes inside and outside the display device, the capacitance of the offset capacitor also changes, thereby improving the signal quality sensed by the output node.

[0029] According to the present invention, the sensing control circuit can determine whether a touch has occurred based on the amount of capacitance change of a sensing capacitor provided between the sensing electrode and an external input. The sensing control circuit can control a constant current circuit configured in the display panel to eliminate at least a portion of the component caused by the capacitance of the parasitic capacitor from the signal provided by the input sensing layer. This increases the ratio of the signal change resulting from a touch to the signal before the touch. The sensing control circuit can easily sense the amount of capacitance change of the sensing capacitor. Reliability is improved for touch detection based on external input and touch location. Therefore, a display device with improved touch performance can be provided.

[0030] Furthermore, according to the present invention, the constant current circuit can be disposed inside the display module. The constant current circuit can be disposed in the display panel, thereby reducing the size of the sensing and control circuit. This reduces the size of the circuit board and the size of the bezel area of ​​the display device. Attached Figure Description

[0031] Figure 1 This is an exploded perspective view of a display device according to an embodiment of the present invention.

[0032] Figure 2 This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0033] Figure 3a This is a plan view of a display panel, a flexible substrate, and a sensing control circuit according to an embodiment of the present invention.

[0034] Figure 3b This is a cross-sectional view showing a portion of a display panel that overlaps with the display area according to an embodiment of the present invention.

[0035] Figure 3c This is a cross-sectional view of a constant current circuit according to an embodiment of the present invention.

[0036] Figure 4a This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0037] Figure 4b This is a diagram illustrating the capacitance generated during the sensing operation of the input sensing layer according to an embodiment of the present invention.

[0038] Figure 5 This is a plan view of the input sensing layer according to an embodiment of the present invention.

[0039] Figure 6 It is according to an embodiment of the present invention. Figure 5 The cross-sectional view shown is the section cut from I-I'.

[0040] Figure 7 This is a block diagram illustrating the sensing operation of the input sensing layer according to an embodiment of the present invention.

[0041] Figure 8 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to an embodiment of the present invention.

[0042] Figure 9 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to another embodiment of the present invention.

[0043] Figure 10 This is a block diagram illustrating the sensing operation of an input sensing layer according to an embodiment of the present invention.

[0044] Figure 11 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to an embodiment of the present invention.

[0045] Figure 12 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to an embodiment of the present invention.

[0046] (Explanation of reference numerals in the attached diagram)

[0047] 100: Window

[0048] 200: Display Module

[0049] 300: Circuit board

[0050] DP: Display Panel

[0051] CE: Second electrode

[0052] ISU: Input Sensing Layer

[0053] DCP: Compensation Electrode

[0054] TIC: Sensing Control Circuit

[0055] VCP: Voltage conversion section

[0056] OFP: Offset Control Unit

[0057] CF: Flexible substrate

[0058] MB: main base board Detailed Implementation

[0059] In this specification, when a constituent element (or region, layer, part, etc.) is referred to as being "on", "connected" or "combined" with other constituent elements, it means that it can be directly configured / connected / combined with other constituent elements or that a third constituent element can be configured between them.

[0060] The same reference numerals refer to the same constituent elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the constituent elements are enlarged for the purpose of effectively illustrating the technical content.

[0061] "and / or" includes all combinations that the associated structure can define.

[0062] The terms "first," "second," etc., can be used to describe various constituent elements, but these constituent elements should not be limited by these terms. The terms are used only for the purpose of distinguishing one constituent element from others. For example, without departing from the scope of the invention, a first constituent element can be named a second constituent element, and similarly, a second constituent element can be named a first constituent element. Unless explicitly indicated differently in the context, singular expressions include plural expressions.

[0063] In addition, terms such as "below," "lower side," "above," and "upper side" are used to explain the relationship between the structures shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions indicated in the accompanying drawings.

[0064] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning as in the context of the related art, and are hereby expressly defined unless interpreted as having an idealized or overly formal meaning.

[0065] Terms such as “including” or “having” should be understood as specifying the presence of features, figures, steps, actions, constituent elements, components, or combinations thereof described in the specification, without pre-excluding the presence or additional possibility of one or more other features or figures, steps, actions, constituent elements, components, or combinations thereof.

[0066] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0067] Figure 1 This is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 2 This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0068] The display device DD can be a device activated by an electrical signal. The display device DD can include various embodiments. For example, the display device DD can include a tablet computer, a laptop computer, a computer, a smart TV, etc. In this embodiment, the display device DD is illustratively illustrated as a smartphone.

[0069] Reference Figure 1The display device DD can display an image through the front FS. The front FS includes a transmission area TA and a border area BZA adjacent to the transmission area TA.

[0070] The front surface FS can be defined as parallel to the surface defined by the first direction DR1 and the second direction DR2. The normal direction of the front surface FS, i.e., the thickness direction of the display device DD, points to the third direction DR3. In this specification, "when viewed on a plane" can mean the view from the third direction DR3. The front (or top) and back (or bottom) surfaces of each layer or unit described below are distinguished by the third direction DR3. However, the directions pointed to by the first to third directions DR1, DR2, and DR3 are relative concepts and can be changed to other directions, such as the opposite directions.

[0071] The display device DD displays an image through the area TA. The image may include at least one of a still image and a moving image.

[0072] The region TA can have quadrilaterals parallel to the first direction DR1 and the second direction DR2, respectively. However, this is an illustrative diagram, and the region TA can have various shapes, and is not limited to any one embodiment.

[0073] The border region BZA may surround the transmission region TA. However, it is illustrative, and the border region BZA may be configured to be adjacent only to one side of the transmission region TA, or it may be omitted. An electronic device according to an embodiment of the present invention may include various embodiments, and is not limited to any one embodiment.

[0074] On the other hand, the display device DD according to the present invention can sense user input applied from the outside through the front FS. User input includes various forms of external input such as a part of the user's body, light, heat, or pressure. In addition, the display device DD can sense input that is in contact with the front FS, as well as input that is close to or adjacent to it.

[0075] In detail, the display device DD may include a window 100, a display module 200, a circuit board 300, and a housing 400. The window 100 and the housing 400 together define the appearance of the display device DD.

[0076] Window 100 is disposed on display module 200 and covers the front surface IS of display module 200. Window 100 may contain an optically transparent insulating material. For example, window 100 may contain glass or plastic. Window 100 may have a multilayer or single-layer structure. For example, window 100 may also have a laminated structure of multiple plastic films bonded with adhesive, or a laminated structure of a glass substrate and plastic films bonded with adhesive.

[0077] Window 100 includes a front surface exposed to the outside. The front surface FS of the aforementioned display device DD can be substantially defined by the front surface of window 100. The transmissive area TA can be an optically transparent area. The transmissive area TA can have a shape corresponding to the effective display area AA defined in display module 200. For example, the transmissive area TA overlaps with the entire surface or at least a portion of the effective display area AA. The image displayed in the effective display area AA of display module 200 can be identified from the outside through the transmissive area TA.

[0078] The border region BZA can be a region with relatively low light transmittance compared to the transmittance region TA. The border region BZA defines the shape of the transmittance region TA. The border region BZA can be adjacent to and surround the transmittance region TA.

[0079] The border area BZA can have a predetermined color. When the window 100 is provided as a glass or plastic substrate, the border area BZA can be a color layer printed or vapor-deposited on one side of the glass or plastic substrate. Alternatively, the border area BZA can also be formed by coloring a corresponding area of ​​the glass or plastic substrate.

[0080] The border area BZA can cover the peripheral area NAA of the display module 200 to cut off the recognition from the outside to the peripheral area NAA. On the other hand, it is illustrated illustratively, and in a window 100 according to an embodiment of the present invention, the border area BZA may also be omitted.

[0081] Display module 200 can display images or sense external input applied from the outside. For details, see [link to documentation]. Figure 2 The display module 200 includes a display panel DP and an input sensing layer ISU disposed on the display panel DP. The display panel DP includes a substrate BS, a circuit element layer DP-CL disposed on the substrate BS, a display element layer DP-OLED, and an insulating layer TFL.

[0082] According to embodiments of the present invention, the display panel DP can be a light-emitting display panel, and its type is not particularly limited. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can contain organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can contain quantum dots and quantum rods, etc. Hereinafter, the display panel DP will be described using an organic light-emitting display panel.

[0083] The display panel DP includes the display area DP-DA and the peripheral area DP-NDA. The display area DP-DA of the display panel DP corresponds to... Figure 1 The effective display area AA shown in the figure corresponds to the surrounding area DP-NDA. Figure 1The surrounding area NAA is shown in the image.

[0084] The substrate BS may include at least one plastic film. As a flexible substrate, the substrate BS may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0085] The circuit element layer DP-CL includes at least one intermediate insulating layer and circuit elements. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines, pixel driving circuits, etc.

[0086] The display element layer of a DP-OLED includes multiple display elements. As an example, the display elements can be organic light-emitting elements. The DP-OLED display element layer may also include organic films such as pixel-deferring films.

[0087] The insulating layer TFL seals the DP-OLED display element layer. The insulating layer TFL protects the DP-OLED display element layer from foreign matter such as moisture, oxygen, and dust particles. As an example, the insulating layer TFL can be a thin-film encapsulation layer, and can consist of more than one layer.

[0088] The input sensing layer (ISU) is directly disposed on the display panel (DP) to sense input applied from the outside (user input). In this specification, "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B. In this embodiment, the input sensing layer (ISU) can be manufactured using a process that is continuous with the display panel (DP).

[0089] Refer again Figure 1 The front side IS of the display module 200 includes an effective display area AA and a peripheral area NAA. The effective display area AA can be a display area for displaying images and also an effective display area for sensing external input. The area TA overlaps at least with the effective display area AA. For example, the area TA overlaps the entire surface or at least a portion of the effective display area AA. Thus, the user can identify an image or provide external input through the area TA. However, this is an illustrative illustration, and the area in the effective display area AA for displaying images and the area for sensing external input can also be separated from each other, and is not limited to any particular embodiment.

[0090] The peripheral area NAA can be the area covered by the border area BZA. The peripheral area NAA is adjacent to the active display area AA. The peripheral area NAA can surround the active display area AA. The peripheral area NAA can be configured with drive circuitry or drive wiring for driving the active display area AA.

[0091] The peripheral NAA area can be configured with various signal lines or pads (PDs) that provide electrical signals to the active display area (AA), or electronic components. The peripheral NAA area is covered by the border area (BZA) and cannot be identified from the outside.

[0092] As an example, pad PD can include... Figure 2 The diagram shows a first pad for electrical connection to the display panel (DP) and a second pad for electrical connection to the input sensing layer (ISU). The first and second pads can be configured on the same layer or on different layers.

[0093] In this embodiment, the display module 200 is assembled in a flat state with the effective display area AA and the peripheral area NAA facing the window 100. However, this is only an illustrative illustration, and a portion of the peripheral area NAA in the display module 200 may be curved. In this case, a portion of the peripheral area NAA faces the back of the display device DD, which can reduce the bezel area BZA at the front FS of the display device DD. Alternatively, the display module 200 may also be assembled in a state where a portion of the effective display area AA is also curved. Alternatively, in the display module 200 according to an embodiment of the present invention, the peripheral area NAA may be omitted.

[0094] The circuit board 300 can be connected to the display module 200. The circuit board 300 may include a flexible substrate CF, a main substrate MB, and a sensing and control circuit TIC. The flexible substrate CF may include an insulating film and conductive wiring mounted on the insulating film. The conductive wiring is connected to the pads PD to electrically connect the circuit board 300 and the display module 200.

[0095] The flexible substrate CF can be assembled into a bent state. Thus, the main substrate MB can be disposed on the back of the display module 200 and stably housed within the space provided by the housing 400.

[0096] The sensing control circuit (TIC) can be configured on the flexible substrate (CF) and electrically connected to a portion of the pads (PD). In this specification, the sensing control circuit (TIC) can be a control... Figure 2 The circuit shown provides a detection signal for the operation of the input sensing layer ISU, or receives a sensing signal from the input sensing layer ISU to sense external inputs. Alternatively, in this embodiment, the flexible substrate CF can be omitted, and the main substrate MB can be directly connected to the display module 200. In this case, the sensing control circuit TIC can be configured on the main substrate MB.

[0097] Although not shown, the display module 200 may also include a drive control circuit for controlling the operation of the display panel DP. The drive control circuit may overlap with and be configured in the surrounding area NAA. Figure 2 The substrate BS shown in the figure.

[0098] The main substrate MB may include signal lines (not shown) and electronic components. The electronic components may be connected to the signal lines and electrically connected to the display module 200.

[0099] Figure 3a This is a plan view of a display panel, a flexible substrate, and a sensing control circuit according to an embodiment of the present invention. Figure 3b This is a cross-sectional view showing a portion of a display panel that overlaps with the display area according to an embodiment of the present invention. Figure 3c This is a cross-sectional view of a constant current circuit according to an embodiment of the present invention.

[0100] Reference Figure 3a In a display panel (DP), a display area (DP-DA) and an adjacent peripheral area (DP-NDA) can be defined. The display area (DP-DA) can be the area where an image is displayed. Multiple pixels (PX) can be configured within the display area (DP-DA). The peripheral area (DP-NDA) can be the area where drive circuitry or drive wiring is configured, etc.

[0101] The display panel DP may include a substrate BS, multiple pixels PX, multiple signal wirings GL, DL, PL, EL, multiple display pads DPD, and a constant current circuit CC.

[0102] Each pixel PX can display one of the primary colors or one of the tertiary colors. The primary colors can include red, green, or blue. The tertiary colors can include various colors such as white, yellow, turquoise, or magenta. However, the colors displayed by each pixel PX are not limited to these.

[0103] Multiple signal traces GL, DL, PL, and EL can be configured on a substrate BS. These traces can be connected to multiple pixels PX to transmit electrical signals to them. The traces GL, DL, PL, and EL may include multiple scan traces GL, multiple data traces DL, multiple power lines PL, and multiple light-emitting control traces EL. However, this is illustrative, and the structure of the traces GL, DL, PL, and EL according to an embodiment of the present invention is not limited thereto. For example, the traces GL, DL, PL, and EL according to an embodiment of the present invention may also include initialization voltage traces.

[0104] The power pattern VDD can be configured in the peripheral area DP-NDA. The power pattern VDD can be connected to multiple power lines PL. Multiple pixels PX can each receive the power voltage ELVDD provided by the power line PL.

[0105] Multiple display pads (DPDs) can be configured in the peripheral area DP-NDA. Multiple display pads (DPDs) can refer to multiple first pads (P1). Multiple display pads (DPDs) may include first pads (P1) and second pads (P2). Multiple first pads (P1) can be provided. Multiple first pads (P1) can be connected to multiple data lines (DL). Multiple first pads (P1) can be referred to as multiple data pads (P1). Second pads (P2) can be connected to the power pattern (VDD) and electrically connected to multiple power lines (PL). Second pads (P2) can be referred to as power pads (P2). The display panel (DP) can provide electrical signals from the outside through the multiple display pads (DPDs) to multiple pixels (PX). Alternatively, the multiple display pads (DPDs) may include pads for receiving other electrical signals in addition to the first pads (P1) and second pads (P2), and are not limited to any particular embodiment.

[0106] The drive control circuit DIC can be mounted on the peripheral area DP-NDA. The drive control circuit DIC can be a chip-shaped timing control circuit. Multiple data routes DL can be electrically connected to multiple first pads P1 via the drive control circuit DIC. However, this is exemplary; according to an embodiment of the present invention, the drive control circuit DIC can also be mounted on a film separate from the display panel DP. The drive control circuit DIC can be electrically connected to multiple display pads DPD through the film.

[0107] A constant current circuit CC can be configured in the peripheral region DP-NDA. The constant current circuit CC may include a first transistor. The first transistor may include a first gate GT, a first source SC, and a first drain DR.

[0108] Multiple pads PD1, PD2, and PD3 can be configured in the peripheral area DP-NDA. These pads can be electrically connected to the constant current circuit CC. The pads PD1, PD2, and PD3 may include a first pad PD1, a second pad PD2, and a third pad PD3. The first pad PD1 can be electrically connected to the first source SC. The second pad PD2 can be electrically connected to the first gate GT. The third pad PD3 can be electrically connected to the first drain DR.

[0109] Multiple pad PDs (reference) Figure 1 The flexible substrate CF can be configured on multiple display pads DPD and multiple pads PD1, PD2, and PD3. Figure 1 The flexible substrate CF can be coupled with multiple pads PD (see reference). Figure 1 Electrical connection.

[0110] The sensing control circuit TIC can be configured on the flexible substrate CF. The sensing control circuit TIC may include a first terminal TM1, a second terminal TM2, and a third terminal TM3.

[0111] The first terminal TM1 can be electrically connected to the first gate GT via the second pad PD2. The second terminal TM2 can be electrically connected to the first source SC via the first pad PD1. The third terminal TM3 can be electrically connected to the first drain DR via the third pad PD3.

[0112] Reference Figure 3b The display panel (DP) can include multiple insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating, semiconductor, and conductive layers are formed through methods such as coating and vapor deposition. Subsequently, photolithography can be used to selectively pattern the insulating, semiconductor, and conductive layers. This process forms the semiconductor patterns, conductive patterns, signal lines, etc., included in the circuit element layer (DP-CL) and the display element layer (DP-OLED). Figure 3b The display panel DP shown in the diagram is described as having a similar design to... Figure 3a The first transistor T1 and the second transistor T2 of the pixel PX shown are additional components.

[0113] The substrate BS may include a synthetic resin layer. The synthetic resin layer may contain a thermosetting resin. The substrate BS may have a multilayer structure. For example, the substrate BS may also have a three-layer structure consisting of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide resin layer, and the material is not particularly limited. The synthetic resin layer may contain at least one of acrylic resins, methacrylic resins, polyisoprene, plastic resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and dinaphthalene-based resins. Furthermore, the substrate BS may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0114] At least one inorganic layer is formed on the substrate BS. The inorganic layer may contain at least one of alumina, titanium oxide, silicon dioxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In this embodiment, the display panel DP is illustrated as including a buffer layer BFL.

[0115] The buffer layer (BFL) increases the adhesion between the substrate (BS) and the semiconductor pattern. The buffer layer (BFL) may include a silicon dioxide layer and a silicon nitride layer. The silicon dioxide layer and the silicon nitride layer may be stacked alternately.

[0116] A semiconductor pattern is configured on the buffer layer BFL. The semiconductor pattern may contain polycrystalline silicon. However, it is not limited to this; the semiconductor pattern may also contain amorphous silicon or metal oxide.

[0117] Figure 3bThis only shows a portion of the semiconductor pattern; other areas of the pixel PX on the plane can also be configured with semiconductor patterns. The semiconductor patterns can be arranged across the pixel PX according to a specific rule. The semiconductor patterns have different electrical properties depending on whether they are doped or not. The semiconductor pattern can include doped and undoped regions. Doped regions can be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant.

[0118] Doped regions have higher conductivity than undoped regions and essentially function as electrodes or signal lines. Undoped regions are essentially equivalent to the active region (or channel) of a transistor. In other words, one part of a semiconductor pattern can be the active region of a transistor, another part can be the source or drain of a transistor, and yet another part can be a connecting electrode or a connecting signal line.

[0119] The source S1, active region A1, and drain D1 of the first transistor T1 are formed from a semiconductor pattern, and the source S2, active region A2, and drain D2 of the second transistor T2 are formed from a semiconductor pattern. The sources S1 and S2 and the drains D1 and D2 extend in opposite directions from the active regions A1 and A2 in cross-section. Figure 3b The diagram shows a portion of the connection signal line SCL formed from a semiconductor pattern. Although not shown separately, the connection signal line SCL can be connected in plane to the drain D2 of the second transistor T2.

[0120] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 overlaps with multiple pixels PX and covers the semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The first insulating layer 10 can contain at least one of aluminum oxide, titanium oxide, silicon dioxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 can be a single-layer silicon dioxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit element layer DP-CL described later can be an inorganic layer and / or an organic layer, and has a single-layer or multi-layer structure. The inorganic layer can contain at least one of the above-mentioned substances.

[0121] Gates G1 and G2 are disposed on the first insulating layer 10. Gates G1 and G2 may be part of a metal pattern. Gates G1 and G2 overlap with active regions A1 and A2. In the process of doping semiconductor patterns, gates G1 and G2 are identical to the mask.

[0122] A second insulating layer 20 covering gates G1 and G2 is disposed on the first insulating layer 10. The second insulating layer 20 overlaps the pixel PX. The second insulating layer 20 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 can be a single-layer silicon dioxide layer.

[0123] An upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G2 of the second transistor T2. The upper electrode UE can be part of a metal pattern. A portion of the gate G2 and the upper electrode UE overlapping therewith can define a capacitor CP (see reference). Figure 3a ).

[0124] A third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single layer of silicon dioxide. A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 penetrating the first to third insulating layers 10-30.

[0125] A fourth insulating layer 40 is disposed on the third insulating layer 30, covering the first connecting electrode CNE1. The fourth insulating layer 40 may be a single layer of silicon dioxide. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 that penetrates the fourth insulating layer 40 and the fifth insulating layer 50.

[0126] A sixth insulating layer 60 is disposed on the fifth insulating layer 50, covering the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0127] Organic light-emitting diodes (OLEDs) include a first electrode AE, a hole control layer HCL, an emissive layer EML, an electronic control layer ECL, and a second electrode CE.

[0128] A first electrode AE ​​is disposed on a sixth insulating layer 60. The first electrode AE ​​is connected to a second connecting electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60. An opening OP is defined in a pixel defining film PDL. The opening OP of the pixel defining film PDL exposes at least a portion of the first electrode AE.

[0129] The display area DP-DA may include a pixel area PXA and a light-shielding area NPXA adjacent to the pixel area PXA. The light-shielding area NPXA may surround the pixel area PXA. In this embodiment, the pixel area PXA is defined as corresponding to a portion of the area of ​​the first electrode AE ​​exposed through the opening OP.

[0130] A hole control layer (HCL) can be jointly configured in pixel region PXA and light-blocking region NPXA. The hole control layer HCL may include a hole transport layer and a hole injection layer. A light-emitting layer (EML) is configured on the hole control layer HCL. The EML can be configured in the region corresponding to the opening OP. That is, the EML can be separately formed in each pixel PX.

[0131] An electronic control layer (ECL) is disposed on the light-emitting layer (EML). The ECL may include an electron transport layer and an electron injection layer. A hole control layer (HCL) and the ECL may be co-formed on multiple pixels (PX) using an open mask. A second electrode (CE) is disposed on the ECL. The second electrode (CE) has a monolithic shape and is co-located on multiple pixels (PX).

[0132] An insulating layer TFL is disposed on the second electrode CE. According to the present invention, the insulating layer TFL may comprise multiple thin films. For example, although not illustrated, the insulating layer TFL may have a structure in which inorganic layers and organic layers are stacked.

[0133] Figure 3c This is a cross-sectional view of a constant current circuit according to an embodiment of the present invention. Figure 3c The explanation addresses the use of... Figure 3b The constituent elements are described, and the same reference numerals are used in the accompanying drawings, but the description of them is omitted.

[0134] Reference Figure 3c The constant current circuit CC may include a first transistor TR. The first transistor TR may include a first gate GT, a first source SC, a first active region AC, and a first drain DR.

[0135] The first source SC, the first active region AC, and the first drain DR can be configured on the buffer layer BFL. The first source SC and the first drain DR can extend from the first active region AC in opposite directions in cross-section.

[0136] A first gate GT may be disposed on a first insulating layer 10. The first gate GT may be part of a metal pattern. The first gate GT may overlap with a first active region AC. In a process of doping semiconductor patterns, the first gate GT is identical to the mask. A second insulating layer 20 may cover the first gate GT.

[0137] Figure 4a This is a cross-sectional view of a display module according to an embodiment of the present invention. Figure 4b This is a diagram illustrating the capacitance generated during the sensing operation of the input sensing layer according to an embodiment of the present invention.

[0138] Reference Figure 4aThe input sensing layer ISU may include a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1, a second sensing insulating layer IS-IL2, a second conductive layer IS-CL2, and a third sensing insulating layer IS-IL3. The first sensing insulating layer IS-IL1 can be directly disposed on the insulating layer TFL. However, the inventive concept is not limited thereto, and the first sensing insulating layer IS-IL1 may be omitted. In this case, the first conductive layer IS-CL1 can be directly disposed on the insulating layer TFL.

[0139] The first conductive layer IS-CL1 and the second conductive layer IS-CL2 can each have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The multi-layer conductive layers can include two or more of transparent conductive layers and metal layers. The multi-layer conductive layers can include metal layers containing different metals from each other.

[0140] The transparent conductive layer can contain ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), PEDOT (poly(3,4-ethylenedioxythiophene)), metal nanowires, or graphene. The metal layer can contain molybdenum, silver, titanium, copper, aluminum, or their alloys. For example, the first conductive layer IS-CL1 and the second conductive layer IS-CL2 can each have a three-layer metal structure, i.e., a titanium / aluminum / titanium three-layer structure. Alternatively, a metal with relatively high durability and low reflectivity can be used in the outer layer, while a metal with high conductivity can be used in the inner layer.

[0141] According to the present invention, the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may each include a sensing electrode for sensing external input. For example, the first conductive layer IS-CL1 may include a connecting sensing electrode, and the second conductive layer IS-CL2 may include a first sensing electrode and a second sensing electrode spaced apart from each other on a plane. The connecting sensing electrode may be electrically connected to either the first sensing electrode or the second sensing electrode.

[0142] Each of the first sensing insulating layer IS-IL1 to the third sensing insulating layer IS-IL3 may comprise an inorganic film or an organic film. In this embodiment, the first sensing insulating layer IS-IL1 may be an inorganic film. However, it is not limited to this; the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be provided as inorganic films, and the third sensing insulating layer IS-IL3 may be provided as an organic film.

[0143] Reference Figure 4bThe input sensing layer (ISU) and the second electrode (CE) of the display panel (DP) are separated by a predetermined distance on the third-direction DR3. The second electrode (CE) may include... Figure 2 The display element layer shown is an organic light-emitting diode OLED of a DP-OLED. Hereinafter, for ease of explanation, the second electrode CE will be described as the driving electrode.

[0144] According to such Figure 4a as well as Figure 4b As shown, a parasitic capacitor Cb is formed between the conductive layers IS-CL1 and IS-CL2 of the input sensing layer ISU and the driving electrode CE. Additionally, when the external input TC contacts or approaches the input sensing layer ISU, a sensing capacitor Ct is formed between the external input TC and the input sensing layer ISU due to the voltage difference between them. In practice, the external input TC... Figure 1 The window 100 described in the text is in front of or near the window.

[0145] According to the present invention, the sensing control circuit TIC (reference) Figure 1 The change in capacitance of the sensing capacitor Ct can be used to determine whether a touch has occurred to the external input TC and the location of the touch.

[0146] On the other hand, the parasitic capacitor Cb described above can have a capacitance corresponding to that of the sensing capacitor Ct. As a result, the reliability of touch detection based on the external input TC and the touch position may be reduced due to the capacitance of the parasitic capacitor Cb.

[0147] According to an embodiment of the present invention, the sensing control circuit TIC can reduce the capacitance of the parasitic capacitor Cb by using an offset capacitor. That is, the sensing control circuit TIC controls the capacitance of the parasitic capacitor Cb by using an offset capacitor, thereby increasing the reliability of touch detection based on external input TC and touch position. Regarding the offset capacitor, through... Figure 7 More detailed explanation.

[0148] Figure 5 This is a plan view of the input sensing layer according to an embodiment of the present invention. Figure 6 It is according to an embodiment of the present invention. Figure 5 The cross-sectional view shown is the section cut from I-I'.

[0149] Reference Figure 5 The input sensing layer (ISU) includes a sensing region (AR) and a non-sensing region (NAR) adjacent to the sensing region (AR). The sensing region (AR) may correspond to the preceding... Figure 1 The effective display area AA of the display module 200 is defined in the middle, and the non-sensing area NAR corresponds to the peripheral area NAA of the display module 200.

[0150] In detail, the input sensing layer ISU includes a first sensing electrode, a second sensing electrode, a first connection portion BSP1, a second connection portion BSP2, a second pad IPD, and a compensation electrode DCP. The first sensing electrode, the second sensing electrode, the first connection portion BSP1, and the second connection portion BSP2 overlap the sensing area AR, and the second pad IPD and the compensation electrode DCP overlap the non-sensing area NAR.

[0151] The first sensing electrode can extend in a first direction DR1 and be arranged in a second direction DR2, and n (n is a natural number) are provided. Each first sensing electrode includes a plurality of first sensing portions SP1 that are spaced apart from each other on a plane and arranged in the first direction DR1.

[0152] The second sensing electrodes can extend in the second direction DR2 and be arranged in the first direction DR1, and m (m is a natural number) are provided. Each second sensing electrode includes a plurality of second sensing portions SP2 that are spaced apart from each other on a plane and arranged in the second direction DR2. The second sensing portions SP2 can be spaced apart from the first sensing portions SP1 on a plane and insulated from each other.

[0153] The first connecting portion BSP1 can connect the first sensing portions SP1 to each other. For example, one first connecting portion BSP1 can electrically connect two first sensing portions SP1 that are adjacent to each other in the first direction DR1.

[0154] The second connecting portion BSP2 can connect the second sensing portions SP2 to each other. For example, one second connecting portion BSP2 can electrically connect two second sensing portions SP2 that are adjacent to each other in the second direction DR2. According to the present invention, the second connecting portion BSP2 and the second sensing portions SP2 can have an integral shape formed by the same process. The first connecting portion BSP1 and the second connecting portion BSP2 can intersect each other in a plane and be insulated from each other in cross-section.

[0155] According to the present invention, the first sensing part SP1, the second sensing part SP2, and the second connecting part BSP2 can be formed by the same process and materials, and can be included in the front. Figure 4a In the second conductive layer IS-CL2 described herein. In other words, the first sensing part SP1, the second sensing part SP2, and the second connecting part BSP2 can be directly disposed on the second sensing insulating layer IS-IL2.

[0156] According to the present invention, the first connecting portion BSP1 may be included in Figure 4aIn the first conductive layer IS-CL1 described herein, the first connecting portion BSP1 can be directly disposed on the first sensing insulating layer IS-IL1. The first connecting portion BSP1 can be electrically connected to the first sensing portion SP1 through contact holes defined in the first sensing insulating layer IS-IL1.

[0157] However, the structure included in the first conductive layer IS-CL1 and the second conductive layer IS-CL2 is not limited to this and can be modified in various ways. For example, the first sensing part SP1, the second sensing part SP2 and the second connecting part BSP2 can be included in the first conductive layer IS-CL1, and the first connecting part BSP1 can also be included in the second conductive layer IS-CL2.

[0158] The second pad IPD includes a first sensing pad IPD1, a second sensing pad IPD2, and a third sensing pad IPD3. Multiple first sensing pads IPD1, second sensing pad IPD2, and third sensing pad IPD3 can each be configured.

[0159] Alternatively, the first sensing pad IPD1 can be connected to one end of the first sensing electrode, and the second sensing pad IPD2 can be connected to the other end of the first sensing electrode. The third sensing pad IPD3 can be connected to one end of the second sensing electrode.

[0160] Although Figure 5 Although not shown in the diagram, the input sensing layer ISU may include: a first line connecting one end of the first sensing pad IPD1 and the first sensing electrode respectively; a second line connecting the other end of the second sensing pad IPD2 and the first sensing electrode respectively; and a third line connecting one end of the third sensing pad IPD3 and the second sensing electrode respectively.

[0161] The first sensing pad IPD1, the second sensing pad IPD2, and the third sensing pad IPD3 can be electrically soldered to... Figure 1 The flexible substrate CF is shown in the figure. Therefore, the sensing control circuit TIC (see reference) Figure 1 It can be electrically connected to the first sensing pad IPD1 and the second sensing pad IPD2, and output the detection signal to the first sensing pad IPD1 and the second sensing pad IPD2 respectively. As a result, the detection signal can be applied to the first sensing electrode through the first sensing pad IPD1 and the second sensing pad IPD2.

[0162] In addition, the sensing control circuit TIC can be electrically connected to the third sensing pad IPD3 to receive sensing signals from the third sensing pad IPD3 connected to the second sensing electrode.

[0163] According to an embodiment of the present invention, the compensation electrode DCP can be superimposed on the non-sensing region NAR and disposed on the first sensing insulating layer IS-IL1. The compensation electrode DCP can be electrically connected to the fourth and fifth sensing pads SPD1 and SPD2. The fourth and fifth sensing pads SPD1 and SPD2 can be superimposed on the non-sensing region NAR and electrically soldered to the flexible substrate CF.

[0164] The sensing control circuit TIC can output a compensation signal to the compensation electrode DCP via the fourth sensing pad SPD1, and receive an offset sensing signal from the compensation electrode DCP via the fifth sensing pad SPD2. As a result, the sensing control circuit TIC can, based on the offset sensing signal, the sensing signal, and... Figure 4b The capacitance of the parasitic capacitor Cb shown in the figure is used to determine whether the external input TC is touched and the touch position.

[0165] Here, the sensing signal can refer to... Figure 5 The mutual capacitance Cm formed between the first and second sensing electrodes shown in the figure (refer to) Figure 8 The capacitance of the mutual capacitance Cm can be determined based on... Figure 4b The capacitance of the sensing capacitor Ct of the external input TC shown in the figure changes. Additionally, the offset sensing signal can refer to the offset capacitor Cx formed by the compensation electrode DCP (see reference). Figure 6 ) capacitor.

[0166] According to the present invention, the capacitance of the parasitic capacitor Cb can be controlled by the capacitance of the offset capacitor Cx formed by the compensation electrode DCP. That is, the capacitance of the parasitic capacitor Cb is canceled out by the capacitance of the offset capacitor Cx, thereby enabling the sensing control circuit TIC to more accurately sense the capacitance change of the mutual capacitance Cm corresponding to the sensing signal.

[0167] For details, refer to Figure 6 The compensation electrode DCP includes a first compensation electrode DCPa and a second compensation electrode DCPb disposed on different layers. The first compensation electrode DCPa can be directly disposed on the first sensing insulating layer IS-IL1 and disposed on the same layer as the first sensing insulating layer IS-IL1. Figure 5 The first connection portion BSP1 shown is on the same layer. The second compensation electrode DCPb can be directly disposed on the second sensing insulating layer IS-IL2, and disposed on the same layer as... Figure 5 The first sensing electrode, the second sensing electrode, and the second connection portion BSP2 shown are on the same layer.

[0168] According to the present invention, in the thickness direction, the first compensation electrode DCPa can be more adjacent to the insulating layer TFL than the second compensation electrode DCPb. Here, the thickness direction can refer to... Figure 1 The third-party DR3 is shown in the figure.

[0169] The first compensation electrode DCPa can be electrically connected to the fourth sensing pad (see reference). Figure 5 The SPD1 receives data from the sensing control circuit (see reference ) via the fourth sensing pad SPD1. Figure 1 The compensation signal output by the TIC. This can be achieved by the second compensation electrode DCPb being electrically connected to the fifth sensing pad (see reference). Figure 5 SPD2), Sensing Control Circuit TIC (refer to SPD2), Figure 1 The offset sensing signal output from the second compensation electrode DCPb is sensed through the fifth sensing pad SPD2.

[0170] In particular, according to the present invention, the compensation signal output to the first compensation electrode DCPa can be a signal whose phase is reversed compared to the detection signal output to the first sensing electrode. As a result, Figure 4b The capacitance of the parasitic capacitor Cb shown in the figure and the capacitance of the offset capacitor Cx formed by the first compensation electrode DCPa and the second compensation electrode DCPb can cancel each other out.

[0171] Figure 7 This is a block diagram illustrating the sensing operation of the input sensing layer according to an embodiment of the present invention. Figure 8 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to an embodiment of the present invention.

[0172] Figure 7 The connection structure between the input sensing layer (ISU), the display panel (DP), and the sensing control circuit (TIC) is disclosed below. Figure 7 as well as Figure 8 The electrical connection characteristics between the structures are explained. The sensing control circuit TIC can be electrically connected to the display panel DP and the input sensing layer ISU through the output node NP.

[0173] For details, refer to Figure 7 A parasitic capacitor Cb is formed between the second electrode CE of the display panel DP and the sensing electrode SP of the input sensing layer ISU. The parasitic capacitor Cb can be electrically connected to the output node NP. The sensing electrode SP can refer to... Figure 5 The first sensing electrode of the first sensing unit SP1 and the second sensing electrode including the second sensing unit SP2 are shown.

[0174] Additionally, in contact with or adjacent to Figure 1 A sensing capacitor Ct can be formed between the external input TC of the front FS of the display device DD shown in the figure and the sensing electrode SP. The sensing capacitor Ct can be electrically connected to the output node NP.

[0175] The input sensing layer (ISU) can be electrically connected to the sensing control circuit (TIC) via the output node (NP). The input sensing layer (ISU) may include a compensation electrode (DCP) to compensate for the capacitance of the parasitic capacitor (Cb). Alternatively, an offset capacitor (Cx) may be formed between a first compensation electrode (DCPa) and a second compensation electrode (DCPb) included in the compensation electrode (DCP), and the offset capacitor (Cx) is electrically connected to the output node (NP).

[0176] According to the present invention, a detection signal may be output to a first sensing unit SP1 included in a first sensing electrode in a sensing electrode SP, and a compensation signal with phase reversal to the detection signal may be output to a first compensation electrode DCPa in a compensation electrode DCP. As a result, the capacitance of the offset capacitor Cx and the capacitance of the parasitic capacitor Cb, which are connected in parallel through the output node NP, can cancel each other out.

[0177] As described above, the sensing control circuit TIC can add the capacitance of the parasitic capacitor Cb, the offset capacitor Cx, and the sensing capacitor Ct, which are input through the output node NP. In this case, as the capacitances of the offset capacitor Cx and the parasitic capacitor Cb cancel each other out, the sensing control circuit TIC can determine the touch position based on the capacitance of the sensing capacitor Ct generated by the external input TC. As a result, the overall reliability of touch detection and touch position based on the external input TC can be improved.

[0178] On the other hand, the capacitance of the parasitic capacitor Cb can be determined according to the display device DD (reference). Figure 1 The temperature of the input sensing layer (ISU) varies with both the internal and external temperatures of the display device (DD). According to the present invention, a compensation electrode (DCP) is also disposed within the input sensing layer (ISU). Therefore, the capacitance of the offset capacitor (Cx) can also vary according to the internal and external temperatures of the display device (DD). That is, corresponding to the change in capacitance of the parasitic capacitor (Cb) based on the internal and external temperatures of the display device (DD), the capacitance of the offset capacitor (Cx) also changes, thereby improving the signal quality sensed by the output node (NP).

[0179] The sensing control circuit TIC according to the present invention includes a voltage conversion unit VCP and an offset control unit OFP. The voltage conversion unit VCP can be electrically connected to the output node NP, senses the capacitance change sensed through the output node NP, and outputs a detection voltage Vop. For example, the voltage conversion unit VCP can sense the capacitance change of the parasitic capacitor Cb, the offset capacitor Cx, and the sensing capacitor Ct, which is the sum of their capacitance changes.

[0180] The offset control unit OFP can be electrically connected to the output node NP to control the capacitance change applied to the output node NP. For example, the offset control unit OFP can disable the component of the parasitic capacitor Cb applied to the output node NP. That is, the capacitance of the parasitic capacitor Cb applied to the output node NP can be controlled by the offset capacitor Cx and the offset control unit OFP.

[0181] The offset control unit OFP includes an auxiliary capacitor unit Cx-P and a switch unit ST-P that controls the operation of the auxiliary capacitor unit Cx-P. The value of the capacitance sensed from the output node NP can be varied due to the auxiliary offset capacitor generated by the auxiliary capacitor unit Cx-P.

[0182] Below, in Figure 8 In the diagram, the offset capacitor Cx generated by the compensation electrode DCP is described as the first offset capacitor Cx, and the auxiliary offset capacitor generated by the auxiliary capacitor section Cx-P is described as the second offset capacitor Cxs.

[0183] Reference Figure 8 , Figure 7 The parasitic capacitor Cb shown may include: a first parasitic capacitor Cb-1 between the first sensing part SP1 of the first sensing electrode and the second electrode CE; and a second parasitic capacitor Cb-2 between the second sensing part SP2 of the second sensing electrode and the second electrode CE.

[0184] Furthermore, the capacitance Cm defined between the first sensing electrode and the second sensing electrode at the corresponding position changes according to the external input TC. In practice, a first sensing capacitor can be formed between the external input TC and the first sensing unit SP1, and a second sensing capacitor can be formed between the external input TC and the second sensing unit SP2, according to the external input TC.

[0185] That is, when the external input TC is close, the capacitance sensed in the output node NP can reflect the capacitance of the first sensing capacitor and the second sensing capacitor respectively. Conversely, when the external input TC is not close, the capacitance sensed from the output node NP can be the sum of the capacitances of the first and second parasitic capacitors Cb-1 and Cb-2 and the capacitances of the first and second offset capacitors Cx and Cxs.

[0186] According to the present invention, the first offset capacitor Cx may be through... Figure 7 The compensation electrode DCP shown is generated and disposed inside the display module 200 DM-A. The first compensation electrode DCPa, one of the two compensation electrodes forming the first offset capacitor Cx, can be electrically connected to the fourth sensing pad SPD1 (see reference). Figure 5The compensation signal SC is received through the fourth sensing pad SPD1. The compensation signal SC can be output from the sensing control circuit TIC. The second compensation electrode DCPb, which forms the first offset capacitor Cx, can be electrically connected to the output node NP.

[0187] That is, the first compensation electrode DCPa and the second compensation electrode DCPb are disposed inside DM-A of the display module 200, so that the capacitance of the first offset capacitor Cx can change according to the internal and external temperature changes of the display module 200.

[0188] Figure 7 The auxiliary capacitor section Cx-P of the offset control unit OFP shown may include at least one second offset capacitor Cxs electrically connected to the output node NP. As an example, Figure 8 The auxiliary capacitor section Cx-P shown in the diagram is described as including a second offset capacitor Cxs.

[0189] The second offset capacitor Cxs can be configured within the internal TIC-A of the sensing control circuit TIC. That is, the offset control unit OFP can control the capacitance sensed in the output node NP via the second offset capacitor Cxs, which is electrically connected to the output node NP. Alternatively, one of the two electrodes forming the second offset capacitor Cxs can receive the offset signal VS, which is essentially the same signal as the compensation signal SC. As a result, the capacitance of parasitic capacitors Cb-1 and Cb-2 can be canceled through the first offset capacitor Cxs and the second offset capacitor Cxs. The other compensation electrode of the two electrodes forming the second offset capacitor Cxs can be electrically connected to the output node NP.

[0190] In particular, according to an embodiment of the present invention, the capacitance of the second offset capacitor Cxs can be smaller than the capacitance of the first offset capacitor Cx. That is, the offset control unit OFP can more precisely control the capacitance change sensed in the output node NP through the second offset capacitor Cxs.

[0191] Figure 7 The offset control unit OFP shown may include a switch ST-P corresponding to the number of second offset capacitors Cxs. As an example, according to... Figure 8 As shown, corresponding to a second offset capacitor Cxs, the switching section ST-P includes a switch ST. One end of the switch ST may be electrically connected to the other compensation electrode of the second offset capacitor Cxs, and the other end of the switch ST may be electrically connected to the output node NP.

[0192] That is, the offset control unit OFP can control the value of the capacitance induced in the output node NP by controlling the operation of the switch ST. For example, to cancel the capacitance of the parasitic capacitor Cb induced from the output node NP, the offset control unit OFP can turn on the switch ST so that the second offset capacitor Cxs is electrically connected to the output node NP. As another example, when no change in the capacitance of the output node NP is required, the offset control unit OFP can turn off the switch ST so that the second offset capacitor Cxs is not electrically connected to the output node NP.

[0193] Figure 7 The voltage conversion unit VCP shown includes an operational amplifier AP, a capacitor Cf, a switch SW, and a resistor RT.

[0194] The first input node (e.g., negative input node) of the operational amplifier AP is input with a signal via the output node NP. The second input node (e.g., positive input node) of the operational amplifier AP is input with a reference signal ref that operates at a constant period. A capacitor Cf is provided between the first input node and the output node of the operational amplifier AP. The capacitor Cf, the switch SW, and the resistor RT can be connected in parallel with each other.

[0195] The reference signal `ref` induces a current in the output node `NP` and is a voltage signal used to sense changes in current caused by touch. As an example, the reference signal `ref` can be implemented as a rectangular wave. Alternatively, the voltage range of such a reference signal `ref` can swing within a predetermined voltage range, while the operational amplifier `AP` converts the current sensed from the output node `NP` into a voltage. The sensed voltage `Vop` of the operational amplifier `AP` can be fed back to the output node `NP` via a switch `SW`.

[0196] On the other hand, although through Figure 8 An example of a voltage converter VCP is shown, but the structure of the voltage converter VCP is not limited to this. For example, the voltage converter VCP may be a structure that omits the resistor RT, or it may include an additional structure connected in parallel with the capacitor Cf.

[0197] Figure 9 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to another embodiment of the present invention.

[0198] and Figure 8 Compared to the circuit diagram shown in the image, Figure 9 The circuit diagram shown is only for... Figure 7 The structure of the offset control unit OFP shown is modified, while the structures of the remaining components can remain substantially the same. Therefore, through... Figure 9 The structure of the offset control unit (OFP) will be explained in detail.

[0199] Reference Figure 9 , Figure 7 The offset control unit OFP shown includes an auxiliary capacitor unit Cx-P equipped with multiple second offset capacitors Cxs1, Cxs2, Cxs3, Cxs4, Cxs5, and Cxs6 (hereinafter referred to as "Cxs1 to Cxs6") and a switching unit ST-P equipped with multiple switches ST1, ST2, ST3, ST4, ST5, and ST6 (hereinafter referred to as "ST1 to ST6") and STx.

[0200] First, the second offset capacitors Cxs1 to Cxs6, connected in parallel, can be configured within the internal TIC-A of the sensing control circuit TIC. Alternatively, one of the two electrodes forming each of the second offset capacitors Cxs1 to Cxs6 may receive the offset signal VS, which is essentially the same signal as the compensation signal SC. The other electrode forming each of the second offset capacitors Cxs1 to Cxs6 can be electrically connected to the output node NP.

[0201] Multiple switches ST1 to ST6 can be configured between the output node NP and multiple second offset capacitors Cxs1 to Cxs6, respectively. The multiple switches ST1 to ST6 can be turned on or off under the control of the sensing control circuit TIC.

[0202] According to the present invention, the offset control unit OFP can control the capacitance change sensed from the output node NP through multiple switches ST1 to ST6. For example, the sensing control circuit TIC can turn on only a portion of the switches ST1 to ST6, while the rest are turned off. As a result, the second offset capacitors Cxs1 to Cxs6 connected to the aforementioned portion of the switches can be electrically connected to the output node NP.

[0203] According to the present invention, the capacitance of each of the second offset capacitors Cxs1 to Cxs6 can be less than the capacitance of the first offset capacitor Cx. Furthermore, the second offset capacitors Cxs1 to Cxs6 can have different capacitances. For example, the capacitance of the first second offset capacitor Cxs1 can be less than the capacitance of the second second offset capacitor Cxs2. The capacitance of the second second offset capacitor Cxs2 can be less than the capacitance of the third second offset capacitor Cxs3. That is, the offset control unit OFP can more precisely control the capacitance changes sensed in the output node NP through the second offset capacitors Cxs1 to Cxs6 and the switches ST1 to ST6.

[0204] Additionally, the offset control unit OFP includes an auxiliary switch STx that controls the first offset capacitor Cx formed within the DM-A inside the display module 200. The auxiliary switch STx can be electrically connected between the output node NP and the second compensation electrode DCPb of the compensation electrode DCP. The offset control unit OFP can control the capacitance of the first offset capacitor Cx supplied to the output node NP via the auxiliary switch STx.

[0205] Figure 10 This is a block diagram illustrating the sensing operation of an input sensing layer according to an embodiment of the present invention.

[0206] Reference Figure 10 The sensing control circuit TIC can be electrically connected to the display panel DP and the input sensing layer ISU via the output node NP. A parasitic capacitor Cb can be formed between the driving electrode CE of the display panel DP and the sensing electrode SP of the input sensing layer ISU. The parasitic capacitor Cb can be electrically connected to the output node NP.

[0207] Additionally, it can be used with Figure 1 The display device DD shown in the figure (refer to) Figure 1 ) before FS (refer to) Figure 1 A sensing capacitor Ct is formed between the contact or adjacent external input TC and the sensing electrode SP. The sensing capacitor Ct can be electrically connected to the output node NP.

[0208] The sensing control circuit TIC can receive a signal SG from the sensing electrode SP. The signal SG may include the capacitance of the parasitic capacitor Cb and the capacitance of the sensing capacitor Ct.

[0209] The display panel DP may include a constant current circuit CC. The constant current circuit CC can be electrically connected to the sensing control circuit TIC through the output node NP. The sensing control circuit TIC can control the constant current circuit CC to eliminate at least a portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal SG input from the self-sensing electrode SP.

[0210] The constant current circuit CC may include a first transistor. The first transistor may include a first gate GT, a first source SC, and a first drain DR. The first source SC can be connected to a second terminal TM2 (see reference). Figure 3a It receives the input signal SG sensed by the sensing electrode SP.

[0211] The sensing control circuit (TIC) may include a control signal unit (CS), a ground electrode (GD), an offset control unit (OFP), and a voltage conversion unit (VCP).

[0212] The control signal unit CS can be controlled via the first terminal TM1 (refer to...) Figure 3aIt is electrically connected to the first gate GT. The control signal unit CS can provide a control voltage CV to the first gate GT.

[0213] The control signal unit CS can use a control voltage CV to control the on-off state of the first transistor. The control voltage CV can be provided in a pulse width modulation manner. The control signal unit CS can control the on-time of the first transistor.

[0214] The grounding electrode GD can be connected to the third terminal TM3 (see reference). Figure 3a The first drain DR is electrically connected to the first drain DR. However, this is illustrative, and the connection relationship of the first drain DR according to an embodiment of the present invention is not limited as long as a structure providing constant voltage is required. For example, the first drain DR can be electrically connected to the power supply line PL (see reference PL). Figure 3a It can also provide the power supply voltage ELVDD to the first drain DR.

[0215] The first transistor can be turned on by controlling the voltage CV to allow the flow of the first current CI.

[0216] The constant current circuit CC can discharge a charge corresponding to the amount of charge in the capacitance of the parasitic capacitor Cb to the ground electrode GD based on the first current CI. At least a portion of the component in the signal SG caused by the capacitance of the parasitic capacitor Cb can be eliminated by the discharged charge.

[0217] According to the present invention, the sensing control circuit TIC can control the constant current circuit CC to eliminate at least a portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal SG input to the self-sensing electrode SP. The reference value of the signal SG sensed in the sensing electrode SP can be reduced by the constant current circuit CC. The proportion of the component caused by the capacitance change of the sensing capacitor Ct to the reference value of the signal input to the output node NP can be increased. The sensing control circuit TIC can easily sense the capacitance change of the sensing capacitor Ct. Reliability can be improved for touch status and touch position based on the external input TC. Therefore, a display device DD (refer to) with improved touch performance can be provided. Figure 1 ).

[0218] The offset control unit OFP can be electrically connected to the output node NP to control the reference value of the signal input to the output node NP. For example, the offset control unit OFP can eliminate at least a portion of the component of the signal applied to the output node NP caused by the capacitance of the parasitic capacitor Cb. That is, the component of the signal applied to the output node NP caused by the capacitance of the parasitic capacitor Cb can be additionally eliminated by the offset control unit OFP in addition to the constant current circuit CC.

[0219] The offset control unit OFP may include an auxiliary capacitor unit Cx-P and a switch unit ST-P that controls the operation of the auxiliary capacitor unit Cx-P. Due to the capacitance of the offset capacitor generated by the auxiliary capacitor unit Cx-P, the reference value of the signal applied to the output node NP can be changed.

[0220] The voltage conversion unit VCP can be electrically connected to the output node NP and sense the change in capacitance of the signal input through the output node NP to output the detection voltage Vop.

[0221] According to the present invention, the sensing control circuit TIC can receive signal input through the output node NP. The constant current circuit CC can eliminate a portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal SG sensed by the sensing electrode SP. The offset capacitor of the auxiliary capacitor section Cx-P can additionally eliminate the remaining portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal processed by the constant current circuit CC. Therefore, the proportion of the component caused by the capacitance change of the sensing capacitor Ct to the reference value of the signal input to the output node NP can be increased. The sensing control circuit TIC can easily sense the capacitance change of the sensing capacitor Ct. Reliability can be improved for touch status and touch position based on the external input TC. Therefore, a display device DD with improved touch performance (refer to) can be provided. Figure 1 ).

[0222] Figure 11 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to an embodiment of the present invention.

[0223] Reference Figure 10 as well as Figure 11 The parasitic capacitor Cb may include a first sensing electrode (refer to...) Figure 7 The first parasitic capacitor Cb-1 between the first sensing unit SP1 and the driving electrode CE (see description) and the second sensing electrode (refer to) Figure 7 (See the description) The second parasitic capacitor Cb-2 is located between the second sensing part SP2 and the driving electrode CE.

[0224] Furthermore, the capacitance Cm defined between the first sensing unit SP1 and the second sensing unit SP2 at the corresponding sites can change according to the external input TC. A sensing capacitor Ct can be formed between the external input TC and the sensing electrode SP according to the external input TC. The sensing capacitor Ct may include a first sensing capacitor formed between the external input TC and the first sensing unit SP1, and a second sensing capacitor formed between the external input TC and the second sensing unit SP2.

[0225] When the external input TC approaches, the signal SG can provide a component caused by the capacitance of the first sensing capacitor and the second sensing capacitor, respectively.

[0226] According to the present invention, the constant current circuit CC can be disposed inside the display module 200 (DM-A). The constant current circuit CC can be disposed on the display panel DP, thereby reducing the size of the sensing control circuit (TIC). This reduces the size of the circuit board 300 (see reference 300). Figure 1 The size of the display device DD (refer to) can be reduced. Figure 1 The border area BZA (refer to) Figure 1 The size of ).

[0227] The constant current circuit CC can be turned on and off by receiving a control voltage CV. In the on-state, the constant current circuit CC can carry a first current CI. The constant current circuit CC can cause at least a portion of the charge in the signal SG to move towards the ground electrode GD via the first current CI. The sensing control circuit TIC can eliminate at least a portion of the component in the signal SG caused by the capacitance of the first parasitic capacitor Cb-1 and the second parasitic capacitor Cb-2 via the constant current circuit CC.

[0228] According to the present invention, the sensing control circuit TIC can reduce the reference value of the signal SG sensed in the sensing electrode SP by utilizing the constant current circuit CC. It can increase the proportion of the reference value of the signal provided to the output node NP by the component caused by the capacitance change of the sensing capacitor Ct. The sensing control circuit TIC can easily sense the capacitance change of the sensing capacitor Ct. Reliability is improved for touch presence and touch position based on the external input TC. Therefore, a display device DD (refer to) with improved touch performance can be provided. Figure 1 ).

[0229] The auxiliary capacitor section Cx-P of the offset control unit OFP may include at least one offset capacitor Cxs electrically connected to the output node NP. Figure 11 The illustration shows an example including one offset capacitor Cxs, but the number of offset capacitors Cxs according to an embodiment of the invention is not limited thereto.

[0230] An offset capacitor Cxs can be configured within the internal TIC-A of the sensing control circuit TIC. The offset control unit OFP can additionally eliminate at least a remaining portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal processed by the constant current circuit CC through the offset capacitor Cxs electrically connected to the output node NP. The offset capacitor Cxs can more precisely control the reference value of the signal supplied to the output node NP. One of the two electrodes forming the offset capacitor Cxs can receive the offset signal CD. The offset signal CD can be output from the sensing control circuit TIC.

[0231] The switching section ST-P of the offset control unit OFP may include a switch corresponding to the number of offset capacitors Cxs. Figure 11 The illustration shows a switching section ST-P corresponding to an offset capacitor Cxs, whereby a switch ST is included. One end of the switch ST may be electrically connected to the offset capacitor Cxs, and the other end of the switch ST may be electrically connected to the output node NP.

[0232] The offset control unit OFP can further eliminate the component in the signal caused by the capacitance of the parasitic capacitor Cb by controlling the operation of the switch ST. For example, when the constant current circuit CC has sufficiently eliminated the component caused by the capacitance of the parasitic capacitor Cb, the offset control unit OFP can open the switch ST. When the constant current circuit CC has not sufficiently eliminated the component caused by the capacitance of the parasitic capacitor Cb, the offset control unit OFP can close the switch ST to further eliminate the component in the signal caused by the capacitance of the parasitic capacitor Cb.

[0233] According to the present invention, the sensing control circuit TIC can eliminate at least a portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal SG input to the self-sensing electrode SP by controlling the constant current circuit CC. The sensing control circuit TIC can additionally eliminate the remaining portion of the component caused by the capacitance of the parasitic capacitor Cb from the signal processed by the constant current circuit CC by controlling the offset control unit OFP. Therefore, the proportion of the component caused by the capacitance change of the sensing capacitor Ct to the reference value of the signal input to the output node NP can be increased. The sensing control circuit TIC can easily sense the capacitance change of the sensing capacitor Ct. Reliability can be improved for touch presence and touch position based on the external input TC. Therefore, a display device DD (refer to) with improved touch performance can be provided. Figure 1 ).

[0234] The voltage conversion unit VCP may include an operational amplifier AP, a capacitor Cf, a switch SW, and a resistor RT.

[0235] The first input node (e.g., negative input node) of the operational amplifier AP is input with a signal transmitted via the output node NP. The second input node (e.g., positive input node) of the operational amplifier AP is input with a reference signal ref that operates at a certain period. A capacitor Cf is provided between the first input node and the output node of the operational amplifier AP. The capacitor Cf, the switch SW, and the resistor RT can be connected in parallel with each other.

[0236] The reference signal ref is a voltage signal used to generate the current at the output node NP and sense the current change caused by touch. As an example, the reference signal ref can be implemented in a rectangular wave form. Alternatively, the voltage range of such a reference signal ref can swing within a predetermined voltage range while the operational amplifier AP converts the current sensed by the output node NP into a voltage. The sensed voltage Vop of the operational amplifier AP can be provided to the output node NP via a switch SW in a feedback manner.

[0237] However, this is illustrative, and the structure of the voltage conversion unit VCP according to an embodiment of the present invention is not limited thereto. For example, the voltage conversion unit VCP may also include a structure that omits the resistor RT or an additional structure that is connected in parallel with the capacitor Cf.

[0238] Figure 12 This is a circuit diagram illustrating the electrical connection relationship between the sensing control circuit and the input sensing layer according to an embodiment of the present invention. Figure 12 The explanation addresses the use of... Figure 11 The constituent elements are described, and the same reference numerals are used in the accompanying drawings, but the description of them is omitted.

[0239] Reference Figure 10 as well as Figure 12 The display panel DP may include multiple constant current circuits CC1, CC2, and CC3. These multiple constant current circuits CC1, CC2, and CC3 can be configured within the internal DM-A of the display module 200. The configuration of multiple constant current circuits CC1, CC2, and CC3 within the display panel DP reduces the size of the sensing control circuit TIC. This reduces the size of the circuit board 300 (see reference). Figure 1 The size of the display device DD (refer to) can be reduced. Figure 1 The border area BZA (refer to) Figure 1 The size of ).

[0240] The multiple constant current circuits CC1, CC2, and CC3 may include a first constant current circuit CC1, a second constant current circuit CC2, and a third constant current circuit CC3. Figure 12 The illustration shows three constant current circuits CC1, CC2, and CC3, but the number of constant current circuits according to an embodiment of the present invention is not limited thereto.

[0241] The first constant current circuit CC1 may include a first transistor, which includes a first gate, a first source, and a first drain. The second constant current circuit CC2 may include a second transistor, which includes a second gate, a second source, and a second drain. The third constant current circuit CC3 may include a third transistor, which includes a third gate, a third source, and a third drain.

[0242] The first gate, the second gate, and the third gate can be electrically connected to multiple terminals of the sensing and control circuit TIC and electrically connected to the control signal unit CS.

[0243] The control signal unit CS can use the first to third control voltages CV1, CV2, and CV3 to control the on-off state of the first to third transistors, respectively.

[0244] The control signal unit CS can provide a first control voltage CV1 to the first gate. The first constant current circuit CC1 can flow a first current CI1 in the on-state. The first constant current circuit CC1 can cause at least a portion of the charge in the signal SG to move towards the ground electrode GD through the first current CI1. The first constant current circuit CC1 can eliminate at least a portion of the capacitance of parasitic capacitors Cb-1 and Cb-2 included in the signal SG.

[0245] The control signal unit CS can provide a second control voltage CV2 to the second gate. The second constant current circuit CC2 can flow a second current CI2 in the on-state. The second constant current circuit CC2 can cause at least a portion of the charge in the signal SG to move towards the ground electrode GD via the second current CI2. The second constant current circuit CC2 can eliminate at least a portion of the capacitance of parasitic capacitors Cb-1 and Cb-2 included in the signal SG.

[0246] The control signal unit CS can provide a third control voltage CV3 to the third gate. The third constant current circuit CC3 can flow a third current CI3 in the on state. The third constant current circuit CC3 can cause at least a portion of the charge in the signal SG to move towards the ground electrode GD through the third current CI3. The third constant current circuit CC3 can eliminate at least a portion of the capacitance of the parasitic capacitors Cb-1 and Cb-2 included in the signal SG.

[0247] The active regions AC of the first to third transistors (refer to) Figure 3c The widths of the currents CI1, CI2, and CI3 can be different from each other. That is, the intensities of the first to third currents CI1, CI2, and CI3 can be different from each other. The amount of signal components caused by the capacitance of parasitic capacitors Cb-1 and Cb-2, which are eliminated by the first to third constant current circuits CC1, CC2, and CC3, can be different from each other.

[0248] The sensing control circuit TIC can selectively control the operation of the first to third constant current circuits CC1, CC2, and CC3 using the first to third control voltages CV1, CV2, and CV3.

[0249] According to the present invention, the sensing control circuit TIC can select at least one of the first to third constant current circuits CC1, CC2, and CC3 based on the capacitance of the parasitic capacitors Cb-1 and Cb-2 to eliminate at least a portion of the component caused by the capacitance of the parasitic capacitors Cb-1 and Cb-2 from the signal SG sensed by the sensing electrode SP. The reference value of the signal SG sensed in the sensing electrode SP can be reduced by the first to third constant current circuits CC1, CC2, and CC3. The proportion of the component caused by the capacitance change of the sensing capacitor Ct relative to the reference value of the signal input to the output node NP can be increased. The sensing control circuit TIC can easily sense the capacitance change of the sensing capacitor Ct. Reliability can be improved for touch presence and touch position based on the external input TC. Therefore, a display device DD (refer to) with improved touch performance can be provided. Figure 1 ).

[0250] The first source, the second source, and the third source can be connected via the second terminal TM2 (refer to...). Figure 3a ) The input of the received signal SG.

[0251] The first drain, the second drain, and the third drain can be connected via the third terminal TM3 (see reference). Figure 3a It is electrically connected to the ground electrode GD.

[0252] As described above, embodiments are disclosed in the accompanying drawings and specification. While specific terminology is used herein, it is for illustrative purposes only and not for limiting the meaning or scope of the invention as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments can be implemented therefrom. Consequently, the true scope of protection of this invention should be determined by the concept of the appended claims.

Claims

1. A display device, wherein, include: Substrate; A display element layer is disposed on the substrate and includes driving electrodes; An insulating layer is disposed on the display element layer and defines the effective display area and the peripheral area adjacent to the effective display area; An input sensing layer is disposed on the insulating layer and includes a sensing electrode that overlaps the effective display area and generates a parasitic capacitance with the driving electrode, and a compensation electrode that overlaps the peripheral area. as well as The sensing control circuit is electrically connected to the sensing electrode and the compensation electrode via an output node. Each of the sensing control circuits uses the capacitance of the first offset capacitor generated through the compensation electrode to cancel the capacitance of the parasitic capacitor input through the output node. The compensation electrode includes a first compensation electrode and a second compensation electrode disposed on different layers to generate the first offset capacitor.

2. The display device according to claim 1, wherein, The input sensing layer includes: A first insulating layer is disposed on the insulating layer; The first conductive layer is disposed on the same layer as the first compensation electrode, i.e., on the first insulating layer. A second insulating layer is disposed on the first conductive layer; and The second conductive layer overlaps with the first compensation electrode and is disposed on the same layer as the second compensation electrode, namely the second insulating layer.

3. The display device according to claim 1, wherein, The sensing electrode includes a first sensing electrode and a second sensing electrode that is spaced apart from the first sensing electrode on a plane and has mutual capacitance with the first sensing electrode. The sensing control circuit outputs the detection signal and the compensation signal, which is phase-inverted with the detection signal, to the first sensing electrode and the first compensation electrode, respectively.

4. The display device according to claim 3, wherein, The sensing control circuit includes: A voltage conversion unit senses the sensing signal output from the second sensing electrode to the output node and the offset sensing signal output from the second compensation electrode to the output node, and outputs a detection voltage; and The offset control unit includes a second offset capacitor connected to the output node.

5. The display device according to claim 4, wherein, The capacitance of the second offset capacitor is less than the capacitance of the first offset capacitor.

6. The display device according to claim 4, wherein, The second offset capacitor includes: The third compensation electrode receives the offset signal corresponding to the compensation signal; and The fourth compensation electrode is connected to the output node.

7. The display device according to claim 6, wherein, The offset control unit also includes a switch configured between the third compensation electrode and the output node.

8. The display device according to claim 4, wherein, The second offset capacitor includes a plurality of auxiliary capacitors electrically connected to the output node and connected in parallel with each other.

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