Display device

Abstract

A display device is provided. The display device includes: a light-emitting element; a first transistor configured to transmit a driving current to the light-emitting element; and a second transistor configured to transmit a data signal to the first transistor, wherein the first transistor includes a first active layer, the second transistor includes a second active layer including an oxide semiconductor, and the light-emitting element includes: a first-conductivity-type semiconductor having a first polarity; a second-conductivity-type semiconductor having a second polarity different from the first polarity; and an active material layer disposed between the first-conductivity-type semiconductor and the second-conductivity-type semiconductor.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device including a light-emitting element having a size in the micron or nanometer unit and an oxide thin-film transistor. Background Art

[0002] With the development of multimedia, display devices have become increasingly important. In response to this development, various types of display devices are being used, such as organic light-emitting diode (OLED) display devices, liquid crystal display (LCD) devices, and the like.

[0003] The device for displaying an image of a display device includes a display panel, such as an OLED panel or an LCD panel. In the above panels, a light-emitting display panel may include a light-emitting element. For example, a light-emitting diode (LED) includes an OLED using an organic material as a fluorescent material and an inorganic LED using an inorganic material as a fluorescent material.

[0004] Compared with an OLED, an inorganic LED using an inorganic semiconductor as a fluorescent material has durability in a high-temperature environment and has the advantage of high blue light efficiency. In addition, even in the manufacturing process which is pointed out as a limitation of a conventional inorganic LED element, a transfer method using dielectrophoresis (DEP) has been developed. Therefore, research is being conducted on inorganic LEDs having excellent durability and excellent efficiency compared with OLEDs. Summary of the Invention

[0005] Technical Problem

[0006] The present invention aims to provide a display device including an oxide thin-film transistor as a circuit element layer for driving a light-emitting element having a fine size.

[0007] It should be noted that the object of the present invention is not limited to the above object, and other objects of the present invention will be apparent to those skilled in the art from the following description.

[0008] Technical Solution

[0009] According to an embodiment, a display device includes: a light-emitting element; a first transistor configured to transmit a driving current to the light-emitting element; and a second transistor configured to transmit a data signal to the first transistor, wherein the first transistor includes a first active layer, the second transistor includes a second active layer including an oxide semiconductor, and the light-emitting element includes: a first-conductive-type semiconductor having a first polarity; a second-conductive-type semiconductor having a second polarity different from the first polarity; and an active material layer disposed between the first-conductive-type semiconductor and the second-conductive-type semiconductor.

[0010] The first active layer of the first transistor may include an oxide semiconductor.

[0011] The oxide semiconductor may include indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO).

[0012] The length of the light-emitting element may be in the range of 4 μm to 7 μm, and the aspect ratio of the light-emitting element may be in the range of 1.2 to 100.

[0013] The first transistor may include a first gate electrode disposed under the first active layer.

[0014] The first active layer may include a first conductivity region, a second conductivity region, and a channel region disposed between the first conductivity region and the second conductivity region.

[0015] The first transistor may further include: a third gate electrode disposed on the first active layer; a first source electrode connected to the first conductivity region through a first contact hole penetrating an interlayer insulating film disposed on the third gate electrode; and a first drain electrode connected to the second conductivity region through a second contact hole penetrating the interlayer insulating film.

[0016] The first active layer may include polysilicon.

[0017] The first transistor may further include a light-blocking layer disposed under the first active layer.

[0018] The second transistor may include: a second gate electrode disposed under the second active layer; a second source electrode connected to one side of the second active layer; and a second drain electrode connected to the other side of the second active layer.

[0019] The display device may further include a data line configured to transmit a data signal, wherein the data line may further include a protrusion disposed to be spaced apart from the second source electrode of the second transistor and disposed to be connected to the second source electrode through a conductive pattern.

[0020] According to another embodiment, a display device includes: a substrate; a first gate electrode disposed on the substrate; a first gate insulating film disposed on the first gate electrode; a first active layer disposed on the first gate insulating film, partially overlapping with the first gate electrode, and including an oxide semiconductor; a first interlayer insulating film disposed on the first active layer; a second gate electrode disposed on the first interlayer insulating film; a second interlayer insulating film disposed on the second gate electrode; a second active layer disposed on the second interlayer insulating film, partially overlapping with the second gate electrode, and including an oxide semiconductor; and a first conductive layer including a first signal line disposed on the second interlayer insulating film and a source electrode formed on one side of the second active layer; wherein the first conductive layer further includes a conductive pattern partially overlapping with one side of the source electrode and the first signal line.

[0021] The display device may further include: a drain electrode disposed on the first gate insulating film and in contact with one side of the first active layer; a via hole layer disposed on the first conductive layer; and at least one light-emitting element disposed on the via hole layer, wherein the drain electrode is electrically connected to one end of the at least one light-emitting element.

[0022] The light-emitting element may include: a first-conductive-type semiconductor having a first polarity; a second-conductive-type semiconductor having a second polarity different from the first polarity; and an active material layer disposed between the first-conductive-type semiconductor and the second-conductive-type semiconductor.

[0023] According to another embodiment, a display device includes: a base layer; a first electrode and a second electrode spaced apart from each other in a first direction on the base layer; at least one light-emitting element connected to at least one of the first electrode and the second electrode and having a shape extending in the first direction; a driving transistor configured to transmit a driving current to the at least one light-emitting element, wherein the driving transistor includes an active layer having an oxide semiconductor, and the light-emitting element includes: a first-conductive-type semiconductor having a first polarity; a second-conductive-type semiconductor having a second polarity different from the first polarity; and an active material layer disposed between the first-conductive-type semiconductor and the second-conductive-type semiconductor.

[0024] The driving transistor may have a gate electrode disposed below the active layer.

[0025] Each of the first electrode and the second electrode may have a shape extending in a second direction different from the first direction on the base layer.

[0026] The display device may further include: a first contact electrode in contact with the first electrode and one end of the at least one light-emitting element; and a second contact electrode in contact with the second electrode and the other end of the at least one light-emitting element.

[0027] The at least one light-emitting element may have a length extending in the first direction and within a range of 4 μm to 7 μm, and an aspect ratio of the at least one light-emitting element may be within a range of 1.2 to 100.

[0028] The first-conductive-type semiconductor, the active material layer, and the second-conductive-type semiconductor may be disposed in a direction parallel to the upper surface of the base layer.

[0029] Details of other embodiments are included in the detailed description and the drawings.

[0030] Advantageous Effects

[0031] According to the present invention, the display device includes a light-emitting element having a size in micrometer or nanometer units.

[0032] According to the present invention, a display device includes a driving transistor including an oxide semiconductor and capable of driving a light-emitting element having a fine size.

[0033] The effects according to the embodiments are not limited to the above-exemplified content, and various more effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a perspective view showing a display device according to an embodiment.

[0035] Figure 2 is a schematic block diagram showing a display device according to an embodiment.

[0036] Figure 3 shows Figure 1 a schematic plan view of a display panel.

[0037] Figure 4 shows Figure 2 a circuit diagram of one sub-pixel.

[0038] Figure 5 is Figure 3 an enlarged schematic view of part A.

[0039] Figure 6 shows a cross-sectional view of a circuit element layer taken along line I-I' of Figure 5

[0040] Figure 7 is a partial plan view showing a circuit element layer according to an embodiment.

[0041] Figure 8 is a cross-sectional view taken along line Ⅱa-Ⅱa' of Figure 7

[0042] Figure 9 shows a cross-sectional view of a display element layer taken along lines I-I' and II-II' of Figure 5

[0043] Figures 10 to 12 is a cross-sectional view showing a circuit element layer according to another embodiment.

[0044] Figure 13 is a schematic view showing a light-emitting element according to an embodiment.

[0045] Figure 14 is a schematic view showing a light-emitting element according to another embodiment. DETAILED DESCRIPTION

[0046] ​​​The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0047] It should also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components.

[0048] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present invention, the first element discussed below could be termed the second element. Similarly, the second element could also be termed the first element.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 is a schematic block diagram showing a display device according to an embodiment. Figure 3 shows Figure 1 a schematic plan view of a display panel of

[0051] Referring to Figures 1 to 3 , a display device 1 according to an embodiment includes a display panel 10, an integrated driving circuit 20, a scan driver 30, a circuit board 40, and a power circuit 50. The integrated driving circuit 20 may include a data driver 21 and a timing controller 22.

[0052] In this specification, the terms "upper", "top", and "upper surface" denote the Z-axis direction, and the terms "lower", "bottom", and "lower surface" denote the direction opposite to the Z-axis direction. In addition, the terms "left", "right", "up", and "down" refer to the directions when viewing the display panel 10 in a plane. For example, the term "left" refers to the direction opposite to the X-axis direction, the term "right" refers to the X-axis direction, the term "up" refers to the Y-axis direction, and the term "down" refers to the direction opposite to the Y-axis direction.

[0053] When observed in a plan view, the display panel 10 may be formed in a rectangular shape. For example, as Figure 1As shown, the display panel 10 may have a planar form with a rectangular shape that has a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may form right angles or may be rounded to have a predetermined curvature. The planar form of the display panel 10 is not limited to a rectangular shape and may be formed as a polygonal shape, a circular shape, or an oval shape different from a rectangular shape. In addition, although in Figure 1 the display panel 10 is shown as being flat, the present invention is not limited thereto. At least one side of the display panel 10 may be formed to be curved with a predetermined curvature.

[0054] The display panel 10 may be divided into a display area DA and a non-display area NDA provided in a peripheral area of the display area DA. The display area DA is an area where a plurality of pixels PX are formed to display an image. The display panel 10 may include data lines DL1 to DLm (m is an integer of 2 or more), scan lines SL1 to SLn (n is an integer of 2 or more) that cross the data lines DL1 to DLm, a first voltage line QVDDL that provides a first voltage QVDD, a second voltage line QVSSL that provides a second voltage QVSS, and pixels PX connected to the data lines DL1 to DLm and the scan lines SL1 to SLn.

[0055] Each pixel PX may include one or more light-emitting elements 300 that emit light within a specific wavelength range to display a color. The light emitted from the light-emitting element 300 may be displayed to the outside through the display area DA of the display panel 10.

[0056] Each pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. The first color may be red, the second color may be green, and the third color may be blue, but the present invention is not limited thereto. In some cases, the sub-pixel PXn may emit multiple lights of the same color. In addition, although in Figure 2 each pixel PX is shown as including three sub-pixels, the present invention is not limited thereto, and each pixel PX may include four or more sub-pixels.

[0057] The integrated driving circuit 20 outputs signals and voltages for driving the display panel 10. To this end, the integrated driving circuit 20 may include a data driver 21 and a timing controller 22.

[0058] The data driver 21 receives digital video data DATA and a source control signal DCS from the timing controller 22. In response to the source control signal DCS, the data driver 21 converts the digital video data DATA into an analog data voltage and supplies the analog data voltage to data lines DL1 to DLm of the display panel 10.

[0059] The timing controller 22 may receive digital video data DATA and timing signals from a main system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The main system may be an application processor of a smart phone or a tablet personal computer (PC) or a system-on-chip of a monitor or a television (TV).

[0060] The timing controller 22 generates control signals to control the operation timings of the data driver 21 and the scan driver 30. The control signals may include a source control signal DCS for controlling the operation timing of the data driver 21 and a scan control signal SCS for controlling the operation timing of the scan driver 30.

[0061] The integrated drive circuit 20 may be disposed in a non-display area NDA provided on one side of the display panel 10. The integrated drive circuit 20 may be formed as an integrated circuit (IC) and may be disposed on the display panel 10 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. However, the present invention is not limited thereto. For example, the integrated drive circuit 20 may be mounted on a circuit board 40 instead of being mounted on the display panel 10.

[0062] In addition, although the integrated drive circuit 20 is shown as including the data driver 21 and the timing controller 22 in Figure 2 , the present invention is not limited thereto. The data driver 21 and the timing controller 22 may not be formed as a single integrated circuit but may be formed as separate ICs. In this case, the data driver 21 may be mounted on the display panel 10 by a COG method, a COP method, or an ultrasonic bonding method, and the timing controller 22 may be mounted on the circuit board 40.

[0063] The scan driver 30 receives a scan control signal SCS from the timing controller 22. In response to the scan control signal SCS, the scan driver 30 generates scan signals and supplies the scan signals to scan lines SL1 to SLn of the display panel 10. The scan driver 30 may include a plurality of transistors and may be formed in the non-display area NDA of the display panel 10. Alternatively, the scan driver 30 may be formed as an IC, and in this case, the scan driver 30 may be mounted on a gate flexible film attached to one side of the display panel 10.

[0064] The circuit board 40 can be attached to pads disposed at an edge on one side of the display panel 10 by using an anisotropic conductive film. Accordingly, leads of the circuit board 40 can be electrically connected to the pads. The circuit board 40 can be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip on film. The circuit board 40 can be bent downward from the display panel 10. In this case, one side of the circuit board 40 can be attached to an edge on one side of the display panel 10, and the other side of the circuit board 40 can be disposed below the display panel 10 and connected to a system board on which a main system is mounted.

[0065] The power supply circuit 50 can generate voltages required to drive the display panel 10 based on main power applied from the system board, and supply the voltages to the display panel 10. For example, the power supply circuit 50 can generate a first voltage QVDD and a second voltage QVSS for driving the light-emitting elements 300 of the display panel 10 based on the main power, and supply the first voltage QVDD and the second voltage QVSS to a first voltage line QVDDL and a second voltage line QVSSL. In addition, the power supply circuit 50 can generate and supply a driving voltage for driving the integrated driving circuit 20 and the scan driver 30 based on the main power.

[0066] Although the power supply circuit 50 has been formed as an IC to be mounted on the Figure 1 circuit board 40, embodiments of the present invention are not limited thereto. For example, the power supply circuit 50 can be formed to be integrated into the integrated driving circuit 20.

[0067] Figure 3 A plan view of the Figure 1 display panel 10 is shown in a relatively detailed manner. In Figure 3 , for ease of description, only data pads DP1 to DPp (p is an integer of 2 or greater), floating pads FD1 and FD2, power pads PP1 and PP2, floating lines FL1 and FL2, a second voltage line QVSSL, data lines DL1 to DLm, a first electrode line 210, and a second electrode line 220 are shown.

[0068] Referring to Figure 3 , a plurality of pixels PX can be provided in a display area DA of the display panel 10, and a plurality of electrode lines 210 and 220 and light-emitting elements 300 between the plurality of electrode lines 210 and 220 can be aligned in each pixel PX. In the drawings, the plurality of pixels PX can be provided in a first direction (X-axis direction) as a horizontal direction and a second direction (Y-axis direction) as a longitudinal direction. Although three sub-pixels PX1, PX2, and PX3 are shown in a portion A of Figure 3 , it is apparent that the display panel 10 can include a larger number of pixels PX or sub-pixels PX1, PX2, and PX3.

[0069] The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 of each pixel PX may be disposed in a region defined in a matrix form by the first electrode line 210, the second electrode line 220, and the data lines DL1 to DLm.

[0070] In addition, Figure 3 the pixel PX may be divided into a plurality of pixels such that each pixel may constitute one pixel PX. As Figure 3 shown, the pixels do not have to be arranged parallel in the first direction (X-axis direction) and the second direction (Y-axis direction), and may be arranged in various structures, such as pixels arranged in a zigzag shape or the like.

[0071] The non-display area NDA may be defined as an area where no pixel PX is disposed and an area other than the display area DA in the display panel 10. The non-display area NDA may be covered by a specific member so as not to be visually recognized from the outside of the display panel 10. Various components for driving the light-emitting element 300 disposed in the display area DA may be disposed in the non-display area NDA. As Figure 3 shown, in the display panel 10, a plurality of pads DP, FP, and PP may be disposed on one side of the display area DA, for example, in the non-display area NDA located at the upper part when viewed in a plan view.

[0072] The plurality of pads may include data pads DP, power pads PP, and floating pads FP. The data pads DP may be connected to a plurality of data lines DL extending to the pixels PX in the display area DA. The data pads DP may transmit data signals for driving the pixels PX to the pixels PX through the data lines DL. One data pad DP may be connected to one data line DL, and the display panel 10 may include as many data pads DP as the number of sub-pixels PXn disposed in the first direction (X-axis direction) of the display area DA.

[0073] The data lines DL1 to DLm may extend long in the second direction (Y-axis direction). One side of the data lines DL1 to DLm may be connected to the integrated driving circuit 20. Therefore, the data voltage of the integrated driving circuit 20 may be applied to the data lines DL1 to DLm.

[0074] The first electrode line 210 may be arranged at a predetermined interval in the first direction (X-axis direction). Therefore, the first electrode line 210 may not overlap with the data lines DL1 to DLm. When manufacturing the display panel 10, the first electrode line 210 is formed such that both end portions of one electrode line are respectively connected to the first floating line FL1 and the second floating line FL2 in the non-display area NDA, and in addition, the connection is disconnected at each pixel PX or each sub-pixel PXn.

[0075] Each second electrode line 220 may extend long in the first direction (X-axis direction). Accordingly, the second electrode lines 220 may overlap with the data lines DL1 to DLm. Further, unlike the first electrode lines 210, the second electrode lines 220 may be connected to a second voltage line QVSSL in the non-display area NDA. Accordingly, a second voltage QVSS of the second voltage line QVSSL may be applied to the second electrode lines 220.

[0076] In the non-display area NDA of the display panel 10, a pad portion PA including data pads DP1 to DPp, floating pads FD1 and FD2, and power pads PP1 and PP2, an integrated driving circuit 20, a first floating line FL1, a second floating line FL2, and a second voltage line QVSSL may be provided.

[0077] The pad portion PA including the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2 may be provided on an edge of one side of the display panel 10, for example, on the edge of the lower side of the display panel 10. The data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2 may be provided to be parallel in the first direction (X-axis direction) in the pad portion PA.

[0078] The circuit board 40 may be bonded to the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2 by using an anisotropic conductive film. Accordingly, the circuit board 40 may be electrically connected to the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2.

[0079] The integrated driving circuit 20 may be connected to the data pads DP1 to DPp through connection lines. The integrated driving circuit 20 may receive digital video data DATA and a timing signal through the data pads DP1 to DPp. The integrated driving circuit 20 may convert the digital video data DATA into an analog data voltage and provide the analog data voltage to the data lines DL1 to DLm of the display panel 10.

[0080] The second voltage line QVSSL may be connected to the first power pad PP1 and the second power pad PP2 of the pad portion PA. The second voltage line QVSSL may extend long in the second direction (Y-axis direction) in the non-display area NDA on the left outer side and the right outer side of the display area DA. The second voltage line QVSSL may be connected to the second electrode lines 220. Accordingly, a second voltage QVSS of the power supply circuit 50 may be applied to the second electrode lines 220 through the circuit board 40, the first power pad PP1, the second power pad PP2, and the second voltage line QVSSL.

[0081] The first floating line FL1 can be connected to the first floating pad FD1 of the pad portion PA. The first floating line FL1 can extend long in the second direction (Y-axis direction) in the non-display area NDA on the left outer side and the right outer side of the display area DA.

[0082] The second floating line FL2 can be connected to the second floating pad FD2 of the pad portion PA. The second floating line FL2 can extend long in the second direction (Y-axis direction) in the non-display area NDA on the left outer side and the right outer side of the display area DA. The first floating pad FD1 and the second floating pad FD2, and the first floating line FL1 and the second floating line FL2 can be dummy pads and dummy lines to which no voltage is applied.

[0083] The first floating line FL1 and the second floating line FL2 are lines for applying an alignment signal during the manufacturing process, and no voltage may be applied to the first floating line FL1 and the second floating line FL2 in the completed display device. Optionally, a ground voltage can be applied to the first floating line FL1 and the second floating line FL2 to prevent static electricity in the completed display device.

[0084] In addition, although not shown in the drawings, in the display panel 10, a first voltage line QVDDL for applying the first voltage QVDD to each pixel PX can be further provided. One side of the first voltage line QVDDL can be connected to another pad (not shown) to apply a predetermined voltage to each pixel PX or each sub-pixel PXn.

[0085] Meanwhile, during the manufacturing process of the display panel 10, an electric field can be formed in each pixel PX or each sub-pixel PXn to align the light-emitting element 300. Specifically, during the manufacturing process, a dielectrophoretic force can be applied to the light-emitting element 300 using the dielectrophoresis method to align the light-emitting element 300. Since a ground voltage is applied to the first electrode line 210 and an alternating voltage (AC) is applied to the second electrode line 220 to form an electric field in the pixel PX or the sub-pixel PXn, the light-emitting element 300 can receive the dielectrophoretic force through the electric field to align between the electrodes.

[0086] Figure 4 is a circuit diagram of Figure 2 one sub-pixel.

[0087] Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may be connected to at least one of the data lines DL1 to DLm, at least one of the scan lines SL1 to SLn, and the first voltage line QVDDL. The data line DLj may transmit a data signal DATA to the sub-pixel PXn, the scan line SLk may transmit a scan signal GW to the sub-pixel PXn, and the first voltage line QVDDL may transmit a driving current or an alignment signal to the sub-pixel PXn.

[0088] Meanwhile, in the present disclosure, terms such as "first" and "second" are used to refer to each component, but these terms are used simply to distinguish the components from each other and do not necessarily refer to the corresponding components. That is, the components defined as first, second, etc. do not have to be limited to a specific structure or position, and in some cases, other numbers may be assigned to the components. Therefore, the numbers assigned to each component can be described through the drawings and the following description, and the first component mentioned below may be the second component within the technical idea of the present invention.

[0089] Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include a light-emitting element 300, a plurality of transistors for supplying current to the light-emitting element 300, and at least one capacitor.

[0090] The plurality of transistors may include a first transistor TR1 for applying a driving voltage to the light-emitting element 300 and a second transistor TR2 for applying a data signal DATA to the gate electrode of the first transistor TR1.

[0091] In Figure 4 Although the sub-pixel PXn has been shown as having a two-transistor one-capacitor (2T1C) structure with one first transistor TR1, one second transistor TR2, and one capacitor Cst, the present invention is not limited thereto. The sub-pixel PXn may include a greater number of transistors and a plurality of capacitors.

[0092] Each of the first transistor TR1 and the second transistor TR2 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0093] Each of the first transistor TR1 and the second transistor TR2 may be formed of a thin-film transistor. In addition, in Figure 4In this case, although each of the first transistor TR1 and the second transistor TR2 is described as being formed of a p-type metal oxide semiconductor field effect transistor (MOSFET), the present invention is not limited thereto. Each of the first transistor TR1 and the second transistor TR2 may be formed of an n-type MOSFET. In this case, the positions of the source electrode and the drain electrode of each of the first transistor TR1 and the second transistor TR2 may be changed. Hereinafter, a case where each of the first transistor TR1 and the second transistor TR2 is formed of a p-type MOSFET will be described.

[0094] One end of the light emitting element 300 is connected to the first electrode line 210 of the display panel 10, and the other end of the light emitting element 300 is connected to the second electrode line 220. As described below, one of the first electrode line 210 and the second electrode line 220 may be an anode electrode, and the other of the first electrode line 210 and the second electrode line 220 may be a cathode electrode. However, the present invention is not limited thereto, and it may be reversible. Hereinafter, a case where the first electrode line 210 is an anode electrode and the second electrode line 220 is a cathode electrode will be described.

[0095] The first electrode line 210 connected to the light emitting element 300 may be connected to Figure 4 the third node N3, and the second electrode line 220 may be connected to the second voltage line QVSSL. The light emitting element 300 may receive a predetermined current or a predetermined signal transmitted to the first node N1 through the third node N3.

[0096] The first transistor TR1 (or driving transistor) may include a first electrode connected (or electrically connected) to the first node N1, a second electrode connected to the first voltage line QVDDL, and a gate electrode connected to the second node N2. The first transistor TR1 may supply a driving voltage applied from the first voltage line QVDDL to the light emitting element 300 based on the voltage of the second node N2 (or the voltage stored in the capacitor Cst to be described below).

[0097] The second transistor TR2 (or switching transistor) may include a first electrode connected to the data line DLj (j is an integer satisfying 1 ≤ j ≤ m), a second electrode connected to the second node N2, and a gate electrode connected to the first scan line SLk (k is an integer satisfying 1 ≤ k ≤ n), and the gate electrode provides a first scan signal GW. The second transistor TR2 may be turned on in response to the first scan signal GW to transmit the data signal DATA transmitted from the data line DLj to the second node N2.

[0098] The capacitor Cst may be connected between the second node N2 and the first voltage line QVDDL. The capacitor Cst may store or hold the provided data signal DATA.

[0099] Hereinafter, the structure and arrangement of components provided in each sub-pixel PXn will be described.

[0100] Figure 5 is Figure 3 an enlarged schematic view of part A of Figure 5 which can be understood as an enlarged view obtained by rotating part A of Figure 3 by up to 180°.

[0101] Referring to Figure 5 , each pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 of each pixel PX may be arranged in a matrix in a region defined by an intersection structure of scan lines SLk and SLk+1 and data lines DLj, DLj+1, DLj+2, and DLj+3. The scan lines SLk and SLk+1 may be arranged to extend long in a first direction (X-axis direction), and the data lines DLj, DLj+1, DLj+2, and DLj+3 may be arranged to extend long in a second direction (Y-axis direction) intersecting the first direction (X-axis direction).

[0102] Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include a first electrode line 210, a second electrode line 220, and a plurality of light-emitting elements 300. The first electrode line 210 and the second electrode line 220 may be electrically connected to the light-emitting element 300 and may each receive a voltage to cause the light-emitting element 300 to emit light. Here, the voltage applied to cause the light-emitting element 300 to emit light may be transmitted through Figure 4 the first transistor TR1 of

[0103] In addition, at least a part of each of the electrode lines 210 and 220 may be used to form an electric field in the pixel PX to align the light-emitting element 300. The voltage applied to align the light-emitting element 300 may be transmitted through Figure 4 the first transistor TR1 of

[0104] The plurality of electrode lines 210 and 220 may include the first electrode line 210 and the second electrode line 220. In an example, the first electrode line 210 may be a pixel electrode separated in each pixel PX, and the second electrode line 220 may be a common electrode commonly connected along a plurality of pixels PX. One of the first electrode line 210 and the second electrode line 220 may be an anode electrode of the light-emitting element 300, and the other thereof may be a cathode electrode of the light-emitting element 300. However, the present invention is not limited thereto and may be reversible.

[0105] The first electrode line 210 and the second electrode line 220 may include electrode bar portions 210S and 220S arranged to extend in a first direction (X-axis direction) and at least one electrode branch portion 210B and 220B extending in a second direction (Y-axis direction) that intersects the first direction and branching from the electrode bar portions 210S and 220S.

[0106] Specifically, the first electrode line 210 may include a first electrode bar portion 210S arranged to extend in the first direction (X-axis direction) and at least one first electrode branch portion 210B branching from the first electrode bar portion 210S to extend in the second direction (Y-axis direction).

[0107] The first electrode bar portion 210S of any one sub-pixel PXn may be arranged to be substantially collinear with the first electrode bar portion 210S of an adjacent sub-pixel PXn belonging to the same row (e.g., a sub-pixel PXn adjacent in the first direction (X-axis direction)). In other words, both ends of the first electrode bar portion 210S of a sub-pixel PXn are spaced apart and terminate between sub-pixels PXn, and the first electrode bar portion 210S of an adjacent sub-pixel PXn may be aligned with an extension line of the first electrode bar portion 210S of a sub-pixel PXn. Therefore, the first electrode bar portion 210S provided in each pixel PX may apply different electrical signals to the first electrode branch portion 210B and may drive the first electrode branch portion 210B individually.

[0108] The arrangement of the first electrode bar portion 210S may be formed such that a single connected bar electrode is formed during the manufacturing process and then disconnected by a laser or the like before aligning the light-emitting element 300.

[0109] The first electrode branch portion 210B may branch from at least a part of the first electrode bar portion 210S and may be arranged to extend in the second direction (Y-axis direction). The first electrode branch portion 210B may terminate in a state spaced apart from the second electrode bar portion 220S, and the second electrode bar portion 220S is arranged to face the first electrode bar portion 210S.

[0110] In addition, one or more first electrode branch portions 210B may be provided in each sub-pixel PXn. Figure 5 Two first electrode branch portions 210B are shown provided, and the second electrode branch portion 220B is provided between the two first electrode branch portions 210B, but the present invention is not limited thereto, and a larger number of first electrode branch portions 210B may be provided. In some embodiments, the second electrode branch portion 220B is provided between the first electrode branch portions 210B such that each sub-pixel PXn may have a symmetric structure based on the second electrode branch portion 220B. However, the present invention is not limited thereto.

[0111] The second electrode line 220 may include a second electrode rod portion 220S and at least one second electrode branch portion 220B. The second electrode rod portion 220S extends in a first direction (X-axis direction) and is arranged to be spaced apart from and opposite to the first electrode rod portion 210S. The second electrode branch portion 220B branches from the second electrode rod portion 220S and extends in a second direction (Y-axis direction) to be spaced apart from and opposite to the first electrode branch portion 210B. However, one end of the second electrode rod portion 220S may extend in the first direction to a plurality of adjacent sub-pixels PXn. Accordingly, both ends of the second electrode rod portion 220S of any one sub-pixel PXn may be connected to one end of the second electrode rod portion 220S of an adjacent sub-pixel PXn in the sub-pixel PXn.

[0112] The second electrode branch portion 220B may be spaced apart from and opposite to the first electrode branch portion 210B and terminate in a state spaced apart from the first electrode rod portion 210S. That is, one end of the second electrode branch portion 220B may be connected to the second electrode rod portion 220S, and the other end thereof may be disposed in the pixel PX in a state spaced apart from the first electrode rod portion 210S.

[0113] The first electrode branch portion 210B extends in one direction of the second direction (Y-axis direction), and the second electrode branch portion 220B extends in the other direction of the second direction (Y-axis direction) such that one end of the first electrode branch portion 210B and one end of the second electrode branch portion 220B may be disposed in opposite directions based on the central portion of the pixel PX. However, the present invention is not limited thereto, and the first electrode rod portion 210S and the second electrode rod portion 220S may be spaced apart from each other in the same direction based on the central portion of the pixel PX. In this case, the first electrode branch portion 210B and the second electrode branch portion 220B respectively branched from the electrode rod portions 210S and 220S may extend in the same direction.

[0114] A plurality of light-emitting elements 300 may be disposed between the first electrode branch portion 210B and the second electrode branch portion 220B. One end of at least some of the plurality of light-emitting elements 300 may be electrically connected to the first electrode branch portion 210B, and the other end thereof may be electrically connected to the second electrode branch portion 220B.

[0115] A plurality of light-emitting elements 300 may be spaced apart from each other in a second direction (Y-axis direction) and disposed substantially parallel to each other. The separation gap between the light-emitting elements 300 is not particularly limited. In some cases, a plurality of light-emitting elements 300 may be disposed adjacent to each other to form a group, and a plurality of other light-emitting elements 300 may be grouped in a state of being spaced apart from each other at regular intervals, may have uneven density, and may be oriented and aligned in one direction.

[0116] The contact electrodes 260 may be disposed on each of the first electrode branch portion 210B and the second electrode branch portion 220B.

[0117] A plurality of contact electrodes 260 may be disposed to extend in the second direction (Y-axis direction) and disposed to be spaced apart from each other in a first direction (X-axis direction). The contact electrodes 260 may be in contact with at least one end of the light-emitting element 300, and the contact electrodes 260 may be in contact with the first electrode line 210 or the second electrode line 220 to receive an electrical signal. Thus, the contact electrodes 260 may transmit the electrical signals transmitted from each of the electrode lines 210 and 220 to the light-emitting element 300.

[0118] The contact electrodes 260 may be disposed to partially cover the first electrode branch portion 210B and the second electrode branch portion 220B, and may include a first contact electrode 261 and a second contact electrode 262 that are respectively in contact with one end and the other end of the light-emitting element 300.

[0119] The first contact electrode 261 may be disposed on the first electrode branch portion 210B and may be in contact with one end of the light-emitting element 300 that is electrically connected to the first electrode line 210. The second contact electrode 262 may be disposed on the second electrode branch portion 220B and may be in contact with the other end of the light-emitting element 300 that is electrically connected to the second electrode line 220.

[0120] In some embodiments, the two ends of the light-emitting element 300 that are electrically connected to the first electrode branch portion 210B and the second electrode branch portion 220B may be conductive semiconductor layers doped with n-type or p-type. When one end of the light-emitting element 300 that is electrically connected to the first electrode branch portion 210B is a conductive semiconductor layer doped with p-type, the other end of the light-emitting element 300 that is electrically connected to the second electrode branch portion 220B may be a conductive semiconductor layer doped with n-type. However, the present invention is not limited thereto and may be reversible.

[0121] Meanwhile, the first electrode bar portion 210S can be electrically connected to the first transistor TR1, which will be described below, through the electrode contact hole CNTD. In addition, although not shown in the drawings, the second electrode bar portion 220S can be connected to the second voltage line QVSSL through an electrode contact hole located in the non-display area NDA. In this case, different from the first electrode bar portion 210S, in each sub-pixel PXn, a separate electrode contact hole can be omitted from the second electrode bar portion 220S. However, the present invention is not limited thereto, and a predetermined electrode contact hole can also be formed in the second electrode bar portion 220S so that the second electrode bar portion 220S can be electrically connected to the second voltage line QVSSL.

[0122] Meanwhile, Figure 5 Only a plan view of the display panel 10 in which the first electrode line 210, the second electrode line 220, and the light-emitting element 300 are provided is shown. However, as described below, the first electrode line 210 and the second electrode line 220 of the display panel 10 can be electrically connected to components in the circuit element layer located below the first electrode line 210 and the second electrode line 220. The components provided in the circuit element layer can constitute a plurality of elements, including a semiconductor layer and a plurality of conductive layers.

[0123] Hereinafter, the specific configuration of the display panel 10 will be described in detail with reference to the plan view and cross-sectional view of the display panel 10.

[0124] Figure 6 is a cross-sectional view of the circuit element layer taken along the Figure 5 line I-I'. Figure 7 is a partial plan view of the circuit element layer according to an embodiment, and Figure 8 is a cross-sectional view taken along the Figure 7 line Ⅱa-Ⅱa'. Figure 9 is a cross-sectional view of the display element layer taken along the Figure 5 line I-I' and line II-II'.

[0125] According to an embodiment, the display panel 10 can include a circuit element layer 10a and a display element layer 10b. The circuit element layer 10a can include the first transistor TR1 and the second transistor TR2 and the capacitor Cst described with reference to Figure 4 and the display element layer 10b can include the first electrode line 210, the second electrode line 220, and the light-emitting element 300. In the drawings, only the layout diagram of one sub-pixel PXn is shown, but it is obvious that other sub-pixels PXn have the same layout. Hereinafter, the description will be based on one sub-pixel PXn.

[0126] In addition, in the following description, even if some components are the same as Figures 1 to 4The components mentioned therein are basically the same, but in order to easily describe the arrangement and connection relationship between the components, new reference numerals are assigned to these components.

[0127] Meanwhile, Figure 6 the line I-I' of Figure 5 may correspond to the line I-I' of Figure 6 That is to say, it can be understood that the cross-sectional view shown in Figure 5 shows the components in the circuit element layer 10a of the plan view located in Figure 9 In addition, the line I-I' and the line II-II' of Figure 5 correspond to the line I-I' and the line II-II' of Figure 9 and it can be understood that Figures 5 to 9 partially shows the components located in the display element layer 10b. Hereinafter, a plurality of components of the display panel 10 will be described in detail with reference to

[0128] Referring to Figures 5 to 9 the circuit element layer 10a may include a first transistor 120, a second transistor 140, a data line 191, a conductive pattern 193, a voltage line 195, and a via hole layer 200.

[0129] The display element layer 10b may be provided on the via hole layer 200 and may include dams 410 and 420, reflection layers 211 and 221, electrode layers 212 and 222, a first insulating layer 510, a first contact electrode 261, a second contact electrode 262, a second insulating layer 520, and a passivation layer 550. The reflection layers 211 and 221 and the electrode layers 212 and 222 may form electrodes 210 and 220.

[0130] Each of the above layers may be formed of a single layer, or may also be formed of a stacked layer including a plurality of layers. In addition, another layer may be further provided between the above layers. In particular, the circuit element layer 10a is not limited to Figures 6 to 8 the structure shown in

[0131] and more conductive layers, insulating layers, and signal lines may be further provided in the circuit element layer 10a. Figures 6 to 8 Hereinafter, the circuit element layer 10a of the display panel 10 will be described with reference to Figure 5 and then the display element layer 10b will be described with reference to Figure 9 and

[0132] First, referring to Figures 6 to 8, the substrate 100 supports the layers disposed thereon. The substrate 100 may be an insulating substrate made of an insulating material such as glass, quartz, polymer resin, etc. Examples of the polymer material may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. The substrate 100 may include a metal material.

[0133] In addition, the substrate 100 may be a rigid substrate or a flexible substrate such as bendable, foldable, rollable, etc. However, the present invention is not limited thereto.

[0134] A buffer layer 110 may be disposed on the substrate 100. The buffer layer 110 may prevent the diffusion of impurity ions and the penetration of water or outdoor air, and perform a surface planarization function. The buffer layer 110 may include silicon nitride, silicon oxide, silicon oxynitride, etc. Meanwhile, a plurality of other layers may be further disposed between the substrate 100 and the buffer layer 110.

[0135] The first transistors 120 (121, 123, 124, and 126) and the second transistors 140 (141, 143, 144, and 146) are disposed on the substrate 100. The first transistor 120 may be a driving transistor for driving the display element layer 10b of the first transistor TR1 as Figure 4 , and the second transistor 140 may be a switching transistor for transmitting the data signal DATA to the first transistor TR1 of the second transistor TR2 as Figure 4 .

[0136] The first transistor 120 includes a first gate electrode 121, a first active layer 126, a first source electrode 123, and a first drain electrode 124. The second transistor 140 includes a second gate electrode 141, a second active layer 146, a second source electrode 143, and a second drain electrode 144.

[0137] The first gate electrode 121 and the second gate electrode 141 are disposed on the buffer layer 110. The first gate electrode 121 may constitute the gate electrode of the first transistor 120, and the second gate electrode 141 may constitute the gate electrode of the second transistor 140. Each of the first gate electrode 121 and the second gate electrode 141 may be formed of a conductive metal layer. For example, each of the first gate electrode 121 and the second gate electrode 141 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0138] The first gate insulating film 130 is disposed on the first gate electrode 121 and the second gate electrode 141. The first gate insulating film 130 may be a gate insulating film having a gate insulating function. The first gate insulating film 130 may include a silicon compound, a metal oxide, etc. For example, the first gate insulating film 130 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These may be used alone or in combination thereof. The first gate insulating film 130 may be a single layer or multiple layers made of a stacked layer of different materials.

[0139] The first active layer 126 and the second active layer 146 are disposed on the first gate insulating film 130. The first active layer 126 and the second active layer 146 may be active layers that form the channels of the first transistor 120 and the second transistor 140. Each of the first active layer 126 and the second active layer 146 may include a channel region.

[0140] The first active layer 126 may overlap with the first gate electrode 121, and the first gate insulating film 130 is interposed between the first active layer 126 and the first gate electrode 121, and the overlapping region may form a first channel region. The second active layer 146 may overlap with the second gate electrode 141, and the first gate insulating film 130 is interposed between the second active layer 146 and the second gate electrode 141, and the overlapping region may form a second channel region.

[0141] Each of the first active layer 126 and the second active layer 146 may be made of an oxide semiconductor. The oxide semiconductor may include binary compounds (AB x ) containing indium, zinc, gallium, tin, Ti, Al, hafnium (Hf), zirconium (Zr), Mg, etc., ternary compounds (AB x C y ) or quaternary compounds (AB x C y D z)。In one embodiment, the oxide semiconductor may include indium tin zinc oxide (ITZO) (which is an oxide including indium, tin, and zinc) or indium gallium zinc oxide (IGZO) (which is an oxide including indium, gallium, and zinc). That is, according to one embodiment, each of the first transistor 120 and the second transistor 140 may have a bottom-gate structure in which a channel region is disposed above the gate electrode 121 or 141, and the channel region may include an oxide semiconductor. Thus, when manufacturing the display device 1, the manufacturing cost of the circuit element layer 10a can be reduced.

[0142] The first source electrode 123, the first drain electrode 124, the second source electrode 143, and the second drain electrode 144 are disposed on the first active layer 126 and the second active layer 146 on the first gate insulating film 130. The first source electrode 123 is disposed on one side of the first active layer 126, and the first drain electrode 124 is disposed on the other side of the first active layer 126. The second source electrode 143 is disposed on one side of the second active layer 146, and the second drain electrode 144 is disposed on the other side of the second active layer 146. Each of the first source electrode 123, the first drain electrode 124, the second source electrode 143, and the second drain electrode 144 may include one or more metals selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu.

[0143] Meanwhile, the data line 191 and the conductive pattern 193 may be further disposed on the first gate insulating film 130. The data line 191 may transmit a data signal (hereinafter referred to as Figure 4 "data signal DATA" in the following). One side of the conductive pattern 193 is disposed on the data line 191, and the other side thereof is disposed on the second source electrode 143 of the second transistor 140. The second transistor 140 may receive the data signal DATA transmitted to the data line 191 through the conductive pattern 193.

[0144] Specifically, for reference Figure 5 、 Figure 7 and Figure 8 description, the data line 191 may extend in one direction. As Figure 5 shown, the data line 191 may extend in the second direction (Y-axis direction), cross the boundary of the pixel PX or the sub-pixel PXn, and extend to an adjacent pixel PX or sub-pixel PXn. The data line 191 may be disposed on one side of a pixel PX or a sub-pixel PXn, for example, disposed adjacent to the left side of a pixel PX or a sub-pixel PXn.

[0145] The gate line GL can extend in one direction and can partially overlap with the data line 191. The gate line GL can extend in the first direction (X-axis direction) and overlap with the data line 191 that extends in the second direction (Y-axis direction). According to one embodiment, the data line 191 may include a protrusion 191a that protrudes in the first direction (X-axis direction) in the region overlapping with the gate line GL.

[0146] Figure 7 The protrusion 191a can be Figure 8 of the data line 191. The protrusion 191a of the data line 191 can protrude in the first direction (X-axis direction) and can terminate at a distance from the second source electrode 143 of the second transistor 140. The protrusion 191a of the data line 191 and the second source electrode 143 of the second transistor 140 can be arranged to be spaced apart from each other, and the conductive pattern 193 can be arranged between the protrusion 191a and the second source electrode 143.

[0147] The data line 191 and the conductive pattern 193 can include the same material as the second source electrode 143. That is, the conductive pattern 193 can include a conductive metal material and can electrically connect the data line 191 to the second source electrode 143. The data signal DATA transmitted from the data line 191 can be transmitted to the second source electrode 143 of the second transistor 140 through the protrusion 191a and the conductive pattern 193.

[0148] The first protective film 150 is disposed on the first source electrode 123, the first drain electrode 124, the second source electrode 143, the second drain electrode 144, the data line 191, and the conductive pattern 193. The first protective film 150 can be formed of an inorganic layer, such as a silicon oxide film (SiO x ), a silicon nitride film (SiN x ), or multiple layers thereof.

[0149] The voltage line 195 is disposed on the first protective film 150. Although not shown in the drawings, the voltage line 195 can be electrically connected to the first transistor 120 to transmit the voltage signals "QVDD" or "QVSS" thereto (see Figure 4 ). The voltage line 195 can extend in one direction. The voltage line 195 can extend in the second direction (Y-axis direction) and cross the boundary of the pixel PX or the sub-pixel PXn to extend to an adjacent pixel PX or sub-pixel PXn. The voltage line 195 can be disposed on one side of a pixel PX or a sub-pixel PXn, for example, disposed adjacent to the right side of a pixel PX or a sub-pixel PXn.

[0150] The second protective film 170 is disposed on the voltage line 195 and the first protective film 150. The second protective film 170 may be arranged to cover other components (not shown in the figure) including the voltage line 195. The second protective film 170 may perform substantially the same functions as the first protective film 150.

[0151] The via hole layer 200 may be formed on the second protective film 170. The via hole layer 200 may be arranged to cover the entire circuit element layer 10a and may perform the function of supporting components of the display element layer 10b, which will be described below. In addition, the via hole layer 200 may perform the function of flattening the steps caused by the first transistor 120, the second transistor 140, and the voltage line 195 of the circuit element layer 10a. The via hole layer 200 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0152] Meanwhile, as described below, the first drain electrode 124 of the first transistor 120 may be electrically connected to the first electrode line 210 of the display element layer 10b, which will be described below, through the electrode contact hole CNTD passing through the via hole layer 200, the second protective film 170, and the first protective film 150. The first transistor 120 may be connected to the voltage line 195 and the second drain electrode 144 of the second transistor 140 and may transmit an electrical signal to the first electrode line 210 of the display element layer 10b.

[0153] In Figures 6 to 8 only some components of the circuit element layer 10a are shown, and the present embodiment is not limited thereto. The circuit element layer 10a may include a greater number of components not shown in the figure.

[0154] Next, the display element layer 10b will be described with reference to Figure 5 and Figure 9 the display element layer 10b will be described.

[0155] A plurality of dams are provided on the via hole layer 200. The plurality of dams may be arranged to be separated from each other in each sub-pixel PXn. The plurality of dams may include a first dam 410 and a second dam 420 disposed adjacent to the central portion of the sub-pixel PXn and a third dam disposed at the boundary between the sub-pixels PXn.

[0156] When ink is ejected using an inkjet printing device during the manufacture of the display panel 10, the third dam may perform the function of preventing the ink from crossing the boundary of the sub-pixel PXn. In addition, when the display panel 10 further includes other components, the other components may be provided on the third dam, and the third dam may perform the function of supporting the other components. However, the present invention is not limited thereto.

[0157] The first bank 410 and the second bank 420 are arranged to be separated from each other and opposite. The first electrode line 210 can be arranged on the first bank 410, and the second electrode line 220 can be arranged on the second bank 420. Refer to Figure 5 and Figure 9 , it can be understood that the first electrode branch portion 210B is arranged on the first bank 410, and the second electrode branch portion 220B is arranged on the second bank 420.

[0158] As described above, the first bank 410, the second bank 420 and the third bank can be formed substantially in the same process. Therefore, the banks can form a single grid pattern. Each of the plurality of banks may include polyimide (PI).

[0159] Each of the plurality of banks may have a structure in which at least a part thereof protrudes from the via hole layer 200. The banks can protrude upward from the flat surface on which the light-emitting element 300 is arranged, and at least a part of each protruding portion may have a slope. The shape of each of the banks having the protruding structure is not particularly limited. As shown in the figure, the first bank 410 and the second bank 420 protrude to the same height, and the third bank may have a shape that protrudes to a higher position.

[0160] The reflective layers 211 and 221 can be respectively arranged on the first bank 410 and the second bank 420, and the electrode layers 212 and 222 can be respectively arranged on the reflective layers 211 and 221. The first reflective layer 211 and the first electrode layer 212 can constitute the first electrode line 210, and the second reflective layer 221 and the second electrode layer 222 can constitute the second electrode line 220.

[0161] The reflective layers 211 and 221 include the first reflective layer 211 and the second reflective layer 221. The first reflective layer 211 can cover the first bank 410, and the second reflective layer 221 can cover the second bank 420. Parts of the reflective layers 211 and 221 are electrically connected to the circuit element layer 10a through contact holes passing through the via hole layer 200.

[0162] Each of the reflective layers 211 and 221 may include a material with a high reflectivity to reflect the light emitted from the light-emitting element 300. For example, each of the reflective layers 211 and 221 includes a material such as Ag, Cu, ITO, IZO or ITZO, but the present invention is not limited thereto.

[0163] The electrode layers 212 and 222 respectively include the first electrode branch portion 210B and the second electrode branch portion 220B. The electrode layers 212 and 222 may have a pattern substantially equivalent to that of the reflective layers 211 and 221. The first reflective layer 211 and the first electrode branch portion 210B are arranged to be spaced apart from the second reflective layer 221 and the second electrode branch portion 220B.

[0164] Each of the electrode layers 212 and 222 includes a transparent conductive material, and thus the light emitted from the light-emitting element 300 can be incident on the reflective layers 211 and 221. For example, each of the electrode layers 212 and 222 may include a material such as ITO, IZO, or ITZO, but the present invention is not limited thereto.

[0165] In some embodiments, the reflective layers 211 and 221 and the electrode layers 212 and 222 may form a structure in which one or more transparent conductive layers including ITO, IZO, or ITZO and one or more metal layers including Ag or Cu are stacked. For example, the reflective layers 211 and 221 and the electrode layers 212 and 222 may form a stacked structure of ITO / Ag / ITO / IZO.

[0166] Meanwhile, in some embodiments, the first electrode line 210 and the second electrode line 220 may be formed as a single layer. That is, the reflective layers 211 and 221 and the electrode layers 212 and 222 may be formed as a single layer to transmit an electrical signal to the light-emitting element 300 and reflect light at the same time. For example, each of the first electrode line 210 and the second electrode line 220 may include an alloy containing Al, Ni, and lanthanum (La) as a conductive material having a high reflectivity. However, the present invention is not limited thereto.

[0167] The first insulating layer 510 is provided to partially cover the first electrode line 210 and the second electrode line 220. The first insulating layer 510 may be provided to cover most of the upper surfaces of the first electrode line 210 and the second electrode line 220, and may expose portions of the first electrode line 210 and the second electrode line 220. The first insulating layer 510 may be provided to partially cover the region where the first electrode line 210 and the second electrode line 220 are spaced apart and the region opposite to the region where the first electrode line 210 and the second electrode line 220 are spaced apart.

[0168] The first insulating layer 510 is provided to expose the relatively flat upper surfaces of the first electrode line 210 and the second electrode line 220, and is provided to allow the electrode lines 210 and 220 to overlap with the inclined surfaces of the first bank 410 and the second bank 420. The first insulating layer 510 forms a flat upper surface on which the light-emitting element 300 can be provided, and the flat upper surface extends in one direction toward the first electrode line 210 and the second electrode line 220. The extending portion of the first insulating layer 510 terminates at the inclined surfaces of the first electrode line 210 and the second electrode line 220. Therefore, the contact electrode 260 can contact the exposed first electrode line 210 and the exposed second electrode line 220, and can smoothly contact the light-emitting element 300 on the flat upper surface of the first insulating layer 510.

[0169] The first insulating layer 510 can protect the first electrode line 210 and the second electrode line 220, and at the same time insulate the first electrode line 210 from the second electrode line 220. In addition, the first insulating layer 510 can prevent the light-emitting element 300 disposed thereon from being damaged due to direct contact with other components.

[0170] The light-emitting element 300 can be disposed on the first insulating layer 510. At least one light-emitting element 300 can be disposed on the first insulating layer 510 between the first electrode line 210 and the second electrode line 220. The light-emitting element 300 can include a plurality of layers disposed in a direction horizontal to the via hole layer 200.

[0171] The light-emitting element 300 of the display panel 10 according to one embodiment can include the conductive semiconductor and the active layer as described above, and the conductive semiconductor and the active layer can be sequentially disposed on the via hole layer 200 in the horizontal direction. As Figure 13 shown in the light-emitting element 300, the first conductive type semiconductor 310, the active material layer 330, the second conductive type semiconductor 320, and the conductive electrode layer 370 can be sequentially disposed on the via hole layer 200 in the horizontal direction. However, the present invention is not limited thereto. The order of the plurality of layers disposed in the light-emitting element 300 can be reversed. In some cases, when the light-emitting element 300 has another structure, the plurality of layers can be disposed in a direction perpendicular to the via hole layer 200.

[0172] The second insulating layer 520 can be partially disposed on the light-emitting element 300. The second insulating layer 520 can protect the light-emitting element 300, and at the same time perform a function of fixing the light-emitting element 300 during the process of manufacturing the display panel 10. The second insulating layer 520 can be disposed to surround the outer surface of the light-emitting element 300. That is, a part of the material of the second insulating layer 520 can be disposed between the bottom surface of the light-emitting element 300 and the first insulating layer 510. The second insulating layer 520 can extend between the first electrode branch portion 210B and the second electrode branch portion 220B in the second direction to have an island shape or a linear shape when observed in a plan view.

[0173] The contact electrodes 260 are disposed on the electrode lines 210 and 220 and the second insulating layer 520. The first contact electrode 261 and the second contact electrode 262 are disposed to be spaced apart from each other on the second insulating layer 520. Therefore, the second insulating layer 520 can insulate the first contact electrode 261 from the second contact electrode 262.

[0174] The first contact electrode 261 may be in contact with at least the first electrode line 210 exposed due to the patterning of the first insulating layer 510 and at least one end portion of the light-emitting element 300. The second contact electrode 262 may be in contact with at least the second electrode line 220 exposed due to the patterning of the first insulating layer 510 and at least the other end portion of the light-emitting element 300. The first contact electrode 261 and the second contact electrode 262 may be in contact with the side surfaces of two end portions of the light-emitting element 300, for example, in contact with the side surfaces of the first-conductive-type semiconductor 310, the second-conductive-type semiconductor 320, or the conductive electrode layer 370. As described above, the first insulating layer 510 forms a flat upper surface so that the contact electrode 260 can be in smooth contact with the side surface of the light-emitting element 300.

[0175] The contact electrode 260 may include a conductive material. For example, the contact electrode 260 may include ITO, IZO, ITZO, Al, etc. However, the present invention is not limited thereto.

[0176] The passivation layer 550 may be formed on the second insulating layer 520 and the second contact electrode 262, and may perform a function of protecting the components of the display element layer 10b from the external environment.

[0177] Each of the first insulating layer 510, the second insulating layer 520, and the passivation layer 550 as described above may include an inorganic insulating material or an organic insulating material. In an example, each of the first insulating layer 510 and the passivation layer 550 may include materials such as SiO x 、SiN x 、SiO x N y 、Al 2 O 3 、aluminum nitride (AlN), etc. The second insulating layer 520 may be made of an organic insulating material including a photoresist, etc. However, the present invention is not limited thereto.

[0178] Hereinafter, the circuit element layer 10a of the display panel 10 according to another embodiment will be described.

[0179] Figures 5 to 9 The display panel 10 including the first transistor 120 and the second transistor 140 of the circuit element layer 10a as described above is shown, in which each of the first transistor 120 and the second transistor 140 has a structure in which active layers 126 and 146 each having a channel region are formed above the gate electrodes 121 and 141. However, the present invention is not limited thereto, and for example, the first transistor 120 and the second transistor 140 may have active layers 126 and 146 formed below the gate electrodes 121 and 141 or may have other structures further including other conductive layers.

[0180] Figure 10is a cross-sectional view showing a circuit element layer according to another embodiment.

[0181] Referring Figure 10 , in the first transistor 120 and the second transistor 140, the gate electrodes 121 and 141 are formed on the active layers 126 and 146 including the channel regions. That is, each of the first transistor 120 and the second transistor 140 may have a top-gate structure.

[0182] The first active layer 126 and the second active layer 146 are disposed on the buffer layer 110. The first active layer 126 and the second active layer 146 may include first conductivity regions 126a and 146a, second conductivity regions 126b and 146b, and channel regions 126c and 146c. The channel regions 126c and 146c may be disposed between the first conductivity regions 126a and 146a and the second conductivity regions 126b and 146b. As described above, each of the first active layer 126 and the second active layer 146 may be an oxide semiconductor.

[0183] The first gate insulating film 130 is disposed on the first active layer 126 and the second active layer 146. The first gate electrode 121 and the second gate electrode 141 are disposed on the first gate insulating film 130. The first active layer 126 may overlap with the first gate electrode 121, and the first gate insulating film 130 is interposed between the first active layer 126 and the first gate electrode 121, and the first channel region 126c is formed in the overlapping region. The second active layer 146 may overlap with the second gate electrode 141, and the first gate insulating film 130 is interposed between the second active layer 146 and the second gate electrode 141, and the second channel region 146c is formed in the overlapping region.

[0184] Meanwhile, in the drawings, although the first gate insulating film 130 is only disposed between the first gate electrode 121 and the second gate electrode 141 and the first active layer 126 and the second active layer 146, the present invention is not limited thereto. That is, as Figure 6 shown, the first gate insulating film 130 may be disposed on the entire buffer layer 110 including the first gate electrode 121 and the second gate electrode 141 thereon.

[0185] The interlayer insulating film 132 is disposed on the first gate electrode 121 and the second gate electrode 141, and is configured to cover the entire first active layer 126, the second active layer 146, and the buffer layer 110. A first contact hole CNT1 and a second contact hole CNT2 are formed in the interlayer insulating film 132 to penetrate the interlayer insulating film 132 to expose a part of the upper surface of the first active layer 126 and another part of the upper surface of the first active layer 126, respectively. A third contact hole CNT3 and a fourth contact hole CNT4 are formed in the interlayer insulating film 132 to penetrate the interlayer insulating film 132 to expose a part of the upper surface of the second active layer 146 and another part of the upper surface of the second active layer 146, respectively. The first contact hole CNT1 may expose the first conductivity region 126a of the first active layer 126, the second contact hole CNT2 may expose the second conductivity region 126b of the first active layer 126, the third contact hole CNT3 may expose the first conductivity region 146a of the second active layer 146, and the fourth contact hole CNT4 may expose the second conductivity region 146b of the second active layer 146.

[0186] The first source electrode 123, the first drain electrode 124, the second source electrode 143, and the second drain electrode 144 may be disposed on the interlayer insulating film 132. The first source electrode 123 is in contact with the first conductivity region 126a formed on one side of the first active layer 126 through the first contact hole CNT1. The first drain electrode 124 is in contact with the second conductivity region 126b formed on the other side of the first active layer 126 through the second contact hole CNT2. The second source electrode 143 is in contact with the first conductivity region 146a formed on one side of the second active layer 146 through the third contact hole CNT3. The second drain electrode 144 is in contact with the second conductivity region 146b formed on the other side of the second active layer 146 through the fourth contact hole CNT4.

[0187] According to one embodiment, in the first transistor 120 and the second transistor 140, the gate electrodes 121 and 141 may be formed on the active layers 126 and 146, and the active layers 126 and 146 may include an oxide semiconductor, and thus the channel regions 126c and 146c may be formed. The description of other components is the same as above, and thus the detailed description thereof will be omitted here.

[0188] Figure 11 is a cross-sectional view showing a circuit element layer according to still another embodiment.

[0189] Reference Figure 11 , according to one embodiment, the circuit element layer 10a may further include a light blocking layer 180 disposed between the substrate 100 and the buffer layer 110. In Figure 11 , only the first transistor 120 is shown as one transistor, but this may be equally applied to the second transistor 140.

[0190] At least one light-blocking layer 180 may be disposed on the substrate 100. The light-blocking layer 180 may be disposed between the substrate 100 and the buffer layer 110, and may perform a function of blocking light incident from the substrate 100 onto the first active layer 126. The light-blocking layer 180 is disposed to overlap with the first active layer 126 disposed on the buffer layer 110. For example, the area where the light-blocking layer 180 is disposed to cover the first active layer 126 may be larger than the area of the first active layer 126. The light-blocking layer 180 may include a material that absorbs incident light or blocks the transmission of incident light. For example, the light-blocking layer 180 may be formed of a single layer or multiple layers, where the single layer or multiple layers are made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

[0191] Meanwhile, the first transistor 120 and the second transistor 140 may be formed to have different structures and be disposed on different layers.

[0192] Figure 12 is a cross-sectional view showing a circuit element layer according to still another embodiment.

[0193] Reference Figure 12 , in the circuit element layer 10a according to one embodiment, a plurality of interlayer insulating films 132a and 132b are disposed on the first gate electrode 121 of the first transistor 120, and the second gate electrode 141 of the second transistor 140 is disposed between the interlayer insulating films 132a and 132b. The interlayer insulating films 132a and 132b may include a first interlayer insulating film 132a and a second interlayer insulating film 132b, and the first interlayer insulating film 132a and the second interlayer insulating film 132b may be sequentially disposed on the first gate electrode 121. The second gate electrode 141 is disposed on the first interlayer insulating film 132a, and the second active layer 146 is disposed on the second interlayer insulating film 132b.

[0194] In Figure 12 , the first transistor 120 may have a structure in which the first gate electrode 121 is formed on the first active layer 126 and may have a shape substantially the same as that of the first transistor 120 in Figure 10 . Except that the first contact hole CNT1 and the second contact hole CNT2 respectively exposing the first conductive region 126a and the second conductive region 126b pass through the first interlayer insulating film 132a and the second interlayer insulating film 132b, Figure 12 the first transistor 120 in Figure 10 is the same as the first transistor 120 in

[0195] Meanwhile, in this case, in addition to the oxide semiconductor, the first active layer 126 of the first transistor 120 may further include other semiconductor materials. For example, the first active layer 126 may include polysilicon. The polysilicon may be formed by crystallizing amorphous silicon. Examples of the crystallization method may include a rapid thermal annealing (RTA) method, a solid phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method, etc., but the present invention is not limited thereto. Optionally, the first active layer 126 may include single crystal silicon, low temperature polysilicon, amorphous silicon, etc. However, the present invention is not limited thereto.

[0196] Hereinafter, the detailed description of the first transistor 120 will be omitted, and the second transistor 140 will be described.

[0197] The second transistor 140 may include a second gate electrode 141 disposed on the first interlayer insulating film 132a, a second active layer 146 disposed on the second interlayer insulating film 132b, and a second source electrode 143 and a second drain electrode 144. A data line 191 to which a data signal DATA is applied and a conductive pattern 193 connecting the data line 191 to the second source electrode 143 may also be disposed on the second interlayer insulating film 132b.

[0198] The first active layer 126, the second active layer 146, the first gate electrode 121, and the second gate electrode 141 may be disposed on different layers. The first active layer 126 and the second active layer 146 each including a semiconductor may respectively constitute a lower semiconductor layer and an upper semiconductor layer in the circuit element layer 10a.

[0199] In addition, in this case, the first transistor 120 and the second transistor 140 may be formed of different types of transistors. In the above description, although the first transistor 120 and the second transistor 140 have been described as being formed as p-type MOSFETs, at least one of the first transistor 120 and the second transistor 140 may be formed as an n-type MOSFET. In addition, one of the first transistor 120 and the second transistor 140 may be formed as a p-type MOSFET, and the other thereof may be formed as an n-type MOSFET. The detailed description of other components will be omitted here.

[0200] Meanwhile, the light emitting element 300 may include a semiconductor crystal to emit light in a specific wavelength range. The light emitting element 300 may emit light upward toward the display element layer 10b.

[0201] Figure 13 It is a schematic diagram showing a light emitting element according to an embodiment.

[0202] The light-emitting element 300 may be a light-emitting diode (LED). Specifically, the light-emitting element 300 may be an inorganic LED having a size in the micron or nanometer unit and made of an inorganic material. The inorganic light-emitting diode may be aligned between two electrodes, and in the two electrodes, a polarity is formed by forming an electric field in a specific direction between the two electrodes facing each other. Since an electric field is formed between the two electrodes, the light-emitting element 300 may be aligned between the two electrodes.

[0203] The light-emitting element 300 may include a semiconductor crystal doped with impurities of any conductive type (e.g., p-type or n-type). The semiconductor crystal may receive an electrical signal applied from an external power source and emit light in a specific wavelength range.

[0204] Reference Figure 13 , according to an embodiment, the light-emitting element 300 may include a first-conductive-type semiconductor 310, a second-conductive-type semiconductor 320, an active material layer 330, and an insulating film 380. In addition, according to an embodiment, the light-emitting element 300 may further include at least one conductive electrode layer 370. Although the light-emitting element 300 is shown in Figure 13 as further including one conductive electrode layer 370, the present invention is not limited thereto. In some cases, the light-emitting element 300 may include a larger number of conductive electrode layers 370, or the conductive electrode layer 370 may be omitted. Even when the number of conductive electrode layers 370 is changed or another structure is further included, the description of the light-emitting element 300 to be made below may be equally applied.

[0205] The light-emitting element 300 may have a shape extending in one direction. The light-emitting element 300 may have a shape such as a nanorod, a nanowire, a nanotube, etc. In an embodiment, the light-emitting element 300 may have a cylindrical shape or a rod shape. However, the shape of the light-emitting element 300 is not limited thereto, and may have various shapes such as a regular hexahedron shape, a rectangular parallelepiped shape, a hexagonal column shape, etc. The plurality of semiconductors included in the light-emitting element 300 to be described below may have a structure in which the semiconductors are sequentially arranged or stacked in one direction.

[0206] According to an embodiment, the light-emitting element 300 may emit light in a specific wavelength range. In an example, the active material layer 330 may emit blue light having a center wavelength range from 450 nm to 495 nm. However, the center wavelength range of the blue light is not limited to the above range, and it should be understood that the center wavelength range includes all wavelength ranges that can be recognized as blue color in the art. In addition, the light emitted from the active material layer 330 of the light-emitting element 300 is not limited thereto, and the light may be green light having a center wavelength range from 495 nm to 570 nm or red light having a center wavelength range from 620 nm to 750 nm.

[0207] For reference Figure 13 To describe the light-emitting element 300 in detail, the first-conductivity-type semiconductor 310 may be an n-type semiconductor having, for example, the first conductivity type. For example, when the light-emitting element 300 emits light in the blue wavelength range, the first-conductivity-type semiconductor 310 may include a semiconductor material having the chemical formula In x Al y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ x + y ≤ 1). For example, the semiconductor material may be one or more of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type impurity. The first-conductivity-type semiconductor 310' may be doped with a first conductive dopant. For example, the first conductive dopant may be Si, Ge, Sn, etc. In an example, the first-conductivity-type semiconductor 310 may be n-GaN doped with n-type Si. The length of the first-conductivity-type semiconductor 310 may be in the range of 1.5 μm to 5 μm, but the present invention is not limited thereto.

[0208] The second-conductivity-type semiconductor 320 is disposed on the active material layer 330 to be described below. For example, the second-conductivity-type semiconductor 320 may be a p-type semiconductor having the second conductivity type. For example, when the light-emitting element 300 emits light in the blue wavelength range or the green wavelength range, the second-conductivity-type semiconductor 320 may include a semiconductor material having the chemical formula In x Al y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ x + y ≤ 1). For example, the semiconductor material may be one or more of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type impurity. The second-conductivity-type semiconductor 320 may be doped with a second conductive dopant. For example, the second conductive dopant may be Mg, Zn, Ca, Se, Ba, etc. In an example, the second-conductivity-type semiconductor 320 may be p-GaN doped with p-type Mg. The length of the second-conductivity-type semiconductor 320 may be in the range of 0.08 μm to 0.25 μm, but the present invention is not limited thereto.

[0209] Meanwhile, in the drawings, although each of the first-conductivity-type semiconductor 310 and the second-conductivity-type semiconductor 320 is shown as being formed as a single layer, the present invention is not limited thereto. In some cases, each of the first-conductivity-type semiconductor 310 and the second-conductivity-type semiconductor 320 may further include a greater number of layers, such as a cladding layer or a tensile strain barrier reduction (TSBR) layer depending on the material of the active material layer 330.

[0210] The active material layer 330 is disposed between the first conductivity type semiconductor 310 and the second conductivity type semiconductor 320. The active material layer 330 may include a material having a single quantum well structure or a multi - quantum well structure. When the active material layer 330 includes a material having a multi - quantum well structure, the active material layer 330 may have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The active material layer 330 may emit light due to the recombination of electron - hole pairs in response to an electrical signal applied through the first conductivity type semiconductor 310 and the second conductivity type semiconductor 320. For example, when the active material layer 330 emits light in the blue wavelength range, the active material layer 330 may include materials such as AlGaN, AlInGaN, etc. In particular, when the active material layer 330 has a multi - quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layers may include materials such as AlGaN or AlInGaN, and the well layers may include materials such as GaN or AlInN. In an example, the active material layer 330 includes AlGaInN as the quantum layer and AlInN as the well layer. As described above, the active material layer 330 may emit blue light with a central wavelength range from 450 nm to 495 nm.

[0211] However, the present invention is not limited thereto, and the active material layer 330 may have a structure in which semiconductor materials with a large bandgap energy and semiconductor materials with a small bandgap energy are alternately stacked according to the wavelength range of the emitted light or include different group - III to group - V semiconductor materials. The active material layer 330 is not limited to emitting light in the blue wavelength range, and in some cases, the active material layer 330 may emit light in the red wavelength range or the green wavelength range. The length of the active material layer 330 may be in the range of 0.05 μm to 0.25 μm, but the present invention is not limited thereto.

[0212] Meanwhile, the light emitted from the active material layer 330 may be emitted to the outer surface of the light - emitting element 300 and the side surface of the light - emitting element 300 in the length direction of the light - emitting element 300. The directivity of the light emitted from the active material layer 330 is not limited to one direction.

[0213] The conductive electrode layer 370 may be an ohmic contact electrode. However, the present invention is not limited thereto, and the conductive electrode layer 370 may be a Schottky contact electrode. The conductive electrode layer 370 may include a conductive metal. For example, the conductive electrode layer 370 may include at least one of Al, Ti, In, Au, Ag, ITO, IZO, and ITZO. In addition, the conductive electrode layer 370 may include a semiconductor material doped with n - type or p - type impurities. The conductive electrode layer 370 may include the same material or different materials, but the present invention is not limited thereto.

[0214] The insulating film 380 is disposed to surround the outer surfaces of the plurality of semiconductors described above. In an example, the insulating film 380 may be disposed to surround at least the outer surface of the active material layer 330 and may extend in one direction in which the light-emitting element 300 extends. The insulating film 380 may perform the function of a protective member. As an example, the insulating film 380 may be formed to surround the side surfaces of the member and expose both ends of the light-emitting element 300 in the longitudinal direction.

[0215] In the drawings, the insulating film 380 is shown as being formed to extend in the longitudinal direction of the light-emitting element 300 to cover from the first conductive type semiconductor 310 to the conductive electrode layer 370, but the present invention is not limited thereto. The insulating film 380 only covers the outer surfaces of some semiconductor layers including the active material layer 330, or only covers a part of the outer surface of the conductive electrode layer 370, so that a part of the outer surface of the conductive electrode layer 370 may be exposed.

[0216] The thickness of the insulating film 380 may be in the range of 10 nm to 1.0 μm, but the present invention is not limited thereto. Preferably, the thickness of the insulating film 380 may be 40 nm.

[0217] The insulating film 380 may include a material having insulating properties, such as SiO x , SiN x , SiO x N y , AlN, Al 2 O 3 and the like. Accordingly, an electrical short circuit that may occur when the active material layer 330 is in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element 300 can be prevented. In addition, since the insulating film 380 protects the outer surface of the light-emitting element 300 including the active material layer 330, a reduction in light-emitting efficiency can be prevented.

[0218] In addition, in some embodiments, the outer surface of the insulating film 380 may be surface-treated. When manufacturing the display panel 10, the light-emitting element 300 may be ejected onto the electrode in a state of being dispersed in a predetermined ink. Here, in order to keep the light-emitting element 300 dispersed in the ink without coalescing with another adjacent light-emitting element 300, the insulating film 380 may be subjected to a hydrophobic or hydrophilic surface treatment.

[0219] Meanwhile, the light-emitting element 300 may have a length h, where the range of the length h is from 1 μm to 10 μm or from 2 μm to 5 μm, and preferably it is about 4 μm. In addition, the diameter of the light-emitting element 300 may be in the range of 300 nm to 700 nm, and the aspect ratio of the light-emitting element 300 may be in the range of 1.2 to 100. However, the present invention is not limited thereto, and the plurality of light-emitting elements 300 included in the display panel 10 may have different diameters according to the difference in the composition of the active material layer 330. Preferably, the diameter of the light-emitting element 300 may be about 500 nm.

[0220] Meanwhile, the display panel 10 may further include a light-emitting element 300 having a structure different from that of Figure 13 the light-emitting element 300.

[0221] Figure 14 is a schematic diagram showing a light-emitting element according to another embodiment.

[0222] Referring to Figure 14 , the light-emitting element 300' may be formed such that a plurality of layers are not stacked in one direction, and each of the plurality of layers surrounds the outer surface of another layer. Except that the shapes of the layers are partially different from each other, Figure 14 the light-emitting element 300' of Figure 13 is the same as the light-emitting element 300 of

[0223] According to one embodiment, the first-conductive-type semiconductor 310' may extend in one direction, and both ends of the first-conductive-type semiconductor 310' may be formed to be inclined toward its central portion. Figure 14 The first-conductive-type semiconductor 310' of

[0224] may have a shape in which a rod-shaped or cylindrical main body and tapered ends on the upper and lower portions of the main body are formed. The upper end portion of the main body may have a steeper slope than the slope of its lower end portion. The active material layer 330' is disposed to surround the outer surface of the main body of the first-conductive-type semiconductor 310'. The active material layer 330' may have an annular shape extending in one direction. The active material layer 330' may not be formed on the upper end portion and the lower end portion of the first-conductive-type semiconductor 310'. That is, the active material layer 330' may only be in contact with the side surface of the first-conductive-type semiconductor 310' parallel thereto.

[0225] A second-conductivity-type semiconductor 320' is disposed to surround an outer surface of the active material layer 330' and an upper end portion of the first-conductivity-type semiconductor 310'. The second-conductivity-type semiconductor 320' may include an annular main body extending in one direction and an upper end portion having a side surface formed to be inclined. That is, the second-conductivity-type semiconductor 320' may be in direct contact with a side surface of the active material layer 330' parallel thereto and an inclined upper end portion of the first-conductivity-type semiconductor 310. However, the second-conductivity-type semiconductor 320' is not formed in a lower end portion of the first-conductivity-type semiconductor 310'.

[0226] An electrode material layer 370' is disposed to surround an outer surface of the second-conductivity-type semiconductor 320'. That is, a shape of the electrode material layer 370' may be substantially the same as a shape of the second-conductivity-type semiconductor 320'. That is, the electrode material layer 370' may be in complete contact with the outer surface of the second-conductivity-type semiconductor 320'.

[0227] An insulating film 380' may be disposed to surround the outer surfaces of the electrode material layer 370' and the first-conductivity-type semiconductor 310'. In addition to the electrode material layer 370', the insulating film 380' may also be in direct contact with a lower end portion of the first-conductivity-type semiconductor 310' and exposed lower end portions of the active material layer 330' and the second-conductivity-type semiconductor 320'.

[0228] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: a base layer; a first transistor disposed on the base layer; a second transistor disposed on the base layer and configured to transmit a data signal to the first transistor, a via layer disposed on the first transistor and the second transistor; a first bank and a second bank disposed on the via layer and spaced apart from each other; a first electrode disposed on the first bank; a second electrode disposed on the second bank and spaced apart from the first electrode; a first insulating layer disposed on at least a part of the first electrode and at least a part of the second electrode; a light-emitting element disposed on the first insulating layer and disposed between the first bank and the second bank, wherein the first transistor is configured to transmit a driving current to the light-emitting element; a second insulating layer partially disposed on the light-emitting element; a first contact electrode disposed on the first electrode and the second insulating layer and in contact with one end of the light-emitting element; and a second contact electrode disposed on the second electrode and the second insulating layer and in contact with the other end of the light-emitting element, wherein, the first transistor includes a first active layer, the second transistor includes a second active layer containing an oxide semiconductor, and the light-emitting element includes: a first-conductive-type semiconductor having a first polarity; a second-conductive-type semiconductor having a second polarity different from the first polarity; and an active material layer disposed between the first-conductive-type semiconductor and the second-conductive-type semiconductor.

2. The display device according to claim 1, wherein, the first active layer of the first transistor includes an oxide semiconductor.

3. The display device according to claim 2, wherein, the oxide semiconductor includes indium gallium tin oxide or indium gallium zinc tin oxide.

4. The display device according to claim 3, wherein, the length of the light-emitting element is in the range of 4 μm to 7 μm, and the aspect ratio of the light-emitting element is in the range of 1.2 to 100.

5. The display device according to claim 2, wherein, the first transistor includes a first gate electrode disposed below the first active layer.

6. The display device according to claim 1, wherein, the first active layer includes a first conductive region, a second conductive region, and a channel region disposed between the first conductive region and the second conductive region.

7. The display device according to claim 6, wherein, the first transistor further includes: a third gate electrode disposed on the first active layer; a first source electrode connected to the first conductive region through a first contact hole passing through an interlayer insulating film disposed on the third gate electrode; and a first drain electrode connected to the second conductive region through a second contact hole passing through the interlayer insulating film.

8. The display device according to claim 7, wherein, the first active layer includes polysilicon.

9. The display device according to claim 8, wherein, the first transistor further includes a light-blocking layer disposed below the first active layer.

10. The display device according to claim 1, wherein, the second transistor includes: a second gate electrode disposed below the second active layer; a second source electrode connected to one side of the second active layer; and a second drain electrode connected to the other side of the second active layer.

11. The display device according to claim 10, further comprising a data line configured to transmit the data signal, wherein, the data line further includes a protrusion disposed to be spaced apart from the second source electrode of the second transistor and configured to be connected to the second source electrode through a conductive pattern.

12. A display device, comprising: a substrate; a first gate electrode disposed on the substrate; a first gate insulating film disposed on the first gate electrode; a first active layer disposed on the first gate insulating film, partially overlapping with the first gate electrode, and including an oxide semiconductor; a first interlayer insulating film disposed on the first active layer; a second gate electrode disposed on the first interlayer insulating film; a second interlayer insulating film disposed on the second gate electrode; a second active layer disposed on the second interlayer insulating film, partially overlapping with the second gate electrode, and including an oxide semiconductor; and a first conductive layer including a first signal line disposed on the second interlayer insulating film and a source electrode formed on one side of the second active layer; a via layer disposed on the conductive layer; a first bank and a second bank disposed on the via layer and spaced apart from each other; a first electrode disposed on the first bank; a second electrode disposed on the second bank and spaced apart from the first electrode; a first insulating layer disposed on at least a part of the first electrode and at least a part of the second electrode; a light-emitting element disposed on the first insulating layer and disposed between the first bank and the second bank, a second insulating layer partially disposed on the light-emitting element; a first contact electrode disposed on the first electrode and the second insulating layer and in contact with one end of the light-emitting element; and a second contact electrode disposed on the second electrode and the second insulating layer and in contact with the other end of the light-emitting element, wherein the first conductive layer further includes a conductive pattern partially overlapping with one side of the source electrode and the first signal line.

13. The display device according to claim 12, further comprising: a drain electrode disposed on the first gate insulating film and in contact with one side of the first active layer; wherein the drain electrode is electrically connected to one end of the at least one light-emitting element.

14. The display device according to claim 13, wherein, the light-emitting element includes: a first-conductive-type semiconductor having a first polarity; a second-conductive-type semiconductor having a second polarity different from the first polarity; and an active material layer disposed between the first-conductive-type semiconductor and the second-conductive-type semiconductor.

15. A display device, comprising: a base layer; a first bank and a second bank disposed on the base layer and spaced apart from each other in a first direction; A first electrode and a second electrode are respectively disposed on the first bank and the second bank, and are spaced apart from each other in the first direction; A first insulating layer is disposed on at least a part of the first electrode and at least a part of the second electrode; At least one light-emitting element is disposed on the first insulating layer and between the first electrode and the second electrode, is connected to at least one of the first electrode and the second electrode, and has a shape extending in the first direction; A second insulating layer is partially disposed on the light-emitting element; A first contact electrode is disposed on the first electrode and the second insulating layer, and is in contact with one end of the light-emitting element; A second contact electrode is disposed on the second electrode and the second insulating layer, and is in contact with the other end of the light-emitting element. A driving transistor is configured to transmit a driving current to the at least one light-emitting element, wherein the driving transistor includes an active layer having an oxide semiconductor, and the light-emitting element includes: A first-conductivity-type semiconductor having a first polarity; A second-conductivity-type semiconductor having a second polarity different from the first polarity; and An active material layer disposed between the first-conductivity-type semiconductor and the second-conductivity-type semiconductor.

16. The display device according to claim 15, wherein, The driving transistor has a gate electrode disposed below the active layer.

17. The display device according to claim 16, wherein, Each of the first electrode and the second electrode has a shape extending in a second direction different from the first direction on the base layer.

18. The display device according to claim 17, wherein, The at least one light-emitting element has a length extending in the first direction and within a range of 4 μm to 7 μm, and an aspect ratio of the at least one light-emitting element is within a range of 1.2 to 100.

19. The display device according to claim 18, wherein, The first-conductivity-type semiconductor, the active material layer, and the second-conductivity-type semiconductor are disposed in a direction parallel to the upper surface of the base layer.

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