Semiconductor device

Abstract

A semiconductor device includes a first substrate, a circuit device disposed on the first substrate, a first interconnection structure electrically connected to the circuit device, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and a channel structure penetrating the gate electrodes, extending perpendicular to the second substrate, and including a channel layer. The semiconductor device further includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via hole integral with the second substrate and extending from a lower surface of the second substrate toward the first substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0031455, filed on March 13, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0003] An exemplary embodiment of the present invention relates to a semiconductor device.

[0004] There is a demand for semiconductor devices with reduced size and the ability to process high-capacity data. Therefore, it may be necessary to increase the integration density of the semiconductor elements constituting such devices. Consequently, as a method to improve the integration density of semiconductor devices, semiconductor devices with vertical transistor structures instead of planar transistor structures have been proposed. Summary of the Invention

[0005] An exemplary embodiment of the present invention is to provide a semiconductor device with improved reliability.

[0006] According to an example embodiment, a semiconductor device includes: a peripheral circuit region including a first substrate, circuit devices disposed on the first substrate, and a first interconnect structure electrically connected to the circuit devices; a memory cell region including a second substrate disposed on an upper portion of the first substrate and having a first region and a second region, a gate electrode, an interlayer insulating layer alternately stacked with the gate electrode, a channel structure, and a second interconnect structure, the gate electrodes being spaced apart from each other and stacked in the first region in a first direction perpendicular to the upper surface of the second substrate, and the gate electrode extending in the second region while having a stepped form in a second direction perpendicular to the first direction, the channel structure penetrating the gate electrode, extending perpendicularly to the second substrate, and including a channel layer, the second interconnect structure being electrically connected to the gate electrode and the channel structure; and a third interconnect structure connecting the first substrate and the second substrate, the third interconnect structure including an upper via extending from the second substrate and including a material of the same material as the second substrate, and a lower interconnect structure connected to the lower portion of the upper via and having a structure corresponding to the first interconnect structure.

[0007] According to an example embodiment, a semiconductor device includes: a first substrate; a circuit device disposed on the first substrate; a first interconnect structure electrically connected to the circuit device; a second substrate disposed on an upper portion of the first interconnect structure; gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to the upper surface of the second substrate; a channel structure penetrating the gate electrodes, extending perpendicularly to the second substrate and including a channel layer; and a ground interconnect structure connecting the first substrate and the second substrate, and including an upper via integral with the second substrate and extending from the lower surface of the second substrate toward the first substrate.

[0008] According to an example embodiment, a semiconductor device includes: a first region including a first substrate, circuit devices disposed on the first substrate, and a first interconnect structure electrically connected to the circuit devices; a second region including a second substrate disposed on an upper portion of the first substrate and comprising a semiconductor material, a gate electrode spaced apart from each other and stacked on the second substrate in a direction perpendicular to the upper surface of the second substrate, a channel structure, and a second interconnect structure electrically connected to the gate electrode and the channel structure, the channel structure penetrating the gate electrode, extending perpendicularly to the second substrate, and including a channel layer; and a third interconnect structure connecting the first substrate and the second substrate, the third interconnect structure including an upper via integral with the second substrate, and a metal structure connected to the upper via. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following specific embodiments, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1A and Figure 1B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0011] Figure 2A and Figure 2B This is an enlarged view of a portion of a semiconductor device according to an example embodiment;

[0012] Figures 3A to 3C This is an enlarged view showing a portion of a semiconductor device according to an example embodiment;

[0013] Figures 4 to 6 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0014] Figure 7A and Figure 7B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 8 A schematic cross-sectional view of a semiconductor device according to an example embodiment; and

[0016] Figures 9A to 9H This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0017] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1A and Figure 1B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment.

[0019] Figure 2A and Figure 2B This is an enlarged view of a portion of a semiconductor device according to an example embodiment. Figure 2A and 2B They are shown respectively Figure 1A The regions “D” and “E” are shown in the image.

[0020] refer to Figures 1A to 2B The semiconductor device 100 may include: a peripheral circuit region PERI including a first substrate 201; a memory cell region CELL including a second substrate 101; a through interconnect region TR including a first via 165 electrically connecting the peripheral circuit region PERI to the memory cell region CELL; and a ground interconnect structure GI connecting the first substrate 201 and the second substrate 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. Alternatively, in an example embodiment, the memory cell region CELL may also be disposed below the peripheral circuit region PERI. The through interconnect region TR may be configured to extend from the memory cell region CELL to the peripheral circuit region PERI. The ground interconnect structure GI may be configured to extend from the lower region of the memory cell region CELL to the peripheral circuit region PERI.

[0021] The peripheral circuit region PERI may include a first substrate 201, a source / drain region 205, a device isolation layer 210 disposed in the first substrate 201, a circuit device 220 disposed on the first substrate 201, a peripheral region insulating layer 290, a lower protective layer 295, and a first interconnect structure L1.

[0022] The first substrate 201 may have an upper surface extending in both the X and Y directions. An active region may be defined by a device isolation layer 210 on the first substrate 201. Source / electrode regions 205, including impurities, may be disposed within a portion of the active region. The first substrate 201 may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 201 may also be provided as a bulk wafer or an epitaxial layer.

[0023] Circuit device 220 may include planar transistors. Each circuit device 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed in a first substrate 201 on both sides of the circuit gate electrode 225.

[0024] The peripheral region insulating layer 290 can be disposed on the circuit device 220 on the first substrate 201. The peripheral region insulating layer 290 may include a first peripheral region insulating layer 292 and a second peripheral region insulating layer 294, and each of the first peripheral region insulating layer 292 and the second peripheral region insulating layer 294 may further include multiple insulating layers. The peripheral region insulating layer 290 may be formed of an insulating material.

[0025] A lower protective layer 295 may be disposed on the upper surface of the third lower interconnect 286 between the first peripheral region insulating layer 292 and the second peripheral region insulating layer 294. In an example embodiment, the lower protective layer 295 may also be disposed on the upper surfaces of the first lower interconnect 282 and the second lower interconnect 284. The lower protective layer 295 may be a layer for preventing contamination caused by the metallic material of the lower interconnect 280 disposed on the lower portion of the lower protective layer 295. The lower protective layer 295 may be formed of a material different from that of the peripheral region insulating layer 290. For example, the lower protective layer 295 may include, for example, silicon nitride.

[0026] The first interconnect structure LI can be an interconnect structure electrically connected to the circuit device 220 and the source / drain region 205. The first interconnect structure LI can include lower contact plugs 270, each having a cylindrical shape, and lower interconnect lines 280, each having a linear shape. The lower contact plugs 270 can include first to third lower contact plugs 272, 274, and 276. The first lower contact plug 272 can be disposed on the circuit device 220 and the source / drain region 205, the second lower contact plug 274 can be disposed on the first lower interconnect line 282, and the third lower insulating plug 276 can be disposed on the second lower interconnect line 284. The lower interconnect lines 280 can include first to third lower interconnect lines 282, 284, and 286. The first lower interconnect line 282 can be disposed on the first lower contact plug 272, the second lower interconnect line 284 can be disposed on the second lower contact plug 274, and the third lower interconnect line 286 can be disposed on the third lower contact plug 276. The first interconnect structure LI can include a conductive material. For example, the first interconnect structure LI may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each element may also include a diffusion barrier. However, in the example embodiment, the number of layers and arrangement of the lower contact plug 270 and the lower interconnect line 280 constituting the first interconnect structure LI may be varied.

[0027] The memory cell region (CELL) may include: a second substrate 101 having a first region A and a second region B; a first horizontal conductive layer 102 and a second horizontal conductive layer 104 on the second substrate 101; a gate electrode 130 stacked on the second substrate 101; a first separation region MS1 ​​and a second separation region MS2 extending through the stacked structure of the gate electrode 130; an upper separation region SS penetrating a portion of the stacked structure; a channel structure CH configured to penetrate the stacked structure; and a second interconnect structure UI electrically connected to the gate electrode 130 and the channel structure CH. The memory cell region (CELL) may also include: a substrate insulating layer 105; an interlayer insulating layer 120 alternately stacked with the gate electrode 130 on the second substrate 101; a gate contact 162 connected to the gate electrode 130; a substrate contact 164 connected to the second substrate 101; a cell region insulating layer 190 covering the gate electrode 130; and an upper protective layer 195. The memory cell region CELL may also have a third region C on the outside of the second substrate 101, and a through interconnect structure such as a second channel via 167 for connecting the memory cell region CELL to the peripheral circuit region PERI may be provided in the third region C.

[0028] A first region A of the first substrate 201 may be a region in which gate electrodes 130 can be vertically stacked and a channel structure CH can be formed, and memory cells may also be disposed in the first region A. A second region B may be a region in which gate electrodes 130 can extend to different lengths, and may be a region for electrically connecting memory cells to a peripheral circuit region PERI. The second region B may be disposed on at least one end of the first region A in at least one direction (e.g., in the X direction).

[0029] The second substrate 101 may have an upper surface extending in both the X and Y directions. The second substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate 101 may also include impurities. The second substrate 101 may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer. The second substrate 101 may also be provided as a bulk semiconductor substrate. The second substrate 101 may have a substantially flat upper surface and a lower surface that may not be flat due to the protrusion of the upper via (GV).

[0030] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be stacked and disposed on the upper surface of the second substrate 101. At least a portion of the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may serve as part of a common source line of the semiconductor device 100. For example, at least a portion of the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may, for example, serve as a common source line together with the second substrate 101. Figure 1B As shown in the enlarged view, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 around the channel layer 140. For example, the first horizontal conductive layer 102 and the second horizontal conductive layer 104 can comprise a semiconductor material, such as polysilicon. In this case, at least the first horizontal conductive layer 102 can be a doped layer, and the second horizontal conductive layer 104 can be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102. According to an example embodiment, the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may not extend across the entire span of the second region B of the second substrate 101. For example, an insulating layer can be disposed in a portion of the second region B instead of the first horizontal conductive layer 102 and the second horizontal conductive layer 104.

[0031] The substrate insulating layer 105 may be disposed in the region formed by partially removing the second substrate 101 and the first horizontal conductive layer 102 and the second horizontal conductive layer 104, and may be configured to be surrounded by the second substrate 101 and the first horizontal conductive layer 102 and the second horizontal conductive layer 104. The lower surface of the substrate insulating layer 105 may be coplanar with the lower surface of the second substrate 101, or may be disposed at a level lower than the lower surface of the second substrate 101. In some example embodiments, the substrate insulating layer 105 may be disposed in the region formed by removing only the second substrate 101. In this case, the substrate insulating layer 105 may have an upper surface substantially coplanar with the upper surface of the second substrate 101, and another insulating layer surrounded by the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may also be disposed on the upper portion. The substrate insulating layer 105 may be formed of an insulating material. For example, the substrate insulating layer 105 may include silicon oxide, silicon oxynitride, or silicon nitride.

[0032] Gate electrodes 130 may be vertically spaced apart and stacked on the second substrate 101, and may form a stacked structure. Gate electrodes 130 may include electrodes that sequentially form the gates of a ground select transistor, a memory cell (e.g., a memory cell transistor), and a string select transistor. The number of gate electrodes 130 forming the memory cell may be determined depending on the capacity of the semiconductor device 100. The number of gate electrodes 130 forming the string select transistor (i.e., the number of string select lines) and the number of gate electrodes forming the ground select transistor (i.e., the number of ground select lines) may be one or more (e.g., two), and such gate electrodes 130 may have the same or different structure as the gate electrodes 130 of the memory cell. Furthermore, gate electrodes 130 may also include gate electrodes 130 disposed above the gate electrodes 130 forming the string select transistor and / or below the gate electrodes 130 forming the ground select transistor, and may utilize gate-induced drain leakage (GIDL) phenomenon to form an erase transistor for erase operations. In addition, some gate electrodes 130 that are adjacent to the gate electrode 130 constituting the string select transistor (e.g., near the string select line) or adjacent to the ground select transistor (e.g., near the ground select line) may be, for example, dummy gate electrodes.

[0033] The gate electrodes 130 can be vertically spaced apart and stacked on the first region A, extending to different lengths from the first region A to the second region B, and can form a stepped structure in a stepped shape. For example... Figure 1A As shown, the gate electrode 130 can form a stepped structure between the gate electrodes 130 in the X direction. In some example embodiments, a number of gate electrodes 130 (e.g., two to six gate electrodes 130) can form a single gate group, and a stepped structure can be formed between the gate groups in the X direction. In this case, the gate electrodes 130 forming the single gate group can be configured to also have a stepped structure in the Y direction. With the stepped structure, the gate electrodes 130 can be formed in a stepped form, wherein the gate electrodes 130 disposed at the lower part extend longer than the gate electrodes 130 disposed at the upper part (i.e., in the Z direction), and can be provided from the end exposed from the interlayer insulating layer 120 to the upper part. In some example embodiments, the gate electrodes 130 can have increased thickness at the ends (i.e., in the X and / or Y directions).

[0034] The gate electrode 130 may include a metallic material, such as tungsten (W). In an example embodiment, the gate electrode 130 may include polycrystalline silicon or a metal silicide material. In an example embodiment, the gate electrode 130 may also include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0035] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate 101, and may extend in the X direction similar to the gate electrodes 130. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0036] The first separation region MS1 ​​and the second separation region MS2 can be configured to penetrate the gate electrode 130 and can extend in the X direction within the first region A and the second region B. The first separation region MS1 ​​and the second separation region MS2 can be configured to be parallel to each other. Figure 1B As shown, the first separation region MS1 ​​and the second separation region MS2 can penetrate the entire gate electrode 130 stacked on the second substrate 101 and can be connected to the second substrate 101. The first separation region MS1 ​​can extend as a single layer along the first region A and the second region B, and the second separation region MS2 can extend only to a portion of the second region B, or can be intermittently disposed in the first region A and the second region B. However, in the example embodiment, the arrangement order, arrangement interval, etc. of the first separation region MS1 ​​and the second separation region MS2 can be changed.

[0037] A separation insulating layer 110 may be disposed in the first separation region MS1 ​​and the second separation region MS2. In an example embodiment, the separation insulating layer 110 may have a shape in which the width toward the second substrate 101 can be reduced due to a high aspect ratio. However, in an example embodiment, a conductive layer may also be disposed within the separation insulating layer 110 in the first separation region MS1 ​​and the second separation region MS2. In this case, the conductive layer may act as a common source line or a contact plug connected to a common source line.

[0038] The upper separation region SS can extend in the x and Z directions between the first separation region MS1 ​​and the second separation region MS2. The upper separation region SS can be located in a portion of the second region B and the first region A, penetrating a portion of the gate electrode 130, including the uppermost gate electrode 130. For example, as... Figure 1B As shown, the upper separation region SS can separate a total of three gate electrodes 130 in the Y direction. However, in the example embodiment, the number of gate electrodes 130 separated by the upper separation region SS can be varied. The upper separation region SS may include an upper separation insulating layer 107.

[0039] Each channel structure CH can form a single memory cell string and can be spaced apart from each other while forming rows and columns on the first region A. The channel structure CH can be configured to form a lattice pattern, or it can be configured in a z-shaped pattern in one direction on the xy plane. The channel structure CH can have a cylindrical shape and can have sloping sides, the width of which decreases towards the second substrate 101 depending on the aspect ratio. In an example embodiment, a dummy channel that does not constitute a memory cell string can be provided at the end of the first region A adjacent to the second region B, and can also be provided at the end of the second region B.

[0040] like Figure 1B As shown in the enlarged view, a channel layer 140 can be disposed in a channel structure CH. The channel layer 140 in the channel structure CH can have an annular shape surrounding a channel insulating layer 150 disposed therein, but in an example embodiment, the channel layer 140 can have a cylindrical or prismatic shape without an internal channel insulating layer 150. The channel layer 140 can be connected to a first horizontal conductive layer 102 in its lower portion. The channel layer 140 can include a semiconductor material, such as polysilicon or monocrystalline silicon. The channel structure CH extends in the Z direction and is linearly disposed in the Y direction between the first separation region MS1 ​​and the second separation region MS2. The upper separation regions SS can be electrically separated from each other by a second interconnect structure UI connected to the channel pad 155.

[0041] In the channel structure CH, channel pads 155 may be disposed on the upper part of the channel layer 140. Channel pads 155 may be configured to cover the upper surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. Channel pads 155 may comprise, for example, doped polysilicon.

[0042] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. The gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially stacked from the channel layer 140. The tunneling layer can tunnel charge to the charge storage layer and may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In an example embodiment, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0043] The unit region insulating layer 190 may cover the second substrate 101, the gate electrode 130 on the second substrate 101, and the peripheral region insulating layer 290. The unit region insulating layer 190 may include a first unit region insulating layer 192 and a second unit region insulating layer 194, and each of the first unit region insulating layer 192 and the second unit region insulating layer 194 may further include multiple insulating layers. The unit region insulating layer 190 may be formed of an insulating material.

[0044] An upper protective layer 195 may be disposed on the upper surface of the first upper interconnect 182 between the first cell region insulating layer 192 and the second cell region insulating layer 194. In an example embodiment, the upper protective layer 195 may also be disposed on the upper surface of the second upper interconnect 184. The upper protective layer 195 may be a layer for preventing contamination caused by the metallic material of the upper interconnect 180 disposed on the lower portion. The upper protective layer 195 may be formed of an insulating material different from the insulating material of the cell region insulating layer 190, and may include, for example, silicon nitride.

[0045] Gate contacts 162 may be connected to gate electrodes 130 in the second region B. For example, each of the plurality of gate contacts 162 may be configured to penetrate at least a portion of the first cell region insulating layer 192 and be connected to one of the gate electrodes 130 exposed above. Substrate contacts 164 may be connected to the second substrate 101 at an end of the second region B. Substrate contacts 164 may penetrate at least a portion of the first cell region insulating layer 192 and may be connected to the second substrate 101. Substrate contacts 164 may, for example, apply an electrical signal to a common source line including the second substrate 101.

[0046] The second interconnect structure UI can be an interconnect structure electrically connected to the gate electrode 130 and the channel structure CH. The second interconnect structure UI can include upper contact plugs 170, each having a cylindrical shape, and upper interconnect lines 180, each having a linear shape. The upper contact plugs 170 can include first to third upper contact plugs 172, 174, and 176. The first upper contact plug 172 can be disposed on the channel pad 155, the gate contact 162, and the substrate contact 164. The second upper contact plug 174 can be disposed on the first upper contact plug 172, and the third upper contact plug 176 can be disposed on the first upper interconnect line 182. The upper interconnect line 180 can include the first upper interconnect line 182 and the second upper interconnect line 184. The first upper interconnect line 182 can be disposed on the second upper contact plug 174, and the second upper interconnect line 182 can be disposed on the third upper contact plug 176. The second interconnect structure UI can include a conductive material. For example, the second interconnect structure UI may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each may also include a diffusion barrier layer. In the example embodiment, the number of layers and arrangement of the lower contact plug 170 and the lower interconnect 180 constituting the second interconnect structure UI may be varied.

[0047] A through-interconnect region TR can be a region comprising a through-interconnect structure for electrically connecting a memory cell region (CELL) and a peripheral circuit region (PERI). The through-interconnect region TR may include: a first via 165 penetrating the second substrate 101 from the top of the memory cell region CELL and extending in the Z direction; and an insulating region surrounding the first via 165. The insulating region may include a sacrificial insulating layer 118, an interlayer insulating layer 120 disposed parallel to the sacrificial insulating layer 118, and a substrate insulating layer 105. The size, arrangement, and shape of the through-interconnect region TR can vary (e.g., depending on the design). Figure 1A In this embodiment, the through interconnect region TR can be disposed in the second region B, but the invention is not limited thereto; the through interconnect region TR can also be disposed in the first region A. The through interconnect region TR can be spaced apart from the first separation region MS1 ​​and the second separation region MS2. For example, the through interconnect region TR can be disposed in the central portion of the first region A between a pair of first separation regions MS1 that are adjacent to each other in the Y direction. Therefore, the sacrificial insulating layer 118 can be retained in the through interconnect region TR.

[0048] The first channel hole 165 can partially penetrate the first unit region insulating layer 192, the insulating region, the lower protective layer 295, and the second peripheral region insulating layer 294 from the top, and can extend perpendicular to the upper surface of the second substrate 101. The upper end of the first channel hole 165 can be connected to the second interconnect structure UI, and the lower end can be connected to the first interconnect structure LI. In the example embodiment, the number, arrangement, and shape of the first channel holes 165 can be varied in the through interconnect region TR. The first channel hole 165 can include a conductive material. For example, the first channel hole 165 can include a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0049] The sacrificial insulating layer 118 may be disposed at the same level as the gate electrode 130 and may have the same thickness as the gate electrode 130, and its side surfaces may contact the gate electrode 130 at the boundary of the through interconnect region TR. The sacrificial insulating layer 118 may be stacked alternately with the interlayer insulating layer 120 and may form an insulating region. The sacrificial insulating layer 118 may be disposed with a width that is the same as or different from the width of the substrate insulating layer 105. The sacrificial insulating layer 118 may be formed of an insulating material different from the insulating material of the interlayer insulating layer 120, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0050] The second via 167 can be disposed in the third region C (outer region of the second substrate 101) of the memory cell region CELL and can extend to the peripheral circuit region PERI. The second via 167 can connect the second interconnect structure UI and the first interconnect structure LI, similar to the first via 165 that passes through the interconnect region TR. However, the second via 167 can penetrate only a portion of the first cell region insulating layer 192 and the second peripheral region insulating layer 294 from the top. The second via 167 can include a conductive material. For example, the second via 167 can include a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0051] A ground interconnect structure GI can be disposed throughout the peripheral circuit region (PERI) and the memory cell region (CELL) to connect the first substrate 201 and the second substrate 101. The ground interconnect structure GI can perform the function of grounding the second substrate 101 during the fabrication of the semiconductor device 100. The ground interconnect structure GI can include a lower interconnect structure corresponding to the first interconnect structure LI by similarly including a lower contact plug 270 and a lower interconnect line 280. The ground interconnect structure GI may also include an upper via GV connected to a third lower interconnect line 286 of the lower interconnect line 280. The ground interconnect structure GI can be referred to as the third interconnect structure, distinguishing it from the first interconnect structure LI and the second interconnect structure UI.

[0052] Despite Figure 1A Only one ground interconnect structure GI is shown, but multiple ground interconnect structures GI can be disposed in the semiconductor device 100 and spaced apart from each other. The ground interconnect structure GI can be disposed on the lower part of the second region B of the second substrate 101. Furthermore, the ground interconnect structure GI can be disposed on the lower part of the first horizontal conductive layer 102 and the second horizontal conductive layer 104 in regions where the first horizontal conductive layer 102 and the second horizontal conductive layer 104 extend longer than the gate electrode 130, but the invention is not limited thereto. In an example embodiment, the ground interconnect structure GI can also be disposed on the lower part of the first region A of the second substrate 101. The ground interconnect structure GI can be spaced apart from the circuit devices 220 of the peripheral circuit region PERI.

[0053] The upper via (GV) can penetrate the second peripheral region insulating layer 294 and the lower protective layer 295, and can be directly connected to the third lower interconnect 286. The upper via (GV) can be integrated with the second substrate 101 of the memory cell region (CELL). Figure 2A As shown, the upper via GV can have the form of the second substrate 101 extending into the via hole towards the first substrate 201. The upper via GV can be formed together with the second substrate 101 and can comprise the same material as the second substrate 101, and there may be no interface surface between the upper via GV and the second substrate 101. Specifically, the upper via GV and the second substrate 101 are formed of the same material. The upper via GV can protrude from the lower surface of the second substrate 101 in a cylindrical or conical shape.

[0054] The via-hole (GV) may further include a barrier layer 103 extending from the lower surface of the second substrate 101. The barrier layer 103 may extend from the lower surface of the second substrate 101 along the inner sidewall of the via to cover the bottom surface of the via. The barrier layer 103 may include a metal nitride. For example, the barrier layer 103 may include titanium nitride (TiN), silicon titanium nitride (TiSiN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof. When the region of the via-hole GV extending from the second substrate 101 comprises a semiconductor material and the third lower interconnect 286 comprises a metallic material, defects may occur at the semiconductor-metal interface surface. However, in this case, since the barrier layer 103 is disposed between the semiconductor layers of the via-hole GV integral with the second substrate 101, and the third lower interconnect 286 is disposed on the lower portion, defects in the via-hole GV can be avoided.

[0055] The through-hole GV can have approximately [value missing] in the Z direction (first direction). To date The height H is within the range of the third lower interconnect 286. Since the upper via GV is formed to connect to the third lower interconnect 286, the upper via GV can have a relatively small height H compared to the thickness of the peripheral region insulating layer 290, thus facilitating the formation of the upper via GV. The diameter of the upper via GV at the top can be larger than the diameter at the bottom. For example, in the entire portion including the upper and lower portions, the upper via GV can have a diameter D1 in the range of about 200 nm to about 300 nm. The diameter D1 of the upper via GV can be larger than the average diameter D2 of the gate contact 162 and the average diameter D3 of the first channel hole 165 and the second channel hole 167, but the invention is not limited thereto. The upper via GV can be configured to recess the third lower interconnect 286 to a certain depth L. The depth L can be approximately... To date Within the range.

[0056] Terms such as “about” or “approximately” can reflect variations in quantity, size, orientation, or layout that are only minor relative and / or do not significantly alter the operation, function, or structure of certain elements. For example, a range of “about 0.1 to about 1” can include, for example, ranges with deviations of 0%–5% around 0.1 and 0%–5% around 1, especially if such deviations maintain the same effect as the listed ranges.

[0057] The lower interconnect structure forming part of the ground interconnect structure GI may include elements similar to the first interconnect structure LI and may be electrically decoupled from the first interconnect structure LI. The lower interconnect structure may include first to third lower contact plugs 272, 274 and 276 spaced apart from the first interconnect structure LI and first to third lower interconnect lines 282, 284 and 286.

[0058] like Figure 2B As shown, in the lower interconnect structure, the lowest first lower contact plug 272 can penetrate a portion of the first peripheral region insulating layer 292, the etch stop layer 291, and the circuit gate dielectric layer 222, and can be connected to the impurity region 207 disposed in the first substrate 201. The circuit gate dielectric layer 222 can be a layer extending from the circuit device 220, and the etch stop layer 291 can be formed on the circuit gate dielectric layer 222, and can perform an etch stop function when the first lower contact plug 272 is formed. The impurity region 207 can be a doped layer formed in the region connected to the first lower contact plug 272 to electrically connect the first lower contact plug 272 to the first substrate 201. In the lower interconnect structure, the first lower contact plug 272 can be connected to the impurity region 207 disposed in the region surrounded by the device isolation layer 210.

[0059] Figures 3A to 3C This is an enlarged view showing a portion of a semiconductor device according to an example embodiment. Figures 3A to 3C It shows the relationship with Figure 1A The area shown corresponds to region "D".

[0060] refer to Figure 3A In semiconductor device 100a, the upper via GVa of the ground interconnect structure GI may include a barrier layer 103a, which covers the inner sidewall and bottom surface of the via. However, compared with... Figure 2A Unlike the example embodiment shown, the barrier layer 103a can be confined within the via and may not extend along the lower surface of the second substrate 101. In this case, the area of ​​the barrier layer 103a exposed through the upper surface of the via can be reduced during the fabrication of the semiconductor device 100a, thereby reducing the process variables caused by the barrier layer 103a.

[0061] The barrier layer 103a having this structure can be formed by a manufacturing method that includes depositing material for forming the barrier layer 103a, forming a sacrificial layer to fill the via holes, performing a planarization process, removing the sacrificial layer, and forming a second substrate 101.

[0062] refer to Figure 3B In semiconductor device 100b, the upper via GVb of the ground interconnect structure GI may include a barrier layer 103b disposed on the lower end of the via. The barrier layer 103b may be formed by a nitriding process. In this case, since the barrier layer 103b is formed while partially consuming the third lower interconnect 286 disposed on the lower part of the via, the barrier layer 103b may extend from the boundary of the via (marked by dashed lines at the lower end of the via) to the upper part of the via and also to the lower part of the via.

[0063] refer to Figure 3C In the semiconductor device 100c, the upper via GVc of the ground interconnect structure GI may include a second substrate 101 and a barrier layer 103, and may also include a metal semiconductor layer 106 disposed between the second substrate 101 and the barrier layer 103. The metal semiconductor layer 106 may be a layer including metal elements included in the barrier layer 103 and semiconductor elements included in the second substrate 101. For example, the metal semiconductor layer 106 may include titanium silicide (TiSi), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), or other metal silicides. When the second substrate 101 is formed according to the process for forming the second substrate 101, the metal semiconductor layer 106 may be formed on the interface surface with the barrier layer 103.

[0064] Figures 4 to 6 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figures 4 to 6It shows the relationship with Figure 1A The area shown corresponds to the area shown.

[0065] refer to Figure 4 In the semiconductor device 100d, the second substrate 101 and the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may have a recessed portion CR formed on the upper part of the ground interconnect structure GI. The recessed portion CR may be disposed on the upper part of the upper via GV, and the center of the recessed portion CR may be disposed in the Z direction on a linear line substantially the same as the center of the upper via GV (i.e., aligned). In an example embodiment, the recessed portion CR may be formed only on the second substrate 101.

[0066] refer to Figure 5 In semiconductor device 100e, the ground interconnect structure GI may include a plurality of upper vias GVe arranged side by side. For example, the ground interconnect structure GI may include two upper vias GVe and a plurality of lower interconnect structures connected to the upper vias GVe in the lower part of each upper via GVe. As shown, the plurality of lower interconnect structures may be separate from each other or may be connected to each other. The arrangement of the upper vias GVe and lower interconnect structures in the ground interconnect structure GI can also be applied to other example embodiments.

[0067] refer to Figure 6 In semiconductor device 100f, a memory cell region CELL may include a region from which a first horizontal conductive layer 102 is partially removed and where a second horizontal conductive layer 104 contacts a second substrate 101. The second horizontal conductive layer 104 may have a concave region SR formed by removing the first horizontal conductive layer 102 from this region. The concave region SR may be configured to overlap at least a portion of a ground interconnect structure GI and / or an upper via GV in the Z direction.

[0068] Figure 7A and Figure 7B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 7A and Figure 7B It shows the relationship with Figure 1A The area shown corresponds to the area shown.

[0069] refer to Figure 7A In the semiconductor device 100g, the ground interconnect structure GI may include an upper via GVg, and a first lower contact plug 272 and a second lower contact plug 274 as the lower interconnect structure, along with a first lower interconnect line 282 and a second lower interconnect line 284. In other words, the ground interconnect structure GI may only include a portion of the first to third lower interconnect plugs 272, 274, and 276 as the lower interconnect structure, and a portion of the first to third lower interconnect lines 282, 284, and 286. Therefore, the upper via GVg may be larger than... Figures 1A to 2BThe example embodiment shown in the diagram illustrates that the upper via GV extends relatively deeper and can be connected to the second lower interconnect 284. Similarly, in this case, the upper via GVg may include, for example... Figure 2A The barrier layer 103 is shown. Furthermore, the diameter of the upper through-hole GVg can be relatively larger than... Figures 1A to 2B The example embodiment shows the diameter of the upper through-hole GV, but the present invention is not limited thereto.

[0070] refer to Figure 7B In semiconductor device 100h, the ground interconnect structure GI may consist only of the upper via GVh. Therefore, the upper via GVh may not be connected to the lower interconnect structure and can extend from the second substrate 101 to the first substrate 201 disposed on the lower portion. Figure 2A Compared to the structure shown, the upper through-hole GVh in the example embodiment may not include the barrier layer 103. Furthermore, the diameter of the upper through-hole GVh can be greater than... Figures 1A to 2B The example embodiment shows the diameter of the upper through-hole GV, but the present invention is not limited thereto.

[0071] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 8 It shows the relationship with Figure 1B The area shown corresponds to the area shown.

[0072] refer to Figure 8 In the semiconductor device 100i, the stacked structure of the gate electrode 130 can be composed of a vertically stacked lower stacked structure and an upper stacked structure, and the channel structure CHi can include a vertically stacked first channel structure CH1 and a second channel structure CH2. When the number of stacked gate electrodes 130 is relatively large, the structure of the channel structure CHi can be introduced to stably form the channel structure CHi.

[0073] In the channel structure CHi, a first channel structure CH1 disposed on the lower portion can be connected to a second channel structure CH2 disposed on the upper portion, and the channel structure CHi can have a curved portion formed by the difference in width in the connection region. The channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 can be connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 155 can be disposed only on the upper end of the second channel structure CH2, which is disposed on the upper portion. In an example embodiment, each of the first channel structure CH1 and the second channel structure CH2 may further include a channel pad 155, and in this case, the channel pad 155 of the first channel structure CH1 can be connected to the channel layer 140 of the second channel structure 155. A relatively thick upper interlayer insulating layer 125 can be disposed on the uppermost portion of the lower stack structure. However, in an example embodiment, the form of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 can be varied.

[0074] Figures 9A to 9H This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Figures 9A to 9H It shows the relationship with Figure 1A The area shown corresponds to the area shown.

[0075] refer to Figure 9A The circuit device 220 and the first interconnect structure LI can be formed on the first substrate 201.

[0076] First, a device isolation layer 210 can be formed in a first substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on the first substrate 201. For example, the device isolation layer 210 can be formed using a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 can be formed of silicon oxide, and the circuit gate electrode 225 can be formed of either polysilicon or a metal silicide layer, but the invention is not limited thereto. Subsequently, an isolation layer 224 and source / drain regions 205 can be formed on the two sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In an exemplary embodiment, the spacer layer 224 may comprise multiple layers. Subsequently, the source / drain regions 205 can be formed by performing an ion implantation process.

[0077] The lower contact plug 270 of the first interconnect structure LI can be formed by partially forming a first peripheral region insulating layer 292; partially removing components by an etching process; and filling it with conductive material. The lower interconnect 280 can be formed, for example, by depositing and patterning conductive material. When forming the first interconnect structure LI, the lower interconnect structure constituting part of the ground interconnect structure GI can be formed together (see...). Figure 1A Therefore, the lower interconnect structure can have the same stacking structure as the first interconnect structure LI.

[0078] The first peripheral region insulating layer 292 may include multiple insulating layers. The first peripheral region insulating layer 292 may be partially formed at each process used to form the first interconnect structure LI. A lower protective layer 295 covering the upper surface of the third lower interconnect 286 may be formed on the first peripheral region insulating layer 292.

[0079] refer to Figure 9B The via hole VH can be formed by forming a second peripheral region insulating layer 294 on the lower protective layer 295 and partially removing the second peripheral region insulating layer 294.

[0080] By forming the second peripheral region insulating layer 294, the entire portion of the peripheral circuit region PERI can be formed.

[0081] The via VH can be a top via GV used to form the ground interconnect structure GI (see...). Figure 1A The via hole (VH) can be formed by removing the second peripheral region insulating layer 294 and the lower protective layer 295 using a mask layer to expose the third lower interconnect 286 of the lower interconnect structure constituting the ground interconnect structure GI. In an example embodiment, the lower protective layer 295 may also act as an etch stop layer when forming the via hole (VH). The via hole (VH) can be formed to partially recess the third lower interconnect 286, but the invention is not limited thereto. For example, the via hole (VH) can be formed to expose the upper surface of the third lower interconnect 286.

[0082] refer to Figure 9C The second substrate 101 of the memory cell region CELL and the upper via GV of the ground interconnect structure GI can be formed on the upper part of the peripheral circuit region PERI.

[0083] Before forming the second substrate 101, an insulating layer can be formed on the second peripheral region 294. Figure 2AThe barrier layer 103 is shown. The second substrate 101 can be formed, for example, of polysilicon and can be formed by a CVD process. When forming the second substrate 101, the material forming the second substrate 101 can fill the vias VH, so that the upper vias GV can be formed. The polysilicon forming the second substrate 101 can, for example, include impurities such as n-type impurities. The second substrate 101 can be formed on the entire portion of the second peripheral region insulating layer 294, can be patterned, and can be removed from a portion of the memory cell region CELL including the third region C. The barrier layer 103 disposed on the lower part of the second substrate 101 can also be removed from the region where the second substrate 101 is removed.

[0084] In the example embodiment, prior to forming each of the barrier layer 103 and the second substrate 101, a process for removing the native oxide film by performing a cleaning process may also be performed. Therefore, the native oxide film may be minimally retained on the upper and lower portions of the barrier layer 103, or may be retained as approximately Or even a thinner thickness. However, in some example embodiments, when the cleaning process is omitted, a natural oxide film may be present on the lower and / or upper surface of the barrier layer 103.

[0085] Furthermore, in the example embodiment, a planarization process may be performed after the second substrate 101 is formed. In this case, the second substrate 101 may have a substantially flat upper surface. Figure 4 In the example embodiment shown, this planarization process can be omitted.

[0086] refer to Figure 9D A first source sacrificial layer 111 and a second source sacrificial layer 112 and a second horizontal conductive layer 104 can be formed, a substrate insulating layer 105 can be formed, and thereafter, sacrificial insulating layer 118 and interlayer insulating layer 120 can be stacked alternately.

[0087] The first source sacrificial layer 111 and the second source sacrificial layer 112 can be stacked on the second substrate 101, such that the first source sacrificial layer 111 can be disposed above and below the second source sacrificial layer 112. The first source sacrificial layer 111 and the second source sacrificial layer 112 can comprise different materials. The first source sacrificial layer 111 and the second source sacrificial layer 112 can be further processed using subsequent techniques. Figure 1A The first horizontal conductive layer 102 shown is used instead. For example, the first source sacrificial layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second source sacrificial layer 112 may be formed of the same material as the sacrificial insulating layer 118. The second horizontal conductive layer 104 may be formed on the first source sacrificial layer 111 and the second source sacrificial layer 112.

[0088] You can set a pass-through interconnect region TR in it (see Figure 1A In the region of the substrate, the first source sacrificial layer 111 and the second source sacrificial layer 112, the second horizontal conductive layer 104 and the second substrate 101 are partially removed to form a substrate insulating layer 105, and the portion is filled with an insulating material.

[0089] The sacrificial insulating layer 118 can be used in subsequent processes with the gate electrode 130 (see...). Figure 1A The sacrificial insulating layer 118 can be formed of a material different from that of the interlayer insulating layer 120, and can be formed of a material that can be selectively etched relative to the interlayer insulating layer 120 under certain etch conditions. For example, the interlayer insulating layer 120 can be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 can be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride, which is different from the material of the interlayer insulating layer 120. In example embodiments, the thickness of the interlayer insulating layer 120 can be different. The thicknesses of the interlayer insulating layer 120 and the sacrificial insulating layer 118, as well as the number of layers of the interlayer insulating layer 120 and the sacrificial insulating layer 118, can be varied.

[0090] In the second region B, photolithography and etching processes can be repeatedly performed on the sacrificial insulating layer 118 using a mask layer, so that the sacrificial insulating layer 118 disposed on the upper part can extend less than the sacrificial insulating layer 118 disposed on the lower part. Therefore, the sacrificial insulating layer 118 can form a stepped structure in a stepped shape in a certain number of units.

[0091] Subsequently, a first unit region insulation layer 192 can be formed to cover the stacked structure of the sacrificial insulation layer 118 and the interlayer insulation layer 120.

[0092] refer to Figure 9E This can form a channel structure CH that penetrates the stacked structure of the sacrificial insulation layer 118 and the interlayer insulation layer 120.

[0093] First, the upper separation region SS (see Figure 1B The upper separation region SS can be formed by partially removing the sacrificial insulation layer 118 and the interlayer insulation layer 120. The upper separation region SS can be formed by exposing the area where the upper separation region SS will be formed using a mask layer; removing a certain amount of the sacrificial insulation layer 118 and the interlayer insulation layer 120 from the top; and depositing insulating material.

[0094] The channel structure CH can be formed by anisotropically etching the sacrificial insulating layer 118 and the interlayer insulating layer 120, and can also be formed by forming and filling vias in the shape of holes. Due to the height of the stacked structure, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the second substrate 101. The channel structure CH can be formed such that the second substrate 101 is partially recessed. Subsequently, at least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pads 155 can be sequentially formed in the channel structure CH.

[0095] The gate dielectric layer 145 can be formed to have a uniform thickness using either an ALD or CVD process. The gate dielectric layer 145 can be formed wholly or partially in this process, and a portion extending perpendicularly to the second substrate 101 along the channel structure CH can be formed during this process. A channel layer 140 can be formed on the gate dielectric layer 145 within the channel structure CH. A channel insulating layer 150 can be formed to fill the channel structure CH and can be an insulating material. However, in an example embodiment, the spaces between the channel layers 140 can be filled with a conductive material instead of the channel insulating layer 150. The channel pads 155 can be formed of a conductive material. For example, the channel pads 155 can be formed of polysilicon.

[0096] refer to Figure 9F The tunnel section can be accessed through the first separation region MS1 ​​and the second separation region MS2 (see...). Figure 1B An opening is formed in the corresponding region to penetrate the stacked structure of the sacrificial insulation layer 118 and the interlayer insulation layer 120, and the sacrificial insulation layer 118 is partially removed through the opening.

[0097] First, a sacrificial spacer layer can be formed in the opening, the second source sacrificial layer 112 can be selectively removed, and subsequently, the first source sacrificial layer 111 can be removed. For example, the first source sacrificial layer 111 and the second source sacrificial layer 112 can be removed by a wet etching process. During the removal of the first source sacrificial layer 111, a portion of the gate dielectric layer 145 exposed from the region where the second source sacrificial layer 112 has been removed can be removed together. According to an example embodiment, a portion of the first source sacrificial layer 111 and the second source sacrificial layer 112 can be retained in the second region B. The first horizontal conductive layer 102 can be formed by depositing a conductive material in the region where the first source sacrificial layer 111 and the second source sacrificial layer 112 have been removed, and the sacrificial spacer layer can be removed from the opening.

[0098] Subsequently, the sacrificial insulation layer 118 can be connected from the through interconnect region TR (see...) Figure 1AThe outer side of the interlayer insulating layer 118 is removed. The sacrificial insulating layer 118 can remain in the through interconnect region TR and can form an insulating region of the through interconnect region TR together with the interlayer insulating layer 120. For example, a wet etching process can be used to selectively remove the sacrificial insulating layer 118 relative to the interlayer insulating layer 120. Therefore, multiple tunnel portions LT can be formed between the interlayer insulating layers 120.

[0099] The region forming the through interconnect region TR can be a region spaced apart from the opening, allowing the sacrificial insulating layer 118 to remain because the etchant does not reach it. Therefore, the through interconnect region TR can be formed in the central region between the first separation region MSI and the second separation region MS2, which are adjacent to each other.

[0100] refer to Figure 9G The gate electrode 130 can be formed by filling the tunnel portion LT from which the sacrificial insulating layer 118 is partially removed with a conductive material. The side surface of the gate electrode 130 can contact the side surface of the sacrificial insulating layer 118 of the through interconnect region TR. The conductive material can include metal, polysilicon, or metal silicide. After forming the gate electrode 130, the insulating layer 110 is separated (see...). Figure 1B It can be formed by removing the conductive material deposited in the opening through an additional process and filling the part with an insulating layer.

[0101] refer to Figure 9H It can form a gate contact 162, a substrate contact 164, and a first channel hole 165 and a second channel hole 167 that penetrate the insulating layer 192 of the first unit region.

[0102] Gate contact 162 can be formed to connect to gate electrode 130 in second region B, and substrate contact 164 can be formed to connect to second substrate 101 at the end of second region B. First via 165 can be formed to connect to first interconnect structure LI of peripheral circuit region PERI in through interconnect region TR, and second via 167 can be formed to connect to first interconnect structure LI of peripheral circuit region PERI in third region C.

[0103] The gate contact 162, substrate contact 164, first channel hole 165, and second channel hole 167 can be formed with different depths. However, the gate contact 162, substrate contact 164, first channel hole 165, and second channel hole 167 can be formed by simultaneously forming contact holes using an etch stop layer or the like, and filling the contact holes with a conductive material. However, in some example embodiments, a portion of the gate contact 162, substrate contact 164, first channel hole 165, and second channel hole 167 can also be formed using different processes.

[0104] After that, refer to again Figure 1AThis can form a second unit region insulating layer 194, an upper protective layer 195, and an upper interconnect structure UI.

[0105] The upper contact plug 170 of the upper interconnect structure UI can be formed by: partially forming the cell region insulating layer 290; partially removing the cell region insulating layer 290 by an etching process; and filling the portion with a conductive material. For example, the upper interconnect 180 can be formed by depositing and patterning a conductive material.

[0106] Therefore, it is possible to manufacture Figures 1A to 2B The semiconductor device 100 shown.

[0107] According to the foregoing example embodiments, since the ground interconnect structure includes an upper via extending from the second substrate, a semiconductor device with improved reliability can be provided.

[0108] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The peripheral circuit area includes: First substrate, Circuit devices, disposed on the first substrate, and A first interconnect structure is electrically connected to the circuit device; The memory cell region includes: A second substrate is disposed on the upper part of the first substrate and has a first region and a second region. Gate electrodes, spaced apart from each other and stacked in the first region in a first direction perpendicular to the upper surface of the second substrate, extend in the second region and have a stepped form in a second direction perpendicular to the first direction. Interlayer insulating layers are stacked alternately with the gate electrodes. A channel structure, penetrating the gate electrode, extending perpendicularly to the second substrate, and including a channel layer, and A second interconnect structure is electrically connected to the gate electrode and the channel structure; and A third interconnect structure connects the first substrate and the second substrate, the third interconnect structure comprising: A through-hole extends from the second substrate and comprises the same material as the second substrate, and The lower interconnect structure is connected to the lower part of the upper through hole and has a structure corresponding to the first interconnect structure.

2. The semiconductor device according to claim 1, wherein, The upper via comprises a semiconductor material, and the region of the lower interconnect structure in contact with the upper via comprises a metallic material.

3. The semiconductor device according to claim 1, in, The first interconnect structure and the lower interconnect structure each include a contact plug and an interconnect line disposed on the contact plug, and The upper through-hole is connected to the interconnect line included in the lower interconnect structure.

4. The semiconductor device according to claim 1, wherein, The upper through hole includes: A barrier layer covering the bottom surface of the passageway; and A semiconductor layer is disposed on the barrier layer, extends from the second substrate, and fills the via.

5. The semiconductor device according to claim 4, wherein, The barrier layer extends from the lower surface of the second substrate to the bottom surface of the via along the inner wall of the via.

6. The semiconductor device according to claim 4, wherein, The barrier layer covers the inner wall and bottom surface of the passage hole and is confined within the passage hole.

7. The semiconductor device according to claim 4, wherein, The barrier layer is formed of metal nitride.

8. The semiconductor device according to claim 1, wherein, The upper through-hole has a height ranging from 3000 Å to 5000 Å in the first direction.

9. The semiconductor device according to claim 1, wherein, The upper through-hole has a diameter ranging from 200 nm to 300 nm.

10. The semiconductor device according to claim 1, wherein, The second substrate has a recessed portion on the upper surface, the recessed portion being aligned with the upper through-hole in the first direction.

11. The semiconductor device according to claim 1, wherein, The third interconnect structure is disposed on the outer side of the end of the gate electrode.

12. The semiconductor device according to claim 1, further comprising: At least one horizontal conductive layer is disposed horizontally on the second substrate below the gate electrode and the interlayer insulating layer, and is in contact with the channel layer.

13. The semiconductor device according to claim 12, wherein, The third interconnect structure is disposed on the lower part of the horizontal conductive layer and is located in a region where the horizontal conductive layer extends further than the gate electrode in the second direction.

14. The semiconductor device according to claim 1, wherein, The upper via is one of a plurality of upper vias in the third interconnect structure, and the plurality of upper vias have the same structure and are arranged side by side with each other.

15. A semiconductor device, comprising: First substrate; Circuit devices are disposed on the first substrate; A first interconnect structure is electrically connected to the circuit device; The second substrate is disposed on the upper part of the first interconnect structure; Gate electrodes, spaced apart from each other, are stacked on the second substrate in a direction perpendicular to the upper surface of the second substrate; A channel structure, penetrating the gate electrode, extending perpendicularly to the second substrate, and including a channel layer; and A ground interconnect structure connecting the first substrate and the second substrate, and including an upper via integral with the second substrate and extending from the lower surface of the second substrate toward the first substrate.

16. The semiconductor device according to claim 15, wherein, The grounding interconnect structure further includes a lower interconnect structure, which is connected to the lower part of the upper through hole and has a structure corresponding to the first interconnect structure.

17. The semiconductor device according to claim 15, wherein, The grounding interconnect structure further includes a lower interconnect structure, which is connected to the lower part of the upper through-hole and has a structure corresponding to a portion of the first interconnect structure.

18. The semiconductor device of claim 15, further comprising: A protective layer is configured to be on the first interconnect structure and parallel to the upper surface of the first substrate. The upper through-hole penetrates the protective layer.

19. A semiconductor device, comprising: The first region includes: First substrate, Circuit devices, disposed on the first substrate, and A first interconnect structure is electrically connected to the circuit device; The second region includes: A second substrate is disposed on the upper part of the first substrate and includes a semiconductor material. Gate electrodes, spaced apart from each other, are stacked on the second substrate in a direction perpendicular to the upper surface of the second substrate. A channel structure, penetrating the gate electrode, extending perpendicularly to the second substrate, and including a channel layer, and A second interconnect structure is electrically connected to the gate electrode and the channel structure; and A third interconnect structure connects the first substrate and the second substrate, the third interconnect structure comprising: A through-hole, integral with the second substrate, and extending from the lower surface of the second substrate toward the first substrate; and A metal structure connected to the upper through hole.

20. The semiconductor device of claim 19, further comprising: A via hole penetrates the gate electrode and the substrate insulating layer disposed below the gate electrode, and connects the first interconnect structure and the second interconnect structure. The upper via includes a semiconductor layer, and the channel hole includes a metal layer.

Images