Display device

Abstract

A display device includes an electronic module; and an electronic panel including a first area overlapping the electronic module, a second area surrounding at least a portion of the first area in a plan view, and a mark disposed in the first area.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0031198, filed on March 13, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to display devices, and more specifically, to display devices that include electronic modules in a display area. Background Technology

[0004] Multimedia devices such as televisions, mobile phones, tablet computers, navigators, and game consoles include display devices that provide images to users.

[0005] In recent years, with the development of display device technology, various types of display devices have been developed. In addition, for user convenience and product aesthetics, display devices with a larger display area (or effective area) and a smaller non-display area (or bezel area) have been developed.

[0006] Display devices may include electronic modules such as cameras or sensors, which receive external signals or provide output signals to the outside. The electronic modules are housed together with the display panel of the display device in a housing or similar enclosure.

[0007] The information disclosed in this background section is only for understanding the background technology of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0008] The applicant recognizes that when electronic modules are placed in the display (non-bordered) area of ​​a display device with a bordered area, it is difficult to align the electronic panel and window module of the display device.

[0009] A display device constructed according to the principles and exemplary embodiments of the present invention provides, for example, effective and precise alignment between the electronic panel and the window module of the display device by providing alignment marks in the electronic panel. Therefore, the production efficiency of the display device can be improved.

[0010] Furthermore, the display device constructed according to the principles and exemplary embodiments of the present invention has a reduced bezel area, and can be easily manufactured even with a reduced bezel area.

[0011] Other features of the inventive concept will be set forth in the following description and will be apparent in part from the description or may be learned by practice of the inventive concept.

[0012] According to an aspect of the invention, the display device includes: an electronic module; and an electronic panel including a first region overlapping the electronic module, a second region surrounding at least a portion of the first region in a plan view, and a mark disposed in the first region.

[0013] The first region may include a panel module region, which includes a central region and a patterned region surrounding the central region. The second region may include an effective region, and the markings may include alignment marks set in the patterned region.

[0014] The electronic panel may also include: a base layer; a plurality of pixels disposed on the base layer in an effective area; and an encapsulation layer disposed on the base layer to cover the pixels, wherein alignment marks may be disposed on the encapsulation layer.

[0015] The electronic panel may further include: a substrate; a plurality of pixels disposed on the substrate in an effective area; an encapsulation layer disposed on the substrate to cover the pixels; and an input sensing layer disposed on the encapsulation layer, and including a plurality of sensing patterns and a plurality of sensing insulating layers disposed between the sensing patterns.

[0016] Alignment marks and one of multiple sensing patterns can be set on the same layer.

[0017] The plurality of sensing insulating layers may include a first sensing insulating layer and a second sensing insulating layer, and an alignment mark may be disposed between the first sensing insulating layer and the second sensing insulating layer.

[0018] The encapsulation layer may include: a first inorganic layer; a second inorganic layer disposed on the first inorganic layer; and an organic layer disposed between the first inorganic layer and the second inorganic layer, wherein the first inorganic layer may not overlap with the central region.

[0019] The second inorganic layer can overlap with the central region.

[0020] The transmittance of the second inorganic layer can be greater than that of the first inorganic layer.

[0021] The display device may also include a window disposed on the encapsulation layer, wherein the window may include: a window substrate, including a window module region overlapping the panel module region in a plan view; and a light blocking layer disposed on one surface of the window substrate in the window module region.

[0022] The window module area may include: a transmissive area that overlaps with the central area in the plan view; and a light-blocking pattern area surrounding the transmissive area, wherein the light-blocking layer may be disposed in the light-blocking pattern area.

[0023] The light-blocking pattern area can overlap with the pattern area in the planar diagram.

[0024] The electronic panel may also include: a base layer; an insulating layer disposed on the base layer; a plurality of pixels disposed on the base layer in an effective area; and an encapsulation layer disposed on the base layer to cover the pixels, wherein alignment marks may be disposed between the insulating layer and the encapsulation layer.

[0025] The markings can be conductive.

[0026] The markings can be optically opaque.

[0027] According to another aspect of the present invention, a display device includes: an electronic module; and an electronic panel, which is divided in a plan view into a first region overlapping the electronic module and a second region surrounding at least a portion of the first region, wherein the electronic panel includes: a plurality of pixels disposed in the second region; an encapsulation layer configured to cover the pixels; and a marker disposed on the encapsulation layer and overlapping the first region in a plan view.

[0028] The first region may include a panel module region having a central region and a patterned region surrounding the central region, the second region may include an effective region, and the markings may include alignment marks set in the patterned region.

[0029] The encapsulation layer may include: a first inorganic layer; a second inorganic layer disposed on the first inorganic layer; and an organic layer disposed between the first inorganic layer and the second inorganic layer, wherein the first inorganic layer may not overlap with the central region, and the second inorganic layer overlaps with the central region.

[0030] The display device may also include a window disposed on the encapsulation layer, wherein the window may include: a window substrate, including a window module region overlapping the panel module region in a plan view; and a light blocking layer disposed on a surface of the window substrate in the window module region.

[0031] The window module area may include: a transmissive area that overlaps with the central area in the plan view; and a light-blocking pattern area surrounding the transmissive area, wherein the light-blocking layer may be disposed in the light-blocking pattern area.

[0032] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0033] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0034] Figure 1 This is a perspective view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0035] Figure 2 This is a perspective view of another exemplary embodiment of a display device constructed according to the principles of the present invention.

[0036] Figure 3 This is a perspective view of another exemplary embodiment of a display device constructed according to the principles of the present invention.

[0037] Figure 4 yes Figure 1 An exploded perspective view of the display device.

[0038] Figure 5 yes Figure 1 A cross-sectional view of the electronic panel of the display device.

[0039] Figure 6 yes Figure 1 A plan view of the display panel of the display device.

[0040] Figure 7 yes Figure 1 A plan view of the input sensing layer of a display device.

[0041] Figure 8 It is along Figure 1 A sectional view taken by line I-I'.

[0042] Figure 9 It is shown Figure 1 A plan view of an exemplary embodiment of the window module area of ​​a display device.

[0043] Figure 10 It is shown Figure 1 A plan view of an exemplary embodiment of the panel module area of ​​the electronic panel of a display device.

[0044] Figure 11 It is along Figure 4 The section cut by line II-II' shows a cross-sectional view of an exemplary embodiment of the electronic panel.

[0045] Figure 12 It is along Figure 4 The section cut by line II-II' shows a cross-sectional view of another embodiment of the electronic panel.

[0046] Figure 13 This is an exploded perspective view of another exemplary embodiment of a display device constructed according to the principles of the present invention.

[0047] Figure 14 It is along Figure 13 The sectional view taken from line III-III'. Detailed Implementation

[0048] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or embodiments of the invention. As used herein, “implementation” and “example” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0049] Unless otherwise stated, the exemplary embodiments described are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, areas and / or aspects, etc. (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0050] The use of crosshairs and / or shading in the accompanying drawings is generally used to clearly define the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a particular process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description. Similarly, the same reference numerals denote the same elements.

[0051] When an element or layer is referred to as being on, connected to, or coupled to another element or layer, it can be directly on, directly connected to, or directly coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there is no intermediate element or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediate element. Furthermore, the DR1 axis, DR2 axis, and DR3 axis are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0052] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0053] For descriptive purposes, spatial relative terms such as "below," "below," "under," "lower," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship between one element(s) and another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as being below or beneath other elements or features would be oriented above those elements or features. Thus, the exemplary term "below" can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. Furthermore, the terms “comprise,” “comprising,” “includes,” and / or “including,” when used in this specification, designate the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “basically,” “about,” and other similar terms are used as approximations, not as terms of degree, and thus to allow for inherent deviations in measured, calculated, and / or provided values ​​that would be recognized by those skilled in the art.

[0055] This document describes various exemplary embodiments with reference to cross-sectional and / or exploded views, which are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, as a result of, for example, manufacturing techniques and / or tolerances, differences from the shapes illustrated should be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shapes of the specific areas shown, but should include deviations in shape caused, for example, by manufacturing processes. In this way, the areas shown in the figures may be substantially schematic, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0057] In the following description, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0058] Figure 1 This is a perspective view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0059] The display device DD1 can be implemented in various exemplary embodiments. For example, the display device DD1 can be included in or implemented as a tablet computer, laptop computer, computer, smart TV, etc. In this exemplary embodiment, a smartphone will be described as an example of the display device DD1.

[0060] Reference Figure 1 The display device DD1 can display an image IM on its front surface FS. The front surface FS can be defined as substantially parallel to the surface defined by the first direction DR1 and the second direction DR2. The front surface FS may include a display area DA and a border area BZA adjacent to the display area DA.

[0061] Display device DD1 displays image IM in display area DA. Figure 1 In the example, the image IM is displayed as a watch and multiple icons.

[0062] The display area DA can have a generally rectangular shape that is substantially parallel to the first direction DR1 and the second direction DR2. However, this is only an example. For example, the display area DA can have various shapes, and the exemplary implementation is not limited to a particular shape.

[0063] The border area BZA is adjacent to the display area DA. The border area BZA can surround the display area DA. However, this is just an example. For example, the border area BZA can be set to be adjacent only to one side of the display area DA, or it can be omitted.

[0064] The normal direction of the front surface FS can correspond to the thickness direction of the display device DD1 (hereinafter referred to as the third direction DR3). In this exemplary embodiment, the front surface (or top surface) or rear surface (or bottom surface) of each component can be defined based on the direction of the displayed image IM. The front surface and the rear surface can be opposite each other on the third direction DR3.

[0065] The directions indicated as the first direction DR1, the second direction DR2, and the third direction DR3 can be relative concepts and therefore can be changed to different directions.

[0066] Display device DD1 can sense user input TC applied from the outside. User input TC includes various types of external input, such as a part of the user's body, light, heat, pressure, etc. In addition, display device DD1 can sense not only inputs in contact with display device DD1, but also other inputs that are close to or adjacent to display device DD1.

[0067] In this exemplary embodiment, the user's input TC is shown as a user's hand applied to the front surface of the display device DD1. However, this is merely an example, and as mentioned above, the user's input TC can be provided in various forms. Furthermore, depending on the structure of the display device DD1, the display device DD1 can sense user input TC applied to the side or back of the display device DD1, but the exemplary embodiment is not limited to a specific structure.

[0068] Display device DD1 may include a window WM and a housing HU. The window WM and the housing HU may be connected to each other to define the appearance of display device DD1.

[0069] The window WM may comprise glass or plastic. The window WM may have a single-layer or multi-layer structure. For example, the window WM may have a laminated structure of multiple plastic films bonded together using an adhesive, or a laminated structure of a glass substrate and plastic films bonded together using an adhesive. The front surface FS of the display device DD1 may be substantially defined by the front surface FS of the window WM.

[0070] A module region MA can be defined within the display area DA of the display device DD1. The module region MA can be an area overlapping with the electronic module described below. The display device DD1 can receive external signals required by the electronic module, or provide signals output from the electronic module via the module region MA. In an exemplary embodiment, the module region MA can be disposed in the display area DA instead of the border area BZA, and thus the surface area of ​​the border area BZA can be reduced.

[0071] Figure 2 This is a perspective view of another exemplary embodiment of a display device constructed according to the principles of the present invention.

[0072] Figure 2 The display device DD2 includes a display area DA. The display area DA includes a first display area DA1, a second display area DA2, and a third display area DA3. The first display area DA1 displays an image IM through the front surface of the display device DD2, and each of the second display area DA2 and the third display area DA3 displays an image IM through the side surface of the display device DD2.

[0073] Each of the first display areas DA1 to the third display areas DA3 can be driven independently to display an independent image IM. Optionally, the first display areas DA1 to the third display areas DA3 can be driven as a single display area DA to display an image.

[0074] The front surface of the display device DD2 (e.g., the display surface on the third-party DR3) may include only the display area DA, but may not include the bezel area. Furthermore, a module area MA may be defined within the display area DA. The module area MA may be an area overlapping with the electronic modules described below.

[0075] Figure 3 This is a perspective view of another exemplary embodiment of a display device constructed according to the principles of the present invention.

[0076] like Figure 3 As shown, the display area DA can be defined on the display device DD3.

[0077] The display area DA includes a first display area DA1, a second display area DA2, a third display area DA3, a fourth display area DA4, and a fifth display area DA5. The first display area DA1 displays the image IM through the front surface of the display device DD3, and each of the second display areas DA2 to the fifth display area DA5 displays the image IM through the side surface of the display device DD3.

[0078] like Figure 3 As shown, the display device DD3 can be a four-sided curved display device, including a second display area DA2 to a fifth display area DA5 disposed on its curved side surfaces.

[0079] The display area DA of the display device DD3 is disposed not only on the front surface of the display device DD3 (e.g., the display surface on the third-party DR3) but also on the side surface of the display device DD3. The display device DD3 may not include bezel areas on either the front or side surfaces. Furthermore, a module area MA may be defined within the display area DA. The module area MA may be an area overlapping with an electronic module described later.

[0080] Figure 1 The display device DD1 shown includes the bezel area BZA, but Figure 2 and Figure 3 The display devices DD2 and DD3 shown do not include the bezel area BZA. All display devices DD1 to DD3 are included in the module area MA defined in the display area DA.

[0081] exist Figures 1 to 3 In this context, the module area MA can be set at a predetermined position within the display area DA. Figure 1 In the example shown, the module region MA is set at the upper right end of the display region DA. Figure 2 and Figure 3 In the example shown, the module region MA is located at the upper center of the display region DA. The module region MA can be located on at least one of the second display region DA2 and the third display region DA3 located on the side surface of the display device DD2. Furthermore, the module region MA can be located on at least one of the second to fifth display regions DA5 located on the side surface of the display device DD3.

[0082] Figure 4 yes Figure 1 An exploded perspective view of the display device.

[0083] Reference Figure 4The display device DD1 may include a window WM, an electronic panel EP, a circuit board DC, an electronic module EM, and a housing HU. The window WM and the housing HU may be connected to each other to define the appearance of the display device DD1.

[0084] A window WM is disposed on an electronic panel EP to cover the front surface IS of the electronic panel EP. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a single-layer structure or a multi-layer structure. For example, the window WM may have a laminated structure of multiple plastic films bonded together by using an adhesive, or a laminated structure of a glass substrate and plastic films bonded together by using an adhesive.

[0085] The window WM includes the front surface FS exposed to the outside. The front surface FS of the display device DD1 can be substantially defined by the front surface FS of the window WM.

[0086] The display area DA of the window WM can be an optically transparent area. The display area DA can have a shape corresponding to the effective area AA of the electronic panel EP. For example, the display area DA substantially overlaps the entire surface of the effective area AA or overlaps with at least a portion of the effective area AA. The image IM displayed in the effective area AA of the electronic panel EP can be seen from the outside through the display area DA.

[0087] The border area BZA can be a region with a relatively lower light transmittance than the display area DA. The border area BZA defines the shape of the display area DA. The border area BZA can be set adjacent to the display area DA to surround the display area DA.

[0088] The border area BZA can have a predetermined color. When the window WM is set to a glass or plastic substrate, the border area BZA can be a colored layer printed or deposited on a surface of the glass or plastic substrate. Alternatively, the border area BZA can be formed by coloring a corresponding area of ​​the glass or plastic substrate.

[0089] The border area BZA can cover the outer perimeter area NAA of the electronic panel EP to prevent the outer perimeter area NAA from being visible from the outside. This is just an example, and... Figure 2 and Figure 3 The window WM of each of the display devices DD2 and DD3 shown may not include the border area BZA.

[0090] The electronic panel EP can display images (IM) and detect user input (TC) (see [link]). Figure 1 The electronic panel EP includes a front surface IS, which includes an active area AA and a peripheral area NAA. The active area AA can be an area activated according to an electrical signal.

[0091] In this exemplary embodiment, the effective area AA can be the display image IM (see...). Figure 1 The area can also be used to detect user input (TC) (see Figure 1 The display area DA overlaps at least with the active area AA. For example, the display area DA substantially overlaps the entire surface of the active area AA or overlaps with at least a portion of the active area AA. Therefore, the user can see the image IM or provide user input TC through the display area DA. However, this is only an example. For example, the area of ​​the active area AA where the image IM is displayed and the area of ​​the active area AA where the user input TC is sensed can be independent of each other, and the exemplary implementation is not limited thereto.

[0092] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA. The peripheral region NAA can surround the active region AA. The drive circuitry or drive lines used to drive the active region AA can be set in the peripheral region NAA.

[0093] Used for applying to the effective area AA, pad ISL-PD, and DP-PD (see...) Figure 6 Various signal lines providing electrical signals, or electronic components, can be located in the peripheral area NAA. The peripheral area NAA can be covered by the border area BZA, and therefore cannot be seen from the outside.

[0094] In this exemplary embodiment, the electronic panel EP can be assembled with the effective area AA and the peripheral area NAA flat, facing the window WM. However, this is merely an example. For instance, a portion of the peripheral area NAA of the electronic panel EP can be bent. Here, a portion of the peripheral area NAA can face the rear surface of the display device DD1 to reduce the surface area of ​​the bezel area BZA on the front surface FS of the display device DD1. Optionally, the electronic panel EP can be assembled with a portion of the effective area AA bent. Optionally, the peripheral area NAA can be omitted in the electronic panel EP.

[0095] Electronic panels (EP) and windows (WM) can be bonded together using transparent adhesive components such as pressure-sensitive adhesive film (PSA), optically clear adhesive film (OCA), or optically clear resin (OCR).

[0096] Furthermore, an anti-reflective element can be disposed between the electronic panel EP and the window WM. The anti-reflective element reduces the reflectivity of external light incident from the upper side of the window WM. In an exemplary embodiment, the anti-reflective element may include a phase retarder and a polarizer.

[0097] The window module area MAa of window WM and the panel module area MAb of electronic panel EP are defined in the plan view at a location overlapping with electronic module EM, as will be described below. Furthermore, the window module area MAa of window WM and the panel module area MAb of electronic panel EP correspond to... Figure 1 The display device DD1 shown has a module area MA. Module areas MAa and MAb can be areas that overlap with the main body (such as the body or shell constituting the electronic module EM) other than the part of the electronic module EM that receives or outputs light.

[0098] Module regions MAa and MAb can be defined differently in shape. In the illustrated embodiment, for ease of explanation, each of module regions MAa and MAb is shown as having a circular shape, but the exemplary embodiment is not limited to this. For example, each of module regions MAa and MAb can have various shapes, such as elliptical shapes, polygonal shapes, and shapes with curved or straight edges, but the exemplary embodiment is not limited to a particular shape.

[0099] At least a portion of the panel module region MAb of the electronic panel EP can be surrounded by the effective region AA. In the illustrated embodiment, the panel module region MAb is spaced apart from the peripheral region NAA. The module region MA is shown as being defined within the effective region AA, such that all edges are surrounded by the effective region AA. In the combined state of the display device DD1 according to the illustrated embodiment, the window module region MAa of the window WM can overlap with the display region DA and is defined at a position spaced apart from the border region BZA.

[0100] The circuit board DC can be connected to the electronic panel EP. The circuit board DC may include a flexible board CF and a main board MB. The flexible board CF may include an insulating film and wires mounted on the insulating film. The wires are connected to pads PD to electrically connect the circuit board DC to the electronic panel EP.

[0101] The flexible board CF can be assembled in a bent state. Therefore, the main board MB can be mounted on the rear surface of the electronic panel EP to be stably housed within the space provided by the housing HU. The flexible board CF can be omitted. Here, the main board MB can be directly connected to the electronic panel EP.

[0102] The motherboard MB may include signal lines and electronic components. The electronic components may be connected to the signal lines for electrical connection to the electronic panel EP. The electronic components generate various electrical signals (e.g., signals for generating an image IM or signals for sensing user input TC) or process sensed signals. The motherboard MB may be configured with multiple corresponding to the electrical signals used for generation and processing, but exemplary embodiments are not limited thereto. An electronic module EM may be electrically connected to the motherboard MB.

[0103] In the display device DD1, the drive circuit that provides electrical signals to the effective area AA can be directly mounted on the electronic panel EP. Here, the drive circuit can be mounted as a chip, or it can be formed together with the pixel PX (to be described). Here, the surface area of ​​the circuit board DC can be reduced or the circuit board DC can be omitted.

[0104] The electronic module EM is positioned below the window WM. The electronic module EM can overlap with the module area MA in the plan view. The electronic module EM can receive external input transmitted through the module area MA or provide output through the module area MA. For example, the electronic module EM can overlap with the effective area AA, thereby preventing the border area BZA from increasing.

[0105] Figure 5 yes Figure 1 A cross-sectional view of the electronic panel of the display device.

[0106] like Figure 5 As shown, the electronic panel EP includes a display panel DP and an input sensing layer ISL. The display panel DP is schematically shown to illustrate the stacking relationship of the input sensing layer ISL.

[0107] like Figure 5 As shown, the display panel DP includes a base layer BL, a circuit element layer DP-CL, a light-emitting element layer DP-OLED, and a thin-film encapsulation layer TFE. The input sensing layer ISL can be disposed on the thin-film encapsulation layer TFE.

[0108] The input sensing layer ISL includes a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1, a second sensing insulating layer IS-IL2, a second conductive layer IS-CL2, and a third sensing insulating layer IS-IL3. The first sensing insulating layer IS-IL1 can be directly disposed on the thin-film encapsulation layer TFE. According to another exemplary embodiment, the first sensing insulating layer IS-IL1 can be omitted, and the first conductive layer IS-CL1 can be directly disposed on the thin-film encapsulation layer TFE.

[0109] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 can have a single-layer structure or a multilayer structure with multiple layers stacked on the third-direction DR3. The conductive layer with a multilayer structure can include at least two or more transparent conductive layers and metal layers. The conductive layer with a multilayer structure can include metal layers comprising different metals. The transparent conductive layer can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layers can include molybdenum, silver, titanium, copper, aluminum, and their alloys. For example, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 can have a three-layer metal structure, such as a titanium / aluminum / titanium three-layer structure. Metals with relatively high durability and low reflectivity can be applied to the outer layer, and metals with high conductivity can be applied to the inner layer.

[0110] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include multiple conductive patterns. Hereinafter, examples will be described of the first conductive layer IS-CL1 including a first conductive pattern and the second conductive layer IS-CL2 including a second conductive pattern. Each of the first and second conductive patterns may include a sensing electrode and a signal line connected to the sensing electrode.

[0111] Each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may comprise an inorganic layer or an organic layer. In this exemplary embodiment, each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may be an inorganic layer. The inorganic layer may comprise at least one of titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. According to another exemplary embodiment, the first sensing insulating layer IS-IL1 may be an organic layer. The organic layer may comprise at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and dinaphthalene-based phenyl resin.

[0112] Although the electronic panel EP is configured as a single substrate, and each of the display panel DP and the input sensing layer ISL is configured as a "layer" type, the exemplary implementation is not limited thereto. In another exemplary implementation, the display panel DP and the input sensing layer ISL may be configured as separate substrates and then bonded together with each other.

[0113] Figure 6 yes Figure 1 A plan view of the display panel of the display device.

[0114] like Figure 6 As shown, the display panel DP includes a driving circuit SDC, multiple signal lines SGL (hereinafter referred to as signal lines), multiple signal pads DP-PD, ISL-PD (hereinafter referred to as signal pads), and multiple pixels PX (hereinafter referred to as pixels).

[0115] The driving circuit SDC may include a scan driving circuit. The scan driving circuit generates multiple scan signals (hereinafter referred to as scan signals) to sequentially output to multiple scan lines SL (hereinafter referred to as scan lines), which will be described later. The scan driving circuit may also output another control signal to the driving circuit of the pixel PX.

[0116] The scan driving circuit may include multiple transistors manufactured using the same process as the driving circuit of the pixel PX, such as low-temperature polycrystalline silicon (LTPS) or low-temperature polycrystalline oxide (LTPO) processes.

[0117] The signal line SGL includes scan lines SL, data lines DL, power lines PL, and control signal lines CSL. Scan lines SL are connected to corresponding pixels in pixel PX, and data lines DL are also connected to corresponding pixels in pixel PX. Power lines PL are connected to pixels PX. Control signal lines CSL provide control signals to the scan drive circuit.

[0118] In this exemplary embodiment, the signal line SGL may further include an auxiliary line SSL. The auxiliary line SSL is connected to the input sensing layer ISL (see [link to ISL]). Figure 7 The signal line is SSL. Optionally, the auxiliary SSL line can be omitted.

[0119] Signal lines (SGLs) can include multiple parts set on different layers. Figure 6 An example is shown, comprising a data line DL with four sections P1 to P4 and an auxiliary line SSL with two sections P10 to P20. The four sections P1 to P4 can be connected to each other via contact holes CNT. The two sections P10 and P20 can be connected to each other via contact holes CNT. The first section P10 of the auxiliary line SSL is connected via contact holes CNT to the input sensing layer ISL, which will be described below (see [link to documentation]). Figure 7 (Signal line)

[0120] Figure 4The pads PD shown may include signal pads DP-PD and ISL-PD. Signal pads DP-PD and ISL-PD may include a first type of signal pad DP-PD connected to data line DL, power line PL, and control signal line CSL, and a second type of signal pad ISL-PD connected to auxiliary line SSL. The first type of signal pad DP-PD and the second type of signal pad ISL-PD are arranged adjacent to each other in a pad area NDA-PA defined within a portion of the peripheral area NAA. Signal pads DP-PD and ISL-PD may be formed using the same process without distinguishing their stack-up structure or constituent materials.

[0121] The effective area AA can be defined as the area on which the pixel PX is disposed. Multiple electronic components can be disposed in the effective area AA. The electronic components include organic light-emitting diodes disposed in each pixel PX and pixel driving circuits connected to the organic light-emitting diodes. Figure 5 The circuit element layer DP-CL shown can be configured with drive circuit SDC, signal line SGL, signal pads DP-PD and ISL-PD, as well as pixel drive circuit.

[0122] For example, a pixel PX may include at least one transistor, at least one capacitor, and an organic light-emitting diode. The pixel PX is connected to the scan line SL and the data line DL. The pixel PX receives a power supply voltage from the power line PL.

[0123] The signal pads DP-PD and ISL-PD of the display panel DP can be electrically connected to... Figure 4 The circuit board shown is DC.

[0124] Figure 6 A portion of the display panel DP shown can be bent. A portion of the peripheral area NAA can be bent relative to a bending axis parallel to the first direction DR1. The bending axis can be defined to overlap with the second portion P3 of the data line DL and the auxiliary line SSL.

[0125] Figure 6 The panel module region MAb of the display panel DP shown is defined within the effective area AA. In an exemplary embodiment, the pixel PX may not be disposed within the panel module region MAb of the display panel DP.

[0126] Figure 7 yes Figure 1 A plan view of the input sensing layer of a display device.

[0127] Reference Figure 7 The input sensing layer ISL is set in Figure 6 The display panel DP is shown. The input sensing layer ISL can detect the user's input TC (see...). Figure 1This allows for the acquisition of location or intensity information from external touch input. In a plan view, the input sensing layer ISL may include a sensing area SA and a line area NSA. The sensing area SA can be defined as the area on which a first sensing electrode SE1 and a second sensing electrode SE2 are disposed. In this exemplary embodiment, the line area NSA may be defined along the edge of the sensing area SA. The sensing area SA and the line area NSA may correspond to the effective area AA and the peripheral area NAA of the display panel DP, respectively.

[0128] In this exemplary embodiment, the input sensing layer ISL can be a capacitive touch sensor. One of the first sensing electrode SE1 and the second sensing electrode SE2 receives a driving signal, and the other of the first sensing electrode SE1 and the second sensing electrode SE2 outputs the capacitance change between the first sensing electrode SE1 and the second sensing electrode SE2 as a sensing signal.

[0129] Each first sensing electrode SE1 has a shape extending in a first direction DR1. Furthermore, the first sensing electrodes SE1 may be arranged sequentially in a second direction DR2. The first sensing electrodes SE1 may include a plurality of first sensing patterns SP1 and a plurality of first auxiliary patterns CP1.

[0130] Each second sensing electrode SE2 has a shape extending in the second direction DR2. Furthermore, the second sensing electrodes SE2 may be arranged sequentially in the first direction DR1. The second sensing electrodes SE2 may include a plurality of second sensing patterns SP2 and a plurality of second auxiliary patterns CP2.

[0131] The first sensing lines TL1-1 to TL1-a may include the same number of signal lines as the first sensing electrode SE1. The first sensing lines TL1-1 to TL1-a may be connected to at least one of the two ends of the first sensing electrode SE1. The second sensing lines TL2-1 to TL2-b may include the same number of signal lines as the second sensing electrode SE2. The second sensing lines TL2-1 to TL2-b may be connected to at least one of the two ends of the second sensing electrode SE2.

[0132] The first sensing lines TL1-1 to TL1-a can be connected via contact holes CNT to the pad area NDA-PA (see...). Figure 6 Some auxiliary lines SSL on one side (see) Figure 6 The second sensing lines TL2-1 to TL2-b can be connected via contact holes CNT to the NDA-PA area located on the pads (see...). Figure 6 Some auxiliary lines SSL on the other side (see) Figure 6 ).

[0133] The contact hole CNT can pass through the insulating layer disposed between the first sensing lines TL1-1 to TL1-a and the second sensing lines TL2-1 to TL2-b and the auxiliary line SSL.

[0134] Figure 7 The panel module region MAb of the input sensing layer ISL shown is defined within the sensing region SA. In an exemplary embodiment, the first sensing electrode SE1 and the second sensing electrode SE2 may not be disposed in the panel module region MAb of the input sensing layer ISL.

[0135] Figure 8 It is along Figure 1 A sectional view taken by line I-I'. Figure 9 It is shown Figure 1 A plan view of an exemplary embodiment of the window module area of ​​a display device, the plan view showing... Figure 1 The window module area. Figure 10 This is a plan view illustrating an exemplary embodiment of an electronic panel.

[0136] like Figure 8 , Figure 9 and Figure 10 As shown, the window WM includes a window substrate WMB and a light-blocking layer BML. In an exemplary embodiment, the window substrate WMB may be a transparent substrate such as a glass substrate, but is not limited thereto. The window module region MAa is defined on the window substrate WMB. The window module region MAa is the region that overlaps with the electronic module EM. The window module region MAa includes a transmissive region TA and a light-blocking pattern region BMA.

[0137] In a planar diagram, the light-blocking pattern region BMA can have a shape that surrounds the transmission region TA. For example... Figure 9 As shown, when the transmission region TA has a circular shape, the light-blocking pattern region BMA can have a closed curve shape (e.g., a ring shape or annular shape) that extends continuously along the edge of the transmission region TA. The shape of the light-blocking pattern region BMA can be designed differently depending on the shape of the transmission region TA.

[0138] The transmissive region TA of the window substrate WMB can be transparent, allowing sufficient external light to be supplied to the electronic module EM. A light-blocking layer BML is disposed on one surface of the window substrate WMB within a light-blocking pattern region BMA. The light-blocking layer BML can be directly disposed on the window substrate WMB through deposition, printing, or coating processes. The light-blocking layer BML prevents external light from being supplied to the electronic module EM. Therefore, the transmittance of the transmissive region TA of the window substrate WMB can be greater than the transmittance of the light-blocking pattern region BMA.

[0139] The light-blocking layer BML can have a multilayer structure. More specifically, the light-blocking layer BML may include multiple layers disposed on the window substrate WMB. One of the multiple layers may be black, and the other layers may be colored. In another exemplary embodiment, a film on which the light-blocking layer BML is printed may be bonded to one surface of the window substrate WMB via an adhesive layer.

[0140] The panel module region MAb is defined on the electronic panel EP. The panel module region MAb is the area that overlaps with the electronic module EM. Furthermore, the panel module region MAb of the electronic panel EP overlaps with the window module region MAa of the window substrate WMB. The panel module region MAb includes a central region CA, a patterned region PA, and a line region LA.

[0141] In the exemplary embodiment shown, the central region CA may have a generally circular shape in the plan view. The patterned region PA may have a ring (annular) shape surrounding the central region CA. The line region LA may have an annular shape surrounding the patterned region PA. However, the central region CA may be designed in various shapes depending on the shape of the receiving or output unit of the electronic module EM. For example, the central region CA may be designed in various shapes such as an ellipse, a polygon, or a shape in which at least one side is curved, as long as it can accommodate the electronic module EM therein.

[0142] The central region CA of the electronic panel EP can correspond to or be wider than the transmissive region TA of the window substrate WMB. The patterned region PA and line region LA of the electronic panel EP can correspond to the light-blocking patterned region BMA of the window substrate WMB.

[0143] In a plan view, the patterned area PA can have a shape surrounding the central area CA. For example... Figure 10 As shown, when the central region CA has a circular shape, the pattern region PA can have a ring shape surrounding the central region CA. Furthermore, the line region LA can have a shape surrounding the pattern region PA.

[0144] The electronic panel EP includes one or more markings, which may take the form of alignment marks AM set in the pattern area PA. Figure 10 In the example shown, the alignment mark AM is depicted as having a "+" shape, but the exemplary implementation is not limited to this. Furthermore, in Figure 10 In the example shown, multiple alignment markers AM are set, and the arrangement intervals and sizes of the alignment markers AM can be varied.

[0145] Figure 11 It is along Figure 4 The line II-II' intercept shows Figure 4A cross-sectional view of an example electronic panel of a display device.

[0146] For ease of description, Figure 11 The following diagram illustratively illustrates some components of the display panel DP and input sensing layer ISL in the assembly of the electronic panel EP. The display panel DP includes a base layer BL, thin-film transistors TR, light-emitting elements ELD, multiple insulating layers 10, 20, 30, 40, 50, and 60, and hole signal lines HSL1 and HSL2. The input sensing layer ISL includes a first sensing insulating layer IS-IL1, a second sensing insulating layer IS-IL2, a third sensing insulating layer IS-IL3, multiple sensing patterns SP1 and SP2, a second auxiliary pattern CP2, and the hole signal line HSL3.

[0147] Insulating layers 10, 20, 30, 40, 50, and 60 may comprise a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60 stacked sequentially. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60 may comprise organic and / or inorganic materials and may have a single-layer structure or a stacked structure.

[0148] In this exemplary embodiment, the substrate BL can be optically transparent. For example, the substrate BL can have a visible light transmittance of about 90% or higher.

[0149] A first insulating layer 10 is disposed on a substrate BL to cover the front surface of the substrate BL. The first insulating layer 10 may include a barrier layer and / or a buffer layer. Therefore, the first insulating layer 10 can prevent oxygen or moisture introduced through the substrate BL from penetrating into the pixel PX, or can provide the pixel PX with a top surface having low surface energy, so that the pixel PX is stably formed on the substrate BL.

[0150] In this exemplary embodiment, the first insulating layer 10 may be optically transparent. For example, the first insulating layer 10 may have a visible light transmittance of about 90% or higher.

[0151] Thin-film transistors (TRs) and light-emitting elements (ELDs) constitute a pixel (PX). Figure 6 The thin-film transistor TR may include a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10.

[0152] Semiconductor pattern SP includes semiconductor materials. For example, semiconductor pattern SP may include group III elements, group V elements, compound or oxide semiconductors of group III elements or group V elements.

[0153] A semiconductor pattern SP can be divided into a channel region CH, an input region IA, and an output region OA. The input region IA and the output region OA are spaced apart from each other, and the channel region CH is located between the input region IA and the output region OA. The channel region CH, the input region IA, and the output region OA can have an integral shape that is connected to each other.

[0154] In a planar diagram, the channel region CH can be the region overlapping with the control electrode CE. Compared to the channel region CH, the input region IA and the output region OA can have relatively high charge mobility. Charge within the semiconductor pattern SP can move from the input region IA to the output region OA through the channel region CH.

[0155] A control electrode CE is disposed on a second insulating layer 20. The second insulating layer 20 is disposed on a first insulating layer 10 to cover a semiconductor pattern SP. In cross-section, the control electrode CE may be spaced apart from the semiconductor pattern SP, and the second insulating layer 20 is located between the control electrode CE and the semiconductor pattern SP.

[0156] The input electrode IE and the output electrode OE are disposed on the third insulating layer 30. The third insulating layer 30 is disposed on the second insulating layer 20 to cover the control electrode CE.

[0157] The input electrode IE passes through the second insulating layer 20 and the third insulating layer 30 and is connected to the input region IA. The output electrode OE is spaced apart from the input electrode IE and is connected to the output region OA. Each of the input electrode IE and the output electrode OE may include a conductive material. The input electrode IE supplies charge to the input region IA, and the output electrode OE transfers the charge that has moved to the output region OA to the light-emitting element ELD.

[0158] In the thin-film transistor TR according to the illustrated exemplary embodiment, the input electrode IE and the output electrode OE can be omitted. For example, the thin-film transistor TR may consist only of the control electrode CE and the semiconductor pattern SP. Here, the input region IA and the output region OA can be used as the input electrode IE and the output electrode OE, and the input electrode IE and the output electrode OE can be used as connection electrodes to connect the thin-film transistor TR to other signal lines or other components. The thin-film transistor TR can be configured in various ways, and the exemplary embodiment is not limited to a specific structure.

[0159] The light-emitting element (ELD) may include a first electrode E1, a second electrode E2, an emission pattern EMP, and a control layer EL. The first electrode E1, second electrode E2, emission pattern EMP, and control layer EL of the light-emitting element ELD may correspond to a DP-OLED light-emitting element layer. The first electrode E1 is disposed on a fourth insulating layer 40. The fourth insulating layer 40 is disposed on a third insulating layer 30 to cover the thin-film transistor TR. The first electrode E1 is connected to the output electrode OE and electrically connected to the thin-film transistor TR.

[0160] The second electrode E2 is disposed on a fifth insulating layer 50 disposed on a fourth insulating layer 40. The fifth insulating layer 50 may comprise organic and / or inorganic materials and have a single-layer or multi-layer structure. The second electrode E2 may have a surface area covering less than the entire surface of the effective region AA or a surface area substantially covering the entire surface of the effective region AA. Therefore, multiple light-emitting elements ELDs may comprise a common second electrode E2. However, this is only an example. For example, a second electrode E2 may be provided for each pixel PX to correspond to the first electrode E1, and the structure is not limited to a specific one.

[0161] An opening may be defined in the fifth insulating layer 50 to expose at least a portion of the first electrode E1. An emission pattern EMP may be disposed in the opening. The emission pattern EMP may include a luminescent material, which may include a fluorescent material or a phosphorescent material. The luminescent material may include an organic luminescent material or an inorganic luminescent material, and exemplary embodiments are not limited thereto.

[0162] A control layer EL is disposed between the first electrode E1 and the second electrode E2. The control layer EL may have a surface area covering less than the entire surface of the effective region AA or substantially covering the entire surface of the effective region AA. The control layer EL may include organic materials. The control layer EL controls the movement of charge to improve the luminous efficiency and lifetime of the light-emitting element ELD. The control layer EL may include electron transport materials, electron injection materials, hole transport materials, or hole injection materials.

[0163] In the exemplary embodiment shown, the control layer EL is depicted as being disposed on the emission pattern EMP, but this is merely an example. For instance, the control layer EL may be disposed between the emission pattern EMP and the first electrode E1, or multiple control layers EL may be disposed respectively between the emission pattern EMP and the first electrode E1 and between the emission pattern EMP and the second electrode E2, but the exemplary embodiment is not limited to a specific structure.

[0164] A sixth insulating layer 60 is disposed on the light-emitting element ELD to seal the light-emitting element ELD. The sixth insulating layer 60 can be... Figure 5 The thin-film encapsulation layer TFE is shown. A cover layer covering the second electrode E2 can be further provided between the second electrode E2 and the sixth insulating layer 60.

[0165] The sixth insulating layer 60 may include a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63 sequentially stacked on the third-direction DR3. However, exemplary embodiments are not limited thereto. For example, the sixth insulating layer 60 may further include multiple inorganic and organic layers.

[0166] The first inorganic layer 61 may cover the second electrode E2. The first inorganic layer 61 may prevent external moisture or oxygen from penetrating into the light-emitting element (ELD). For example, the first inorganic layer 61 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer 61 may be formed by a chemical vapor deposition process.

[0167] The transmittance of the first inorganic layer 61 can be less than that of the base layer BL. For example, the first inorganic layer 61 may include silicon nitride (SiN). x This will be described in detail below.

[0168] An organic layer 62 may be disposed on the first inorganic layer 61 to contact the first inorganic layer 61. The organic layer 62 may provide a flat surface on the first inorganic layer 61. Curves on the top surface of the first inorganic layer 61 or particles present on the first inorganic layer 61 may be covered by the organic layer 62 to prevent the surface condition of the top surface of the first inorganic layer 61 from affecting the components disposed on the organic layer 62. Furthermore, the organic layer 62 may reduce stress between layers in contact with each other. The organic layer 62 may include organic materials and is formed by solution methods such as spin coating, slot coating, or inkjet printing.

[0169] The second inorganic layer 63 can be disposed on the organic layer 62 to cover the organic layer 62. Compared with the second inorganic layer 63 disposed on the first inorganic layer 61, the second inorganic layer 63 can be formed relatively stably on a flat surface. The second inorganic layer 63 can seal off moisture discharged from the organic layer 62 to prevent moisture from being introduced.

[0170] The second inorganic layer 63 can be optically transparent. For example, the second inorganic layer 63 can have a visible light transmittance of about 90% or higher. Compared with the first inorganic layer 61, the second inorganic layer 63 can have a relatively high transmittance. The second inorganic layer 63 may include silicon oxide (SiO2). x ) or silicon oxynitride (SiON).

[0171] The second inorganic layer 63 can be formed by a chemical vapor deposition process. Each of the first inorganic layer 61, the organic layer 62, and the second inorganic layer 63 may include multiple layers and is not limited to a specific structure.

[0172] In this exemplary embodiment, the input sensing layer ISL (see Figure 7 The first sensing pattern SP1, the second sensing pattern SP2, and the second auxiliary pattern CP2 are shown as being disposed on the display panel DP. However, the exemplary embodiment is not limited thereto. As described above, the first sensing pattern SP1, the second sensing pattern SP2, and the second auxiliary pattern CP2 may be some components of the input sensing layer ISL. The first sensing pattern SP1, the second sensing pattern SP2, and the second auxiliary pattern CP2 together with the seventh insulating layer 70 constitute the input sensing layer ISL.

[0173] The input sensing layer ISL may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73 stacked sequentially. A seventh insulating layer 70 may be configured to overlap with each of the active area AA and the panel module area MAb.

[0174] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may be optically transparent. For example, each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a visible light transmittance of about 90% or higher. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have an inorganic layer, an organic layer, or a stacked structure of inorganic and organic layers.

[0175] In this exemplary embodiment, the first sensing pattern SP1 and the second sensing pattern SP2 are disposed on the same layer, and the second auxiliary pattern CP2 is disposed on a layer different from the second sensing pattern SP2. Each of the first sensing pattern SP1, the second sensing pattern SP2, and the second auxiliary pattern CP2 may include a transparent conductive oxide. The second auxiliary pattern CP2 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72. The second sensing pattern SP2 may pass through the second sensing insulating layer 72 and be connected to the second auxiliary pattern CP2. The first auxiliary pattern CP1 (see...) Figure 7 The first auxiliary pattern CP1 and the first sensing pattern SP1 can be disposed on the same layer. For example, the first auxiliary pattern CP1 can be directly connected to the first sensing pattern SP1.

[0176] However, this is merely an example. For instance, the second auxiliary pattern CP2 and the second sensing pattern SP2 can be disposed on the same layer. The first auxiliary pattern CP1 can be disposed on a different layer than the first sensing pattern SP1. Alternatively, the first sensing pattern SP1 and the second sensing pattern SP2 can be disposed on different layers. The input sensing layer ISL can be configured in various ways, and the exemplary embodiments are not limited to a particular structure.

[0177] The hole signal lines HSL1, HSL2, and HSL3 are located in the panel module area MAb. The panel module area MAb may include a center area CA, a pattern area PA, and a line area LA.

[0178] The central region CA can be the area of ​​the electronic module EM that substantially overlaps with the receiving unit of the electronic panel EP. As used herein, "electronic module" can be any electrical device that receives external input or an output unit that provides output, such as a camera or sensor. For example, when the electronic module EM is a camera module, the central region CA can be the area of ​​the panel module region MAb that overlaps with the lens. The central region CA can also be the area in the panel module region MAb that has the highest light transmittance.

[0179] The via signal lines HSL1, HSL2, and HSL3 are set in the line area LA. Figure 11 For ease of description, some of the corresponding first hole signal lines HSL1, second hole signal line HSL2, and third hole signal line HSL3 are shown.

[0180] The first hole signal line HSL1 and the second hole signal line HSL2 can be the display panel DP (see...). Figure 6 The signal line SGL is shown in the diagram. The first hole signal line HSL1 is shown as being disposed between the second insulating layer 20 and the third insulating layer 30. The first hole signal line HSL1 may be a scan line SL connected to a pixel PX disposed adjacent to the panel module region MAb. The first hole signal line HSL1 may provide the same scan signal to the pixels PX disposed spaced apart from each other and in which the panel module region MAb is located via the line region LA.

[0181] The second hole signal line HSL2 is shown located between the third insulating layer 30 and the fourth insulating layer 40. The second hole signal line HSL2 may be a data line DL connected to a pixel PX disposed adjacent to the panel module region MAb. The second hole signal line HSL2 is electrically connected via line regions LA to pixels PX spaced apart from each other and between which the panel module regions MAb are located.

[0182] The third hole signal line HSL3 is disposed on the first sensing insulating layer 71 to form the input sensing layer ISL. In this exemplary embodiment, the third hole signal line HSL3 is shown disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, but this is only an example. For example, the third hole signal line HSL3 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. The third hole signal line HSL3 may be a connecting line connected to the sensing patterns SP1 and SP2 disposed adjacent to the panel module area MAb.

[0183] The electronic panel EP may also include at least one recessed portion GV1 and GV2, a dam portion DM, and a planarization pattern OCT. The recessed portions GV1 and GV2, the dam portion DM, and the planarization pattern OCT are disposed in the panel module area MAb.

[0184] Recessed portions GV1 and GV2 can be provided in the patterned area PA of the panel module area MAb. Recessed portions GV1 and GV2 can be provided by recessing at least a portion of the base layer BL. Recessed portions GV1 and GV2 have a depth that does not penetrate the base layer BL. Recessed portions GV1 and GV2 may include a first recessed portion GV1 and a second recessed portion GV2 spaced apart from each other.

[0185] The first groove portion GV1 may be defined as being relatively adjacent to the effective region AA and filled with the organic layer 62. The second groove portion GV2 may be defined as being relatively adjacent to the central region CA and sequentially covered by a first inorganic layer 61 and a second inorganic layer 63 spaced apart from the organic layer 62. Each of the first groove portion GV1 and the second groove portion GV2 has a closed line shape around the central region CA or a discontinuous line shape around at least a portion of the edge of the central region CA, but is not limited to the specific exemplary embodiment.

[0186] One end of the first insulating layer 10 may have an undercut shape protruding from each of the first recessed portion GV1 and the second recessed portion GV2. The control layer EL and the second electrode E2 are respectively cut off by the first recessed portion GV1 and the second recessed portion GV2. The electronic panel EP may also include recessed portions GV1 and GV2 to prevent the continuity of the control layer EL or the second electrode E2 from forming a penetration path for external moisture or oxygen, thereby preventing damage to components disposed in the effective area AA.

[0187] Some patterns, separate from the control layer EL or the second electrode E2, can be formed inside each of the first recessed portion GV1 and the second recessed portion GV2, and covered by at least one of the first inorganic layer 61 and the second inorganic layer 63. Therefore, during the manufacturing process of the electronic panel EP, the influence of some patterns on other components due to movement can be prevented. Thus, the process reliability of the electronic panel EP can be improved. However, this is merely an example. For instance, in the electronic panel EP according to an exemplary embodiment, the recessed portions GV1 and GV2 can be provided individually or omitted, and are not limited to a specific structure.

[0188] A dam portion DM is disposed within the panel module region MAb to delineate the formation area of ​​the organic layer 62 into a predetermined area and to prevent additional expansion of the organic layer 62. The dam portion DM may be disposed between the first recess portion GV1 and the second recess portion GV2. The dam portion DM is shown as a stacked structure comprising multiple insulating patterns IP1 and IP2. However, this is merely an example. For instance, the dam portion DM may have a single-layer structure, and the exemplary embodiments are not limited to a particular structure.

[0189] The planarization pattern OCT comprises an organic material. The planarization pattern OCT can be disposed on the front surface of the panel module region MAb. The planarization pattern OCT covers the non-planarized surfaces in the panel module region MAb that are provided due to the dam portion DM or the recess portions GV1 and GV2, to provide a flat surface thereon. Therefore, a flat surface can be smoothly provided even in areas of the panel module region MAb where the organic layer 62 is not disposed.

[0190] Planarized patterned OCTs can be optically transparent. For example, planarized patterned OCTs can have a visible light transmittance of about 90% or higher.

[0191] According to an exemplary embodiment, the first inorganic layer 61 can be removed from the central region CA. Compared to the second inorganic layer 63, the first inorganic layer 61 can have a relatively low transmittance. According to an exemplary embodiment, the transmittance of the central region CA can be improved by providing a first inorganic layer 61 with a shape that does not overlap with the central region CA.

[0192] Furthermore, the electronic panel EP according to the exemplary embodiment may also include an alignment mark AM. The alignment mark AM may be disposed in the pattern area PA. The alignment mark AM may be disposed on the same layer as any one of the first sensing pattern SP1, the second sensing pattern SP2, and the second auxiliary pattern CP2. Figure 11 In the example shown, the alignment mark AM is disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, but the exemplary embodiment is not limited thereto. For example, the alignment mark AM may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. In another exemplary embodiment, the alignment mark AM may be disposed on the third sensing insulating layer 73 in an embossed or recessed shape.

[0193] Alignment marks AM can comprise metallic or inorganic insulating materials. Alignment marks AM can be patterned by dry etching or wet etching, or by using a laser. Alignment marks AM can be formed using various processes, and exemplary embodiments are not limited to a particular process or structure. Alignment marks AM can be optically opaque. Figure 8 In the exemplary embodiment shown, the alignment mark AM overlaps with the light-blocking pattern area BMA of the window WM, and is therefore not visible to the user.

[0194] Reference Figure 8 and Figure 11 The alignment device aligns the electronic panel EP and the window WM to position them, thereby attaching the electronic panel EP to the window WM. The alignment device includes a camera, which captures an alignment mark AM on the panel module area MAb at the top of the electronic panel EP. The alignment device can identify the alignment mark AM included in the image received by the camera and align the electronic panel EP and the window WM relative to the identified alignment mark AM.

[0195] Alignment marks (AM) can have various geometric patterns recognizable by alignment equipment and are easily identifiable when line segments intersect with patterns containing line segments. For example, alignment marks (AM) can be in the form of "H", "T", "F", "X", etc. The form is in the shape of characters such as "T".

[0196] Alignment mark AM can not only be set Figure 1 The panel module area MAb of the display device DD1 shown can be located in the bezel area BZA of the display device DD1. However, Figure 2 The display device DD2 shown is Figure 3 The display device DD3 shown does not include the border area adjacent to the display area DA.

[0197] Each of the display devices DD1, DD2, and DD3 includes an alignment mark AM in the panel module area MAb of the electronic panel EP. Therefore, even for display devices that do not include a bezel area, the alignment device can easily align the electronic panel EP and the window WM using the alignment mark AM.

[0198] Figure 12 It is along Figure 4 The section cut by line II-II' shows another example of an electronic panel.

[0199] For ease of description, Figure 12 The diagram shows some components of the display panel DP and the input sensing layer ISL in the assembly of the electronic panel EP2. Additionally, with... Figure 11 The same components of the electronic panel EP shown are indicated by the same reference numerals, and repeated descriptions will be omitted for the sake of convenience.

[0200] like Figure 12 As shown, the electronic panel EP2 includes alignment marks AM2. Alignment marks AM2 can be disposed within the patterned area PA. For example, alignment marks AM2 are disposed between the first insulating layer 10 and the second inorganic layer 63, but the exemplary embodiment is not limited thereto. In another exemplary embodiment, alignment marks AM2 can be disposed on the first insulating layer 10 in an embossed or recessed shape. Furthermore, alignment marks AM2 can comprise multiple layers sequentially stacked.

[0201] The alignment mark AM2 may comprise a metallic or inorganic insulating material. The alignment mark AM2 may be patterned by dry etching or wet etching, or it may be patterned using a laser. The alignment mark AM2 may be formed using various processes, and exemplary embodiments are not limited to a particular process. The alignment mark AM2 may be optically opaque. The alignment mark AM2 is related to... Figure 8 The light-blocking pattern area BMA of the window WM shown overlaps and is therefore not visible to the user.

[0202] Figures 1 to 3Each of the display devices DD1, DD2, and DD3 shown includes an alignment mark AM2 in the panel module area MAb of the electronic panel EP2. Therefore, even for display devices that do not include a bezel area, the alignment device can easily align the electronic panel EP2 and the window WM using the alignment mark AM2.

[0203] Figure 13 This is an exploded perspective view of another exemplary embodiment of a display device constructed according to the principles of the present invention. Figure 14 It is along Figure 13 The sectional view taken from line III-III'.

[0204] like Figure 13 As shown, with Figure 4 Compared to the display device DD1 shown, the display device DD4 may further include an anti-reflective member POL and an adhesive member ADL. A module region MA can be defined within the display area DA of the display device DD4. The module region MA may be an area overlapping with the electronic module EM. The window module region MAa of the window WM, the hole portion MA-P of the anti-reflective member POL, the panel module region MAb of the electronic panel EP3, and the electronic module EM are defined at positions where they overlap in the plan view. Furthermore, in the positions where the window WM, the anti-reflective member POL, and the electronic panel EP3 are joined together, the window module region MAa, the hole portion MA-P, and the panel module region MAb overlap with the module region MA.

[0205] An anti-reflective element (POL) can be disposed between the window WM and the electronic panel EP3. The anti-reflective element POL reduces the reflectivity of external light (hereinafter referred to as external light) incident outside the window WM to the electronic panel EP3. In this exemplary embodiment, the anti-reflective element POL may include a polarizing film or a color filter.

[0206] An adhesive member ADL is disposed between the antireflective member POL and the window WM. The adhesive member ADL bonds the antireflective member POL to the window WM. When the antireflective member POL according to the exemplary embodiment is a color filter disposed on the electronic panel EP3, the adhesive member ADL can substantially bond the electronic panel EP3 to the window WM. The adhesive member ADL may include an optically clear adhesive, an optically clear resin, or a pressure-sensitive adhesive. However, the exemplary embodiment is not limited thereto.

[0207] An antireflective member POL according to an exemplary embodiment may include an aperture portion MA-P. The aperture portion MA-P may be defined at a location corresponding to the central region CA. The aperture portion MA-P may be a portion with a transmittance greater than that of the surrounding portion.

[0208] like Figure 14As shown, the anti-reflective component POL may include an aperture portion MA-P and a polarizing portion PP. The polarizing portion PP may be a portion with polarization characteristics and may be any portion other than the aperture portion MA-P. The polarizing portion PP overlaps with the effective region AA, the line region LA, and the patterned region PA.

[0209] The aperture portion MA-P may overlap with the central region CA. The aperture portion MA-P may have a size corresponding to the central region CA. In this exemplary embodiment, the aperture portion MA-P may be defined by decolorizing a portion of the antireflective member POL to remove polarization characteristics. In another exemplary embodiment, the aperture portion MA-P may be an aperture passing through the antireflective member POL.

[0210] The light-blocking layer BML of the window WM overlaps with the pattern area PA and the line area LA. Therefore, the alignment mark AM and the hole signal lines HSL1, HSL2, and HSL3 are not visible to the user.

[0211] In a display device constructed according to the principles and exemplary embodiments of the present invention, an electronic module can be disposed within the effective area of ​​the display panel. The bezel area of ​​the display device can be minimized, and the effective area of ​​the display device can be maximized. Furthermore, alignment marks can be disposed within the module area in which the electronic module is disposed within the effective area of ​​the display panel, and thus, the display panel and the window module can be easily connected to each other. Therefore, production efficiency can be improved.

[0212] While certain exemplary embodiments and examples have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that would be apparent to those skilled in the art.

Claims

1. A display device, including: Electronic module; A light-blocking layer is disposed on one surface of the window substrate; as well as Electronic panels, including: The first region overlaps with the electronic module; The second region, in the plan view, surrounds at least a portion of the first region and includes an effective area; and A marker is set in the first area; The first region includes a panel module region, which includes a central region overlapping the electronic module and a patterned region surrounding the central region. The markings include alignment marks disposed in the patterned area and overlapping with the light-blocking layer in the plan view. The effective area surrounds the pattern area.

2. The display device according to claim 1, wherein, The electronic panel further includes a base layer, including an upper side, a portion of which is recessed to form a groove portion, the groove portion overlapping the mark in a plan view.

3. The display device according to claim 2, wherein, The electronic panel also includes: Multiple pixels are disposed on the upper side of the base layer in the effective area; and An encapsulation layer is disposed on the upper side of the base layer to cover the plurality of pixels. The alignment mark is disposed on the encapsulation layer.

4. The display device according to claim 2, wherein, The electronic panel also includes: Multiple pixels are disposed on the upper side of the base layer in the effective area; An encapsulation layer is disposed on the upper side of the base layer to cover the plurality of pixels; and An input sensing layer is disposed on the encapsulation layer and includes multiple sensing patterns and multiple sensing insulating layers disposed between the sensing patterns.

5. The display device according to claim 4, wherein, One of the plurality of sensing patterns and the alignment mark are disposed on the same layer.

6. The display device according to claim 4, wherein, The plurality of sensing insulating layers include a first sensing insulating layer and a second sensing insulating layer, and The alignment mark is disposed between the first sensing insulating layer and the second sensing insulating layer.

7. A display device, including: Electronic module; A light-blocking layer is disposed on one surface of the window substrate; as well as The electronic panel, in a plan view, is divided into a first region that overlaps with the electronic module and a second region surrounding at least a portion of the first region, including an effective region; The electronic panel includes: Multiple pixels are set in the second region; An encapsulation layer configured to cover the plurality of pixels; and A marker is provided on the encapsulation layer, which overlaps with the first region in the plan view; The first region includes a panel module region, which includes a central region overlapping the electronic module and a patterned region surrounding the central region. The markings include alignment marks disposed in the patterned area and overlapping with the light-blocking layer in the plan view. The effective area surrounds the pattern area.

8. The display device according to claim 7, wherein, The electronic panel further includes a base layer, including an upper side, a portion of which is recessed to form a groove portion, the groove portion overlapping the mark in a plan view.

9. The display device according to claim 8, wherein, The encapsulation layer includes: First inorganic layer; A second inorganic layer is disposed on the first inorganic layer; and An organic layer is disposed between the first inorganic layer and the second inorganic layer. The first inorganic layer does not overlap with the central region, while the second inorganic layer overlaps with the central region.

10. The display device according to claim 8, further comprising a window disposed on the encapsulation layer, in, The window includes: The window substrate includes a window module region that overlaps with the panel module region in the plan view; and The light-blocking layer is disposed on one surface of the window substrate in the window module region.

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