Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are provided, the display device including: a substrate; a first bank pattern and a second bank pattern on the substrate and spaced apart from each other; a first electrode on the first bank pattern and a second electrode on the second bank pattern; a light emitting element between the first bank pattern and the second bank pattern; an insulating pattern on the light emitting element and exposing a first end and a second end of the light emitting element adjacent to the first bank pattern and the second bank pattern, respectively; a third electrode contacting the first electrode and the first end of the light emitting element; and a fourth electrode contacting the second electrode and the second end of the light emitting element, wherein a thickness of the insulating pattern is in a range of about 50% to about 150% of a thickness of the first bank pattern.

Description

Technical Field

[0001] Some embodiments of this disclosure relate to a display device and a method of manufacturing the same. Background Technology

[0002] Light-emitting diodes (LEDs) can exhibit relatively good durability even in harsh environments, and can have excellent performance in terms of lifespan and brightness.

[0003] To apply light-emitting diodes (LEDs) to lighting or display devices, the LEDs can be adapted to be connected to electrodes capable of applying power to them. The arrangement between the LEDs and electrodes has been studied in various ways, taking into account the intended use, minimizing the space occupied by the electrodes, manufacturing methods, and / or driving methods. Summary of the Invention

[0004] Some embodiments of this disclosure provide a display device and a method thereof formed by a simple manufacturing process by reducing the number of masks.

[0005] A display device according to some embodiments of the present disclosure includes: a substrate; a first dam pattern and a second dam pattern, on the substrate and spaced apart from each other; a first electrode and a second electrode, the first electrode being on the first dam pattern and the second electrode being on the second dam pattern; a light-emitting element, between the first dam pattern and the second dam pattern; an insulating pattern on the light-emitting element, exposing a first end and a second end of the light-emitting element adjacent to the first dam pattern and the second dam pattern, respectively; a third electrode, contacting the first electrode and the first end of the light-emitting element; and a fourth electrode, contacting the second electrode and the second end of the light-emitting element, wherein the thickness of the insulating pattern is in the range of about 50% to about 150% of the thickness of the first dam pattern.

[0006] The third and fourth electrodes can be made of the same material and can be formed on the same layer.

[0007] The maximum height of the upper surface of the insulating pattern relative to the substrate can be greater than or equal to the height of the upper surface of the first or second dam pattern.

[0008] The maximum height of the upper surface of the insulating pattern relative to the substrate can be equal to the height of the upper surface of the first dam pattern.

[0009] The insulating pattern may include side surfaces facing the first electrode and the second electrode respectively, and an upper surface between the side surfaces, wherein the third electrode does not overlap with the upper surface of the insulating pattern.

[0010] The first embankment pattern may include a first side surface facing the first end of the light-emitting element and an upper surface parallel to the upper surface of the substrate, wherein the third electrode is on the first side surface of the first embankment pattern.

[0011] The third electrode may not be superimposed on the upper surface of the first embankment pattern.

[0012] The display device may further include: a dummy electrode, spaced apart from the third electrode and contacting a second side surface of the first embankment pattern facing a first side surface of the first embankment pattern; and a fifth electrode, on a side surface of the second embankment pattern and spaced apart from the fourth electrode.

[0013] The height of one end of the third electrode that contacts the first end of the light-emitting element relative to the substrate can be equal to the height of the other end of the third electrode that contacts the first electrode.

[0014] In a planar diagram, the distance between the third and fourth electrodes can vary in the directions in which the third and fourth electrodes extend.

[0015] The distance between the third and fourth electrodes in the overlapping portion with the light-emitting element can be greater than the distance between the third and fourth electrodes in the non-overlapping portion without the light-emitting element.

[0016] Relative to the substrate, the height of the upper surface of the insulating pattern superimposed on the light-emitting element can be equal to the maximum height of the upper surface of the first electrode, and the height of the upper surface of the insulating pattern not superimposed on the light-emitting element can be approximately equal to the height of the upper surface of the first embankment pattern.

[0017] The height of the upper surface of the insulating pattern relative to the substrate can be greater than the maximum height of the upper surface of the first electrode.

[0018] The first dam pattern may include an upper surface parallel to the upper surface of the substrate, wherein the third electrode is not superimposed on the upper surface of the first dam pattern.

[0019] The display device may further include a pixel circuit layer between the substrate and the first embankment pattern and include at least one transistor electrically connected to the first electrode or the second electrode.

[0020] The first dam pattern may directly cover one of the source electrode and the drain electrode of at least one transistor, wherein the source electrode and the drain electrode are connected to a first electrode or a second electrode through a contact hole in the first dam pattern.

[0021] A method for manufacturing a display device according to some embodiments of the present disclosure includes the following steps: forming a spaced-apart first dam pattern and a second dam pattern on a substrate; forming a first electrode and a second electrode on the first dam pattern and the second dam pattern, respectively; aligning a light-emitting element between the first dam pattern and the second dam pattern; forming an insulating pattern on the light-emitting element exposing a first end and a second end of the light-emitting element, the first end and the second end being adjacent to the first dam pattern and the second dam pattern, respectively; forming an electrode layer on the substrate covering the first electrode, the second electrode and the insulating pattern; forming a photoresist on the electrode layer; and forming a third electrode and a fourth electrode by removing at least a portion of the photoresist and a first portion of the electrode layer overlapping the insulating pattern using an etching technique.

[0022] The thickness of the insulating pattern can be in the range of about 50% to about 150% of the thickness of the first dike pattern.

[0023] The steps of forming the third and fourth electrodes may include: forming a dummy electrode from the electrode layer by removing the portion of the electrode layer that overlaps with the first embankment pattern, the dummy electrode being spaced apart from the third electrode.

[0024] The height of the upper surface of the insulating pattern relative to the substrate can be greater than the maximum height of the upper surface of the first electrode.

[0025] In a display device according to some embodiments of the present disclosure, the thickness of the second insulating layer (or insulating pattern) located on the light-emitting element can range from about 50% to about 150% of the thickness of the embankment pattern. The height of the upper surface of the second insulating layer relative to the substrate can be greater than or approximately equal to the height of the upper surface of the embankment pattern. Therefore, the first contact electrode and the second contact electrode can be formed substantially simultaneously or concurrently by a single etching process without the need for separate masks (and without the need for exposure or photolithography processes).

[0026] Furthermore, the manufacturing method of the display device according to some embodiments of this disclosure can form a first contact electrode (or a third electrode) and a second contact electrode (or a fourth electrode) substantially simultaneously or concurrently from the contact electrode layer by forming a photoresist on the contact electrode layer and removing a portion of the photoresist and a portion of the contact electrode layer (e.g., the portion superimposed with the second insulating layer) by dry etching. Therefore, the number of masks used in the manufacturing process can be reduced, thereby simplifying the manufacturing process of the display device. Attached Figure Description

[0027] Figure 1A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure.

[0028] Figure 1B yes Figure 1A A cross-sectional view of the light-emitting element.

[0029] Figure 2A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure.

[0030] Figure 2B yes Figure 2A A cross-sectional view of the light-emitting element.

[0031] Figure 3A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure.

[0032] Figure 3B yes Figure 3A A cross-sectional view of the light-emitting element.

[0033] Figure 4A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure.

[0034] Figure 4B yes Figure 4A A cross-sectional view of the light-emitting element.

[0035] Figure 5 This is a top plan view illustrating a display device according to some embodiments of the present disclosure.

[0036] Figures 6A to 6E It is shown that it includes Figure 5 A circuit diagram of an example pixel in a display device.

[0037] Figure 7A and Figure 7B It is shown that it includes Figure 5 Circuit diagrams of other examples of pixels in a display device.

[0038] Figure 8 It is shown that it includes Figure 5 A top view of an example of pixels in a display device.

[0039] Figure 9 It shows along Figure 8 A cross-sectional view of an example of pixels captured by line I-I'.

[0040] Figure 10 yes Figure 9 An enlarged sectional view of region Q2.

[0041] Figure 11A It is magnification Figure 8 Top view of region Q1.

[0042] Figure 11B It shows along Figure 11A A cross-sectional view of an example of pixels captured by line II-II'.

[0043] Figures 12 to 14 It shows along Figure 8 Another example of a cross-sectional view of the pixels intercepted by the line I-I'.

[0044] Figures 15A to 15H This is a cross-sectional view showing a method of manufacturing a display device according to some embodiments of the present disclosure.

[0045] Figure 16 It is shown that it includes Figure 5 A top view of an example of pixels in a display device.

[0046] Figure 17 It shows along Figure 16 A cross-sectional view of an example of pixels captured by line III-III'.

[0047] Figures 18A to 18C This is a cross-sectional view showing a method of manufacturing a display device according to some embodiments of the present disclosure. Detailed Implementation

[0048] The features of the inventive concept and methods of carrying out the inventive concept can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different ways and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and these embodiments will fully convey to those skilled in the art aspects and features of the inventive concept. Therefore, processes, elements, and techniques that are not essential for those skilled in the art to fully understand the aspects and features of the inventive concept are not described.

[0049] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the accompanying drawings and written description, and therefore their description will not be repeated. Furthermore, for clarity, parts unrelated to the description of the embodiments may not be shown. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity.

[0050] Various embodiments are described herein with reference to sectional views that serve as schematic illustrations and / or intermediate structures. Thus, variations in the shape of the illustrations, for example, due to manufacturing techniques and / or tolerances, will be anticipated. Furthermore, for the purpose of describing embodiments according to the concept of this disclosure, the specific structural and functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as limited to the shape of the specifically shown areas, but will include deviations in shape due to, for example, manufacturing processes.

[0051] For example, an injection region shown as rectangular will typically have chamfered or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from an injection region to a non-injection region. Similarly, a buried region formed by injection can cause some injection in the area between the buried region and the surface through which the injection occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the areas of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of this disclosure.

[0052] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0053] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0054] For ease of explanation, spatial relative terms such as “below,” “under,” “down,” “below,” “above,” “above,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will then be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged “above” a second component, this means that the first component is arranged above or below the second component based on the direction of gravity, and not limited to its upper side.

[0055] Furthermore, in this specification, the phrase "in a plane" or "plan view" refers to the target portion viewed from above, and the phrase "in a cross-section" refers to the cross-section formed by vertically cutting the target portion viewed from the side.

[0056] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "bonded to" another element, layer, region, or component, that element, layer, region, or component may be directly formed on, connected to, or bonded to the other element, layer, region, or component, or indirectly formed on, connected to, or bonded to the other element, layer, region, or component, such that one or more intermediate elements, intermediate layers, intermediate regions, or intermediate components may exist. However, "directly connected / directly bonded" refers to a component being directly connected to or bonded to another component without any intermediate components. Similarly, other expressions describing relationships between components, such as "between," "directly between," or "proximately" and "directly proximate," can be interpreted in a similar manner. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intermediate elements or layers.

[0057] For the purposes of this disclosure, when a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements without modifying any individual elements within the list. For example, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ), or any variations thereof. Similarly, a statement such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any combination and all combinations of one or more of the associated listed items. For example, a statement such as “A and / or B” can include A, B, or A and B.

[0058] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. Unless the context clearly indicates otherwise, the singular form “a” as used herein is intended to include the plural form as well. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0060] As used herein, the terms “substantially,” “approximately,” and other similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Taking into account the measurement being discussed and the errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), “approximately” or “approximately” as used herein includes the stated value and indicates a range of acceptable deviations from the specific value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” indicates “one or more embodiments of this disclosure.”

[0061] When one or more embodiments can be implemented differently, the specific process sequence may be performed in a sequence different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0062] Furthermore, any numerical range disclosed and / or recorded herein is intended to include all subranges with the same numerical precision within the recorded range. For example, the range “1.0 to 10.0” is intended to include all subranges between the recorded minimum value of 1.0 and the recorded maximum value of 10.0 (and includes both the recorded minimum value of 1.0 and the recorded maximum value of 10.0), i.e., all subranges having a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10.0, such as 2.4 to 7.6. Any maximum numerical limit recorded herein is intended to include all lower numerical limits contained therein, while any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly record any subranges included within the range expressly recorded herein.

[0063] The electronic devices or electronic apparatuses and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0064] Furthermore, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0065] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as having an idealized or overly formal meaning, unless expressly defined herein.

[0066] Figure 1A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure. Figure 1B yes Figure 1A A cross-sectional view of the light-emitting element. Figure 2A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure. Figure 2B yes Figure 2A A cross-sectional view of the light-emitting element. Figure 3A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure. Figure 3B yes Figure 3A A cross-sectional view of the light-emitting element. Figure 4A This is a diagram illustrating a light-emitting element according to some embodiments of the present disclosure. Figure 4B yes Figure 4A A cross-sectional view of the light-emitting element.

[0067] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A and Figure 3B A light-emitting element manufactured using an etching technique is shown and described below. Figure 4A and Figure 4B A light-emitting element manufactured by a growth method is shown and will be described thereafter. The type and / or shape of the light-emitting element are not limited to... Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B The embodiments shown are illustrated in the figure.

[0068] First, refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A and Figure 3B The light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as a light-emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0069] In some embodiments, the light-emitting element (LD) may have a shape extending in one direction. If the extension direction / elongation direction of the light-emitting element (LD) is referred to as the length direction, the light-emitting element (LD) may have opposite ends extending in the extension direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at one end of the light-emitting element (LD), and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the other end of the light-emitting element (LD).

[0070] Light-emitting elements (LDs) can have various shapes. For example, an LD can have a longer rod-like or strip-like shape in its length direction (e.g., it can have an aspect ratio greater than 1). For example, the length L of the LD in its length direction can be larger than its diameter D (or it can be larger than the width of its cross-section). LDs can include light-emitting diodes manufactured in ultra-small sizes to have a diameter D and / or a length L on the micrometer or nanometer scale. The dimensions of the LD can be varied so that it can meet the suitable conditions / design requirements of the corresponding lighting device or self-emissive display device.

[0071] The first semiconductor layer 11 may include at least one N-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an N-type semiconductor layer doped with a first conductive dopant such as Si, Ge, Sn, etc. However, the materials constituting the first semiconductor layer 11 are not limited to these, and various other materials may constitute the first semiconductor layer 11.

[0072] The active layer 12 may be located on the first semiconductor layer 11 and may be formed as a single quantum well structure or a multiple quantum well structure. The position of the active layer 12 may vary depending on the type of light-emitting element (LD). The active layer 12 may emit light with a wavelength of about 400 nm to about 900 nm and may use a dual heterostructure. In some embodiments, a capping layer doped with a conductive dopant may be formed on the upper and / or lower portion of the active layer 12. For example, the capping layer may be formed of an AlGaN layer or an InAlGaN layer. According to some embodiments, materials such as AlGaN, InAlGaN, etc., may be used to form the active layer 12, and various materials may constitute the active layer 12.

[0073] When an electric field with a voltage (e.g., a predetermined voltage or higher) is applied across the light-emitting element LD, the LD emits light while electron-hole pairs combine in the active layer 12. By controlling the light emission of the LD using this principle, the LD can be used as a light source for pixels in various light-emitting devices and display devices.

[0074] The second semiconductor layer 13 may be located on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. The second semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor layer doped with a second conductive dopant such as Mg. However, the materials constituting the second semiconductor layer 13 are not limited to these, and various other materials may constitute the second semiconductor layer 13.

[0075] In some embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) along the length of the light-emitting element LD. For example, along the length of the light-emitting element LD, the first semiconductor layer 11 may have a width wider than the second semiconductor layer 13 (or a thickness thicker than the second semiconductor layer 13). Therefore, as... Figures 1A to 3BAs shown, compared to the lower surface of the first semiconductor layer 11, the active layer 12 of the light-emitting element LD can be closer to the upper surface of the second semiconductor layer 13.

[0076] In some embodiments, in addition to the first semiconductor layer 11, active layer 12, and second semiconductor layer 13 described above, the light-emitting element LD may further include an additional electrode 15 located on the second semiconductor layer 13. Furthermore, according to some embodiments, such as... Figure 3A and Figure 3B As shown, the light-emitting element LD may also include another additional electrode 16 located at one end of the first semiconductor layer 11.

[0077] The additional electrodes 15 and 16 may be ohmic contact electrodes, but are not limited thereto, and according to some embodiments may be Schottky contact electrodes. The additional electrodes 15 and 16 may comprise, individually or in combination, metals or metal oxides (e.g., chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) and their oxides or alloys, and ITO), but this disclosure is not limited thereto.

[0078] The materials included in each of the additional electrodes 15 and 16 may be the same or different from each other. The additional electrodes 15 and 16 may be substantially transparent or translucent. Therefore, light generated by the light-emitting element LD can be transmitted through the additional electrodes 15 and 16 to be emitted to the outside of the light-emitting element LD. According to some embodiments, the additional electrodes 15 and 16 may include opaque metal, wherein light generated from the light-emitting element LD is emitted to the outside of the light-emitting element LD through a region other than the two ends of the light-emitting element LD, and does not pass through the additional electrodes 15 and 16.

[0079] In some embodiments, the light-emitting element LD may further include an insulating film 14. However, according to some embodiments, the insulating film 14 may be omitted, or the insulating film 14 may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0080] The insulating film 14 can reduce or prevent electrical short circuits that might occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, by forming the insulating film 14, surface defects of the light-emitting element LD can be reduced or minimized, thereby improving lifetime and efficiency. Additionally, when multiple light-emitting elements LD are closely positioned, the insulating film 14 can reduce or prevent unwanted short circuits that might occur between the light-emitting elements LD. In some embodiments, short circuits between the active layer 12 and external conductive materials can be prevented regardless of whether the insulating film 14 is provided.

[0081] like Figure 1A and Figure 1B As shown, the insulating film 14 can be arranged to completely surround the outer peripheral surface of the light-emitting stacked member comprising the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. For better understanding and ease of description, Figure 1A The diagram shows a state in which a portion of the insulating film 14 is removed, and in which the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 in the actual light-emitting element LD can be surrounded by the insulating film 14.

[0082] The insulating film 14 may have the form of completely surrounding the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15, but this disclosure is not limited thereto.

[0083] According to some embodiments, such as Figure 2A and Figure 2B As shown, the insulating film 14 may surround the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but not entirely surround the outer peripheral surface of the additional electrode 15 located on the second semiconductor layer 13. Optionally, the insulating film 14 may surround only a portion of the outer peripheral surface of the additional electrode 15 and not the remaining portion. However, the insulating film 14 may expose both ends of the light-emitting element LD. For example, in addition to the additional electrode 15 located on one side of the second semiconductor layer 13, the insulating film 14 may also expose one end of the first semiconductor layer 11. Furthermore, according to some embodiments, such as... Figure 3A and Figure 3B As shown, when the additional electrodes 15 and 16 are located at the respective ends of the light-emitting element LD, the insulating film 14 can expose at least one area of ​​each of the additional electrodes 15 and 16. Alternatively, in other embodiments, the insulating film 14 may be omitted.

[0084] According to some embodiments of this disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include at least one insulating material selected from the group consisting of SiO2, Si3N4, Al2O3 and TiO2, but is not limited thereto, and may include various materials having insulating properties.

[0085] When an insulating film 14 is provided for the light-emitting element LD, the possibility of a short circuit between the active layer 12 and the first electrode and / or the second electrode can be reduced, or a short circuit between the active layer 12 and the first electrode and / or the second electrode can be prevented. Furthermore, by forming the insulating film 14, surface defects of the light-emitting element LD can be reduced or minimized, thereby improving lifespan and efficiency. Additionally, when multiple light-emitting elements LD are closely positioned, the insulating film 14 can reduce or prevent unwanted short circuits that might otherwise occur between the light-emitting elements LD.

[0086] Light-emitting elements (LDs) can be used as light sources for various display devices. LDs can be manufactured using surface treatment processes. For example, when multiple LDs are mixed with a flowing solution or solvent and supplied to each light-emitting area (e.g., to the light-emitting area of ​​each pixel or subpixel), each LD can be surface-treated so that it can be uniformly sprayed without unevenly agglomerating in the solution.

[0087] Light-emitting devices, including light-emitting elements (LDs), can be used in various types of devices (including display devices) that require a light source. For example, when multiple light-emitting elements (LDs) are positioned in the light-emitting area of ​​each pixel of a display panel, the LDs can serve as the light source for each pixel. However, the applications of LDs are not limited to the embodiments described above. For example, LDs can also be used in other types of devices that require a light source (such as lighting devices).

[0088] Next, refer to Figure 4A and Figure 4B This will describe a light-emitting element (LD) manufactured by a growth method.

[0089] In the description of the light-emitting element LD manufactured by the growth method, the differences from the previously described embodiments will be focused on, and the parts of the light-emitting element LD manufactured by the growth method that are not specifically described are consistent with the embodiments described above.

[0090] Reference Figure 4A and Figure 4B According to some embodiments of the present disclosure, the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to some embodiments, the light-emitting element LD may include a core-shell structured light-emitting pattern 10, which may have: a first semiconductor layer 11 located at the center; an active layer 12 surrounding at least one side or a portion of the first semiconductor layer 11; a second semiconductor layer 13 surrounding at least one side or a portion of the active layer 12; and an additional electrode 15 surrounding at least one side or a portion of the second semiconductor layer 13.

[0091] The light-emitting element (LD) can be arranged in a polygonal horn shape extending in one direction. For example, the LD can be arranged in a hexagonal horn shape. When the direction of extension of the LD is referred to as the length direction, the LD can have one end (e.g., the lower end) and another end (e.g., the upper end) in the length direction. At one end of the LD (e.g., at the lower end), a portion of one of the first semiconductor layer 11 and the second semiconductor layer 13 can be exposed, and at the other end of the LD (e.g., at the upper end), a portion of the other semiconductor layer 11 and the second semiconductor layer 13 can be exposed. For example, a portion of the first semiconductor layer 11 can be exposed at one end of the LD (e.g., the lower end), and a portion of the second semiconductor layer 13 can be exposed at the other end of the LD (e.g., the upper end). In this case, when the LD is used as a light source for a display device, the exposed portion of the first semiconductor layer 11 can contact one of the driving electrodes used to drive the LD, and the exposed portion of the second semiconductor layer 13 can contact the other driving electrode.

[0092] According to some embodiments, when the light-emitting element LD includes an additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 may be exposed at the other end (e.g., the upper end) of the light-emitting element LD. In this case, when the light-emitting element LD is used as a light source for a display device, the exposed portion of the additional electrode 15 may contact another driving electrode for electrical connection to an electrode.

[0093] In some embodiments, the first semiconductor layer 11 may be located at the core or center of the light-emitting element LD. The light-emitting element LD may be configured with a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal horn shape, the light-emitting element LD and the light-emitting pattern 10 may also have a hexagonal horn shape.

[0094] The active layer 12 may be disposed and / or formed to surround the outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD. For example, the active layer 12 may be disposed and / or formed to surround the region other than one end (e.g., the lower side) of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD.

[0095] The second semiconductor layer 13 may be disposed and / or formed to surround the active layer 12 along the length of the light-emitting element LD, and may include semiconductor layers of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer.

[0096] In some embodiments, the light-emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be a Schottky contact electrode or an ohmic contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto.

[0097] As described above, the light-emitting element (LD) can be implemented as a hexagonal horn shape with protruding ends, and can be implemented as a core-shell structure light-emitting pattern 10 including a first semiconductor layer 11 at its center, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 can be located at one end (or the lower end) of the light-emitting element LD with the hexagonal horn shape, and the additional electrode 15 can be located at the other end (or the upper end) of the light-emitting element LD.

[0098] Additionally, according to some embodiments, the light-emitting element LD may also include an insulating film 14 disposed on the outer peripheral surface of the light-emitting pattern 10 having a core-shell structure. The insulating film 14 may include a transparent insulating material.

[0099] Figure 5 This is a top plan view illustrating a display device according to some embodiments of the present disclosure. Figure 5 Is using Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B A schematic top view of a display device in which one of the light-emitting elements is used as the light source.

[0100] exist Figure 5 For better understanding and ease of description, the structure of the display device is briefly shown with the display area for displaying the image as the center. However, according to some embodiments, at least one driver (e.g., scan driver, data driver, etc.) and / or multiple signal lines may be further arranged in the display device.

[0101] Reference Figures 1A to 5 The display device according to some embodiments of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and including at least one light-emitting element LD, a driver disposed on the substrate SUB and driving the pixels PXL, and a line unit for connecting the pixels PXL to the driver.

[0102] Depending on the method of driving the light-emitting element (LD), the display device can be classified as a passive matrix type display device or an active matrix type display device. For example, when the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light-emitting element (LD), and may include a switching transistor that transmits data signals to the driving transistor.

[0103] Considering resolution, contrast ratio, and operating speed, active matrix display devices in which each pixel PXL is selected and turned on or off have become mainstream, but this disclosure is not limited thereto. Passive matrix display devices in which each group of pixels PXL is turned on or off can also use constituent elements (e.g., first electrode and second electrode) for driving light-emitting elements LD.

[0104] The base SUB can include the display area DA and the non-display area NDA.

[0105] According to some embodiments, the display area DA can be located in the central area of ​​the display device, and the non-display area NDA can be located in the edge area of ​​the display device, surrounding the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited to this, and their positions can be changed.

[0106] The display area DA can be an area in which pixels PXL for displaying images are configured. The non-display area NDA can be an area in which drivers for driving pixels PXL are configured, as well as a portion of the line unit that connects pixels PXL to the drivers.

[0107] The display area DA can have various shapes. For example, the display area DA can be set as a closed polygon including sides containing straight lines. Alternatively, the display area DA can be set as a circular shape and / or an elliptical shape including sides containing curves. In addition, the display area DA can be set as various shapes such as a semicircle or a semi-ellipse including sides containing straight lines and / or curves.

[0108] The non-display area NDA can be disposed on at least one side of the display area DA. In some embodiments of this disclosure, the non-display area NDA can surround the periphery or edge of the display area DA.

[0109] In the non-display area NDA, a first line unit connected to pixel PXL and a second line unit connected to the first line unit and connected to the driver used to drive pixel PXL can be configured.

[0110] Line units can electrically connect the driver to the pixel PXL. A line unit can be a signal line connected to each pixel PXL and a fan-out line connected to each pixel PXL; these signal lines can be scan lines, data lines, light control lines, etc.

[0111] The substrate SUB can include a transparent insulating material and can transmit light. The substrate SUB can be a rigid substrate or a flexible substrate.

[0112] One region on the base SUB can be set as a display region DA, allowing pixel PXL to reside thereon, and the remaining region on the base SUB can be set as a non-display region NDA. For example, the base SUB may include a display region DA and a non-display region NDA surrounding the display region DA, where the display region DA includes the pixel region in which each pixel PXL resides.

[0113] Each of the pixels PXL can be disposed on the substrate SUB in the display area DA. In some embodiments of this disclosure, the pixels PXL can be arranged in the display area DA in a stripe or pentile arrangement, but this disclosure is not limited thereto.

[0114] Each pixel PXL may include at least one light-emitting element (LD) driven by corresponding scan signals and data signals. The LD may have dimensions as small as micrometers or nanometers and may be connected in parallel with adjacent LDs, but this disclosure is not limited thereto. The LD may be the light source for each pixel PXL.

[0115] Each pixel PXL may include at least one light source driven by corresponding signals (e.g., scan signals and data signals) and / or by power sources (e.g., a first driving power source and a second driving power source). For example, each pixel PXL may include Figures 1A to 4B One of the light-emitting elements (LDs) shown may, for example, include at least one ultra-small light-emitting element (LD) having a size on the order of nanometers to micrometers. However, the types of light-emitting element (LDs) that can be used as a light source for each pixel PXL are not limited to this.

[0116] In some embodiments of this disclosure, the color, type, and / or number of pixels PXL are not specifically limited. For example, the color of light emitted from each pixel PXL can be varied.

[0117] The driver can control the driving of the pixel PXL by providing signals and power (e.g., predetermined signals and predetermined power) to each pixel PXL through line units.

[0118] The driver may include a scan driver that provides scan signals to pixel PXL via scan lines, an optical emission driver that provides optical emission control signals to pixel PXL via optical emission control lines, a data driver that provides data signals to pixel PXL via data lines, and a timing controller. The timing controller can control the scan driver, the optical emission driver, and the data driver.

[0119] Figures 6A to 6E All are shown as included Figure 5 A circuit diagram of an example pixel in a display device. Figures 6A to 6E The diagram illustrates electrical connections of constituent elements included in a pixel PXL, which can be applied to an active display device, according to some embodiments. However, the types of constituent elements included in the pixel PXL are not limited thereto.

[0120] exist Figures 6A to 6E In, the area where the constituent elements are provided and including Figure 5 Each of the constituent elements in the pixels PXL shown is referred to as a pixel PXL. According to some embodiments, Figures 6A to 6E Each pixel PXL shown can be set in the PXL position. Figure 5 Any one of the pixels PXL in the display device, and the pixels PXL may have substantially the same or similar structure to each other.

[0121] Reference Figures 1A to 6E A pixel PXL (hereinafter referred to as a 'pixel') may include a light-emitting unit EMU that generates light with a brightness corresponding to the data signal. Additionally, the pixel PXL may also include a pixel driving circuit PXC for driving the light-emitting unit EMU.

[0122] According to some embodiments, the light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in parallel between a first power line PL1 and a second power line PL2, with a first driving power supply VDD applied to the first power line PL1 and a second driving power supply VSS applied to the second power line PL2. For example, the EMU may include a first electrode ELT1 (or a first alignment electrode) connected to the first driving power supply VDD via a pixel driving circuit PXC and the first power line PL1, a second electrode ELT2 (or a second alignment electrode) connected to the second driving power supply VSS via the second power line PL2, and a plurality of light-emitting elements (LDs) connected in parallel between the first electrode ELT1 and the second electrode ELT2 and arranged in the same direction. In some embodiments of this disclosure, the first electrode ELT1 may be an anode, and the second electrode ELT2 may be a cathode.

[0123] In some embodiments of this disclosure, each of the light-emitting elements (LDs) included in the light-emitting unit (EMU) may include a first terminal connected to a first driving power supply VDD via a first electrode ELT1 and a second terminal connected to a second driving power supply VSS via a second electrode ELT2. The first driving power supply VDD and the second driving power supply VSS may have different voltage potentials than each other. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. In this case, during the light-emitting period of pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to the threshold voltage of the light-emitting element LD or a higher voltage.

[0124] As described above, each light-emitting element LD, connected in parallel with each other between a first electrode ELT1 and a second electrode ELT2 supplied with voltages of different potentials and in the same direction (e.g., in the forward direction), can constitute each effective light source. These effective light sources can be grouped to form the light-emitting unit EMU of pixel PXL.

[0125] The light-emitting elements (LDs) of the light-emitting unit (EMU) can emit light with a brightness corresponding to the driving current supplied through the corresponding pixel driving circuit (PXC). For example, during each frame period, the pixel driving circuit (PXC) can supply the light-emitting unit (EMU) with a driving current corresponding to the grayscale value of the corresponding frame data. The driving current supplied to the light-emitting unit (EMU) can flow through the light-emitting elements (LDs) connected in the same direction. Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing therein, the light-emitting unit (EMU) can collectively emit light with a brightness corresponding to the driving current.

[0126] At the same time, Figures 6A to 6E The illustration shows an embodiment in which light-emitting elements (LDs) are connected to each other in the same direction between a first driving power supply VDD and a second driving power supply VSS, but this disclosure is not limited thereto. According to some embodiments, in addition to the light-emitting elements (LDs) constituting each effective light source, the light-emitting unit (EMU) may also include at least one ineffective light source. For example, as... Figure 6D and Figure 6E As shown, a reverse light-emitting element LDr can be further connected between the first electrode ELT1 and the second electrode ELT2 of the light-emitting unit (EMU). The reverse light-emitting element LDr can be connected in parallel with the light-emitting element LD, which constitutes the effective light source, between the first electrode ELT1 and the second electrode ELT2, but it can also be connected in the opposite direction to the light-emitting element LD. Even when a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode ELT1 and the second electrode ELT2, the reverse light-emitting element LDr can remain in an inactive state, such that current substantially does not flow through the reverse light-emitting element LDr.

[0127] The pixel driving circuit PXC can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, when pixel PXL is located in the i-th row (i is a natural number) and j-th column (j is a natural number) of display area DA, the pixel driving circuit PXC of pixel PXL can be connected to the i-th scan line Si and j-th data line Dj of display area DA. According to some embodiments, such as Figure 6A and Figure 6B As shown, the pixel driving circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. However, the structure of the pixel driving circuit PXC is not limited to... Figure 6A and Figure 6B The structure shown.

[0128] First, refer to Figure 6A The pixel driving circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0129] The first terminal of the second transistor T2 (switching transistor) can be connected to the data line Dj, and the second terminal of the second transistor T2 can be connected to the first node N1. Here, the first and second terminals of the second transistor T2 can be different terminals. For example, when the first terminal is the source electrode, the second terminal can be the drain electrode. Then, the gate electrode of the second transistor T2 can be connected to the scan line Si.

[0130] The second transistor T2 can be turned on when a scan signal of a voltage (e.g., a low voltage) that enables the second transistor T2 to conduct is supplied from the scan line Si, thereby electrically connecting the data line Dj to the first node N1. At this time, the data signal corresponding to the frame is supplied to the data line Dj, and therefore, the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 charges the storage capacitor Cst.

[0131] The first terminal of the first transistor T1 (or driving transistor) can be connected to the first driving power supply VDD, and the second terminal of the first transistor T1 can be electrically connected to the first electrode ELT1 of each of the light-emitting elements LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0132] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the other electrode of the storage capacitor Cst can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1, and can maintain the charged voltage until the data signal of the next frame is supplied.

[0133] Figure 6A and Figure 6B Each of the figures shows a pixel driving circuit PXC including a second transistor T2 for transmitting data signals to the pixel PXL, a storage capacitor Cst for storing the data signals, and a first transistor T1 for supplying a driving current corresponding to the data signals to the light-emitting element LD.

[0134] However, this disclosure is not limited thereto, and the structure of the pixel driving circuit PXC can be modified in various ways. For example, the pixel driving circuit PXC may also include at least one transistor element such as a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light-emitting element LD, and / or may also include other circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0135] In addition, Figure 6A In this embodiment, the transistors included in the pixel driving circuit PXC (e.g., the first transistor T1 and the second transistor T2) are shown as P-type transistors, but this disclosure is not limited thereto. That is, in other embodiments, at least one of the first transistor T1 and the second transistor T2 included in the pixel driving circuit PXC may be changed to an N-type transistor.

[0136] Next, refer to Figures 1A to 6B According to some embodiments of this disclosure, the first transistor T1 and the second transistor T2 can be implemented as N-type transistors. Aside from changes in the connection positions of some constituent elements due to the change in transistor type, Figure 6B The pixel driving circuit PXC shown can have the same characteristics as... Figure 6A The pixel driving circuit of PXC has a roughly similar construction or operation. Therefore, a brief description is provided below.

[0137] In some embodiments of this disclosure, Figure 6B The pixel driving circuit PXC shown may include a first transistor T1 and a second transistor T2 as N-type transistors, and may also include a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are N-type transistors, the light-emitting unit EMU may be connected between the first driving power supply VDD and the pixel driving circuit PXC to stabilize the storage capacitor Cst, which is charged with a voltage corresponding to the data signal supplied to the first node N1. However, this disclosure is not limited thereto; according to some embodiments, Figure 6A The light-emitting unit (EMU) shown can be connected between the pixel driving circuit (PXC) and the second driving power supply (VSS). In some embodiments of this disclosure, the structure of the pixel driving circuit (PXC) is not limited to... Figure 6A and Figure 6BThe construction shown is illustrated. For example, the pixel driving circuit PXC can be as follows: Figure 6C and Figure 6D The landform shown.

[0138] like Figure 6C and Figure 6D As shown, the pixel driving circuit PXC can be connected to the scan line Si and data line Dj of the pixel PXL. For example, when the pixel PXL is located in the i-th row and j-th column of the display area DA, the pixel driving circuit PXC of the pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0139] Furthermore, according to some embodiments, the pixel driving circuit PXC can also be connected to at least one other scan line. For example, a pixel PXL located in the i-th row of the display area DA can be further connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. Additionally, according to some embodiments, besides the first driving power supply VDD and the second driving power supply VSS, the pixel driving circuit PXC can also be connected to a third power supply. For example, the pixel driving circuit PXC can be connected to the initialization power supply Vint.

[0140] The pixel driving circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0141] One electrode (e.g., the source electrode) of the first transistor T1 (or driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and the other electrode (e.g., the drain electrode) of the first transistor T1 can be connected to one end of the light-emitting element LD via the sixth transistor T6. Furthermore, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls the driving current flowing through the light-emitting element LD between the first driving power supply VDD and the second driving power supply VSS in response to the voltage of the first node N1.

[0142] A second transistor T2 (or a switching transistor) can be connected between the source electrode of the first transistor T1 and the j-th data line Dj connected to the pixel PXL. Furthermore, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to the pixel PXL. The second transistor T2 can be turned on when a scan signal with a gate on-state voltage (e.g., a low voltage) is supplied from the i-th scan line Si, to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0143] The third transistor T3 can be connected between the first node N1 and the drain electrode of the first transistor T1. Furthermore, the gate electrode of the third transistor T3 can be connected to the i-th scan line Si. The third transistor T3 can be turned on when a scan signal supplying a gate on-state voltage from the i-th scan line Si is applied, thereby electrically connecting the first node N1 and the drain electrode of the first transistor T1.

[0144] The fourth transistor T4 can be connected between the first node N1 and the initialization power line to which the initialization power supply Vint is applied. Furthermore, the gate electrode of the fourth transistor T4 can be connected to the previous scan line, for example, the (i-1)th scan line Si-1. The fourth transistor T4 can be turned on when a scan signal supplies a gate-on voltage from the (i-1)th scan line Si-1 to transmit the voltage of the initialization power supply Vint to the first node N1. Here, the initialization power supply Vint can have a voltage less than or approximately equal to the lowest voltage of the data signal.

[0145] The fifth transistor T5 can be connected between the first drive power supply VDD and the first transistor T1. Furthermore, the gate electrode of the fifth transistor T5 can be connected to a corresponding light emission control line, such as the i-th light emission control line Ei. The fifth transistor T5 can be turned off when a light emission control signal with a gate cutoff voltage is supplied from the i-th light emission control line Ei, and can be turned on under other conditions.

[0146] The sixth transistor T6 can be connected between the first transistor T1 and one end of the light-emitting element LD (or the second node N2). Furthermore, the gate electrode of the sixth transistor T6 can be connected to the i-th light emission control line Ei. The sixth transistor T6 can be turned off when a light emission control signal with a gate cutoff voltage is supplied from the i-th light emission control line Ei, and can be turned on under other conditions.

[0147] The seventh transistor T7 can be connected between the initialization power line and one end of the light-emitting element LD. Furthermore, the gate electrode of the seventh transistor T7 can be connected to one of the scan lines in the next stage, for example, the (i+1)th scan line Si+1. The seventh transistor T7 can be turned on when a scan signal supplying a gate-on voltage from the (i+1)th scan line Si+1 is applied, and can supply the initialization power supply Vint voltage to one end of the light-emitting element LD.

[0148] A storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can store the data signal supplied to the first node N1 during each frame period and the voltage corresponding to the threshold voltage of the first transistor T1.

[0149] exist Figure 6C and Figure 6DIn this embodiment, the transistors included in the pixel driving circuit PXC (e.g., first transistor T1 to seventh transistor T7) are all shown as P-type transistors, but this disclosure is not limited thereto. For example, in other embodiments, at least one of the first transistor T1 to seventh transistor T7 may be changed to an N-type transistor.

[0150] In some embodiments of this disclosure, the construction of the pixel driving circuit PXC is not limited to... Figures 6A to 6D The construction shown is illustrated. For example, the pixel driving circuit PXC can be as follows: Figure 6E The landform shown.

[0151] like Figure 6E As shown, the pixel driving circuit PXC can also be connected to the control line CLI and the sensing line SENj. For example, the pixel driving circuit PXC of pixel PXL located in the i-th row and j-th column of display area DA can be connected to the i-th control line CLI and the j-th sensing line SENj of display area DA. Besides... Figure 6A and Figure 6B In addition to the first transistor T1 and the second transistor T2 shown, the pixel driving circuit PXC described above may also include a third transistor T3.

[0152] The third transistor T3 can be connected between the first transistor T1 and the sensing line SENj. For example, one electrode of the third transistor T3 can be connected to a terminal of the first transistor T1 connected to the first electrode ELT1 (e.g., the source electrode), and the other electrode of the third transistor T3 can be connected to the sensing line SENj. Alternatively, when the sensing line SENj is omitted, the other electrode of the third transistor T3 can be connected to the data line Dj. The pixel driving circuit PXC may also include a light-emitting element capacitor C. OLED Light-emitting element capacitor C OLED One electrode can be connected to the first electrode ELT1, and the other electrode can be connected to the second drive power supply VSS.

[0153] According to some embodiments, the gate electrode of the third transistor T3 can be connected to the control line CLI. On the other hand, when the control line CLI is omitted, the gate electrode of the third transistor T3 can be connected to the scan line Si. The third transistor T3 can be turned on by a control signal of a gate on-state voltage (e.g., a high level) supplied from the control line CLI during a predetermined sensing period to electrically connect the sensing line SENj to the first transistor T1.

[0154] According to some embodiments, the sensing period can be a period for extracting characteristic information (e.g., the threshold voltage of the first transistor T1) of each pixel PXL located in the display area DA. During the sensing period described above, the first transistor T1 can be turned on by supplying a voltage (e.g., a predetermined reference voltage that can turn on the first transistor T1) to the first node N1 via data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. Additionally, the first transistor T1 can be connected to the sensing line SENj by turning on the third transistor T3 by supplying a control signal to the third transistor T3 with a gate turn-on voltage. Therefore, characteristic information including the threshold voltage of the first transistor T1 for each pixel PXL can be extracted via the sensing line SENj described above. The extracted characteristic information can be used to transform image data so that characteristic deviations between pixels PXL can be compensated.

[0155] At the same time, Figure 6E The illustration shows an embodiment where the first transistor T1 through the third transistor T3 are all N-type transistors, but this disclosure is not limited thereto. For example, in other embodiments, at least one of the first transistor T1 through the third transistor T3 described above can be changed to a P-type transistor. Additionally, in Figure 6E The example disclosed shows that the light-emitting unit EMU is connected between the pixel driving circuit PXC and the second driving power supply VSS, but the light-emitting unit EMU can be connected between the first driving power supply VDD and the pixel driving circuit PXC.

[0156] In addition, Figures 6A to 6E The diagram shows all the light-emitting elements (LDs) constituting each light-emitting unit (EMU) connected in parallel, but this disclosure is not limited thereto. According to some embodiments, the EMU can be configured to include at least one series group comprising multiple light-emitting elements (LDs) connected in parallel with each other. That is, the EMU can be configured as a hybrid series / parallel structure. Reference will be made later. Figure 7A and Figure 7B The embodiments described above are described below.

[0157] The structures applicable to the pixel PXL of this disclosure are not limited to... Figures 6A to 6E The embodiments shown are illustrated, and the corresponding pixels can have various structures. Additionally, in other embodiments of this disclosure, each pixel PXL can be formed inside a passive light-emitting display device. In this case, the pixel driving circuit PXC can be omitted, and the two ends of the light-emitting element LD included in the light-emitting unit EMU can be directly connected to scan lines Si-1, Si and Si+1, data line Dj, a first power line PL1 with a first driving power supply VDD applied, a second power line PL2 with a second driving power supply VSS applied, and / or a predetermined control line.

[0158] Figures 7A to 7B It is shown that it includes Figure 5 Circuit diagrams of other examples of pixels in a display device. Figure 7A and Figure 7B In this context, the light-emitting unit (EMU) of each pixel PXL can be constructed as multiple cascaded groups connected continuously to each other. To avoid [further details in the description] Figure 7A and Figure 7B The embodiments are described repeatedly, and will omit the details. Figures 6A to 6E Repeated description of similar or identical constructions (e.g., pixel drive circuit PXC) in the embodiments.

[0159] First, refer to Figure 7A The light-emitting unit (EMU) may include multiple light-emitting elements connected in series with each other. For example, the EMU may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a fourth light-emitting element LD4 connected in series in the forward direction between a first driving power supply VDD and a second driving power supply VSS to form an effective light source. In the following examples, at least one of the first light-emitting elements LD1 to the fourth light-emitting element LD4 is arbitrarily referred to as a light-emitting element LD or multiple light-emitting elements LD, or the first light-emitting elements LD1 to the fourth light-emitting elements LD4 are generally referred to as light-emitting elements LD or multiple light-emitting elements LD.

[0160] One end of the first light-emitting element LD1 (e.g., the second semiconductor layer) can be connected to the first driving power supply VDD through the first electrode ELT1, and the other end of the first light-emitting element LD1 (e.g., the first semiconductor layer) can be connected to one end of the second light-emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 connected between the first series group and the second series group (e.g., between the first light-emitting element LD1 and the second light-emitting element LD2).

[0161] One end of the second light-emitting element LD2 can be connected to the first intermediate electrode CTE1, and the other end (e.g., the first semiconductor layer) can be connected to one end (e.g., the second semiconductor layer) of the third light-emitting element LD3 through the second intermediate electrode CTE2 connected between the second series group and the third series group (e.g., between the second light-emitting element LD2 and the third light-emitting element LD3).

[0162] One end of the third light-emitting element LD3 can be connected to the second intermediate electrode CTE2, and the other end (e.g., the first semiconductor layer) can be connected to one end (e.g., the second semiconductor layer) of the fourth light-emitting element LD4 through the third intermediate electrode CTE3 connected between the third series group and the fourth series group (e.g., between the third light-emitting element LD3 and the fourth light-emitting element LD4).

[0163] One end of the fourth light-emitting element LD4 can be connected to the third intermediate electrode CTE3, and the other end (e.g., the first semiconductor layer) can be connected to the second driving power supply VSS through the second electrode ELT2.

[0164] As described above, the first light-emitting element LD1 to the fourth light-emitting element LD4 can be connected in series between the first electrode ELT1 and the second electrode ELT2 of the light-emitting unit EMU of pixel PXL.

[0165] In a light-emitting unit (EMU) with a structure in which light-emitting elements (LDs) are connected in series (for example, compared to an EMU with a structure in which light-emitting elements (LDs) are connected in parallel), the voltage applied between the first electrode ELT1 and the second electrode ELT2 can be increased, and the magnitude of the drive current flowing through the EMU can be reduced. Therefore, when the EMU of each pixel PXL is configured as a series structure, the power consumption of the display device can be reduced.

[0166] According to some embodiments, at least one series group can be arranged in the form of multiple light-emitting elements (LDs) connected in parallel with each other. In this case, the light-emitting unit (EMU) of each pixel PXL can be configured as a hybrid series / parallel structure. For example, the light-emitting unit (EMU) can be as follows: Figure 7B The landform shown.

[0167] Next, refer to Figure 7B The light-emitting unit (EMU) of the pixel PXL may include multiple series groups (e.g., multiple groups connected in series, each group including multiple light-emitting elements connected in parallel), which are sequentially connected between a first driving power supply VDD and a second driving power supply VSS. Furthermore, each series group may include at least one light-emitting element LD connected in the forward direction between two electrodes of the electrode pair constituting the corresponding series group. For example, the light-emitting unit EMU may include a first series group SET1 to a third series group SET3 sequentially connected to the first driving power supply VDD and the second driving power supply VSS. Each of the first series group SET1 to the third series group SET3 may include two electrodes (e.g., ELT1 and ELT2a, ELT2b and ELT3a, ELT3b and ELT4) constituting the corresponding series group electrode pair and multiple light-emitting elements LD connected in parallel in the forward direction (e.g., in the same direction) between the two electrodes (e.g., between ELT1 and ELT2a, between ELT2b and ELT3a, or between ELT3b and ELT4).

[0168] The first series group SET1 may include a first electrode ELT1 and a second electrode ELT2a as an electrode pair included in the light-emitting unit (EMU), and may include at least one first light-emitting element LD1 connected between the first electrode ELT1 and the second electrode ELT2a. For example, the first series group SET1 may include a first electrode ELT1 connected to a first driving power supply VDD via a pixel driving circuit PXC, a second electrode ELT2a connected to a second driving power supply VSS, and a plurality of first light-emitting elements LD1 connected between the first electrode ELT1 and the second electrode ELT2a. One end (e.g., the second semiconductor layer) of each first light-emitting element LD1 may be electrically connected to the first electrode ELT1 of the first series group SET1, and the other end (e.g., the first semiconductor layer) may be electrically connected to the second electrode ELT2a of the first series group SET1. The first light-emitting elements LD1 may be connected in parallel between the first electrode ELT1 and the second electrode ELT2a of the first series group SET1, and may be connected in the same direction (e.g., in the forward direction) between the first electrode ELT1 and the second electrode ELT2a.

[0169] According to some embodiments, at least one reverse light-emitting element LDr (see...) Figure 6E The reverse light-emitting element LDr can be further connected in the first series group SET1. The reverse light-emitting element LDr can be connected in parallel between the first electrode ELT1 and the second electrode ELT2a together with the first light-emitting element LD1 constituting the effective light source, but it can also be connected between the first electrode ELT1 and the second electrode ELT2a in the opposite direction to the first light-emitting element LD1. Even when a driving voltage (e.g., a forward driving voltage) is applied between the first electrode ELT1 and the second electrode ELT2a, the reverse light-emitting element LDr can remain inactive, such that essentially no current flows through the reverse light-emitting element LDr.

[0170] The second series group SET2 may include a 2b electrode ELT2b and a 3a electrode ELT3a as an electrode pair included in the light-emitting unit EMU, and may include at least one second light-emitting element LD2 connected between the 2b electrode ELT2b and the 3a electrode ELT3a. For example, the second series group SET2 may include a 2b electrode ELT2b connected to a first driving power supply VDD via the pixel driving circuit PXC and the first series group SET1, a 3a electrode ELT3a connected to a second driving power supply VSS, and a plurality of second light-emitting elements LD2 connected between the 2b electrode ELT2b and the 3a electrode ELT3a. One end of each second light-emitting element LD2 (e.g., a second semiconductor layer) may be electrically connected to the 2b electrode ELT2b of the second series group SET2, and the other end (e.g., a first semiconductor layer) may be electrically connected to the 3a electrode ELT3a of the second series group SET2. The second light-emitting element LD2 can be connected in parallel between the 2b electrode ELT2b and the 3a electrode ELT3a of the second series group SET2, and can be connected in the same direction (e.g., in the positive direction) between the first driving power supply VDD and the second driving power supply VSS through the 2b electrode ELT2b and the 3a electrode ELT3a.

[0171] According to some embodiments, at least one reverse light-emitting element LDr (see...) Figure 6E It can be further connected between the second electrode ELT2b and the third electrode ELT3a. The reverse light-emitting element LDr can be connected in parallel between the second electrode ELT2b and the third electrode ELT3a together with the second light-emitting element LD2 that constitutes an effective light source, but it can be connected between the second electrode ELT2b and the third electrode ELT3a in the opposite direction to the second light-emitting element LD2.

[0172] In some embodiments of this disclosure, the second a electrode ELT2a of the first series group SET1 and the second b electrode ELT2b of the second series group SET2 can be integrally disposed and connected to each other. That is, the second a electrode ELT2a of the first series group SET1 and the second b electrode ELT2b of the second series group SET2 can constitute a second electrode ELT2 electrically connecting the first series group SET1 and the second series group SET2. As described above, when the second a electrode ELT2a of the first series group SET1 and the second b electrode ELT2b of the second series group SET2 are integrally disposed, the second a electrode ELT2a and the second b electrode ELT2b can be considered as different regions or parts of the second electrode ELT2.

[0173] The third series group SET3 may include a third electrode ELT3b and a fourth electrode ELT4 as an electrode pair included in the light-emitting unit (EMU), and may include at least one third light-emitting element LD3 connected to the third electrode ELT3b and the fourth electrode ELT4. For example, the third series group SET3 may include a third electrode ELT3b connected to a first driving power supply VDD via a pixel driving circuit PXC and a previous series group (e.g., a first series group SET1 and a second series group SET2), a fourth electrode ELT4 connected to a second driving power supply VSS, and a plurality of third light-emitting elements LD3 connected between the third electrode ELT3b and the fourth electrode ELT4. One end of each third light-emitting element LD3 (e.g., a second semiconductor layer) may be electrically connected to the third electrode ELT3b of the third series group SET3, and the other end (e.g., a first semiconductor layer) may be electrically connected to the fourth electrode ELT4 of the third series group SET3. The third light-emitting element LD3 can be connected in parallel between the 3b electrode ELT3b and the fourth electrode ELT4 of the third series group SET3, and can be connected in the same direction (e.g., in the positive direction) between the first driving power supply VDD and the second driving power supply VSS through the 3b electrode ELT3b and the fourth electrode ELT4.

[0174] According to some embodiments, at least one reverse light-emitting element LDr (see...) Figure 6E It can be further connected between the 3b electrode ELT3b and the fourth electrode ELT4. The reverse light-emitting element LDr can be connected in parallel with the third light-emitting element LD3, which constitutes an effective light source, between the 3b electrode ELT3b and the fourth electrode ELT4, but it can be connected between the 3b electrode ELT3b and the fourth electrode ELT4 in the opposite direction to the third light-emitting element LD3.

[0175] In some embodiments of this disclosure, the third electrode ELT3a of the second series group SET2 and the third electrode ELT3b of the third series group SET3 can be integrally disposed and connected to each other. That is, the third electrode ELT3a of the second series group SET2 and the third electrode ELT3b of the third series group SET3 can constitute a third electrode ELT3 electrically connecting the second series group SET2 and the third series group SET3. As described above, when the third electrode ELT3a of the second series group SET2 and the third electrode ELT3b of the third series group SET3 are integrally disposed, the third electrode ELT3a and the third electrode ELT3b can be different corresponding parts or regions of the third electrode ELT3.

[0176] In the embodiments described above, the first electrode ELT1 of the first series group SET1 can be the anode of the light-emitting unit EMU of each pixel PXL, and the fourth electrode ELT4 of the third series group SET3 can be the cathode of the light-emitting unit EMU.

[0177] As described above, the light-emitting unit (EMU) of the pixel PXL, which includes the light-emitting element LD connected as a series / parallel hybrid structure, can be easily adjusted according to the product specifications applied.

[0178] Specifically, compared to a light-emitting unit (EMU) with light-emitting elements (LDs) connected in complete parallel, a light-emitting unit EMU including LDs connected in a series / parallel hybrid structure can reduce the drive current. Furthermore, compared to a light-emitting unit EMU with all LDs connected in series, a light-emitting unit EMU including LDs connected in a series / parallel hybrid structure can reduce the drive voltage applied across the EMU. Additionally, when all LDs are connected in series, if at least one of the series-connected LDs is not fully connected in the forward direction (e.g., a reverse-emitting element LDr), the drive current can be blocked in the path of flow through the pixel PXL, resulting in dark spot defects. On the other hand, when the LDs are connected in a series / parallel hybrid structure, even if some LDs are not connected in the forward direction or include a reverse-emitting element LDr in one or more series groups, or even if defects occur in one or more LDs, the drive current can still flow through another LD in the corresponding series group. Therefore, defects in the pixel PXL can be prevented or reduced.

[0179] Figure 8 It is shown that it includes Figure 5 A top view of an example of pixels in a display device.

[0180] Reference Figure 8 A pixel PXL (or pixel region PXA) may include a light-emitting region EMA in which at least one pair of first electrodes ELT1 and second electrodes ELT2 are positioned and at least one light-emitting element LD is positioned between the first electrodes ELT1 and the second electrodes ELT2. According to some embodiments, the light-emitting region EMA may be defined by a dam BNK surrounding the light-emitting region EMA. The dam BNK may serve as a dam structure to prevent a solution containing the light-emitting element LD from flowing into the light-emitting region EMA of an adjacent pixel PXL, or as a dam structure to control the amount of solution supplied to each light-emitting region EMA when supplying the light-emitting element LD to the light-emitting region EMA.

[0181] The first electrode ELT1 and the second electrode ELT2 can extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1.

[0182] According to some embodiments, each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, the first electrode ELT1 may have a multi-layer structure including a first reflective electrode and a first conductive capping layer, and the second electrode may have a multi-layer structure including a second reflective electrode and a second conductive capping layer.

[0183] According to some embodiments, the first electrode ELT1 can be connected to the first connecting electrode CNL1. The first electrode ELT1 can be integrally connected to the first connecting electrode CNL1. For example, the first connecting electrode CNL1 can extend in a first direction DR1, and the first electrode ELT1 can be formed by branching at least one branch from the first connecting electrode CNL1. When the first electrode ELT1 and the first connecting electrode CNL1 are integrally formed, the first connecting electrode CNL1 can be considered as a region of the first electrode ELT1. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the first electrode ELT1 and the first connecting electrode CNL1 can be formed separately from each other, thereby being electrically connected to each other through at least one contact hole or through hole.

[0184] According to some embodiments, the first connecting electrode CNL1 may have a single-layer structure or a multi-layer structure. As an example, the first connecting electrode CNL1 may include a first sub-connecting electrode integrally connected to the first reflective electrode and a second sub-connecting electrode integrally connected to the first conductive capping layer. According to some embodiments, the first connecting electrode CNL1 may have the same cross-sectional structure (or stacked structure) as the first electrode ELT1, but is not limited thereto.

[0185] The first electrode ELT1 and the first connecting electrode CNL1 can be connected to the pixel driving circuit PXC of pixel PXL (e.g., through the first contact hole CH1) Figures 6A to 6C (PXC of any of the pixel driving circuits shown in the diagram).

[0186] According to some embodiments, the first contact hole CH1 may be located outside the light-emitting area EMA of pixel PXL. For example, the first contact hole CH1 may be located around the corresponding light-emitting area EMA and overlapped with the embankment BNK. In this case, because the first contact hole CH1 is covered by the embankment BNK, it is possible to reduce or prevent the reflection of the pattern in the light-emitting area EMA. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, at least one first contact hole CH1 may be located inside the light-emitting area EMA.

[0187] According to some embodiments, the pixel driving circuit PXC may be located below the light-emitting element LD positioned in the corresponding pixel region PXA. For example, each pixel driving circuit PXC may be formed in a pixel circuit layer (or a circuit element layer including circuit elements such as transistors) below the light-emitting element LD to be connected to the first electrode ELT1 through the first contact hole CH1.

[0188] According to some embodiments, the second electrode ELT2 can be connected to the second connecting electrode CNL2. For example, the second electrode ELT2 can be integrally connected to the second connecting electrode CNL2. For example, the second connecting electrode CNL2 can extend in the first direction DR1, and the second electrode ELT2 can be formed by branching at least one branch from the second connecting electrode CNL2. When the second electrode ELT2 and the second connecting electrode CNL2 are integrally formed, the second connecting electrode CNL2 can be considered as a region of the second electrode ELT2. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the second electrode ELT2 and the second connecting electrode CNL2 are formed separately from each other, thereby being electrically connected to each other through at least one contact hole or through hole.

[0189] According to some embodiments, similar to the first connecting electrode CNL1, the second connecting electrode CNL2 may have a single-layer structure or a multi-layer structure.

[0190] According to some embodiments, the second electrode ELT2 and the second connecting electrode CNL2 can be connected to the second driving power supply VSS (see...). Figure 6A For example, the second electrode ELT2 and the second connecting electrode CNL2 can be connected through the second contact hole CH2 and through the second power line PL2 connected to the second drive power supply VSS (see...). Figure 6A Connect to the second drive power supply VSS.

[0191] According to some embodiments, the second contact hole CH2 may be located outside the light-emitting area EMA of pixel PXL. For example, the second contact hole CH2 may be located around the corresponding light-emitting area EMA and overlapped with the embankment BNK. In this case, because the second contact hole CH2 is covered by the embankment BNK, it is possible to reduce or prevent the reflection of the pattern in the light-emitting area EMA. However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, at least one second contact hole CH2 may be located inside the light-emitting area EMA.

[0192] The first dam pattern PW1 (and the third dam pattern PW3) can be located below the first electrode ELT1 and superimposed on a region of the first electrode ELT1. The second dam pattern PW2 can be located below the second electrode ELT2 and superimposed on a region of the second electrode ELT2. The first dam pattern PW1 and the second dam pattern PW2 can be spaced apart from each other in the light-emitting region EMA and can protrude upward from the corresponding regions of the first electrode ELT1 and the second electrode ELT2. For example, the first electrode ELT1 can be located on the first dam pattern PW1 so that the first dam pattern PW1 is on the substrate SUB (see Figure 5 The second electrode ELT2 protrudes in the height direction (or thickness direction) of the substrate SUB, and can be located on the second embankment pattern PW2 to extend from the second embankment pattern PW2 onto the substrate SUB (see...). Figure 5 It protrudes in the height direction.

[0193] According to some embodiments, at least one light-emitting element (LD) (e.g., multiple light-emitting elements LD) can be arranged between the first electrode ELT1 and the second electrode ELT2 of the pixel PXL. In a light-emitting region EMA positioned such that the first electrode ELT1 and the second electrode ELT2 can face each other, multiple light-emitting elements LD can be connected in parallel.

[0194] At the same time, Figure 8 In the diagram, the light-emitting element LD is shown extending in a first direction DR1 (e.g., in a horizontal direction) between the first electrode ELT1 and the second electrode ELT2, but the arrangement direction of the light-emitting element LD is not limited to this. For example, at least one of the light-emitting elements LD may be arranged in a diagonal direction.

[0195] Each of the light-emitting elements (LDs) can be electrically connected between the first electrode ELT1 and the second electrode ELT2 of the pixel PXL. For example, the first end of each of the light-emitting elements (LDs) can be electrically connected to the first electrode ELT1, and the second end of each of the light-emitting elements (LDs) can be electrically connected to the second electrode ELT2.

[0196] In some embodiments, the first end of each of the light-emitting elements (LDs) may not be directly located on the first electrode ELT1, but instead may be electrically connected to the first electrode ELT1 via at least one contact electrode (e.g., via the first contact electrode CNE1 (or the third electrode)). However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the first end of the light-emitting element (LD) may directly contact the first electrode ELT1, thereby being electrically connected to the first electrode ELT1.

[0197] Similarly, the second end of each of the light-emitting elements (LDs) may not be directly located on the second electrode ELT2, but instead may be electrically connected to the second electrode ELT2 via at least one contact electrode (e.g., the second contact electrode CNE2 (or the fourth electrode)). However, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the second end of each of the light-emitting elements (LDs) may directly contact the second electrode ELT2, thereby being electrically connected to the second electrode ELT2.

[0198] According to some embodiments, each of the light-emitting elements (LDs) can be a light-emitting diode with an ultra-small size (e.g., nanometer to micrometer scale) using a material with an inorganic crystal structure. For example, such as Figures 1A to 4B As shown in any of them, each of the light-emitting elements LD can be an ultra-small light-emitting diode with a size ranging from nanometer to micrometer.

[0199] According to some embodiments, the light-emitting element (LD) can be prepared in the form of a dispersion in a solution (e.g., a predetermined solution) and can be supplied to the light-emitting area EMA of each pixel PXL using an inkjet printing method or a slot coating method. For example, the LD can be mixed with a volatile solvent to be supplied to the light-emitting area EMA. In this case, when a voltage (e.g., a predetermined voltage) is supplied to the first electrode ELT1 and the second electrode ELT2 of the pixel PXL, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, and the LD self-aligns between the first electrode ELT1 and the second electrode ELT2. After the LD is aligned, the solvent can be evaporated or removed by a suitable method, thereby stably distributing the LD between the first electrode ELT1 and the second electrode ELT2. In addition, by forming a first contact electrode CNE1 and a second contact electrode CNE2 on the first end and the second end of the LD, respectively, the LD can be stably connected between the first electrode ELT1 and the second electrode ELT2.

[0200] According to some embodiments, a first contact electrode CNE1 can be formed on at least one region of a first end of a light-emitting element LD and a corresponding first electrode ELT1, such that the first end of the light-emitting element LD (e.g., Figure 9 The first terminal EP1 shown can be physically and / or electrically connected to the first electrode ELT1. Similarly, the second contact electrode CNE2 can be formed on at least one region of the second terminal of the light-emitting element LD and its corresponding second electrode ELT2, such that the second terminal of the light-emitting element LD (e.g., Figure 9 The second terminal EP2 shown can be physically and / or electrically connected to the second electrode ELT2.

[0201] Light-emitting elements (LDs) located in pixel region PXA can be grouped to form the light source of the corresponding pixel PXL. For example, when a driving current flows in at least one pixel PXL during each frame period, the light-emitting elements (LDs) connected in the positive direction between the first electrode ELT1 and the second electrode ELT2 of pixel PXL can emit light with a brightness corresponding to the driving current.

[0202] Figure 9 It shows along Figure 8 A cross-sectional view of an example of pixels captured by line I-I'. Figure 10 yes Figure 9 An enlarged sectional view of region Q2.

[0203] First, refer to Figure 8 and Figure 9 The pixel circuit layer (PCL) and the light-emitting element layer (LDL) can be sequentially located on the substrate (SUB) (or base layer). For example, the pixel circuit layer (PCL) can be formed on one surface of the substrate (SUB), and the light-emitting element layer (LDL) can be formed on the surface of the substrate (SUB) on which the pixel circuit layer (PCL) is formed. According to some embodiments, the pixel circuit layer (PCL) and the light-emitting element layer (LDL) can be completely formed in the display area DA of the display device (see [reference]). Figure 5 )middle.

[0204] According to some embodiments, the pixel circuit layer PCL may include the pixel driving circuitry PXC constituting the pixel PXL (see...). Figures 6A to 7B ) circuit elements.

[0205] The light-emitting element layer (LDL) can include the light-emitting element (LD) of the pixel PXL.

[0206] For example, the pixel circuit layer PCL may include Figures 6A to 7B The first transistor T1 is shown. Additionally, in some embodiments, the pixel circuit layer PCL may also include... Figures 6A to 7B The storage capacitor Cst shown, and the various signal lines connected to the pixel drive circuit PXC (e.g., Figures 6A to 7B The scan line Si and data line Dj shown are connected to the pixel drive circuit PXC and / or the light-emitting element LD, and various power lines (e.g., first power line PL1 and second power line PL2).

[0207] In addition, the pixel circuit layer PCL includes multiple insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI (or gate insulating film), an interlayer insulating layer ILD (or interlayer insulating film), and a passivation layer PSV (or protective layer) sequentially stacked on one surface of the substrate SUB.

[0208] According to some embodiments, a buffer layer (BFL) can reduce or prevent impurities from diffusing into circuit elements. The buffer layer (BFL) can consist of a single layer or multiple layers, with at least two layers. When the buffer layer (BFL) is configured as multiple layers, each layer can be made of the same material or different materials. Meanwhile, according to some embodiments, the buffer layer (BFL) can be omitted.

[0209] According to some embodiments, the first transistor T1 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. While the first transistor T1 is shown as having a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, this disclosure is not limited thereto. For example, in other embodiments of this disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 disposed in at least one transistor may be integrated with the semiconductor layer SCL, respectively.

[0210] The semiconductor layer SCL can be located on the buffer layer BFL. For example, the semiconductor layer SCL can be located between the substrate SUB on which the buffer layer BFL is formed and the gate insulating layer GI. The semiconductor layer SCL may include a first region contacting the first transistor electrode ET1, a second region contacting the second transistor electrode ET2, and a channel region located between the first region and the second region. According to some embodiments, one of the first region and the second region may be a source region, and the other of the first region and the second region may be a drain region.

[0211] According to some embodiments, the semiconductor layer SCL can be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. Additionally, the channel region of the semiconductor layer SCL can be an intrinsic semiconductor, which is a semiconductor pattern without impurities therein, and each of the first and second regions of the semiconductor layer SCL can be a semiconductor pattern doped with a corresponding impurity (e.g., a predetermined impurity).

[0212] The gate electrode GE can be located on the semiconductor layer SCL, with the gate insulating layer GI disposed between them. For example, the gate electrode GE can be located between the gate insulating layer GI and the interlayer insulating layer ILD, while being superimposed on at least one region of the semiconductor layer SCL.

[0213] The first transistor electrode ET1 and the second transistor electrode ET2 may be located on the semiconductor layer SCL and the gate electrode GE, with at least one interlayer insulating layer ILD disposed between them. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be located between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, each of the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to a first region and a second region of the semiconductor layer SCL, respectively, through contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0214] On the other hand, according to some embodiments, either the first transistor electrode ET1 or the second transistor electrode ET2 of at least one transistor (e.g., the first transistor T1) disposed in the pixel driving circuit PXC can be electrically connected to the first electrode ELT1 of the light-emitting element layer LDL located on the passivation layer PSV through the first contact hole CH1 of the passivation layer PSV.

[0215] According to some embodiments, at least one signal line and / or power line may be connected to an electrode of a circuit element constituting the pixel driving circuit PXC (see...). Figures 6A to 7B The second power line PL2, used to supply the second driving power supply VSS, can be located on the same layer as the gate electrode GE of each of the first transistor T1 and the second transistor T2, and can be electrically connected to the second electrode ELT2 of the light-emitting element layer LDL located on the passivation layer PSV through a bridging pattern BRP located on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and through at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2 can be varied.

[0216] The light-emitting element layer LDL may include a first dam pattern PW1, a second dam pattern PW2 and a third dam pattern PW3, a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a light-emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a second contact electrode CNE2 and a third contact electrode CNE3 and a third insulating layer INS3, which are sequentially located and / or formed on the pixel circuit layer PCL.

[0217] The first dam pattern PW1 and the second dam pattern PW2 can be located on the pixel circuit layer PCL. The first dam pattern PW1 and the second dam pattern PW2 can be positioned spaced apart from each other in the light-emitting region EMA. The first dam pattern PW1 and the second dam pattern PW2 can protrude from the third-direction DR3 on the pixel circuit layer PCL. For example, the thickness TH1 of the first dam pattern PW1 and the second dam pattern PW2 (see...) Figure 10The diameter can be in the range of about 1.5 μm to about 2.5 μm. According to some embodiments, the first embankment pattern PW1 and the second embankment pattern PW2 can have substantially the same height as each other, but this disclosure is not limited thereto.

[0218] According to some embodiments, the first dam pattern PW1 may be located between the pixel circuit layer PCL and the first electrode ELT1. The first dam pattern PW1 may be positioned adjacent to the first end EP1 of the light-emitting element LD. For example, the first side surface SS1 of the first dam pattern PW1 may be located at a certain distance from the first end EP1 of the light-emitting element LD and adjacent to the first end EP1 of the light-emitting element LD, and may be positioned facing the first end EP1.

[0219] According to some embodiments, the second dam pattern PW2 can be located between the pixel circuit layer PCL and the second electrode ELT2. The second dam pattern PW2 can be positioned adjacent to the second end EP2 of the light-emitting element LD. For example, one side surface of the second dam pattern PW2 can be located at a certain distance from but adjacent to the second end EP2 of the light-emitting element LD, and can be positioned facing the second end EP2.

[0220] According to some embodiments, the first dike pattern PW1 and the second dike pattern PW2 can have various shapes. For example, as... Figure 9 As shown, both the first dam pattern PW1 and the second dam pattern PW2 can have a trapezoidal cross-sectional shape in which the width narrows upwards (e.g., away from the base SUB). In this case, each of the first dam pattern PW1 and the second dam pattern PW2 can have an upper surface US that is substantially parallel to the upper surface of the base SUB and a first side surface SS1 and a second side surface SS2 that are inclined relative to the upper surface of the base SUB. However, the shapes of the first dam pattern PW1 and the second dam pattern PW2 are not limited to this. For example, the first dam pattern PW1 and / or the second dam pattern PW2 can have a semi-circular or semi-elliptical cross-sectional shape in which the width narrows upwards with the dam pattern. In this case, each of the first dam pattern PW1 and the second dam pattern PW2 can have a curved surface at at least one side surface. When the first dam pattern PW1 and the second dam pattern PW2 have semi-circular or semi-elliptical cross-sections, a portion of the first dam pattern PW1 and the second dam pattern PW2 can be defined as the upper surface of the first dam pattern PW1 and the second dam pattern PW2, and the angle between the tangent (or tangent plane) of this portion and the upper surface of the substrate SUB can be about 30 degrees or less, or about 10 degrees or less. That is, the shape of the first dam pattern PW1 and the second dam pattern PW2 in this disclosure is not specifically limited and can be varied. In addition, according to some embodiments, at least one of the first dam pattern PW1 and the second dam pattern PW2 can be omitted, or their positions can be changed.

[0221] The first dam pattern PW1 and the second dam pattern PW2 may include insulating materials comprising inorganic and / or organic materials. For example, the first dam pattern PW1 and the second dam pattern PW2 may include materials other than SiN. x or SiO x In addition, it includes at least one inorganic layer comprising one or more different inorganic insulating materials. Optionally, the first dam pattern PW1 and the second dam pattern PW2 may include at least one organic layer and / or a photoresist layer, or may consist of a single-layer or multi-layer insulator comprising a combination of organic / inorganic materials, wherein the at least one organic layer comprises one or more different organic insulating materials. That is, the constituent materials of the first dam pattern PW1 and the second dam pattern PW2 can be varied.

[0222] In some embodiments, the first dam pattern PW1 and the second dam pattern PW2 can be used as reflective members. For example, the first dam pattern PW1 and the second dam pattern PW2, together with the first electrode ELT1 and the second electrode ELT2 disposed thereon, can be used as reflective members to guide light emitted from each light-emitting element LD in a desired direction, thereby improving the light efficiency of the pixel PXL.

[0223] The first electrode ELT1 and the second electrode ELT2 can be located on the first embankment pattern PW1 and the second embankment pattern PW2, respectively. The first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other in the light-emitting region EMA.

[0224] According to some embodiments, the first electrode ELT1 and the second electrode ELT2, respectively located on the first dam pattern PW1 and the second dam pattern PW2, may have shapes corresponding to the first dam pattern PW1 and the second dam pattern PW2, respectively. For example, the first electrode ELT1 and the second electrode ELT2 may protrude on the third-direction DR3 and have inclined surfaces or curved surfaces corresponding to the shapes of the first dam pattern PW1 and the second dam pattern PW2, respectively.

[0225] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one material selected from, but is not limited to, metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti and their alloys, conductive oxides such as ITO, IZO, ZnO and ITZO, and conductive polymers such as PEDOT.

[0226] Furthermore, each of the first electrode ELT1 and the second electrode ELT2 may consist of a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. Additionally, each of the first electrode ELT1 and the second electrode ELT2 may optionally further include at least one of multiple transparent electrode layers located above and / or below the reflective electrode layers and multiple conductive capping layers covering the upper portion of the multiple reflective electrode layers and / or the multiple transparent electrode layers.

[0227] According to some embodiments, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 can be made of a conductive material with uniform reflectivity. For example, the reflective electrode layer may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and their alloys, but is not limited thereto. That is, the reflective electrode layer can be made of various reflective conductive materials. When each of the first electrode ELT1 and the second electrode ELT2 includes a reflective electrode layer, light emitted from both ends of the light-emitting element LD (e.g., from the first end EP1 and the second end EP2) can be further advanced in the direction of displaying the image (e.g., the forward direction). For example, when the first electrode ELT1 and the second electrode ELT2 are positioned facing the first end EP1 and the second end EP2 of the light-emitting element LD and simultaneously have inclined surfaces or curved surfaces corresponding to the shapes of the first embankment pattern PW1 and the second embankment pattern PW2, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD can be reflected by the first electrode ELT1 and the second electrode ELT2 and can be further advanced or guided towards the third direction DR3. Therefore, the efficiency of light emitted from the light-emitting element LD can be improved.

[0228] Furthermore, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 can be made of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but is not limited thereto. In some embodiments, each of the first electrode ELT1 and the second electrode ELT2 may consist of three layers having a stacked structure of ITO / Ag / ITO. As described above, when the first electrode ELT1 and the second electrode ELT2 are composed of multiple layers, at least two layers, the voltage drop caused by signal delay (e.g., due to RC delay) can be minimized. Therefore, the desired voltage can be efficiently transmitted to the light-emitting element LD.

[0229] Furthermore, because each of the first electrode ELT1 and the second electrode ELT2 includes a conductive overlay layer covering the reflective electrode layer and / or the transparent electrode layer, damage to the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 due to defects occurring in the manufacturing process of the pixel PXL can be reduced or prevented. However, the conductive overlay layer may be optionally included in the first electrode ELT1 and the second electrode ELT2, and may be omitted according to some embodiments. Additionally, the conductive overlay layer may be considered as a constituent element of each of the first electrode ELT1 and the second electrode ELT2, or as a separate constituent element located on the first electrode ELT1 and the second electrode ELT2.

[0230] The first insulating layer INS1 may be located on one or more corresponding regions of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover one or more corresponding regions of the first electrode ELT1 and the second electrode ELT2, and may include an opening that exposes another region of the first electrode ELT1 and the second electrode ELT2.

[0231] In some embodiments, the first insulating layer INS1 may initially be formed to completely cover the first electrode ELT1 and the second electrode ELT2. For example... Figure 9 As shown, after supplying and aligning the light-emitting element LD on the first insulating layer INS1, the first insulating layer INS1 can be partially opened or removed to expose a portion of the side and top surfaces of each of the first electrode ELT1 and the second electrode ELT2. Optionally, after the supply and alignment of the light-emitting element LD are completed, the first insulating layer INS1 can be patterned as a separate pattern partially located below the light-emitting element LD.

[0232] In other words, the first insulating layer INS1 can be placed between the first electrode ELT1 and the second electrode ELT2 and the light-emitting element LD, and can expose at least one area of ​​each of the first electrode ELT1 and the second electrode ELT2. After the first electrode ELT1 and the second electrode ELT2 are formed, the first insulating layer INS1 can be formed to cover the first electrode ELT1 and the second electrode ELT2, thereby reducing or preventing damage to the first electrode ELT1 and the second electrode ELT2, and / or reducing or preventing metal deposition in subsequent (multiple) processes. In addition, the first insulating layer INS1 can stably support each light-emitting element LD.

[0233] The light-emitting element LD can have a light-emitting region EMA (see INS1) formed therein, which contains a first insulating layer INS1. Figure 8The light-emitting element (LD) is supplied and aligned in the light-emitting region (EMA) by means of inkjet printing, etc., and the light-emitting element (LD) can be arranged between the first electrode (ELT1) and the second electrode (ELT2) by applying a voltage (e.g., a predetermined alignment voltage / alignment signal) to the first electrode (ELT1) and the second electrode (ELT2).

[0234] The second insulating layer INS2 (or insulating pattern) may be located on the light-emitting element LD (e.g., the light-emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2), and may expose the first end EP1 and the second end EP2 of the light-emitting element LD. For example, the second insulating layer INS2 may not cover the first end EP1 and the second end EP2 of the light-emitting element LD, and may only be partially located on a region of the light-emitting element LD. The second insulating layer INS2 may be formed in a separate pattern, but is not limited thereto. Furthermore, as... Figure 9 As shown, when there is a gap between the first insulating layer INS1 and the light-emitting element LD before the second insulating layer INS2 is formed, the gap can be filled by the second insulating layer INS2. Therefore, the light-emitting element LD can be supported more stably.

[0235] like Figure 10 As shown, the second insulating layer INS2 may include a first side surface SS1 facing the first electrode ELT1, a second side surface SS2 facing the second electrode ELT2, and an upper surface US that is substantially parallel to the upper surface of the substrate SUB between the first side surface SS1 and the second side surface SS2. Figure 9 As shown, the second insulating layer INS2 may have a trapezoidal cross-section, but the cross-sectional shape of the second insulating layer INS2 is not limited to this.

[0236] According to some embodiments, the thickness TH2 of the second insulating layer INS2 can be in the range of about 50% to about 150% of the thickness TH1 of the first dam pattern PW1 (and / or the second dam pattern PW2). For example, when the thickness TH1 of the first dam pattern PW1 is about 2 μm, the thickness TH2 of the second insulating layer INS2 can be in the range of about 1 μm to about 3 μm, in the range of about 1.5 μm to about 2.5 μm, or about 2 μm.

[0237] Reference Figure 10 And as will be referred to later Figure 15F and Figure 15GDescribed, in order to form the first contact electrode CNE1 and the second contact electrode CNE2 in a single etching process without a separate mask, the depth DEP1 of the trench formed between the first dam pattern PW1 and the second insulating layer INS2 (e.g., the depth of the trench relative to the upper surface US of the second insulating layer INS2, or the depth DEP2 of the trench formed between the second dam pattern PW2 and the second insulating layer INS2) can be greater than about half the thickness TH1 of the first dam pattern PW1 (and / or the second dam pattern PW2), for example, it can be greater than about 1 μm. Therefore, the thickness TH2 of the second insulating layer INS2 can be greater than about 50% of the thickness TH1 of the first dam pattern PW1.

[0238] As the thickness TH2 of the second insulating layer INS2 increases, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed more easily, but the thickness of the light-emitting element layer LDL will increase, and defects may occur in the second insulating layer INS2. Therefore, the thickness TH2 of the second insulating layer INS2 can be about 150% smaller than the thickness TH1 of the first embankment pattern PW1.

[0239] According to some embodiments, the maximum height of the upper surface US of the second insulating layer INS2 relative to the upper surface of the substrate SUB can be greater than or approximately equal to the height H1 of the upper surface US of the first dam pattern PW1 and / or the second dam pattern PW2.

[0240] The thickness TH2 of the second insulating layer INS2 (or a portion of the second insulating layer INS2) stacked with the light-emitting element LD can be equal to the thickness TH3 of the second insulating layer INS2 not stacked (or not stacked) with the light-emitting element LD. However, because a step (or height difference) is formed relative to the substrate SUB due to the presence of the light-emitting element LD, the height H2 of the upper surface US of the second insulating layer INS2 stacked with the light-emitting element LD can be greater than the height H3 of the upper surface of the second insulating layer INS2 not stacked with the light-emitting element LD.

[0241] Relative to the substrate SUB, the height H2 of the upper surface US of the second insulating layer INS2 stacked with the light-emitting element LD can be greater than or approximately equal to the height H1 of the upper surface US of the first dam pattern PW1 and / or the upper surface US of the second dam pattern PW2, and the height H3 of the upper surface of the second insulating layer INS2 not stacked with the light-emitting element LD can be less than the height H1 of the upper surface US of the first dam pattern PW1 and / or the second dam pattern PW2.

[0242] When considering the thickness of the first electrode ELT1 (e.g., about 0.2 μm), the thickness of the first insulating layer INS1 (e.g., about 0.3 μm), and the thickness of the light-emitting element LD, the height H2 of the upper surface US of the second insulating layer INS2 stacked with the light-emitting element LD relative to the substrate SUB can be equal to the height H1 of the upper surface of the first embankment pattern PW1 and / or the second embankment pattern PW2.

[0243] The first contact electrode CNE1 and the second contact electrode CNE2 can be located on the first electrode ELT1 and the second electrode ELT2, and on the first end EP1 and the second end EP2 of the light-emitting element LD. In some embodiments, such as Figure 9 As shown, the first contact electrode CNE1 and the second contact electrode CNE2 can be located on the same layer. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed using the same conductive material in the same process.

[0244] The first contact electrode CNE1 and the second contact electrode CNE2 can electrically connect the first end EP1 and the second end EP2 of the light-emitting element LD to the first electrode ELT1 and the second electrode ELT2, respectively.

[0245] The first contact electrode CNE1 can be located on the first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 can be positioned to contact the first electrode ELT1 in a region of the first electrode ELT1 not covered by the first insulating layer INS1 (e.g., contacting the first side surface of the first electrode ELT1, or contacting the first side surface SS1 of the first embankment pattern PW1). Alternatively, the first contact electrode CNE1 can be located on the first end EP1 to contact the first end EP1 of the light-emitting element LD adjacent to the first electrode ELT1. That is, the first contact electrode CNE1 can be positioned to cover the first end EP1 of the light-emitting element LD and at least one corresponding region of the first electrode ELT1. Therefore, the first end EP1 of the light-emitting element LD can be electrically connected to the first electrode ELT1.

[0246] According to some embodiments, the first contact electrode CNE1 may be located on the first side surface SS1 of the second insulating layer INS2, and may not overlap with the upper surface US of the second insulating layer INS2. The first contact electrode CNE1 may completely cover the first side surface SS1 of the second insulating layer INS2, and the height of one end of the first contact electrode CNE1 (e.g., the end of the first contact electrode CNE1 in contact with the second insulating layer INS2) may be approximately equal to the height H2 of the upper surface US of the second insulating layer INS2. Alternatively, the first contact electrode CNE1 may be located on one side surface of the first electrode ELT1, and may not overlap with the upper surface of the first electrode ELT1. The first contact electrode CNE1 may completely cover one side surface of the first electrode ELT1, and the height of the other end of the first contact electrode CNE1 (e.g., the end of the first contact electrode CNE1 in contact with the first electrode ELT1) may be approximately equal to the height of the upper surface of the first electrode ELT1. The first contact electrode CNE1 may be located on the first side surface SS1 of the first embankment pattern PW1, and may not overlap with the upper surface US of the first embankment pattern PW1. In other words, in a plan view (e.g., when viewed in a plane), the first contact electrode CNE1 can be spaced apart from the upper surface US of the first embankment pattern PW1.

[0247] Similarly, the second contact electrode CNE2 can be located on the second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 can be positioned to contact the second electrode ELT2 in a region not covered by the first insulating layer INS1 (e.g., on a side surface of the second electrode ELT2 not covered by the first insulating layer INS1, or on a side surface of the second embankment pattern PW2 not covered by the first insulating layer INS1). Alternatively, the second contact electrode CNE2 can be located on the second end EP2 of the light-emitting element LD to contact the second end EP2 of the light-emitting element LD in a region adjacent to the second electrode ELT2. That is, the second contact electrode CNE2 can be positioned to cover both the second end EP2 of the light-emitting element LD and at least one corresponding region of the second electrode ELT2. Therefore, the second end EP2 of the light-emitting element LD can be electrically connected to the second electrode ELT2.

[0248] According to some embodiments, the second contact electrode CNE2 may be located on the second side surface SS2 of the second insulating layer INS2, and may not be superimposed on the upper surface US of the second insulating layer INS2. Alternatively, the second contact electrode CNE2 may be located on a side surface of the second electrode ELT2, and may not be superimposed on the upper surface of the second electrode ELT2. The second contact electrode CNE2 may also be located on a side surface of the second embankment pattern PW2, and may not be superimposed on the upper surface of the second embankment pattern PW2.

[0249] The third contact electrode CNE3 (or the fifth electrode) may be located on the second electrode ELT2 to contact the second electrode ELT2, and may be spaced apart from the second contact electrode CNE2. For example, the third contact electrode CNE3 may be positioned to contact the second electrode ELT2 in an area not covered by the first insulating layer INS1 (e.g., the other side of the second electrode ELT2 not covered by the first insulating layer INS1 or the other side of the second embankment pattern PW2 not covered by the first insulating layer INS1). With respect to the second embankment pattern PW2, the third contact electrode CNE3 may be symmetrical to the second contact electrode CNE2, and may be substantially the same as or similar to the second contact electrode CNE2. Therefore, its repeated description will be omitted.

[0250] According to some embodiments, and with reference to Figure 9 The light-emitting element layer (LDL) may also include a dummy contact electrode CNE_D1 (or a dummy electrode). The dummy contact electrode CNE_D1 may be located on the first electrode ELT1 to contact the first electrode ELT1, and may be spaced apart from the first contact electrode CNE1. For example, the dummy contact electrode CNE_D1 may be positioned to contact the first electrode ELT1 in an area not covered by the first insulating layer INS1 (e.g., the second side surface of the first electrode ELT1 not covered by the first insulating layer INS1 or the second side surface SS2 of the first embankment pattern PW1 not covered by the first insulating layer INS1). The dummy contact electrode CNE_D1 may not contact any light-emitting element.

[0251] The third insulating layer INS3 may be completely formed and / or located on one surface of the substrate SUB to cover the first dam pattern PW1, the second dam pattern PW2 and the third dam pattern PW3, the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1, the second contact electrode CNE2 and the third contact electrode CNE3, and the dummy contact electrode CNE_D1. The third insulating layer INS3 may include, but is not limited to, a thin film encapsulation layer comprising at least one inorganic layer and / or an organic layer. Additionally, according to some embodiments, at least one overlay layer may further be located on the third insulating layer INS3.

[0252] According to some embodiments, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may consist of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include various types of currently known organic / inorganic insulating materials (including SiN). xFurthermore, the constituent materials of each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 are not specifically limited. Additionally, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may comprise different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may comprise the same insulating material.

[0253] For reference Figure 9 and Figure 10 As described, the thickness TH2 of the second insulating layer INS2 can be in the range of about 50% to about 150% of the thickness TH1 of the first dam pattern PW1 and / or the second dam pattern PW2, and the height H2 (or maximum height) of the upper surface US of the second insulating layer INS2 relative to the substrate SUB can be greater than or equal to the height H1 of the upper surface US of the first dam pattern PW1 and / or the second dam pattern PW2. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed substantially simultaneously or concurrently by a single etching process without a separate mask (and also without a separate exposure or photolithography process). The first contact electrode CNE1 and the second contact electrode CNE2 formed by the single etching process can be located on the side surfaces of the first electrode ELT1 and the second electrode ELT2 (or the first dam pattern PW1 and the second dam pattern PW2), respectively, and can be non-overlapping with the upper surfaces of the first electrode ELT1 and the second electrode ELT2 (or the first dam pattern PW1 and the second dam pattern PW2).

[0254] Figure 11A It is magnification Figure 8 Top view of region Q1. Figure 11B It shows along Figure 11A A cross-sectional view of an example of pixels captured by line II-II'. Figure 11A and Figure 11B In the middle, it is concentrated in the light-emitting element layer LDL (see Figure 9 (), briefly showing the pixels.

[0255] First, refer to Figures 8 to 11A In the plan view, the distance between the first contact electrode CNE1 and the second contact electrode CNE2 in the first direction DR1 may not be constant, and may be changed in the second direction DR2 (or in the extension direction of the first embankment pattern PW1).

[0256] like Figure 11A As shown, the first distance D1 between the first contact electrode CNE1 and the second contact electrode CNE2 at the portion overlapping with the light-emitting element LD can be larger than the second distance D2 between the first contact electrode CNE1 and the second contact electrode CNE2 at the portion not overlapping with the light-emitting element LD.

[0257] like Figure 11B As shown, the height H2 of the second insulating layer INS2 stacked with the light-emitting element LD can be greater than the height H3 of the second insulating layer INS2 not stacked with the light-emitting element LD. That is, a step can be formed on the upper surface of the second insulating layer INS2 due to the light-emitting element LD. Therefore, the following will refer to... Figure 15F The thickness of the described photoresist (e.g., the photoresist formed on the second insulating layer INS2 to form the first contact electrode CNE1 and the second contact electrode CNE2) can be varied in the first direction DR1. For example, the photoresist can fill the recessed portions (or valleys) of the second insulating layer INS2, and the thickness of the photoresist in the portion not stacked with the light-emitting element LD can be greater than the thickness of the photoresist in the portion stacked with the light-emitting element LD. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 can be etched relatively more in the portion where the photoresist thickness is relatively small, and the first contact electrode CNE1 and the second contact electrode CNE2 can be etched relatively less in the portion where the photoresist thickness is relatively large. Therefore, the first distance D1 between the first contact electrode CNE1 and the second contact electrode CNE2 in the portion stacked with the light-emitting element LD can be greater than the second distance D2 between the first contact electrode CNE1 and the second contact electrode CNE2 in the portion not stacked with the light-emitting element LD.

[0258] Figures 12 to 14 It shows along Figure 8 Another example of a cross-sectional view of pixels intercepted by line I-I'. Figures 12 to 14 In the middle, it is shown that... Figure 9 The corresponding sectional view. In the following examples, the view will be omitted or simplified and included. Figure 9 The pixels in each embodiment have the same construction, and the differences between them will be mainly described. Parts not specifically described in other embodiments follow the embodiments described above.

[0259] First, refer to Figure 8 , Figure 9 and Figure 12 The light-emitting element layer LDL may also include a shielding layer SHL.

[0260] The first insulating layer INS1 may also be located on a portion of the second side surface SS2 and the upper surface US of the first embankment pattern PW1 (or the first electrode ELT1).

[0261] The shielding layer SHL can be located on the first insulating layer INS1, and can be located on a portion of the second side surface SS2 and the upper surface US of the first embankment pattern PW1 (or the first electrode ELT1). For example, the shielding layer SHL can be located in a plan view around the light-emitting area EMA (see...). Figure 8 The form of ) is located in the outer region of the luminescent area EMA, and can be combined with the embankment BNK (see Figure 8 The electrodes are stacked. Additionally, the shielding layer SHL can be formed to cover the upper portion of the first electrode ELT1 and the second electrode ELT2 in a region adjacent to the outer region of the light-emitting region EMA.

[0262] According to some embodiments, the shielding layer SHL can be a conductive pattern comprising at least one conductive material. For example, the shielding layer SHL can consist of at least one transparent conductive layer comprising a transparent conductive material (such as IZO), but is not limited thereto. That is, the shielding layer SHL can be composed of various conductive materials, and there are no specific limitations on the materials constituting it.

[0263] The shielding layer SHL allows the light-emitting elements (LDs) to be properly aligned within the light-emitting region EMA. For example, the shielding layer SHL can counteract the additional electric field generated between adjacent pixels PXL. Therefore, alignment of the light-emitting elements (LDs) in the outer regions of pixels PXL can be reduced or prevented, and the light-emitting elements (LDs) can be properly aligned within the light-emitting region EMA of each pixel PXL.

[0264] The shielding layer SHL can be in an electrically isolated floating state, but is not limited to this. For example, in other embodiments, the shielding layer SHL can be connected to a voltage source (e.g., a predetermined reference voltage source).

[0265] The dummy contact electrode CNE_D1 can be formed on one side surface (or inclined surface) of the shielding layer SHL, and the height of one end of the dummy contact electrode CNE_D1 (e.g., one end of the dummy contact electrode CNE_D1 that contacts the shielding layer SHL) can be almost equal to the height of the upper surface of the shielding layer SHL.

[0266] Reference Figure 9 and Figure 13 The height H2_1 (e.g., maximum height) of the upper surface of the second insulating layer INS2_1 (or insulating pattern) relative to the substrate SUB can be greater than the height H1 of the first dike pattern PW1 and / or the second dike pattern PW2.

[0267] For example, the height H2_1 of the second insulating layer INS2_1 stacked with the light-emitting element LD can be substantially equal to the height of the upper surface of the first electrode ELT1. For example, the height H3_1 of the second insulating layer INS2_1 not stacked with the light-emitting element LD can be substantially equal to the height H1 of the upper surface of the first embankment pattern PW1.

[0268] In this configuration, the first contact electrode CNE1 and the second contact electrode CNE2 can be appropriately configured to be separated from each other on the upper surface of the second insulating layer INS2_1. Furthermore, excessive etching of the portion of the first contact electrode CNE1 that contacts the first electrode ELT1 can be reduced or prevented, the first contact electrode CNE1 can be more stably connected to the first electrode ELT1, and the contact resistance between the first contact electrode CNE1 and the first electrode ELT1 can be reduced.

[0269] Reference Figure 9 and Figure 14 The passivation layer PSV can be omitted in the pixel circuit layer PCL_1.

[0270] The first dike pattern PW1_1 and the second dike pattern PW2_1 (and the third dike pattern PW3_1) can be formed directly on the interlayer insulating layer (ILD).

[0271] For example, the first dam pattern PW1_1 can cover the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1. One of the first transistor electrode ET1 and the second transistor electrode ET2 can be connected to or electrically connected to the first electrode ELT1 through the first contact hole CH1_1 passing through the first dam pattern PW1_1. For example, the second dam pattern PW2_1 can cover the bridging pattern BRP. The second power line PL2 can be connected to or electrically connected to the second electrode ELT2 through the bridging pattern BRP and the second contact hole CH2_1 passing through the second dam pattern PW2_1. That is, refer to Figures 6A to 7B The circuit elements of the pixel driving circuit PXC described can be superimposed with the first dike pattern PW1_1 and the second dike pattern PW2_1 (and can also be superimposed with the third dike pattern PW3_1).

[0272] The layer including the first dam pattern PW1_1 and the second dam pattern PW2_1 can planarize the upper surface of the pixel circuit layer PCL_1 and also provide space in which the light-emitting element LD can be positioned. Since the passivation layer PSV is omitted, the manufacturing process of the display device can be simplified.

[0273] Figures 15A to 15H These are cross-sectional views sequentially illustrating methods of manufacturing a display device according to some embodiments of the present disclosure. Figures 15A to 15H In China, focus on reference Figure 9 The structure of some of the constituent elements of the pixel circuit layer PCL described is schematically shown, and repeated detailed descriptions will be omitted.

[0274] First, refer to Figure 9 , Figure 13 and Figure 15AA pixel circuit layer PCL (e.g., a pixel circuit layer PCL including a passivation layer PSV) can be prepared to be formed on a substrate SUB.

[0275] A first dam pattern PW1, a second dam pattern PW2 (and a third dam pattern PW3) can be formed on the pixel circuit layer PCL. For example, see reference Figure 9 As described, a first dam pattern PW1 and a second dam pattern PW2 can be formed on the passivation layer PSV of the pixel circuit layer PCL. For example, as shown in reference... Figure 14 As described, a first dam pattern PW1 and a second dam pattern PW2 can be positioned on the interlayer insulating layer (ILD). The first dam pattern PW1 and the second dam pattern PW2 can be positioned spaced apart from each other in a first direction DR1.

[0276] Reference Figure 15B A first electrode ELT1 and a second electrode ELT2 can be formed on a first dam pattern PW1 and a second dam pattern PW2, respectively. The first electrode ELT1 and the second electrode ELT2 can be positioned spaced apart from each other. The first electrode ELT1 can be superimposed on the first dam pattern PW1 and can cover the first dam pattern PW1. The second electrode ELT2 can be superimposed on the second dam pattern PW2 and can cover the second dam pattern PW2.

[0277] Reference Figure 15C A first insulating layer INS1 can be formed on the first electrode ELT1, the second electrode ELT2, and the passivation layer PSV. The first insulating layer INS1 can be formed on the passivation layer PSV or the first insulating layer INS1 can be patterned so that the first insulating layer INS1 covers a region of the first electrode ELT1 and the second electrode ELT2 and covers the passivation layer PSV exposed by the first electrode ELT1 and the second electrode ELT2.

[0278] Reference Figure 15D The light-emitting element LD can be located between the first dike pattern PW1 and the second dike pattern PW2, and the second insulating layer INS2_1 can be located on the light-emitting element LD.

[0279] The light-emitting element (LD) can be supplied or positioned to a reference. Figure 8 The light-emitting region EMA is described. The light-emitting element LD can be dispersed in a solution (or solvent) and can be supplied to the light-emitting region EMA by inkjet printing or the like. However, the method of supplying the light-emitting element LD is not limited to this, and various other methods besides those described above can be used to supply the light-emitting element LD to the light-emitting region EMA.

[0280] Next, an alignment voltage can be applied to the first electrode ELT1 and the second electrode ELT2, and an electric field can be formed in the light-emitting region EMA. Therefore, the light-emitting element LD can self-align between the first electrode ELT1 and the second electrode ELT2.

[0281] A ground voltage GND can be applied to the first electrode ELT1, and an AC voltage AC can be applied to the second electrode ELT2. Alternatively, an AC voltage AC can be applied to the first electrode ELT1, and a ground voltage GND can be applied to the second electrode ELT2.

[0282] The supply and alignment steps of the light-emitting element (LD) can be performed sequentially or substantially simultaneously. For example, the LD can be aligned by supplying an alignment voltage to the first electrode ELT1 and the second electrode ELT2 while simultaneously supplying the LD to the light-emitting region EMA. Alternatively, after supplying the LD to the light-emitting region EMA, the LD can be aligned by supplying an alignment voltage to the first electrode ELT1 and the second electrode ELT2. In other words, there are no specific limitations on the order and / or method of supplying and aligning the LD.

[0283] After aligning the light-emitting element LD, the light-emitting element LD can be stably arranged between the first electrode ELT1 and the second electrode ELT2 by evaporating the solution or by using another method to remove the solution.

[0284] A second insulating layer INS2_1 can be formed on the light-emitting element LD, that is, the second insulating layer INS2_1 is formed on the light-emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2. The second insulating layer INS2_1 can fill the space between the first insulating layer INS1 and the light-emitting element LD.

[0285] The second insulating layer INS2_1 can be partially patterned to expose the first end EP1 and the second end EP2 of the light-emitting element LD. Alternatively, when forming the pattern of the second insulating layer INS2_1, the first insulating layer INS1 can be partially removed. In this case, the first electrode ELT1 and the second electrode ELT2 can be exposed.

[0286] For reference Figure 10 As described, the thickness TH2 of the second insulating layer INS2_1 can be in the range of about 50% to about 150% of the thickness TH1 of the first dike pattern PW1 and / or the second dike pattern PW2. Additionally, as referenced... Figure 10As described, relative to the substrate, the height (or maximum height) of the upper surface of the second insulating layer INS2_1 can be greater than or approximately equal to the height H1 of the upper surface of the first embankment pattern PW1. For example, relative to the substrate, the height H2 of the upper surface of the second insulating layer INS2_1 stacked with the light-emitting element LD can be greater than the height H1 of the upper surface of the first embankment pattern PW1, and can be approximately equal to the height of the upper surface of the first electrode ELT1. For example, relative to the substrate, the height H3 of the upper surface of the second insulating layer INS2_1 not stacked with the light-emitting element LD can be approximately equal to the height H1 of the upper surface of the first embankment pattern PW1.

[0287] Reference Figure 15E The contact electrode layer CNE0 (or mother electrode layer) can be completely formed on the passivation layer PSV so that the contact electrode layer CNE0 covers the second insulating layer INS2_1, the first insulating layer INS1, the first electrode ELT1, and the second electrode ELT2.

[0288] Reference Figure 15F A photoresist PR (or photoresist layer) can be formed on the contact electrode layer CNE0. The photoresist PR may include, but is not limited to, a positive photoresist composition.

[0289] Photoresist PR can be filled between the first embankment pattern PW1 and the second insulating layer INS2_1, and between the second embankment pattern PW2 and the second insulating layer INS2_1. Therefore, the thickness TH_P2 of the photoresist PR that is not superimposed on the second insulating layer INS2_1 (and not superimposed on the first embankment pattern PW1 and the second embankment pattern PW2) can be larger than the thickness TH_P1 of the photoresist PR that is superimposed on the second insulating layer INS2_1 (or superimposed on the first embankment pattern PW1 and the second embankment pattern PW2). In the etching process described later, the thickness of the second insulating layer INS2_1 should be large enough that the photoresist PR that is not superimposed on the second insulating layer INS2_1 (and not superimposed on the first embankment pattern PW1 and the second embankment pattern PW2) is not unintentionally removed (e.g., only the photoresist PR superimposed on the second insulating layer INS2_1 and / or the first embankment pattern PW1 and the second embankment pattern PW2 can be removed).

[0290] Reference Figure 15G A portion of the photoresist PR and a portion of the contact electrode layer CNE0, which are superimposed on the second insulating layer INS2_1 (and the first dam pattern PW1 and the second dam pattern PW2), can be removed through an etching process (or etching technique). For example, by using a dry etching process with gas plasma or active gas, it is possible to etch approximately completely at a given thickness (e.g., the thickness from the upper surface of the photoresist PR to the upper surface of the second insulating layer INS2_1 on the third-direction DR3). Figure 15FThe structure shown is such that the portion of the contact electrode layer CNE0 that overlaps with the second insulating layer INS2_1 can be removed, thus forming the first contact electrode CNE1 and the second contact electrode CNE2. Even if the etching rate of the photoresist PR differs from that of the contact electrode layer CNE0, the photoresist PR that is not overlapped with the first dam pattern PW1 and the second dam pattern PW2 (e.g., the relatively thick portion of the photoresist PR) can be retained in the etching process, and the first contact electrode CNE1 and the second contact electrode CNE2 underneath can be protected.

[0291] Alternatively, the portion of the contact electrode layer CNE0 that overlaps with the first dam pattern PW1 and the second dam pattern PW2 can be removed to form a dummy contact electrode CNE_D1 and a third contact electrode CNE3.

[0292] For reference, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed concurrently or substantially simultaneously using exposure techniques. For example, by removing the portion of the contact electrode layer CNE0 that overlaps with the second insulating layer INS2_1 using an exposure unit, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed substantially simultaneously or concurrently. However, because the second insulating layer INS2_1 can adequately expose both ends of the light-emitting element LD, the width of the upper surface of the second insulating layer INS2_1 (e.g., the width in the first direction DR1) can be smaller than the length of the light-emitting element LD, and it may not be easy to separate the contact electrode layer CNE0 from the upper surface of the second insulating layer INS2_1 depending on the specifications (or resolution or quality) of the exposure unit. Therefore, according to the manufacturing method of the prior art, the first contact electrode CNE1 can be formed first, then a separate insulating layer can be formed on the first contact electrode CNE1, and then the second contact electrode CNE2 can be formed on the insulating layer. In this case, the manufacturing process of the display device becomes complicated.

[0293] Therefore, by utilizing the step (or thickness deviation) of the photoresist PR caused by the second insulating layer INS2_1 and etching techniques, the manufacturing method of the display device according to some embodiments of the present disclosure can more simply and easily form the first contact electrode CNE1 and the second contact electrode CNE2 without further processes (and masks) and without being limited by the exposure unit.

[0294] Reference Figure 15H Residues of photoresist PR can be removed. For example, by using a separate stripper (e.g., a stripper for removing dry etching residues, a photoresist stripper, etc.), the photoresist PR retained in areas not superimposed with the first dam pattern PW1 and the second dam pattern PW2 can be removed.

[0295] Next, a third insulating layer INS3 can be completely formed on one surface of the substrate SUB, such that the third insulating layer INS3 covers the first dam pattern PW1 and the second dam pattern PW2 (and the third dam pattern PW3), the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1, the second contact electrode CNE2 and the third contact electrode CNE3, and the dummy contact electrode CNE_D1.

[0296] For reference Figures 15A to 15H The manufacturing method of the display device according to some embodiments of the present disclosure describes a method in which a second insulating layer INS2_1 is formed to have a thickness ranging from about 50% to about 150% of the thickness of the first dam pattern PW1 (and / or the second dam pattern PW2), a photoresist PR is formed on the contact electrode layer CNE0, and a portion of the photoresist PR and a portion of the contact electrode layer CNE0 (e.g., the portion overlapping with the second insulating layer INS2_1) can be removed by a dry etching technique to form a first contact electrode CNE1 and a second contact electrode CNE2. That is, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed concurrently or substantially simultaneously without a separate mask. Therefore, the manufacturing process of the display device can be simplified.

[0297] Figure 16 It is shown that it includes Figure 5 A top view of an example of pixels in a display device. Figure 16 It shows the relationship with Figure 8 The corresponding attached diagram. Figure 17 It shows along Figure 16 A cross-sectional view of an example of pixels captured by line III-III'. Figure 17 It shows the relationship with Figure 9 The corresponding diagram.

[0298] First, refer to Figure 8 and Figure 16 Pixel PXL_1 and Figure 8 The difference between pixel PXL and pixel PXL_1 is that pixel PXL_1 includes a first contact electrode CNE1_1 and a second contact electrode CNE2_1. Because, apart from the first contact electrode CNE1_1 and the second contact electrode CNE2_1, pixel PXL_1 is otherwise substantially equivalent to or similar to [the other pixel]. Figure 8 The pixel value is PXL, so repeated descriptions will be omitted.

[0299] The first contact electrode CNE1_1 may be formed on the first end EP1 of the light-emitting element LD and on at least one corresponding region of the first electrode ELT1, so that the first end EP1 of the light-emitting element LD is physically connected to and / or electrically connected to the first electrode ELT1. The width of the first contact electrode CNE1_1 in the first direction DR1 may be larger than the width of the first embankment pattern PW1 in the first direction DR1.

[0300] Similarly, the second contact electrode CNE2_1 can be formed on the second end of the light-emitting element LD and on at least one corresponding region of the second electrode ELT2, so that the second end of the light-emitting element LD is physically connected to and / or electrically connected to the second electrode ELT2. The width of the second contact electrode CNE2_1 in the first direction DR1 can be larger than the width of the second embankment pattern PW2 in the first direction DR1.

[0301] Reference Figure 9 and Figure 17 Pixel PXL_1 and Figure 9 The difference between pixel PXL and pixel PXL is that pixel PXL_1 includes a second insulating layer INS2_2 (or insulating pattern), a first contact electrode CNE1_1 and a second contact electrode CNE2_1.

[0302] Because, apart from the second insulating layer INS2_2, the first contact electrode CNE1_1, and the second contact electrode CNE2_1, pixel PXL_1 is essentially equivalent to or similar to... Figure 9 The pixel value is PXL, so repeated descriptions will be omitted.

[0303] The thickness of the second insulating layer INS2_2 can be in the range of about 100% to about 150% of the thickness of the first dam pattern PW1 and / or the second dam pattern PW2. For example, when the thickness TH1 of the first dam pattern PW1 is about 2 μm, the thickness of the second insulating layer INS2_2 can be in the range of about 2 μm to about 3 μm, or it can be about 2 μm.

[0304] Relative to the substrate SUB, the height H2_2 of the upper surface of the second insulating layer INS2_2 can be greater than the height H1 of the first dam pattern PW1 and / or the second dam pattern PW2.

[0305] For example, the height H2_2 of the second insulating layer INS2 stacked with the light-emitting element LD can be greater than the height of the upper surface of the first electrode ELT1. For example, the height H3_2 of the second insulating layer INS2 not stacked with the light-emitting element LD can be greater than or substantially equal to the height of the upper surface of the first electrode ELT1.

[0306] In this configuration, the first contact electrode CNE1_1 can be continuously formed on the upper surface US of the first embankment pattern PW1 (or the first electrode ELT1) and on the first side surface SS1 and the second side surface SS2. That is, the first contact electrode CNE1_1 can cover the first embankment pattern PW1 (or the first electrode ELT1) and is not separated from the upper surface US of the first embankment pattern PW1.

[0307] Similarly, the second contact electrode CNE2_1 can be continuously formed on the upper surface and two side surfaces of the second embankment pattern PW2 (or the second electrode ELT2). That is, the second contact electrode CNE2_1 can cover the second embankment pattern PW2 (or the second electrode ELT2) and is not separated from the upper surface of the second embankment pattern PW2.

[0308] For reference Figure 16 and Figure 17 The thickness of the second insulating layer INS2_2 can be in the range of about 100% to about 150% of the thickness of the first dam pattern PW1 and / or the second dam pattern PW2, and the height of the upper surface of the second insulating layer INS2_2 relative to the substrate SUB can be greater than or equal to the height of the upper surfaces of the first dam pattern PW1 and the second dam pattern PW2 (or the upper surfaces of the first electrode ELT1 and the second electrode ELT2). Therefore, the corresponding contact area between the first contact electrode CNE1_1 and the first electrode ELT1, and the second contact electrode CNE2_1 and the second electrode ELT2, can be increased, allowing for a more stable connection between the first electrode ELT1, the second electrode ELT2, and the light-emitting element LD.

[0309] Figures 18A to 18C These are cross-sectional views sequentially illustrating methods of manufacturing a display device according to some embodiments of the present disclosure. Figures 18A to 18C In the middle, it is shown that... Figures 15F to 15H The corresponding attached diagram. Figures 18A to 18C In China, focus on reference Figure 17 The structure of some of the constituent elements of the pixel circuit layer PCL described is schematically shown, and repeated detailed descriptions will be omitted.

[0310] First, refer to Figure 17 and Figure 18A It is possible to prepare a structure including a passivation layer PSV (or a pixel circuit layer PCL formed on a substrate SUB), a first dam pattern PW1 and a second dam pattern PW2 (and a third dam pattern PW3), a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a light-emitting element LD, a second insulating layer INS2_2, and a contact electrode layer CNE0.

[0311] For reference Figures 15A to 15EThe described structure can be sequentially formed on the passivation layer PSV, including a first dam pattern PW1, a second dam pattern PW2 (and a third dam pattern PW3), a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a light-emitting element LD, a second insulating layer INS2_2, and a contact electrode layer CNE0.

[0312] For reference Figure 17 As described, the thickness of the second insulating layer INS2_2 can be in the range of about 100% to about 150% of the thickness of the first dike pattern PW1 and / or the second dike pattern PW2. (See reference...) Figure 17 As described, relative to the substrate SUB, the height of the upper surface US of the second insulating layer INS2_2 can be greater than the height H1 of the upper surface US of the first embankment pattern PW1, and can also be greater than the height of the upper surface of the first electrode ELT1.

[0313] A photoresist PR (or photoresist layer) can be formed on the contact electrode layer CNE0. The photoresist PR can fill the space between the first dam pattern PW1 and the second insulating layer INS2_2, and between the second dam pattern PW2 and the second insulating layer INS2_2. Simultaneously, because the upper surface of the second insulating layer INS2_2 protrudes further than the upper surfaces of the first electrode ELT1 and the second electrode ELT2 (or the upper surfaces of the first dam pattern PW1 and the second dam pattern PW2), the photoresist PR on the second insulating layer INS2_2 can diffuse toward the first electrode ELT1 and the second electrode ELT2, and the thickness of the photoresist PR superimposed on the second insulating layer INS2_2 can be smaller than the thickness of other portions of the photoresist PR (e.g., portions not superimposed on the second insulating layer INS2_2).

[0314] Reference Figure 18B The portion of the photoresist PR superimposed on the second insulating layer INS2_2 and a portion of the contact electrode layer CNE0 can be removed by an etching process (or etching technique). For example, by dry etching, it is possible to completely etch at a given thickness (e.g., the thickness on the third-direction DR3 from the upper surface of the photoresist PR superimposed on the second insulating layer INS2_2 to the upper surface of the second insulating layer INS2_2). Figure 18A The structure shown is such that the portion of the contact electrode layer CNE0 that overlaps with the second insulating layer INS2_2 can be removed to form the first contact electrode CNE1_1 and the second contact electrode CNE2_1.

[0315] Only the portion of the photoresist PR superimposed on the second insulating layer INS2_2 can be removed; for example, the photoresist PR superimposed on the first dam pattern PW1 and the second dam pattern PW2 can be retained. Therefore, the first contact electrode CNE1_1 can remain as a single electrode on the first dam pattern PW1 without being separated into multiple contact electrodes. Similarly, the second contact electrode CNE2_1 can remain as a single uniform electrode on the second dam pattern PW2, instead of multiple separate contact electrodes.

[0316] Reference Figure 18C This can remove photoresist PR residue. For example, photoresist PR residue in areas not overlapped with the second insulating layer INS2_2 can be removed by using a separate stripping solution.

[0317] Next, a third insulating layer INS3 can be completely formed on one surface of the substrate SUB, such that the third insulating layer INS3 covers the first dam pattern PW1 and the second dam pattern PW2 (and the third dam pattern PW3), the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, and the first contact electrode CNE1_1 and the second contact electrode CNE2_1.

[0318] For reference Figures 18A to 18C The manufacturing method of the display device according to some embodiments of the present disclosure describes a method for forming a second insulating layer INS2_2 with a thickness in the range of about 100% to about 150% of the thickness of the first dam pattern PW1 (and / or the second dam pattern PW2), and a photoresist PR can be formed on the contact electrode layer CNE0. Alternatively, the manufacturing method of the display device can be achieved by dry etching to form a first contact electrode CNE1 and a second contact electrode CNE2 that respectively cover the first dam pattern PW1 and the second dam pattern PW2 in a plan view by removing only a portion of the photoresist PR and a portion of the contact electrode layer CNE0 (e.g., the portion overlapping with the second insulating layer INS2_2).

[0319] The technical scope of this disclosure can be determined by the technical scope of the appended claims. Furthermore, all changes or modifications within the meaning and scope of the claims and their equivalents shall be construed as being included within the scope of this disclosure.

Claims

1. A display device, the display device comprising: Base; The first and second dike patterns are on the base and are spaced apart from each other; A first electrode and a second electrode, wherein the first electrode is on the first embankment pattern and the second electrode is on the second embankment pattern; A light-emitting element is located between the first embankment pattern and the second embankment pattern; An insulating pattern is formed on the light-emitting element, exposing a first end and a second end of the light-emitting element that are respectively adjacent to the first dam pattern and the second dam pattern; The third electrode contacts the first electrode and the first end of the light-emitting element; as well as The fourth electrode contacts the second electrode and the second end of the light-emitting element. The thickness of the insulating pattern is in the range of 50% to 150% of the thickness of the first embankment pattern. Wherein, relative to the substrate, the maximum height of the upper surface of the insulating pattern is greater than or equal to the maximum height of the upper surface of the first electrode or the second electrode, and The insulating pattern includes side surfaces facing the first electrode and the second electrode respectively, and an upper surface between the side surfaces, wherein the third electrode and the fourth electrode do not overlap with the upper surface of the insulating pattern.

2. The display device according to claim 1, wherein, The third electrode and the fourth electrode are made of the same material and are formed on the same layer.

3. The display device according to claim 1, wherein, The maximum height of the upper surface of the insulating pattern relative to the substrate is equal to the maximum height of the upper surface of the first electrode.

4. The display device according to claim 1, wherein, The first embankment pattern includes a first side surface facing the first end of the light-emitting element and an upper surface parallel to the upper surface of the substrate. The third electrode is located on the first side surface of the first embankment pattern.

5. The display device according to claim 4, wherein, The third electrode is not superimposed on the upper surface of the first embankment pattern.

6. A method for manufacturing a display device, the method comprising the following steps: A first dike pattern and a second dike pattern are formed on the base; A first electrode and a second electrode are formed on the first embankment pattern and the second embankment pattern, respectively; Align the light-emitting elements between the first embankment pattern and the second embankment pattern; An insulating pattern is formed on the light-emitting element to expose a first end and a second end of the light-emitting element, wherein the first end and the second end are adjacent to the first embankment pattern and the second embankment pattern, respectively. An electrode layer covering the first electrode, the second electrode, and the insulating pattern is formed on the substrate; A photoresist is formed on the electrode layer; as well as By using an etching technique to remove at least a portion of the photoresist and a first portion of the electrode layer overlapping the insulating pattern, a third and fourth electrode are formed from the electrode layer. The thickness of the insulating pattern is in the range of 50% to 150% of the thickness of the first embankment pattern, and Wherein, relative to the substrate, the maximum height of the upper surface of the insulating pattern is greater than or equal to the maximum height of the upper surface of the first electrode or the second electrode.

7. The manufacturing method according to claim 6, wherein, The steps of forming the third electrode and the fourth electrode include: forming a dummy electrode from the electrode layer by removing the portion of the electrode layer that overlaps with the first embankment pattern, the dummy electrode being spaced apart from the third electrode.

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