Ceramic electronic component, method for manufacturing the same, and circuit substrate

Abstract

This invention provides a ceramic electronic component capable of readily forming external electrodes, including a sintered substrate layer and a plating layer, on a ceramic body, a method for manufacturing the same, and a circuit board. The ceramic electronic component of this invention includes a ceramic body and a pair of external electrodes. The ceramic body includes a pair of end faces and side faces connecting the pair of end faces. The side faces are composed of a pair of end regions adjacent to the pair of end faces and an intermediate region located between the pair of end regions. The pair of external electrodes covers the pair of end faces and the pair of end regions of the side faces, and includes a pair of substrate layers and a pair of plating layers. The pair of substrate layers have an outer surface with a surface roughness Ra difference of less than 40 nm from the intermediate region of the side faces. The pair of plating layers cover the outer surfaces of the pair of substrate layers and have a pair of extension regions extending from the outer surfaces of the pair of substrate layers to the intermediate region of the side faces. Preferably, the contact angle between the pair of extensions and the intermediate region of the side faces is an acute angle.

Description

Technical Field

[0001] The present invention relates to a ceramic electronic component having a pair of external electrodes, a method for manufacturing the same, and a circuit board. Background Technology

[0002] Patent Document 1 discloses a multilayer ceramic capacitor having external electrodes including a base layer and a plating layer. In the manufacturing method of the multilayer ceramic capacitor disclosed in Patent Document 1, a base layer is formed on a ceramic body by sintering a conductive paste, and a plating layer is formed on the base layer using a wet plating method.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-201106 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] However, in the stacked ceramic capacitors with a plating layer disposed on the ceramic body through a substrate layer as described above, the plating layer is prone to defects. In response, the inventors of this application have discovered that by performing a specific pretreatment on the ceramic body to which the substrate layer is formed, the occurrence of plating defects can be reduced.

[0008] In view of the above, the object of the present invention is to provide a ceramic electronic component capable of forming an external electrode including a base layer and a plating layer on a ceramic body, a method for manufacturing the same, and a circuit board.

[0009] Means for solving technical problems

[0010] To achieve the above objectives, one embodiment of the present invention provides a ceramic electronic component comprising a ceramic body and a pair of external electrodes.

[0011] The ceramic body includes a pair of end faces and a side surface connecting the pair of end faces, the side surface being composed of a pair of end regions adjacent to the pair of end faces and an intermediate region located between the pair of end regions.

[0012] The pair of external electrodes cover the pair of end regions of the pair of end faces and the pair of side faces, including a pair of base layers and a pair of plating layers. The pair of base layers have an outer surface with a surface roughness Ra difference of less than 40 nm from the middle region of the side faces. The pair of plating layers cover the outer surface of the pair of base layers and have a pair of extensions extending from the outer surface of the pair of base layers to the middle region of the side faces.

[0013] Preferably, the contact angle between the pair of extensions and the middle region of the side surface is an acute angle.

[0014] In this ceramic electronic component, the extension of the plating extends from the outer surface of the substrate to the middle region of the side surface of the ceramic body. In this structure, by keeping the difference in surface roughness Ra between the outer surface of the substrate and the middle region of the side surface of the ceramic body small, the contact angle between the extension of the plating and the middle region of the side surface of the ceramic body can be reduced. This suppresses the peeling of the external electrode originating from the extension of the plating.

[0015] Yes, the base layer may be composed primarily of nickel.

[0016] Yes, the base layer may contain ceramic components.

[0017] It is possible that the difference in surface roughness Ra between the outer surface of the pair of substrate layers and the middle region of the side surface is less than 30 nm.

[0018] It is possible that the surface roughness Ra of the outer surface of the substrate layer is greater than 10 nm and less than 200 nm.

[0019] It is possible that the surface roughness Ra of the intermediate region is greater than 10 nm and less than 150 nm.

[0020] In one aspect of the method for manufacturing a ceramic electronic component according to the present invention, a composite sintered body is formed, the composite sintered body comprising a ceramic body and a pair of substrate layers, the ceramic body comprising a pair of end faces and side faces connecting the pair of end faces, the pair of substrate layers extending from the pair of end faces to the side faces and spaced apart from each other on the side faces.

[0021] The composite sintered body is subjected to blast polishing.

[0022] Using a wet plating method, a pair of coatings covering the outer surfaces of the pair of base layers are formed on the composite sintered body that has undergone the jet milling process.

[0023] In this technical solution, by performing jet milling on the composite sintered body composed of a ceramic body and a substrate layer, the outer surface of the substrate layer can be uniformly ground. This removes metal oxides that form on the outer surface of the substrate layer during firing, thus preventing uneven coating formation on the outer surface of the substrate layer. Furthermore, by utilizing jet milling, the difference in surface roughness Ra between the outer surface of the substrate layer and the middle region of the side surface of the ceramic body can be kept small, thereby obtaining a structure that suppresses the peeling of the external electrode.

[0024] Alternatively, the step of performing jet milling may include: making the difference in surface roughness Ra between the outer surface of the pair of substrates and the region between the pair of substrates in the side surface less than 40 nm.

[0025] Alternatively, the pair of coatings may have a pair of extensions extending from the outer surfaces of the pair of base layers to the side surfaces. In this case, the contact angle between the pair of extensions and the side surfaces may be acute.

[0026] Alternatively, the step of making the composite sintered body may include simultaneously firing the ceramic body and the pair of substrate layers.

[0027] One embodiment of the circuit board of the present invention includes the ceramic electronic component, a substrate body, a pair of terminals, and solder.

[0028] The pair of terminals are disposed on the substrate body.

[0029] The solder connects the pair of external electrodes and the pair of terminals.

[0030] Invention Effects

[0031] Using this invention, it is possible to provide ceramic electronic components capable of forming external electrodes, including a base layer and a coating, on a ceramic body, as well as a method for manufacturing the same and a circuit board. Attached Figure Description

[0032] Figure 1 This is a perspective view of a multilayer ceramic capacitor according to one embodiment of the present invention.

[0033] Figure 2 It is along the above-mentioned multilayer ceramic capacitor Figure 1 A cross-sectional view of line A-A'.

[0034] Figure 3 It is along the above-mentioned multilayer ceramic capacitor Figure 1 A cross-sectional view of line B-B'.

[0035] Figure 4 It is along the above-mentioned multilayer ceramic capacitor Figure 1 A cross-sectional view of the C-C' line.

[0036] Figure 5 This is a partial cross-sectional view showing an enlarged portion of the aforementioned multilayer ceramic capacitor.

[0037] Figure 6 This is a flowchart illustrating the manufacturing method of the aforementioned multilayer ceramic capacitor.

[0038] Figure 7 This is a three-dimensional view of the ceramic body produced in step S01.

[0039] Figure 8 This is a cross-sectional view of the composite unsintered body obtained in step S02.

[0040] Figure 9 This is a cross-sectional view of the composite sintered body obtained in step S03.

[0041] Figure 10 This is a partial cross-sectional view showing the coating formation process in step S05.

[0042] Figure 11 This is a graph showing the relationship between ΔRa and the defect rate of the coating.

[0043] Figure 12 This is a side view of the circuit board using the aforementioned multilayer ceramic capacitor.

[0044] Explanation of reference numerals in the attached figures

[0045] 10…Layered ceramic capacitor, 11…Ceramic body, 12, 13…Internal electrodes, 14, 15…External electrodes, 14a, 15a…Base layer, 14b, 15b…Plating, 14b1, 15b1…Extension, E…End face, S1, S2…Side surface, P1…End region of side surface, P2…Middle region of side surface, Q…Outer surface of base layer. Detailed Implementation

[0046] The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0047] In the accompanying figures, the X, Y, and Z axes, which are orthogonal to each other, are appropriately shown. The X, Y, and Z axes are the same in all the accompanying figures.

[0048] 1. Basic structure of multilayer ceramic capacitor 10

[0049] Figures 1-4 This is a diagram illustrating a multilayer ceramic capacitor 10 according to one embodiment of the present invention. Figure 1 This is a three-dimensional view of the multilayer ceramic capacitor 10. Figure 2 It is along Figure 1 A cross-sectional view of line A-A'. Figure 3 It is along Figure 1 A cross-sectional view of line B-B'. Figure 4 It is along Figure 1 A cross-sectional view of the C-C' line.

[0050] The multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14, and a second external electrode 15. The multilayer ceramic capacitor 10 can be configured in various sizes according to its application, etc. For example, the dimensions along the X-axis, Y-axis, and Z-axis can be 1.0 mm, 0.5 mm, and 0.5 mm, respectively.

[0051] The ceramic body 11 is formed as a hexahedron, which has an outer surface including a pair of end faces E, a pair of first side faces S1, and a pair of second side faces S2. In the ceramic body 11, the pair of end faces E extending parallel to the YZ plane are connected along the X-axis by the first side faces S1 extending parallel to the XY plane and the second side faces S2 extending parallel to the XZ plane.

[0052] The end face E and the side faces S1 and S2 of the ceramic body 11 are all formed as flat surfaces. In this embodiment, a flat surface is any surface that can be considered flat when viewed as a whole. It does not have to be a plane in the strict sense. For example, it also includes surfaces with small uneven shapes or gentle curved shapes that exist within a specified range.

[0053] Each external electrode 14, 15 covers both end faces E of the ceramic body 11 and is positioned opposite to the ceramic body 11 in the X-axis direction. The external electrodes 14, 15 extend from each end face E of the ceramic body 11 to the first side face S1 and the second side face S2, and are spaced apart from each other in the X-axis direction on the first side face S1 and the second side face S2.

[0054] The ceramic body 11 is formed of dielectric ceramic. The ceramic body 11 has a plurality of first internal electrodes 12 and second internal electrodes 13 covered by dielectric ceramic. The plurality of internal electrodes 12 and 13 are sheet-like extending along the XY plane and are alternately arranged along the Z-axis direction.

[0055] That is, in the ceramic body 11, internal electrodes 12 and 13 are formed in opposing regions of the ceramic layer in the Z-axis direction. The first internal electrode 12 is led out from the opposing region to one end face E and connected to the first external electrode 14. The second internal electrode 13 is led out from the opposing region to another end face E and connected to the second external electrode 15.

[0056] With this structure, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, the voltage is applied to the multiple ceramic layers in the opposing regions of the internal electrodes 12 and 13. Thus, in the multilayer ceramic capacitor 10, a charge corresponding to the voltage between the first external electrode 14 and the second external electrode 15 can be accumulated.

[0057] In the ceramic body 11, to increase the capacitance of each ceramic layer between the internal electrodes 12 and 13, a dielectric ceramic with a high dielectric constant can be used. Examples of dielectric ceramics with a high dielectric constant include perovskite structures containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0058] In addition, dielectric ceramics can also be composed of strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), etc.

[0059] 2. Detailed structure of the multilayer ceramic capacitor 10

[0060] The multilayer ceramic capacitor 10 of this embodiment has a structure that allows for the stable formation of good external electrodes 14 and 15 on the ceramic body 11. Therefore, the external electrodes 14 and 15 of this embodiment can easily achieve good connectivity with the internal electrodes 12 and 13, and good solder wetting during installation can be easily ensured.

[0061] Specifically, in the multilayer ceramic capacitor 10, the first external electrode 14 has a first base layer 14a and a first plating layer 14b, and the second external electrode 15 has a second base layer 15a and a second plating layer 15b. The base layers 14a and 15a are composed of sintered films of conductive materials, and the plating layers 14b and 15b are composed of wet-plated films of metals.

[0062] The base layers 14a and 15a are adjacent to the end face E and the side faces S1 and S2 of the ceramic body 11, forming the innermost layer of the external electrodes 14 and 15. By providing the base layers 14a and 15a in the external electrodes 14 and 15, the connection between the end face E of the ceramic body 11 and the internal electrodes 12 and 13 can be obtained more reliably.

[0063] like Figure 2 , 3 As shown, the sides S1 and S2 of the ceramic body 11 are composed of a pair of end regions P1 located at both ends in the X-axis direction and an intermediate region P2 located between the pair of end regions P1. The pair of end regions P1 are covered by the base layers 14a and 15a, while the intermediate region P2 is not covered by the base layers 14a and 15a.

[0064] The plating layers 14b and 15b cover the ceramic body 11 from the base layers 14a and 15a, forming the outermost layers of the external electrodes 14 and 15. In the multilayer ceramic capacitor 10, by setting the plating layers 14b and 15b, which have a higher solder wettability than the base layers 14a and 15a, as the outermost layers of the external electrodes 14 and 15, installation can be easily achieved.

[0065] The coatings 14b and 15b cover the entire outer surface Q of the base layers 14a and 15a, and have extensions 14b1 and 15b1 extending inward in the X-axis direction beyond the base layers 14a and 15a. The extensions 14b1 and 15b1 of the coatings 14b and 15b are in direct contact with the middle region P2 of the sides S1 and S2 of the ceramic body 11.

[0066] Figure 5 This is a partial cross-sectional view showing the enlarged extensions 14b1 and 15b1 of the plating layers 14b and 15b in the multilayer ceramic capacitor 10 and their vicinity. In the multilayer ceramic capacitor 10, the external electrodes 14 and 15 have the same structure; therefore, for ease of explanation, [the following is a partial cross-sectional view showing the extensions 14b1 and 15b1 of the plating layers 14b and 15b1 and their vicinity]. Figure 5 The reference numerals for the external electrodes 14 and 15 are also shown in the accompanying drawings.

[0067] In the multilayer ceramic capacitor 10, the difference in surface roughness Ra, ΔRa, is small in the middle region P2 between the outer surfaces Q of the substrate layers 14a and 15a and the side surfaces S1 and S2 of the ceramic body 11. Specifically, ΔRa is preferably 40 nm or less, and more preferably 30 nm or less. If ΔRa is small, the relationship between the surface roughness Ra of each surface can be arbitrary.

[0068] According to this structure, in the multilayer ceramic capacitor 10, the angle formed by the surfaces of the extensions 14b1 and 15b1 relative to the intermediate region P2 of the sides S1 and S2 of the ceramic body 11 is defined as follows: Figure 5 The contact angle θ shown is small. Specifically, it is preferable that the contact angle θ of the extensions 14b1 and 15b1 is an acute angle.

[0069] In the external electrodes 14 and 15, by making the contact angle θ of the extensions 14b1 and 15b1 acute, it is not easy to apply an external force in the direction that causes the extensions 14b1 and 15b1 to peel off from the middle region P2 of the sides S1 and S2 of the ceramic body 11. Therefore, the connection between the extensions 14b1 and 15b1 and the middle region P2 of the sides S1 and S2 of the ceramic body 11 is not easily hindered.

[0070] Therefore, in the multilayer ceramic capacitor 10, the peeling of the external electrodes 14 and 15 originating from the extensions 14b1 and 15b1 can be prevented. Thus, in the multilayer ceramic capacitor 10, adverse conditions such as reduced moisture resistance caused by the peeling of the external electrodes 14 and 15 can be prevented, thereby achieving high reliability.

[0071] The surface roughness Ra of the middle region P2 of the sides S1 and S2 of the ceramic body 11 can be measured, for example, in the area of ​​the ceramic body 11 that is exposed and not covered by the coatings 14b and 15b.

[0072] Furthermore, the surface roughness Ra of the outer surfaces Q of the substrate layers 14a and 15a can be measured, for example, by peeling off the plating layers 14b and 15b. The peeling off of the plating layers 14b and 15b can be performed, for example, using a plating stripping solution. More specifically, the plating layers 14b and 15b can be peeled off by stirring the plating stripping solution impregnated with the multilayer ceramic capacitor 10, thereby exposing the substrate layers 14a and 15a.

[0073] The surface roughness Ra of the middle region P2 of the sides S1 and S2 of the ceramic body 11 and the outer surface Q of the base layers 14a and 15a can be measured using a laser microscope (e.g., Olympus Corporation, model: OLS4100). Alternatively, the surface roughness Ra measurement can be performed, for example, within a defined rectangular area (250 μm × 250 μm) on each surface. Furthermore, to exclude outliers, for example, the surface roughness Ra can be measured at 5 locations with a measurement length of 250 μm each, and the average of the three middle values ​​after removing the maximum and minimum values ​​from the five obtained values ​​can be used. Here, surface roughness Ra refers to the arithmetic mean roughness.

[0074] On the outer surface Q of the substrate layers 14a and 15a, covering the entire region thereof, the surface roughness Ra is preferably 10 nm or more and less than 200 nm, more preferably 30 nm or more and less than 150 nm. Thus, in the multilayer ceramic capacitor 10, a coating layer 14b and 15b of uniform thickness can be easily formed covering the entire region of the outer surface Q of the substrate layers 14a and 15a.

[0075] Furthermore, in the middle region P2 of the sides S1 and S2 of the ceramic body 11, the surface roughness Ra is preferably 10 nm or more and less than 150 nm, more preferably 20 nm or more and less than 120 nm. As a result, it is easy to keep the contact angle θ between the extensions 14b1 and 15b1 and the middle region P2 of the sides S1 and S2 of the ceramic body 11 to be smaller.

[0076] The substrate layers 14a and 15a are typically formed with Ni (nickel) as the main component. However, the main components of the substrate layers 14a and 15a may also be, for example, Cu (copper), Pd (palladium), and Ag (silver). In this embodiment, the main component refers to the component with the highest content.

[0077] Furthermore, to improve the bonding strength between the substrate layers 14a and 15a and the ceramic body 11, it is preferable that the substrate layers 14a and 15a contain ceramic components. The ceramic components contained in the substrate layers 14a and 15a are typically dielectric ceramics of the same composition as the ceramic body 11, but other ceramics may be used as needed.

[0078] Furthermore, in the multilayer ceramic capacitor 10, the plating layers 14b and 15b are prone to unevenness due to the presence of low-conductivity metal oxides on the outer surfaces Q of the substrate layers 14a and 15a. Therefore, it is preferable to have less metal oxide on the outer surfaces Q of the substrate layers 14a and 15a.

[0079] The coatings 14b and 15b can be a single-layer structure consisting of a single coating film, or a stacked structure consisting of multiple coating films. As an example, the coatings 14b and 15b can be a stacked structure obtained by sequentially stacking a Cu (copper) film, a Ni (nickel) film, and a Sn (tin) film from the outer surface Q side of the substrate layers 14a and 15a.

[0080] 3. Manufacturing method of multilayer ceramic capacitor 10

[0081] Figure 6 This is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 10 according to this embodiment. Figures 7-11 This is a diagram illustrating the manufacturing process of the multilayer ceramic capacitor 10. Below, according to... Figure 6 And refer to appropriately Figures 7-11 The manufacturing method of the multilayer ceramic capacitor 10 is described.

[0082] 3.1 Step S01: Ceramic Body Production

[0083] In step S01, the process is as follows: Figure 7 The unfired ceramic body 111 is shown. The unfired ceramic body 111 can be obtained, for example, by stacking multiple ceramic sheets in the Z-axis direction and then hot-pressing them together. The unfired internal electrodes 112 and 113 can be configured by pre-printing a conductive paste with a predetermined pattern on the ceramic sheets.

[0084] Ceramic sheets are unfired dielectric green sheets obtained by forming ceramic slurry into sheet form. Ceramic sheets can be formed into sheet form, for example, using a roller coater or a doctor blade. The composition of the ceramic slurry is adjusted to obtain a ceramic body 11 with a specified composition.

[0085] 3.2 Step S02: Basement Formation

[0086] In step S02, unfired base layers 114a and 115a are formed on the unfired ceramic body 111 produced in step S01. Thus, an unfired base layer is obtained. Figure 8 The composite unsintered body 111a is shown. The base layers 114a and 115a can be formed, for example, by applying a conductive paste to the ceramic body 111.

[0087] In the composite unsintered body 111a, ceramic components can be incorporated into the base layers 114a and 115a, for example, by mixing ceramic powder into a conductive paste. As a result, a high degree of bonding between the base layers 14a and 15a and the ceramic body 11 can be obtained in the sintered composite body 11a.

[0088] 3.3 Step S03: Firing

[0089] In step S03, the composite unsintered body 111a obtained in step S02 is sintered. Thus, the composite unsintered body 111a is sintered to obtain... Figure 9 The composite sintered body 11a is shown. The firing of the composite unsintered body 111a can be carried out, for example, under a reducing atmosphere or a low oxygen partial pressure atmosphere. The firing conditions of the composite unsintered body 111a can be appropriately determined.

[0090] In step S03, the ceramic body 111 constituting the composite unsintered body 111a and the base layers 114a and 115a connected to the internal electrodes 112 and 113 exposed at the end face E of the ceramic body 111 are simultaneously fired. As a result, good connectivity between the internal electrodes 12 and 13 and the base layers 14a and 15a can be obtained in the fired composite sintered body 11a.

[0091] More specifically, the internal electrodes 112, 113 and the base layers 114a, 115a, which are mainly composed of metal, begin to shrink at a stage earlier than the ceramic body 111. However, the internal electrodes 112, 113 and the base layers 114a, 115a, which are already connected in the unfired stage, shrink as a whole, thereby making it easy to maintain their connection after sintering.

[0092] Therefore, in the multilayer ceramic capacitor 10, the connection between the internal electrodes 12 and 13 and the external electrodes 14 and 15 can be ensured. Consequently, in the multilayer ceramic capacitor 10, it is less likely that the capacitance will decrease or the equivalent series resistance (ESR) will increase due to poor connection between the internal electrodes 12 and 13 and the external electrodes 14 and 15.

[0093] 3.4 Step S04: Jet milling

[0094] In step S04, the composite sintered body 11a obtained in step S03 is subjected to jet grinding. In jet grinding, abrasive composed of fine particles is sprayed onto the composite sintered body 11a to grind the outer surfaces Q of the base layers 14a and 15a that constitute the outer surface of the composite sintered body 11a and the middle region P2 of the sides S1 and S2 of the ceramic body 11.

[0095] The abrasive used in the jet milling apparatus M only needs to have sufficiently high hardness relative to the composite sintered body 11a, and can be formed, for example, from zirconium oxide or alumina. Furthermore, the particle size of the abrasive only needs to be sufficiently small relative to the composite sintered body 11a, for example, it can be in the range of 10 μm to 1200 μm.

[0096] The inventors of this application have discovered that jet polishing is an excellent pretreatment for the composite sintered body 11a in order to form coatings 14b and 15b. That is, by performing jet polishing on the composite sintered body 11a, the entire outer surface of the composite sintered body 11a can be made into a state suitable for forming good coatings 14b and 15b.

[0097] More specifically, in jet polishing, by spraying a large quantity of abrasive particles composed of small, fine particles, each possessing its own energy, the impact applied to the outer surface of the composite sintered body 11a can be made uniform. Therefore, in jet polishing, regardless of the machinability of the surface being treated, uneven shapes can be smoothed out, i.e., the surface roughness Ra can be reduced.

[0098] Therefore, in the jet milling of the composite sintered body 11a, the surface roughness Ra can be reduced simultaneously for the outer surface Q of the base layer 14a and 15a, which is mainly composed of metal, and the middle region P2 of the side surfaces S1 and S2 of the ceramic body 11, which is mainly composed of ceramic, which have significantly different machinability.

[0099] Therefore, by jet milling the composite sintered body 11a, the difference ΔRa between the surface roughness Ra of the outer surfaces Q of the base layers 14a and 15a and the intermediate region P2 of the sides S1 and S2 of the ceramic body 11 can be reduced. That is, in the multilayer ceramic capacitor 10, a structure with a small ΔRa can be achieved by jet milling.

[0100] Furthermore, by jet milling the composite sintered body 11a, metal oxides generated on the outer surfaces Q of the substrate layers 14a and 15a during firing can be uniformly removed. As a result, the conductivity on the outer surfaces Q of the substrate layers 14a and 15a is improved, thus enabling uniform precipitation of metal using a wet plating method.

[0101] The surface roughness Ra of the outer surface of the composite sintered body 11a and the difference between the surface roughness Ra and ΔR can be adjusted by adjusting the conditions of the jet milling. Examples of jet milling conditions include, for instance, the type and size of the abrasive, the amount and speed of abrasive projection, and the processing time. Furthermore, the jet milling in step S04 can be either dry or wet, and any known technique can be applied as needed.

[0102] Here, we will describe tumbling and chemical polishing, which are representative polishing techniques used in the manufacturing process of the multilayer ceramic capacitor 10. Tumbling and chemical polishing cannot achieve the same state as jet polishing in this embodiment, where the entire outer surface of the composite sintered body 11a is made suitable for forming good plating layers 14b and 15b.

[0103] That is, during tumbling, the composite sintered bodies 11a collide with each other, thus applying large, uneven impacts to the outer surface of the composite sintered bodies 11a. Therefore, during tumbling, the difference in surface roughness Ra ΔRa tends to increase in the middle region P2 between the outer surfaces Q of the base layers 14a and 15a with significantly different workability and the sides S1 and S2 of the ceramic body 11.

[0104] In chemical polishing, the outer surface of the composite sintered body 11a is dissolved. The unevenness on the outer surface Q of the base layers 14a and 15a is amplified by this dissolution, thus increasing the surface roughness Ra. Consequently, the coatings 14b and 15b formed on the outer surface Q of the base layers 14a and 15a are prone to becoming uneven.

[0105] Alternatively, chemical polishing can dissolve and remove the metal oxides formed on the outer surface Q of the base layers 14a and 15a during firing. However, during chemical polishing, the dissolution of the ceramic body 11 also occurs simultaneously with the dissolution of the metal oxides, which can easily lead to poor shape or short lifespan of the multilayer ceramic capacitor 10.

[0106] 3.5 Step S05: Coating Formation

[0107] In step S05, coatings 14b and 15b are formed on the composite sintered body 11a, which underwent spray milling in step S04. The coatings 14b and 15b are formed using an electrolytic or electroless wet plating method. Thus, the external electrodes 14 and 15 are completed, obtaining... Figures 1-4 The stacked ceramic capacitor 10 shown.

[0108] Figure 10 This is a diagram illustrating the process of step S05. On the outer surfaces Q of the highly conductive substrate layers 14a and 15a, the growth of coatings 14b and 15b is promoted. Furthermore, the conductivity on the outer surfaces Q of the substrate layers 14a and 15a is uniform, and the overall surface roughness Ra is small; therefore, the growth of coatings 14b and 15b proceeds uniformly.

[0109] On the other hand, it is difficult to form coatings 14b and 15b in the middle region P2 of the sides S1 and S2 of the ceramic body 11, which have low conductivity. Therefore, coatings 14b and 15b will not be formed in most of the area of ​​the middle region P2 of the sides S1 and S2 of the ceramic body 11, which extends centrally in the X-axis direction.

[0110] However, in the middle region P2 of the sides S1 and S2 of the ceramic body 11, metal precipitation is induced (induced) by the precipitation of metal in the outer surface Q of the base layers 14a and 15a, resulting in metal precipitation at both ends in the X-axis direction adjacent to the base layers 14a and 15a. As a result, extensions 14b1 and 15b1 of the coatings 14b and 15b are formed.

[0111] In particular, in this embodiment, the surface roughness Ra in the middle region P2 of the sides S1 and S2 of the ceramic body 11 is close to that of the outer surface Q of the base layers 14a and 15a, that is, it has the same smoothness. Therefore, the middle region P2 of the sides S1 and S2 of the ceramic body 11 together with the outer surface Q of the base layers 14a and 15a constitutes a series of smooth surfaces.

[0112] Therefore, in the middle region P2 of the sides S1 and S2 of the ceramic body 11, the growth of the extensions 14b1 and 15b1 at both ends in the X-axis direction is promoted by the growth force of the coatings 14b and 15b on the outer surfaces Q of the base layers 14a and 15a. As a result, the contact angle θ of the extensions 14b1 and 15b1 decreases.

[0113] 4. Examples and Comparative Examples

[0114] As embodiments and comparative examples of the present invention, 100 samples of multilayer ceramic capacitors 10 with different surface roughness Ra differences ΔRa were produced using the same manufacturing method as described above. In each multilayer ceramic capacitor 10, the configurations other than the surface roughness Ra were identical.

[0115] For each of the multilayer ceramic capacitors 10, the presence of defects such as unevenness or peeling of the plating layers 14b and 15b is evaluated, and the number of samples with defects in the plating layers 14b and 15b is counted. Figure 11 The figure represents the result. For each of the multilayer ceramic capacitors 10, it shows a plot with the difference in surface roughness Ra ΔRa on the horizontal axis and the defect rate of the plating layers 14b and 15b on the vertical axis.

[0116] like Figure 11As shown, for the multilayer ceramic capacitor 10 with a surface roughness Ra difference ΔRa of less than 40 nm, no defects in the plating layers 14b and 15b were observed. However, for the multilayer ceramic capacitor 10 with a surface roughness Ra difference ΔRa exceeding 40 nm, a trend was observed where defects in the plating layers 14b and 15b occurred more frequently as the surface roughness Ra difference ΔRa increased.

[0117] Furthermore, it is known that in the multilayer ceramic capacitor 10 with a surface roughness Ra difference ΔRa of 30 nm or less, exceptionally high solder wettability can be obtained, and the plating layers 14b and 15b can be formed more effectively. Additionally, it is known that in the multilayer ceramic capacitor 10 with a surface roughness Ra difference ΔRa of 30 nm or less, the stress applied to the end regions P1 and the middle region P2 of the side surfaces S1 and S2 is equal during the formation of the plating layers 14b and 15b in the ceramic body 11, thus reducing the likelihood of cracking.

[0118] Furthermore, to achieve a surface roughness difference ΔRa of less than 10 μm, it is necessary to increase the processing time of jet grinding and improve the precision of grinding conditions such as abrasive particle size, thus resulting in a significant increase in manufacturing costs. Therefore, a surface roughness difference ΔRa of 10 μm or more is preferred.

[0119] 5. Other implementation methods

[0120] The embodiments of the present invention have been described above, but the present invention is not limited to the embodiments described above, and various modifications can be made.

[0121] For example, the present invention can be applied not only to multilayer ceramic capacitors, but also to all ceramic electronic components having a structure including a pair of external electrodes. Examples of ceramic electronic components to which the present invention can be applied, besides multilayer ceramic capacitors, include, for example, chip varistors, chip thermistors, and multilayer inductors.

[0122] Furthermore, the ceramic electronic components of this invention can be used to construct the circuit board of this invention. As an example, Figure 12 The circuit board 200 shown includes: a multilayer ceramic capacitor 10 as described in the above embodiment; a substrate body 201; a pair of terminals 202; and solder 203. The pair of terminals 202 are disposed on the substrate body 201. External electrodes 14 and 15 of the multilayer ceramic capacitor 10 are respectively bonded to the pair of terminals 202 via solder 203. In the circuit board 200, the plating layers 14b and 15b of the external electrodes 14 and 15 have high solder wettability; therefore, a more reliable bonding between the external electrodes 14 and 15 and the pair of terminals 202 via solder 203 can be obtained.

Claims

1. A ceramic electronic component, characterized in that, include: A ceramic body includes a pair of end faces and side surfaces connecting the pair of end faces, the side surfaces being formed by a pair of end regions adjacent to the pair of end faces and an intermediate region located between the pair of end regions; and A pair of external electrodes covering a pair of end faces and a pair of end regions of the side faces, comprising a pair of base layers and a pair of plating layers, wherein the pair of base layers have an outer surface with a surface roughness Ra difference of less than 40 nm from the intermediate region of the side faces, and the pair of plating layers cover the outer surfaces of the pair of base layers and have a pair of extensions extending from the outer surfaces of the pair of base layers to the intermediate region of the side faces to contact the intermediate region of the side faces. The contact angle between the pair of extensions and the middle region of the side surface is an acute angle.

2. The ceramic electronic component as described in claim 1, characterized in that: The base layer is primarily composed of nickel.

3. The ceramic electronic component as described in claim 1 or 2, characterized in that: The base layer contains ceramic components.

4. The ceramic electronic component as described in any one of claims 1 to 3, characterized in that: The difference in surface roughness Ra between the outer surface of the pair of base layers and the middle region of the side surface is less than 30 nm.

5. The ceramic electronic component as described in any one of claims 1 to 4, characterized in that: The surface roughness Ra of the outer surface of the substrate layer is greater than 10 nm and less than 200 nm.

6. The ceramic electronic component as described in any one of claims 1 to 5, characterized in that: The surface roughness Ra of the intermediate region is greater than 10 nm and less than 150 nm.

7. A method for manufacturing a ceramic electronic component, characterized in that, include: The steps for fabricating a composite sintered body include a ceramic body and a pair of base layers. The ceramic body includes a pair of end faces and side faces connecting the pair of end faces. The pair of base layers extend from the pair of end faces to the side faces and are spaced apart from each other on the side faces. The composite sintered body is subjected to a jet milling step; and The step of forming a pair of coatings on the composite sintered body that has undergone the aforementioned spray milling using a wet plating method, wherein the pair of coatings covers the outer surfaces of the pair of substrate layers and has a pair of extensions extending from the outer surfaces of the pair of substrate layers to the side surfaces to contact the side surfaces. In the step of performing jet milling, the difference in surface roughness Ra between the outer surface of the pair of substrate layers and the region between the pair of substrate layers in the side surface is less than 40 nm. In the step of forming a pair of coatings, the pair of coatings are formed such that the contact angle between the pair of extensions and the side surface is an acute angle.

8. The method for manufacturing ceramic electronic components as described in claim 7, characterized in that: The steps for producing the composite sintered body include simultaneously firing the ceramic body and the pair of substrate layers.

9. A circuit board, characterized in that, include: A ceramic body includes a pair of end faces and a side surface connecting the pair of end faces, the side surface being formed by a pair of end regions adjacent to the pair of end faces and an intermediate region located between the pair of end regions; A pair of external electrodes covering the pair of end faces and the pair of end regions of the side faces, comprising a pair of base layers and a pair of plating layers, the pair of base layers having an outer surface with a surface roughness Ra difference of less than 40 nm from the middle region of the side faces, the pair of plating layers covering the outer surface of the pair of base layers and having a pair of extensions extending from the outer surface of the pair of base layers to the middle region of the side faces to contact the middle region of the side faces; substrate body; A pair of terminals disposed on the substrate body; and The solder that joins the pair of external electrodes and the pair of terminals The contact angle between the pair of extensions and the middle region of the side surface is an acute angle.

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