Semiconductor device with buried bias pad

Abstract

The present disclosure relates to a semiconductor device with a buried bias pad. An integrated circuit includes a bias pad located within a buried oxide layer. A semiconductor material layer is located above the buried oxide layer. The semiconductor material layer includes a doped region for a transistor. An interlayer dielectric (ILD) material covers the semiconductor material layer and a gate electrode of the transistor. The integrated circuit includes one or more bias contacts extending through the ILD material within an isolation region in the semiconductor material layer. The bias contact is electrically connected to a first bias pad. An isolation structure insulates the one or more bias contacts from the doped region of the transistor within the semiconductor material layer. The one or more bias contacts are electrically connected to an interconnect structure of the integrated circuit, which is configured to connect a voltage source to the bias pad.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices having buried bias pads. Background Art

[0002] The breakdown voltage of an integrated circuit is related to the thickness of the buried oxide layer between the substrate and the transistors of the integrated circuit. Increasing the breakdown voltage of the transistors of the integrated circuit increases the operating voltage window of the integrated circuit and prolongs the functional life of the integrated circuit. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a buried oxide layer located above a substrate; a semiconductor material layer located above the buried oxide layer, the semiconductor material layer comprising a plurality of doped regions; a transistor, wherein the transistor comprises a gate electrode and the plurality of doped regions; an isolation region located in the semiconductor material layer; an interlayer dielectric (ILD) material located above the semiconductor material layer and the gate electrode; a first bias contact extending through the ILD material and the isolation region to reach the buried oxide layer; and an interconnect structure electrically connected to the buried oxide layer through the first bias contact.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a buried oxide layer located above a substrate; a semiconductor material layer located above the buried oxide layer; a transistor having a source well and a drain well located in the semiconductor material layer; a first bias pad located in the buried oxide layer between the source well and the substrate; a second bias pad located in the buried oxide layer between the drain well and the substrate; a first deep trench isolation structure (DTI) ring, wherein the first bias pad is surrounded by the first DTI ring in the buried oxide layer; and a second DTI ring surrounding the second bias pad in the buried oxide layer, the first DTI ring and the second DTI ring sharing a central DTI segment.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: surrounding a first bias pad with a dielectric material; adding dopants to a semiconductor material layer above the first bias pad; depositing a gate dielectric material and a gate electrode material above a top surface of the semiconductor material layer; etching the gate dielectric material and the gate electrode material to isolate a first gate electrode above the semiconductor material layer; depositing an interlayer dielectric (ILD) material above the first gate electrode and the semiconductor material layer; etching at least one bias contact opening, the at least one bias contact opening reaching down to the first bias pad; filling the at least one bias contact opening with a bias contact material; and electrically connecting at least one bias contact to an interconnect structure of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a graph of breakdown voltage of an integrated circuit as a function of substrate voltage according to some embodiments.

[0007] Figure 1B is a flow chart of a method of manufacturing an integrated circuit according to some embodiments.

[0008] Figure 2 is a cross-sectional view of an integrated circuit according to some embodiments.

[0009] Figure 3 is a cross-sectional view of an integrated circuit according to some embodiments.

[0010] Figure 4 is a cross-sectional view of an integrated circuit according to some embodiments.

[0011] Figure 5 is a cross-sectional view of an integrated circuit according to some embodiments.

[0012] Fig. 6A is a top view of an integrated circuit according to some embodiments.

[0013] Figure 6B is a cross-sectional view of an integrated circuit according to some embodiments.

[0014] Fig. 7A is a top view of an integrated circuit according to some embodiments.

[0015] Figure 7B is a cross-sectional view of an integrated circuit according to some embodiments.

[0016] Fig. 8A is a top view of an integrated circuit according to some embodiments.

[0017] Figure 8B is a cross-sectional view of an integrated circuit according to some embodiments.

[0018] Fig. 9 is a cross-sectional view of an integrated circuit according to some embodiments.

[0019] Fig.10 is a cross-sectional view of an integrated circuit according to some embodiments.

[0020] Figures 11A-11H is a cross-sectional view of an integrated circuit during a manufacturing process according to some embodiments.

[0021] Figures 12A-12D is a cross-sectional view of an integrated circuit during a manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements, etc. are possible. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] Transient voltages or uncontrolled voltages in the substrate beneath the transistor affect the switching speed of the transistor and introduce noise into the signals generated by the integrated circuit. In some integrated circuits, the switching speed of the transistor is also affected by a circuit structure that adjusts the voltage to the substrate to prevent transient or uncontrolled voltage changes in the substrate beneath the transistor. In some embodiments of the present disclosure, a bias pad is used to adjust the voltage, and the bias pad is embedded in a buried oxide layer between the transistor of the integrated circuit and the substrate of the integrated circuit. The bias pad is formed by dividing a bias pad material layer (e.g., a semiconductor material layer, a metal layer, or a conductive material) into areas that meet the following items: the lateral dimensions of a transistor in the integrated circuit, a well of a transistor in the integrated circuit, or a cell area of ​​the integrated circuit having multiple transistors or other circuit elements. The bias pad is electrically connected to the integrated circuit interconnect structure. In some embodiments, the bias pad is electrically connected to a reference voltage (V ss ). In some embodiments, the bias pad is electrically connected to a voltage having a value between a reference voltage and ground. The bias pad is connected to an interconnect structure of the integrated circuit via a bias contact. The bias contact extends through a semiconductor material layer (which has a doped well for a transistor source and drain region) and through a portion of a buried oxide layer until the bias pad. The bias contact transmits or applies a voltage to the bias pad, and thereby generates or applies a characterized electrical environment to the transistor above the bias pad. In some embodiments, the applied voltage is a fixed voltage. In some embodiments, the bias pad is electrically connected to ground. In some embodiments, both the substrate and the bias pad receive the applied voltage, as described herein, to apply the characterized electrical environment to the transistor above the bias pad. The bias contact, the bias pad, and the method for manufacturing the bias contact and the bias pad are as follows.

[0025] Figure 1Ais a graph 100 of breakdown voltages of integrated circuits as a function of substrate voltages according to some embodiments. In graph 100, a breakdown voltage trend line 104 for N-type doped transistors is plotted in comparison to a breakdown voltage trend line 102 for P-type doped transistors. The voltage applied to the substrate is plotted along the horizontal axis of graph 100, with lower values ​​on the left side of the horizontal axis and higher voltage values ​​on the right side. The breakdown voltages of the transistors and the integrated circuit are plotted on the Y-axis or vertical axis of graph 100, with the lower breakdown voltage at the bottom of the vertical axis and the higher breakdown voltage at the top of the axis. In graph 100, the highest point on the breakdown voltage trend line indicates that the breakdown voltage maximums of the two types of transistors (e.g., P-type or PMOS and N-type or NMOS) each occur at different substrate voltages. In order to increase the overall breakdown voltage performance of the integrated circuit throughout the integrated circuit, the present disclosure describes a structure that includes individual bias pads located within a buried oxide layer for which a bias voltage (e.g., an applied voltage, similar to Figure 1A In some embodiments, multiple bias pads are located in the buried oxide layer under different sides of the transistor to accommodate different bias breakdown values ​​of the N-well or P-well in the transistor structure, respectively.

[0026] Figure 1B is a flow chart of a method 140 for manufacturing an integrated circuit according to some embodiments. The method 140 includes an operation 142 in which a first oxide layer is deposited over a substrate of the integrated circuit. The execution of operation 142 corresponds to Fig.11ADeposition of the first oxide layer 1106 in, as described below. In some embodiments, the substrate is a semiconductor material (e.g., silicon, doped silicon, GaAs, or another semiconductor material). In some embodiments, the substrate is a P-doped substrate. In some embodiments, the substrate is an N-doped substrate. In some embodiments, the substrate is a rigid crystalline material that is not a semiconductor material (e.g., diamond, sapphire, aluminum oxide (Al2O3), etc.), and the integrated circuit is manufactured on this material. In some embodiments, the substrate is subject to leakage current between the wells of the transistors or other elements of the integrated circuit; in these embodiments, an insulating layer (e.g., a buried oxide layer) is deposited over the semiconductor material to electrically isolate the substrate from the transistors of the integrated circuit. By reducing the leakage current by manufacturing a buried oxide layer over the substrate, the power consumption of the integrated circuit during circuit operation and during the idle time period of the integrated circuit is reduced. In some integrated circuits, the buried oxide layer is a single layer of insulating material over the top surface of the substrate. In the present disclosure, the buried oxide layer includes at least two layers of insulating material deposited in a separate insulating material deposition step. By depositing buried oxide layers in two separate insulating material deposition steps, a conductive material (e.g., bias pad material) layer is deposited above a first oxide layer and below a second oxide layer (see below, operation 150). The first oxide layer electrically isolates the bias pad material (or the bias pad after fabrication, see below, operation 158, fabrication of an isolation structure) from the substrate and other components of the integrated circuit.

[0027] According to some embodiments, the first oxide layer is a silicon dioxide (SiO2) layer. In some embodiments, the first oxide layer is an inorganic nitride layer (e.g., silicon nitride (Si x N y) etc.). In some embodiments, the first oxide layer is deposited over the top surface of the substrate. In some embodiments, the first oxide layer is deposited over the top surface of the substrate by chemical vapor deposition (CVD) using, for example, a combination of argon (Ar), silane (SiH4), and oxygen (O2) or water (H2O). The CVD-deposited oxide does not contain a dopant unless it is intentionally included in the dopant reaction gas mixture used to form the CVD-deposited oxide. In some embodiments, the first oxide layer is grown from the top surface of the substrate by, for example, rapid thermal processing (RTP). In some embodiments, the RTP growth of the first oxide layer includes treating a substrate of semiconductor material in an ambient air including one or more of argon, oxygen or water vapor at a temperature greater than 300 degrees Celsius (°C). The oxide growth by RTP forms a dense and uniform oxide layer to electrically isolate the substrate from the bias pad and the integrated circuit. The RTP-grown oxide layer includes dopants present in an upper region of the substrate near the top surface because the substrate material (semiconductor material, for example, silicon, doped silicon, GaAs, etc.) is incorporated into the RTP-grown oxide. In some embodiments, a first oxide layer is formed on a top surface of the integrated circuit by depositing and curing a liquid material to form an oxide, such as spin-on glass (SOG), BPSG (boron phosphorus spin-on glass), or FSG (fluorinated quartz glass).

[0028] In some embodiments, the thickness of the first oxide layer is about 50 angstroms. In the range of about 50 nanometers (nm), but other thicknesses are also within the scope of the present disclosure. Based on some methods of growing or depositing oxides on semiconductor material layers, a first oxide layer with a thickness of less than about 50 angstroms does not provide sufficient electrical insulation or coverage. Incomplete coverage of the thinner first oxide layer can result in leakage current into the substrate. By depositing an insulator material (by, for example, chemical vapor deposition, physical vapor deposition (PVD), etc.) onto a substrate with good coverage and good insulation properties, a first oxide layer with a film thickness of about 50 nm is obtained to reduce and / or eliminate leakage current from the transistor well into the substrate.

[0029] The method 140 includes an optional operation 144, in which a portion of the first oxide layer is modified to have a reduced thickness compared to the thickness of the first oxide layer when operation 142 is completed. The performance of operation 142 corresponds to the thinning of the first oxide layer 1106 deposited in operation 140 as described above. In some embodiments, the performance of operation 142 is performed on, for example, the first transistor 1103A, but not on the second transistor 1103B, or vice versa. In some embodiments of the method 140, the electrical environment applied to the transistor during the manufacturing process is homogeneous across the entire integrated circuit or semiconductor substrate (or semiconductor wafer), and these embodiments omit optional operation 144 because the thickness of the first oxide layer, the bias pad, and the second oxide layer (see below) on top of the bias pad are similar across the entire integrated circuit or semiconductor substrate. In some embodiments of method 140, the electrical environment applied to the transistor is heterogeneous across the integrated circuit or semiconductor substrate, and these embodiments include one or more film thickness modification operations, such as operation 144, operation 148, and / or operation 152 described below. According to some embodiments, the thickness of the first oxide layer is not less than 100 angstroms after optional operation 144 to avoid breakdown of the first oxide layer when a voltage is applied to the bias pad and the substrate below the bias pad. In some embodiments, voltages with opposite signs (e.g., positive for the bias pad and negative for the substrate) are applied to the substrate and the bias pad, which causes breakdown of the first oxide layer when the first oxide layer is too thin.

[0030] In some embodiments, the first oxide is thinned under an entire transistor in a cell of an integrated circuit, while the first oxide thickness is not modified under another transistor in the same cell. In some embodiments, the first oxide is thinned under one well of the transistor, while the first oxide thickness is not modified under a different well of the transistor. In some embodiments, the thinned portion of the first oxide layer and the unmodified portion of the first oxide layer intersect under the transistor and are separated by forming an isolation structure.

[0031] Method 140 includes operation 146, in which a bias pad material layer is deposited over the first oxide layer. The performance of operation 146 corresponds to the deposition of bias pad material layer 1108, as follows Fig.11AAs described above, the bias pad material layer includes a conductive material. In some embodiments, the conductive material is a metal film. In some embodiments, the metal film includes tungsten, cobalt, titanium, tantalum, nickel, or an alloy thereof. According to some embodiments, the metal film used for the bias pad material layer is the same material that forms a bias contact from the bias pad through the semiconductor material layer and the upper portion of the buried oxide layer. According to some embodiments, the bias pad material layer is a semiconductor material. In some embodiments, the semiconductor material is polysilicon. In some embodiments, the semiconductor material is a III-V type semiconductor material, for example, gallium arsenide (GaAs) and the like.

[0032] In some embodiments of method 140, the bias pad material layer is a metal film, in which the metal film is deposited by, for example, sputtering the material layer from a target above the top surface of the first oxide layer. In embodiments of method 140 where the bias pad material layer is a semiconductor material, the semiconductor material is deposited by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. According to some embodiments, the bias pad material is a pure (undoped) semiconductor material. According to some embodiments, the bias pad material is doped during deposition. According to some embodiments, the bias pad material is such a semiconductor material: a metal silane layer is grown on the semiconductor material by depositing metal atoms on the semiconductor material layer and annealing to allow the metal and silicon (or other semiconductor material) atoms to diffuse into each other. According to some embodiments, the metal silane layer is capable of transmitting the voltage applied to the bias pad across the bias pad, and thus generating a desired electrical environment under the transistor faster than the undoped or lightly doped semiconductor material of the bias pad.

[0033] According to some embodiments, the thickness of the bias pad material layer is in the range of about 10 nm to about 100 nm, but other thicknesses are also within the scope of the present disclosure. Bias pad materials having a thickness less than about 10 nm are prone to not completely covering the first oxide layer, thereby generating a non-uniform electric field below the semiconductor material layer having the transistor well. Bias pad material layers having a thickness greater than about 100 nm do not provide an increased benefit in applying an electric field to the semiconductor material layer. However, as the thickness of the bias pad material layer increases (e.g., greater than 100 nm), filling of the isolation structure extending through the bias pad material layer becomes more difficult, and sometimes produces voids or gaps in the isolation structure material.

[0034] Method 140 includes optional operation 148, wherein a portion of the biasing layer material is modified. Optional operation 148 is performed to adjust the thickness of biasing pad material layer 1108, as follows: Fig.11A In some embodiments, the execution of the optional operation 148 causes a transistor (eg, the first transistor 1103A or the second transistor 1103B, such as Fig. 11BIn some embodiments, the execution of optional operation 148 causes a plurality of adjacent transistors (eg, both the first transistor 1103A and the second transistor 1103B, as shown below) to be thinned. Fig. 11B In some embodiments, the modification is to reduce the thickness of a portion of the bias pad material layer. In some embodiments, the modification is to form an isolated bias pad from the bias pad material layer prior to depositing the second oxide layer (see below, operation 150). In some embodiments, the modification includes both reducing the thickness of a portion of the bias pad material layer and forming an isolated bias pad from the bias pad material layer.

[0035] In some embodiments of the present disclosure, the electrical characteristics below the well of the transistor are modified by changing the thickness of the bias pad layer, rather than reducing the thickness of a portion of the buried oxide. According to some embodiments, the thickness of the bias pad material layer is modified by applying a patterned material layer above the top surface of the bias pad material layer and transferring the pattern to the patterned material layer. According to some embodiments, the patterned material layer is a photoresist layer. According to some embodiments, the patterned material can be patterned using electron beam or extreme ultraviolet (EUV) lithography. In some embodiments, the pattern applied to the patterned material layer includes a pattern corresponding to an opening in the patterned material layer, which corresponds to the location where the bias pad material layer will be thinned.

[0036] The bias pad material layer is thinned by etching. In some embodiments, the bias pad material layer is thinned by performing a dry or plasma etching process to anisotropically remove exposed portions of the bias pad material while leaving covered portions of the bias pad material unmodified. The dry etching or plasma etching process configured to remove metal or metal-containing bias pad materials includes a halogenated reactant, such as hydrochloric acid (HCl), hydrofluoric acid (HF), hydrogen bromide (HBr), chlorine (Cl2), fluorine (F2), etc.

[0037] An anisotropic dry etch or plasma etch process has a more vertical profile than an isotropic etch process, thereby preserving the size of the bias pad material below the patterned material layer and avoiding undercutting of the patterned material layer. Undercutting can cause a large number of voids in the integrated circuit during the manufacturing process. In some embodiments, the undercut becomes significant enough to affect the electrical connection between the bias pad and the bias contact to the bias pad.

[0038] In some embodiments, a wet etchant is used to thin the bias pad material layer. According to some embodiments, the wet etchant provides greater uniformity of removal during the thinning process. In some embodiments, undercutting of the patterned material layer during thinning of the bias pad material layer is compensated by modifying (reducing) the size of the openings in the patterned material layer to make the openings smaller. In some embodiments, undercutting of the patterned material layer by isotropic etching during the wet etch thinning process is intentionally combined to achieve the desired size of the thinned bias pad, or recess in the bias pad material layer (e.g., before forming an isolation structure through the bias pad material layer).

[0039] In some embodiments, wet etchants are used for larger openings or larger thinned areas in the patterned material layer because wet etchants are less likely to leave residues from the thinning process on the top surface of the patterned material layer. In embodiments where the offset pad material layer is a metal or metal-containing material, wet etching reduces the likelihood of metal residues contaminating the integrated circuit.

[0040] In some embodiments of the method, the modification is to form an isolated bias pad from the bias pad material layer prior to depositing the second oxide layer (see below, operation 150). Separating the bias pad material layer into individual bias pads is performed to avoid damaging circuit components when the integrated circuit design places the isolation structure close to vulnerable circuit elements (e.g., as shown below). Fig.10 In the integrated circuit 1000, the deep trench isolation structures (DTI) 1022A and DTI 1022C are separated from the transistors (or from the wells 1012A, 1012B, and 1012C) and extend through the semiconductor material layer 1012 and the second oxide layer 1010 to the first oxide layer 1006. However, the DTI 1022B is located directly below the gate electrode 1014G and extends only from the second oxide layer 1010 to the first oxide layer 1006. Since it is impossible to form the DTI 1022B without destroying the semiconductor material layer 1012 in the transistor area, the bias pad material layer is divided into individual pads before depositing the second oxide layer (see operation 150 below) or depositing the semiconductor material layer (see operation 154 below).

[0041] Method 140 includes operation 150, in which a second oxide layer is deposited over the bias layer material. The performance of operation 150 corresponds to the deposition of the second oxide layer 1110, as follows Fig.11AAs shown. A second oxide layer is deposited over the bias pad material by a chemical vapor deposition (CVD) process such as low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), etc. Since the bias pad material layer is not always a semiconductor material, the second oxide layer is not grown, and sometimes the first oxide layer is not grown. The thickness of the second oxide layer is in the range of about 10nm to about 100nm, but other thicknesses are also within the scope of the present disclosure. The second oxide layer is a buried oxide layer that is in direct contact with the semiconductor material layer of the well of the transistor containing the integrated circuit (see operation 154 below). The second oxide layer is thick enough so that the potential between the bias plate and the well of the transistor protects the well of the transistor and the channel region of the transistor from transient or uncontrolled voltages in the substrate without inhibiting carrier movement or causing breakdown of the second oxide layer. A second oxide layer thickness of less than about 10nm is prone to breakdown, while a thickness greater than about 100nm is more likely to cause problems with filling the DTI extending through the second oxide layer, and problems with filling the openings for the bias contacts and substrate contacts formed in the following operation 164.

[0042] According to some embodiments, method 140 includes optional operation 152, wherein the thickness of the second oxide layer is modified. The performance of optional operation 152 corresponds to reducing the thickness of the second oxide layer (see second oxide layer 1110) before depositing the semiconductor material layer 1112 in operation 154 as described below, as follows Fig.11A As shown. In some embodiments, the second oxide layer has an uneven top surface because the modification to the thickness of the bias pad material layer and / or the first oxide layer is transferred through the second oxide layer. In some embodiments, a chemical mechanical polishing (CMP) step is performed in optional operation 152 to flatten the top surface of the second oxide layer (and incidentally thin some areas of the second oxide layer above the "thick" portion above the first oxide or bias pad material layer). Optional operation 152 is performed when the uneven top surface of the second oxide layer is further translated to the uneven top surface of the semiconductor material layer having the well of the integrated circuit. The uneven surface of the semiconductor material layer is more likely to cause uneven switching speeds or unpredictable channel lengths because the top surface of the semiconductor material layer is not uniformly flat, but textured according to the underlying layer.

[0043] Method 140 includes operation 154, in which a semiconductor material layer is deposited over the second oxide layer. Operation 154 may be performed corresponding to the deposition of a semiconductor material layer (eg, semiconductor material layer 1112), as follows: Fig.11AIn some embodiments, the semiconductor material layer includes, for example, pure silicon, doped silicon, silicon germanium (SiGe), or a III-V type semiconductor, such as gallium arsenide (GaAs). In some embodiments, the semiconductor material layer is deposited by atomic layer deposition or chemical vapor deposition (CVD) of the semiconductor material using, for example, silane gas. In some embodiments, the semiconductor layer is formed by depositing a silicon layer, followed by depositing a semiconductor material rich in dopants, and heat treating the film to interdiffuse the dopant and silicon to form a dopant-rich region at the top surface of the integrated circuit for use in the source, drain, and channel of the transistor.

[0044] According to some embodiments, method 140 includes operation 156, in which a dopant is added to the semiconductor material layer. In some embodiments, the dopant is added to the semiconductor material layer to form an N-well, a P-well, and a drift region of a channel of a transistor for an integrated circuit. In a non-limiting example, the dopant is added to an N-well (e.g., N-well 1112C) in the first transistor 1103A, or to an N-well 1112D in the second transistor 1103B. In a non-limiting example, the dopant is added to a P-well (e.g., P-well 1112A) in the first transistor 1103A or a P-well 1112F in the second transistor 1103B. In some embodiments, the dopant is added to the semiconductor material layer by, for example, applying a patterned material layer to mask portions of the semiconductor material layer that are to remain undoped (e.g., regions outside a source, drain, or HVNW (high voltage N-well) of an integrated circuit), transferring a pattern to the patterned material layer to expose portions of the semiconductor layer that are to receive the dopant, and implanting the dopant from an ion source implantation tool. In some embodiments, the steps of depositing a patterned material layer, transferring the pattern to the patterned material layer, and adding dopants by an ion source implantation tool are performed separately for each doped region in the semiconductor material layer. In some embodiments, some doped regions are added to the semiconductor material layer together with the same patterned material layer, but the substrate is maintained at different inclinations or tilts to direct the implanted dopants to different regions of the exposed region of the semiconductor material layer. In some embodiments, dopants are added to form an N-well for the source or drain of a transistor. In some embodiments, dopants are added to form a P-well for the drain or source of a transistor. In some embodiments, N-type dopants are added to form HVNW (high voltage N-well) between transistor wells in the semiconductor material layer. In some embodiments, dopants are added at low implantation energies to form lightly doped regions (LDD regions) at the top surface of the transistor well directly below the contact of the transistor source or transistor drain. The LDD region at the top surface of the transistor well increases the carrier density, reduces the potential required to switch the transistor to the "on" or activated state, and reduces the current (I onIn some embodiments, dopants are implanted into the LDD regions in the P-well 1112A, for example, the LDD regions 1115A. Fig.11F shown.

[0045] Method 140 includes operation 158, in which an isolation structure of the integrated circuit is fabricated. As described below, an opening for the isolation structure (see Fig. 11B Some openings 1121B are used for shallow isolation structures (see Fig. 11C 1122B, 1122D), and some openings 1121A are used for deep trench isolation structures (see Fig. 11C 1120A, 1120C, 1120F). The deep trench isolation structure (DTI) as described above is an isolation structure that extends through the semiconductor material layer, the second oxide layer, the bias pad material layer, and into the first oxide layer. In some embodiments, the DTI extends through the first oxide layer and into the substrate below the first oxide layer. In some embodiments, the DTI corresponds to the location of a cell boundary in an integrated circuit. In some embodiments, the DTI corresponds to an isolation wall surrounding an isolation region of a semiconductor layer (in which a bias contact extends through the semiconductor material layer and the region electrically isolates a transistor well from a bias contact, or a semiconductor material that is in direct contact with a bias contact extending through the isolation region). In some embodiments, the DTI electrically isolates a bias pad (having a first voltage) in one cell from a bias pad (having a second voltage) in a second (adjacent) cell. In some embodiments, the DTI electrically isolates a bias pad under one transistor in a cell from a second bias pad under a second transistor in the same cell, so that each bias pad has a different voltage than another bias pad in the same cell. In some embodiments, the DTI electrically isolates multiple bias pads beneath a single transistor and the DTI is fabricated prior to depositing a layer of semiconductor material.

[0046] A shallow trench isolation structure (STI) is formed on a top portion of a semiconductor material layer and extends partially (but not completely) through the semiconductor material layer. STI is used in integrated circuits to increase the spacing between a conductive material (e.g., a source contact) and a gate electrode above a channel of a transistor. STI is aligned with DTI in a cell of an integrated circuit.

[0047] The STI or DTI is manufactured by depositing a patterned material layer (photoresist, EUV resist, electron beam mask material) over the top surface of the film stack at a given stage of the integrated circuit manufacturing process, transferring the pattern to the patterned material layer, and forming an isolation structure (STI or DTI) within an opening in the patterned material layer. In some embodiments, an opening for the isolation structure is formed in the film stack by etching the film stack using a dry or plasma etching process. As the opening deepens, the chemistry of the etching plasma changes depending on the (one or more) materials being etched. In some embodiments, the insulating material (e.g., silicon dioxide) used to bury the oxide layer includes fluorocarbons, such as CF4, trifluoromethane (CHF3), difluoromethane (CH2F2), and gaseous HF. In some embodiments, oxygen is included in the etching plasma to remove polymers accumulated during the etching process. During separation and etching, a carrier gas such as argon is used to adjust the total concentration of chemically active etchant molecules to balance polymer formation on the surface of the integrated circuit and control the profile of the isolation structure opening. The isolation structure openings are formed using an anisotropic etch process (eg, high directionality, associated with strong bombardment energy or large acceleration voltage) to maintain straight isolation structure sidewalls and reduce the possibility of voids or packets in the isolation structure fill material.

[0048] In some embodiments, DTI is fabricated in the cell before STI is fabricated. In some embodiments, DTI and STI are fabricated after deposition of a semiconductor material layer and formation of a transistor well in the semiconductor material layer. In some embodiments, the fabrication process includes multiple iterations of fabricating STI and DTI in order to produce bias pads for transistors and accommodate changes in transistor design associated with bias pads.

[0049] According to some embodiments, method 140 includes operation 160, in which a gate electrode is fabricated over the semiconductor material layer. Non-limiting examples of gate electrodes are Fig.11E 1, where components 1114G1 and 1114G2 cover the drift regions and wells of the first transistor and the second transistor of the integrated circuit 1100. In operation 160, as a method of manufacturing a gate electrode (e.g., Fig.11E A thin gate oxide layer is deposited over the top surface of the semiconductor material layer to electrically isolate the channel region (below the gate oxide layer and between the source well and the drain well) from the gate electrode. In some embodiments, the gate oxide is a silicon dioxide layer (with a dielectric constant κ of about 3.7 to 3.9). In some embodiments, the gate oxide includes hafnium dioxide (HfO2, with a dielectric constant κ>12). In some embodiments, the gate oxide is a high-k dielectric (κ>3.9) other than hafnium dioxide (e.g., ZrO2, etc.).

[0050] In some embodiments, the gate electrode is manufactured by a dummy gate manufacturing process, wherein a blanket layer of a first interlayer dielectric (ILD) material is deposited over a gate oxide layer over a semiconductor material layer, an opening is formed in the first ILD material to expose a portion of the gate oxide layer, and a dummy gate material and a plurality of liner materials are deposited in the opening. In some embodiments of the dummy gate manufacturing process, the dummy gate material is removed and filled with a gate electrode material before forming contacts to a source well (source region) and a drain well (drain region) of the transistor. In some embodiments of the dummy gate manufacturing process, the dummy gate material is removed and filled with a gate electrode material after forming source and drain contacts by the first ILD material.

[0051] In some embodiments, a blanket layer of gate electrode material is deposited over the gate oxide layer, a patterned material layer is deposited over the gate electrode material, and patterned with remaining lines or remaining features corresponding to the location of the gate electrode over the channel of the transistor in the integrated circuit. In some embodiments, the gate electrode material layer is etched to remove unprotected gate electrode material and unprotected gate oxide material and expose the semiconductor material layer having transistor wells (source, drain, HVNW, etc.) therein. In some embodiments, one or more spacer layers are deposited over the gate electrode stack (remaining portions of gate electrode material and remaining portions of gate oxide) and etched back to leave remaining portions of the spacer layer on the sides of the remaining portions of the gate electrode material and the remaining portions of the gate oxide.

[0052] In some embodiments, the gate electrode is part of a fin field effect transistor (FinFET), and the gate electrode extends continuously on the top and sides of a fin of dielectric material (with a source well, a drain well, and a channel therein). In some embodiments, the fin field effect transistor includes a plurality of fins made of a dielectric material layer, which are separated from each other by an insulating material (e.g., the first ILD described above with reference to the dummy gate manufacturing process). In some embodiments, the gate electrode is a material line separated from a flat semiconductor material layer or a planar semiconductor material layer by a remaining portion of the gate dielectric layer.

[0053] Method 140 includes operation 162, in which an interlayer dielectric (ILD) film is deposited over a gate electrode and a well of the integrated circuit. Depositing the ILD film over the gate electrode and the well of the integrated circuit corresponds to deposition of the ILD film. In some embodiments, the ILD film includes at least one insulating material, such as silicon dioxide, spin-on glass, borophosphosilicate glass, or some other dielectric or insulating material having a dielectric constant κ of about 4. In some embodiments, the ILD film is a low-κ dielectric material having a dielectric constant κ of less than about 2.5, such as, Etc. In some embodiments, the ILD film is deposited by a variation of a CVD process, such as PECVD (plasma enhanced CVD), LPCVD (low pressure CVD), LACVD (laser assisted CVD), etc. In some embodiments, the ILD film is formed by depositing a liquid material over the top of a wafer or substrate, spinning the wafer or substrate to produce a reduction in the film thickness of the liquid material, and curing the liquid material to trigger, for example, cross-linking within the ILD film, or polymerization of the liquid material, or producing a degassing effect as the solvent or liquid component evaporates, while the solid material remains behind to form the ILD film.

[0054] Method 140 includes operation 164, in which the contact is fabricated by ILD. A non-limiting example of fabricating the contact by ILD is Fig.11G 1, wherein contacts 1118A-1118C are fabricated down to bias pads 1108A-1108C, drain contacts 1116D1 are fabricated down to drain well 1112A, source contacts 1116S1 are fabricated down to N well 1112C, and gate contacts 1116G1 are fabricated to gate electrode 1114G1. The transistors are formed into different groups to facilitate profile control and selectivity of the etching process relative to the material on the bottom or side of the contact opening during the contact opening etching process. Etching contacts involves the step of depositing a patterned material layer over the top surface of the deposited ILD film in operation 162. Etching contacts also involves the step of transferring a pattern to the patterned material layer, wherein the openings in the patterned material correspond to the locations of the contacts in the etched (one or more) materials. Etching contacts also involves at least one etching step in which material exposed at the bottom of the openings in the patterned material is removed by a liquid or plasma type etchant to expose the underlying material for a predetermined amount of time or until a particular material or film is exposed at the bottom of the etched opening.

[0055] In some embodiments, the contact is a transistor contact that is electrically connected to a source well, a drain well, or a gate electrode of a transistor in a semiconductor device. In some embodiments, the contact is a bias contact that extends downward from the top surface of the first ILD film to a bias pad that is embedded in a buried oxide layer or sandwiched between a first oxide layer and a second oxide layer and is surrounded by a deep trench isolation structure in the buried oxide layer that surrounds the bias pad. In some embodiments, the contact is a substrate contact that extends downward from the top surface of the first ILD film to the substrate. In some embodiments, the substrate contact intersects and is electrically connected to a bias pad in the buried oxide layer. In some embodiments, the substrate contact is separated from the bias pad and the bias contact is in the buried oxide layer.

[0056] The contacts are filled with metal or metal-containing compounds, such as tungsten, cobalt, nickel, titanium, tantalum, etc., and alloys thereof. The contacts are filled by sputtering the metal or metal-containing compound, or by atomic layer deposition of the metal-containing compound on the exposed sidewalls and bottom of the contact openings, and allowing the metal-containing compound to grow and fill the contact openings. After filling the contact openings, a chemical mechanical polishing step is performed to remove the contact metal from the top surface of the first ILD film and isolate the top ends of the contacts from each other. In some embodiments, the etching process for forming the contact openings is performed sequentially so that, for example, shallower contacts (e.g., transistor contacts) are separated from deeper contacts (e.g., bias contacts and substrate contacts).

[0057] According to some embodiments, method 100 includes operation 166, wherein the transistor contact is connected to an interconnect structure of the integrated circuit. In some embodiments, the transistor contact is electrically connected to other contacts or vias in the interconnect structure. In some embodiments, the transistor contact is electrically connected to a conductive line in an ILD layer above a dielectric material layer containing the transistor contact. Fig.11H In the non-limiting example described in , conductive line 1124A electrically connects bias contact 1118B and drain contact 1116D1 , and conductive line 1124B electrically connects source contact 1116S2 to bias contact 1118C, and conductive lines 1124A and 1124B are within ILD layer 1119 .

[0058] According to some embodiments, the above operations are performed in an order different from the order presented above. In some embodiments, the above operations are performed in the case where other operations are mixed therein. In some embodiments, some of the above operations are omitted from the method while still producing the structure described below. Such changes in the above method do not limit the scope of the present disclosure, and those skilled in the art will understand it as a natural change that occurs within the scope of the present disclosure but does not affect the scope of the present disclosure when changes are made to the structure disclosed herein.

[0059] Figure 2 2 is a cross-sectional view of an integrated circuit 200 according to some embodiments. The integrated circuit 200 includes a substrate 204, wherein a first cell 201A of the integrated circuit abuts a second cell 201B. A cell boundary 202 indicates a transition point between the first cell 201A and the second cell 201B. In some embodiments, the first cell 201A is a high voltage cell and the second cell 201B is a low voltage cell. A first oxide layer 206 has been deposited on a top surface of the substrate 204. A bias pad material layer 208 is above the first oxide layer 206. The bias pad material layer 208 has been divided into individual bias pads 208A, 208B, 208C, and 208D. The bias pad 208A is in the second cell 201B. The bias pads 208B, 208C, and 208D are in the first cell 201A. The individual bias pads are separated by a trench isolation structure (DTI), as described below.

[0060] A second oxide layer 210 is above the top surface of each bias pad 208A-208D. A semiconductor material layer 212 is above the second oxide layer 210. The semiconductor material layer 212 includes a plurality of wells for transistors of the integrated circuit 200. The first transistor 203A is a PMOS device, wherein the source well 212C is an N-doped well 212C, the drain well 212A is a P-doped well, and the channel region includes a P drift region 212B. In the first transistor 203A, the source well 212C includes two LDD regions 215B and 215C. The LDD region 215B has a net P-type doping profile, and the N-type dopant concentration of the LDD region 215C is greater than the N-type dopant concentration in the well 212C. The drain well 212A includes a P-type doped LDD region 215A. Including LDD regions in the source well 212C and drain well 212A promotes an increase in carrier density at the boundaries between the LDD regions and the wells in which they are located. Including a P-type doped LDD region 215B in the source well 212C promotes high carrier concentration adjacent to the channel region directly beneath the gate electrode 214G1.

[0061] The second transistor 203B is an NMOS device having a P-doped source well 212F, an N-doped drain well 212D, and a channel region including an N-doped drift region 212E between the source well 212F and the drain well 212D. The second transistor 203B includes an LDD region 215D in the drain well 212D, an LDD region 215E in the P-doped source well 212F, and an LDD region 215F in the source well 212F. The LDD region 215F has a higher concentration of P-type dopants than the doping in the P-doped well 212F. The LDD region 215E has a net N-type dopant concentration. The LDD region 215E in the source well 212F generates a high carrier concentration at the P / N junction where the LDD region 215E meets the LDD region 215F and the P-doped source well 212E. The high carrier concentration in the source well 212F at the P / N junction enhances the ability of the second transistor 203B to turn on quickly.

[0062] Shallow trench isolation structures (STI) extend partially through the semiconductor material layer 212. Deep trench isolation structures (DTI) extend completely through the semiconductor material layer 212. Some deep trench isolation structures also extend through the second oxide layer 210 and the offset liner material layer 208 to create various offset pads 208A-208D.

[0063] A first interlayer dielectric (ILD) film 214 is above the top surface of the semiconductor material layer 212. As described above in method 140, the first ILD film 214 electrically isolates the transistor in the first unit 201A from the transistor in the second unit 201B, and in each transistor, the source, drain, gate electrode (and the contact electrically connected to them) are electrically isolated from each other. In the integrated circuit 200, two different types of contacts extend through the first ILD film 214. Bias contacts 218A, 218B and 218C extend through the first ILD film 214, the semiconductor material layer 212 and the second oxide layer 210 to be electrically connected to each bias pad. Bias contact 218A is electrically connected to bias pad 218A in the second unit 201B. Bias contact 218B is electrically connected to bias pad 208B in the first unit 201A. Bias contact 218C is electrically connected to bias pad 208C in first unit 201A. Bias contact conducts electric potential from the interconnect structure of integrated circuit 200 downward to bias pad under transistor to modify the electric environment around source well and channel region of transistor in integrated circuit. In integrated circuit 200, bias pad 208A, bias pad 208B and bias pad 208C are configured to modify the electric environment under a single transistor. In some embodiments, each bias contact conducts different electric potential to the bias pad connected to the bias contact. In some embodiments, each bias contact conducts the same electric potential to the bias pad connected thereto.

[0064] The bias contact 218A extends through the first ILD film 214, the semiconductor material layer 212, and the second oxide layer 210, and extends downward to the bias pad 208A. In some embodiments, the bias contact abuts against the top surface of the bias pad 208A. In some embodiments, the bias contact 218A extends downward into the bias pad 208A. The bias contact 218A is laterally separated from the STI 220A and the STI 220B.

[0065] In a similar manner, bias contact 218B and bias contact 218C extend through first ILD film 214, semiconductor material layer 212, and second oxide layer 210, and extend down to bias pad. Bias contact 218B is laterally separated from STI 220B and STI 220C. Bias contact 218C is laterally separated from STI 220G and STI 220H.

[0066] The integrated circuit 200 includes transistor contacts that extend downward through the first ILD film 214 to the source, drain, and electrode of each transistor. For example, in the first transistor 203A, the source contact 216S1 extends downward through the first ILD film 214 to the top surface of the N-well 212C, connecting to the LDD regions 215B and 215C at the top of the N-well 212C. The drain contact 216D1 extends downward through the ILD film 214 to the LDD region 215A at the top of the drain well 212A. The gate contact 216G1 extends downward through the first ILD film to the top surface of the gate electrode 214G1. The gate electrode 214G1 abuts against the top surface of the N-well 212C, the top surface of the drift region 212B, and the top surface of the STI 220D. The STI 220D separates the gate electrode 214G1 from the P-doped drain well 212A and from the P-doped LDD region 215A at the top of the drain well 212A.

[0067] The transistor contacts in the second transistor 203B are as follows. The drain contact 216D2 extends downward through the first ILD film 214 to the LDD region 215D at the top of the N well 212D. The source contact 216S2 extends downward through the first ILD film 214 to the LDD regions 215E and 215F at the top of the source well 212F. The gate contact 216G2 extends downward through the first ILD film to the top surface of the gate electrode 214G2. The gate electrode 214G2 extends on the top surfaces of the STI 220F, the N-doped drift region 212, and the source well 212F. According to some embodiments, the gate electrode extends above the top surface of the LDD region in the source well.

[0068] Figure 3 is a cross-sectional view of integrated circuit 300 according to some embodiments. Elements of integrated circuit 300 that match the structure and function of the above-described elements of integrated circuit 200 are given the same identifying reference numerals increased by 100. The differences between integrated circuit 300 and integrated circuit 200 are described herein below.

[0069] In the integrated circuit 300, the second unit 301B includes a bias contact 318A extending downward through the first ILD film 314, the semiconductor material layer 312, and the second oxide layer 310 to the bias pad 308A. The bias contact 318A is laterally separated from the STI 320A and the STI 320B. In the first unit 301A, the bias contacts 318B and 318C are located at different positions than the bias contacts 218B and 218C in the integrated circuit 200. The bias contact 318B extends through the first ILD film 314, the STI 320C, the DTI 322C, and the second oxide layer 310 before reaching the bias pad 308B. Similarly, the bias contact 318C extends through the first ILD film 314, the semiconductor material layer 312, and the second oxide layer 310 before reaching the bias pad 308C. Bias contacts 318B and bias contacts 318C represent bias contacts that are electrically isolated from the semiconductor material of semiconductor material layer 312. According to some embodiments of the present disclosure, the bias contacts extending through the semiconductor material layer are isolated from transistors within the isolation region of the semiconductor material layer. See, for example, isolation regions 227A and 227B in integrated circuit 200. In some embodiments such as integrated circuit 300, the bias contacts are electrically isolated from the transistors of the integrated circuit by positioning the bias contacts so that they extend through the isolation structure and are laterally separated from the semiconductor material by the surrounding insulating material of the deep trench isolation structure. According to some embodiments, the manufacturer chooses to position the bias contacts within the deep trench isolation structure in order to save space within the integrated circuit by eliminating the isolation region (see isolation region 227B in integrated circuit 200) to reduce the die area of ​​the integrated circuit. According to some embodiments, each bias contact in a cell of the integrated circuit is positioned within and extends through the deep trench isolation structure. According to some embodiments, some bias contacts in the cell extend through the deep trench isolation structure and some bias contacts extend through the isolation region in the semiconductor material layer. The positioning of the bias contacts within the cell of the integrated circuit is related to the amount of space available for positioning the bias contacts and the process window for manufacturing the bias contacts, i.e., the selectivity of the etching process to the dielectric material of the first ILD film, the semiconductor material exposed below the first ILD film, and the semiconductor material layer thickness of the second oxide layer above the bias pad.

[0070] Figure 44 is a cross-sectional view of an integrated circuit 400 according to some embodiments of the present disclosure. In the integrated circuit 400, elements having functions and structures similar to those described above with respect to the integrated circuit 200 are given the same identifying reference numerals increased by 200, and the differences between the integrated circuit 200 and the integrated circuit 400 described above are discussed below. In the integrated circuit 200, the substrate 204 is electrically isolated from the interconnect structure of the integrated circuit. In the integrated circuit 400, the substrate is electrically connected to the interconnect structure of the integrated circuit through a substrate contact 424. The substrate contact 424 extends downward from the top surface of the first ILD film to the substrate 404. In some embodiments, the substrate contact 424 abuts against the top surface of the substrate 404. In some embodiments, the substrate contact 424 extends downward into the substrate 404. The substrate contact 424 is separated from the semiconductor material in the semiconductor material layer 412 by the dielectric material of the DTI 422F and the STI 420H. The DTI 422F and the STI 420H serve as an insulating sleeve for the substrate contact 424. Since substrate contact 424 is electrically isolated from bias contact 418C, substrate 404 and bias pads 408B and 408C are configured for application of three independent voltages.

[0071] Figure 5 5 is a cross-sectional view of an integrated circuit 500 according to some embodiments of the present disclosure. In integrated circuit 400, elements of the integrated circuit corresponding to elements of integrated circuit 400 having similar structures and / or functions are given the same identifying reference numerals increased by 100. The differences between integrated circuit 500 and integrated circuit 400 are described below. In integrated circuit 500, bias contact 524 extends downward from the top surface of first ILD film 514 to substrate 504. Unlike substrate contact 424 in integrated circuit 400 (which is electrically isolated from semiconductor material layer 412), substrate contact 524 extends downward from the top surface of first ILD film 514 through semiconductor material layer 512, second oxide layer 510, bias pad 508D, and first oxide layer 506 before reaching substrate 504. The bias contact 524 is electrically isolated from the bias contact 518C and from the transistors (first transistor 503A and second transistor 503B) by a DTF 522F, which is laterally separated from both the substrate contact 524 and the bias contact 518C. In some embodiments, the substrate contact is separated from the bias pad but also extends through the semiconductor material layer. In some embodiments, the substrate contact extends through the semiconductor material layer and the bias contact extends through the DTI structure that acts as an insulating sleeve. In some embodiments, all bias contacts and substrate contacts extend through the isolation structure and are separated from the semiconductor material layer.

[0072] Fig. 6Ais a top view of an integrated circuit 600 according to some embodiments. In some embodiments, Fig. 6A A single transistor corresponding to a cell of an integrated circuit (see e.g. Figure 2 The first transistor 203A or Figure 2 600). In the integrated circuit 600, the cross-sectional line AA' extends through the isolation structure 604, the cell region 602, the isolation region 606 and the bias contact 608. The isolation region 606 includes a plurality of bias contacts. The bias contact 608 is a column-type or column-type bias contact having a cylindrical or cylindrical structure. The cell region 602 is a portion of the semiconductor material layer that includes the source well, drain well and channel of the transistor of the integrated circuit 600. The isolation region 606 is a portion of the semiconductor material layer that is isolated from the cell region 602 by the isolation structure 604.

[0073] Figure 6B 6 is a cross-sectional view of an integrated circuit 640, whose structure corresponds to the structure of the integrated circuit 600 described above. The integrated circuit 640 includes a substrate 644, a first oxide layer 646, a bias pad material layer 648, a second oxide layer 650, a semiconductor material layer 652, and a first ILD film 654. The bias contact 658 extends downward through the first ILD film 654, through the isolation region 656 (corresponding to the isolation region 606 in the integrated circuit 600), and the second oxide layer 650 before reaching the bias pad 648A. The bias pad 648A extends below the entire transistor well 659 within the DTI 662B (on one side of the transistor well 659) and the DTI 662C (on the opposite side of the transistor well 659). The bias contact 658 is equivalent to the contact described above, for example, Figure 2 In some embodiments, DTI 662A, 662B and 662C form a ring around the periphery of, for example, isolation region 606 and cell region 602 (equivalent to transistor well 659), and follow a contour similar to the shape of isolation structure 604, as described above in conjunction with Fig. 6A Comparing the integrated circuit 600 with the integrated circuit 640, the isolation structures 604 in the integrated circuit correspond to the shallow trench isolation structures and the deep trench isolation structures in the semiconductor material layer 652, as follows: STI 660A and DTI 662A correspond to the isolation structures 604 located on the far side of the isolation region 606 from the cell region 602, STI 660B and DTI 662B correspond to the isolation region 604 between the isolation region 606 and the cell region 602, and STI 660C and DTI 662C correspond to the isolation structures 604 located on the far side of the cell region 602 from the isolation region 606 in the integrated circuit 600.

[0074] Fig. 7A700 according to some embodiments. Elements of integrated circuit 700 having similar functions to elements of integrated circuit 600 have the same identifying reference numerals increased by 100. Section line BB' extends through integrated circuit 700 at a position similar to the position of section line A-A' in integrated circuit 600. The differences between integrated circuit 700 and integrated circuit 600 will be described below. In integrated circuit 700, bias contact 708 is a bar-type bias contact. Unlike column-type bias contact 608 in integrated circuit 600, bias contact 708 has a deep trench structure filled with a conductive material to transmit an applied voltage to a bias pad transistor in a cell area of ​​the integrated circuit. In some embodiments, including a bar-type bias contact instead of a column-type bias contact depends on the process window used to manufacture the bias contact. In some embodiments of the integrated circuit, loading issues associated with the etching process for the deep openings for the bias contacts are of lower priority, including strip-type contacts, because of the large number of contacts between the bias pads and the interconnect structure of the integrated circuit. Strip-type contacts have greater flexibility when positioning electrical connections from the interconnect structure down to the bias contacts. Column-type bias contacts generally require greater precision in positioning the electrical connections for the column-type bias contacts and have a tighter process window to ensure that the size of the electrical connections to the column-type bias contacts does not increase the resistance between the interconnect structure and the bias pads below the cell area of ​​the integrated circuit.

[0075] Figure 7B 7 is a cross-sectional view of an integrated circuit 740, whose structure corresponds to the structure of the above-mentioned integrated circuit 700. The integrated circuit 740 includes a substrate 744, a first oxide layer 746, a bias pad material layer 748, a second oxide layer 750, a semiconductor material layer 752, and a first ILD film 754. The bias contact 758 extends downward through the first ILD film 754, through the isolation region 756 (corresponding to the isolation region 606 in the integrated circuit 600), and the second oxide layer 750 before reaching the bias pad 748A. Comparing integrated circuit 700 with integrated circuit 740, the isolation structure 704 in the integrated circuit corresponds to a shallow trench isolation structure and a deep trench isolation structure within the semiconductor material layer 752, as follows: STI 760A and DTI 762A correspond to the isolation structure 704 located on the far side of the isolation structure 706 from the cell region 702, STI 760B and DTI 762B correspond to the isolation region 704 between the isolation region 706 and the cell region 702, and STI 760C and DTI 762C correspond to the isolation structure 704 located on the far side of the cell region 702 from the isolation region 706 in the integrated circuit 700.

[0076] Fig. 8A 800 . FIG. 800 is a top view of integrated circuit 800 according to some embodiments. Section line CC' extends through integrated circuit 800 at the same location as section line AA' extends through integrated circuit 600. Section line CC' extends through isolation structures 804A and 804B, isolation region 806, cell region 802, and reaches bias contact 808. In integrated circuit 800, bias contact 808 is a pillar-type bias contact similar to bias contact 608 in integrated circuit 600. Cell region 802 is completely surrounded by isolation region 806. Isolation structure 804A is completely surrounded by isolation region 806 within a semiconductor material layer, located between cell region 802 and isolation region 806. Cell region 802 includes a portion of a semiconductor material layer in which source wells, drain wells, and channel regions of transistors are fabricated. The isolation region 806 includes a portion of the semiconductor material layer outside the cell region through which a bias contact and / or substrate contact extends to make an electrical connection between an interconnect structure of the integrated circuit and a bias pad or substrate below the cell region 802 .

[0077] Figure 8B is a cross-sectional view of integrated circuit 840 according to some embodiments. Elements of integrated circuit 840 that have the same structure or function as elements of integrated circuit 640 have the same identifying reference numerals increased by 200.

[0078] In the integrated circuit 840, a substrate 844 has a first oxide layer 846 deposited thereon. A bias pad material layer 848 is above the first oxide layer 846 and below the second oxide layer 850. A semiconductor material layer 852 is between the second oxide layer 850 and the first ILD film 854. Bias contacts 808A and 808B extend through the semiconductor material layer 852 within the isolation region 56. The isolation region 856 is separated from the cell region 802 by the following: STI 860B and DTI 862B located on the side of the cell region closest to the bias contact 808A, and STI 860D and STI 862D located on the side of the cell region 802 closest to the bias contact 808B. The isolation region 856 is separated from the rest of the semiconductor material layer 852 by the following: STI 860A and DTI 862A immediately adjacent to the bias contact 808A, and STI 860C and DTI 862C immediately adjacent to the bias contact 808B. Thus, all sides of the cell region 802 are surrounded by dielectric material (the second oxide layer 850 at the bottom, the STI and DTI structures within the semiconductor material layer 852, and the first ILD film 854 on the top side), through which the transistor contacts extend. In the integrated circuit 840, the DTI 862A extends through the semiconductor material layer 852, the second oxide layer 850, and the bias pad material layer 848, down to the first oxide layer 846. The DTI 862C extends through the film stack of the integrated circuit 840 in a manner similar to the DTI 862A. DTI 862A and DTI 862C comprise buried portions of isolation structure 804B in integrated circuit 800 and isolate bias pad 848A from the remainder of bias pad material layer 848 .

[0079] Fig. 9 is a cross-sectional view of integrated circuit 900 according to some embodiments. Elements of integrated circuit 900 having similar structure or function as elements of integrated circuit 200 have the same identifying reference numerals increased by 700. The differences between elements of integrated circuit 900 and integrated circuit 200 are described below.

[0080] In the integrated circuit 900, the first transistor 903A and the second transistor 903B have bias pads of different shapes. For the first transistor 903A, the second oxide layer 910 has a first thickness 908, the bias pad 908B has a bias pad thickness 930B, and the oxide layer 906 has a first oxide layer thickness 930C. For the second transistor 903B, the second oxide layer 910 has a second oxide layer thickness 932A, which is less than the second oxide layer thickness 930A below the first transistor 903A. For the second transistor 903B, the bias pad 908C has a bias pad thickness 932B, which is greater than the bias pad thickness 930B. Under the second transistor 903B, the first oxide layer 906 has a first oxide layer thickness 932C. In the integrated circuit 900, the first oxide layer thickness 930C is the same as the first oxide layer thickness 932C. Varying the thickness of the bias pad or the thickness of the second oxide layer beneath the transistor provides the manufacturer with the opportunity to modify the strength of the electric field experienced by the well of the transistor as a result of the voltage transmitted to the bias pad by the bias contact. In some embodiments, the second oxide layer has the same thickness (e.g., the second oxide layer 930A and the second oxide layer 932A are the same thickness), and the first oxide layer has different thicknesses between different transistors. According to some embodiments, steps associated with reducing the thickness of the film stack beneath the transistor are performed after depositing the bias pad material and before depositing the second oxide layer (these steps are, in particular, depositing a patterned material layer, transferring a pattern to the patterned material, wherein the openings in the pattern correspond to the locations where the bias pad material is to be thinned, and etching away the exposed portions of the bias pad material using a liquid etchant or plasma etching). In order to provide a smooth and flat surface prior to depositing the semiconductor material layer, the second oxide layer is deposited according to some versions of method 140 such that a chemical mechanical polishing step is performed to reduce the thickness of the second oxide layer to a minimum second oxide thickness within a cell or across the entire semiconductor wafer (see, e.g., Fig. 9 The thickness of the second oxide layer 932A in FIG. 1 is a value corresponding to that of the second oxide layer 932A in FIG. 1 , without having a protrusion or an uneven top surface of the second oxide layer.

[0081] Fig.10 is a cross-sectional view of an integrated circuit 1000 according to some embodiments. The integrated circuit 1000 is similar to the above-mentioned Figure 6B The integrated circuit 640, however Figure 6B1000 has a single bias pad 648A, while the integrated circuit 1000 has two bias pads 1008B and 1008C separated by DTI 1024, as further described below. In the integrated circuit 1000, the first cell 1001A and the second cell 1001B meet at the cell boundary 1002A. The cell boundary 1002A extends through the DTI 1022A. The cell boundary 1002B extends through the DTI 1022C. The film stack below the transistor 1003 is as follows: the first oxide layer 106 is deposited above the top surface of the substrate 1004. The bias pad material layer 1008 is deposited above the top surface of the first oxide layer 1006. The second oxide layer 1010 is deposited above the top surface of the bias pad material 1008. The semiconductor material layer 1012 is deposited above the top surface of the second oxide layer 1010 and includes a doped well for the transistor 1003. The shallow trench isolation structure (STI) extends through the top of the semiconductor material layer 1012, but does not extend to the top surface of the second oxide layer 1010. The deep trench isolation structure (DTI) has three versions. The first version of DTI (DTI 1023A, DTI 1023B, and DTI 1023C) extends through the entire semiconductor material layer 1012, extending down to the second oxide layer 1010. The second version of DTI (DTI 1022A and DTI 1022C) extends through the semiconductor material layer 1012, the second oxide layer 1010, and the bias pad material layer 1008, extending down to the first oxide layer 1006. The third version of DTI (DTI 1024) extends from the second oxide layer 1010 through the bias pad material layer 1008, extending down to the first oxide layer 1006. DTI 1024 does not extend through the semiconductor material layer 1012. DTI 1024 is completely below transistor 1003. DTI 1024 separates the lower transistor 1003 (i.e., bias pad material layer 1008) into two separate bias pads, namely bias pad 1008B and bias pad 1008C. In the first cell 1001A, bias contact 1018B extends through the first ILD film 1014, the semiconductor material layer 1012, and the second oxide layer 1010, extending downward to bias pad 1008B. Bias contact 1018C extends through the first ILD film 1014, the semiconductor material layer 1012, and the second oxide layer 1010, extending downward to bias pad 1008C. Since bias pad 1008B and bias pad 1008C are separated and electrically isolated from each other by DTI 1024, bias pad 1008B and bias pad 1008C are configured to receive independent voltage set points under different sides of transistor 1003.Thus, the bias pad 1008B is configured to exert a stronger influence on the P-doped source well 1012C, and the bias pad 1008C is configured to exert a stronger influence on the doped drain well 1012 and the N-type doped drift region 1012B under the electrode 1014G. The bias contact 1018A in the second cell 1001B is configured to receive independent voltage set points from the bias contacts 1018B and 1018C and the bias pads 1008B and 1008C in the first cell 1001A.

[0082] Figures 11A-11H is a cross-sectional view of an integrated circuit during a manufacturing process according to some embodiments.

[0083] Fig.11A 1 is a cross-sectional view of an integrated circuit 1100 during a manufacturing process according to some embodiments. In the integrated circuit 1100, a first cell 1101A is separated from a second cell 1101B at a cell boundary 1102. For both the first cell 1101A and the second cell 1101B, a first oxide layer 1106 is deposited over a substrate 1104. The deposition of the first oxide layer 1106 corresponds to operation 142 in the method 140, as described above. A bias pad material layer 1108 is deposited over the first oxide layer 1106 in both the first cell 1101A and the second cell 1101B. The deposition of the bias pad material layer 1108 corresponds to operation 146 in the method 140, as described above. A second oxide layer 1110 is deposited over the bias pad material layer 1108 in both the first cell 1101A and the second cell 1101B. The deposition of the second oxide layer corresponds to the execution of operation 150 in the method 140, as described above. A semiconductor material layer 1112 is deposited over the second oxide layer 1110 in both the first cell 1101A and the second cell 1101B. The deposition of the semiconductor material layer 1112 corresponds to the execution of operation 154 in the method 140, as described above. The oxide layer is deposited on the substrate by, for example, a variant of chemical vapor deposition (CVD), in which silane (SiH4) and oxygen molecules react to form a SiO2 film on the top surface of the substrate. The semiconductor material layer 1112 is deposited by, for example, CVD, or epitaxial growth of a film using thermal decomposition of silane (SiH4) or a silyl halide (e.g., SiCl4, SiBr4, etc.). In an embodiment in which the bias pad material layer 1108 is a semiconductor material, the deposition is performed in a manner similar to the deposition of the semiconductor material layer 1112. In an embodiment in which the bias pad material layer 1108 is a metal-containing layer, the film deposition is performed by, for example, sputtering metal atoms from a metal target onto the first oxide layer 1106 to a thickness suitable for shielding the transistor from the voltage in the substrate 1104.

[0084] Fig. 11Bis a cross-sectional view of integrated circuit 1100 during a manufacturing process according to some embodiments. Fig.11A In comparison, Fig. 11B In FIG. 1 , a patterned material layer 1113 has been deposited over a semiconductor material layer 1112. The patterned material layer 1113 has been exposed and developed to form an opening 1123 therein. The blanket layer below the opening 1123 has been etched to form an opening (trench) for a deep trench isolation structure, which will be described below with respect to FIG. Fig. 11C Further described. The first type of opening 1121A extends through the semiconductor material layer 1112 and stops on the top surface of the second oxide layer 1110. A short deep trench isolation structure 1122A (short DTI) is formed by filling the first type of opening 1121A with a dielectric material (e.g., silicon dioxide). The second type of opening 1121B extends through the semiconductor material layer 1112, the second oxide layer 1110, and the bias pad material layer 1108 to form an isolated bias pad. A long deep trench isolation structure 1122B (long DTI) is formed by filling the second type of opening 1121B with a dielectric material. In some embodiments, the second type of opening 1121B extends downward to the first oxide layer 1106. In some embodiments, the second type of opening 1121B extends downward into the bias pad material layer 1108, but does not extend to the first oxide layer 1106. The depth of the second type of opening 1121B is at least related to the selectivity of the etching process for the bias pad material layer relative to the etching rate of the second oxide layer 1110 and / or the semiconductor material layer. In some embodiments, the depth of the second type of opening 1121B is also related to the process conditions used to form the second type of opening to achieve a profile of the second type of opening that does not reduce the effective area of ​​the unit under the circuit design specifications.

[0085] Fig. 11C is a cross-sectional view of an integrated circuit 1100 during a manufacturing process according to some embodiments of the present disclosure. Fig. 11B compared to, Fig. 11C The wafer includes isolation structure trenches, for example, each of the first type of opening 1121A and the second type of opening 1121B, which have been filled with dielectric material to form shallow DTI 1122A and deep DTI 1122B. After filling the openings with the dielectric material, the wafer surface is planarized (by, for example, chemical mechanical polishing (CMP)) to expose the top surface of the semiconductor material layer 1112 between the different filled isolation structure trenches.

[0086] Long DTIs such as long DTI 1122B separate bias pads from each other. For example, bias pad 1108A in second cell 1101B is separated from bias pad 1108B across cell boundary 1102, where long DTI 1122B is located at cell boundary 1102. Bias pad 1108C is separated from bias pad 1108B by a long DTI that separates a PMOS transistor (or first transistor 1103A) from an NMOS transistor (or second transistor 1103B). Another of the second type of openings 1121B separates bias pad 1108C from bias pad 1108D.

[0087] exist Fig. 11C In the embodiment of the present invention, a patterned material layer 1121 has been added above the top surface of the semiconductor material layer. A set of openings 1123 in the patterned material layer 1121 corresponds to the location of shallow trench isolation structures (STI) in the integrated circuit 1100. The patterned material portion 1121A masks the active area 1112Y of the semiconductor material layer 1112. The patterned material portion 1121B masks the active area 1112Z of the semiconductor material layer 1112. The active areas 1112Y and 1112Z are located at the bottom of the semiconductor material layer 1112. Fig. 11C 1120A-1120H) are added to the semiconductor material layer after the STI (1120A-1120H) is formed in the semiconductor material layer 1112. In some embodiments, the STI at the top of the long DTI extends around the active area of ​​the cell. Fig. 11C , STIs 1120B and 1120E appear different in the cross-sectional view of the first cell 1101A, but are actually a single STI extending around the perimeter of the active region 1112Y and around the bias pad 1108B. Similarly, DTIs 1122B and 1122E extend around the perimeter of the active region 1112Y and the bias pad 1108B. Similarly, the bias pad 1108C and the active region 1112Z are surrounded by a single STI (as shown by STIs 1120E and 1120H) and a single long DTI (as shown by DTIs 1122D and 1122F) (see also FIG. Fig. 6A , an isolation structure 604, and Figure 6B , DTI 662A and 662C).

[0088] The STIs 1120A-1120H are formed to oxidize the top surface of the semiconductor material layer. In some embodiments, oxygen-rich plasma is used to oxidize the exposed upper portion of the semiconductor material layer 1112 within the opening 1123 in the patterned material layer 1113. In some embodiments, an etching process is performed to remove the upper portion of the semiconductor material layer 1112 from the bottom of the opening 1123, and the opening in the semiconductor material layer is filled with a dielectric material and planarized by a CMP process to expose the semiconductor material layer.

[0089] and Fig. 11C In comparison, Fig.11D , the active regions 1112Y and 1112Z have been implanted with P-type and N-type dopant atoms to form doped regions 1112A-1112F for the active regions. For the first transistor 1103A (PMOS transistor), the P-doped well 1112A is separated from the N-doped well 1112C by the P-doped drift region 1112B. The STI 1120D separates the top surface of the P-doped well 1112A from the top surface of the P-doped drift region 1112B. There is no STI to separate the top surface of the P-doped drift region 1112B from the top surface of the N-doped well 1112C. For the second transistor 1103B (NMOS transistor), the N-doped well 1112D is separated from the P-doped well 1112F by the N-doped drift region 1112E. The STI 1120F separates the top surface of the N-doped well 1112D from the top surface of the N-doped drift region 1112E. There is no STI separating the top surface of the N-doped drift region 1112E from the top surface of the P-doped well 1112F. Adding doped regions in two different wells in the semiconductor material layer 1112 corresponds to the performance of operation 156 in method 140, as described above. In some embodiments, steps that are also part of operation 156 include the following steps: as part of manufacturing a transistor (e.g., a first transistor 1103A and a second transistor 1103B), dopants for source / drain regions and / or LDD regions are added to the semiconductor material layer 1112, as described below.

[0090] Fig.11E is a cross-sectional view of an integrated circuit 1100 according to some embodiments of the present disclosure. Fig.11D compared to, Fig.11EThe formation of a gate electrode 1114G1 in the first transistor 1103A and a gate electrode 1114G2 in the second transistor 1103B are depicted. The gate electrodes 1114G1 and 1114G2 are formed by depositing a blanket gate dielectric material layer (not shown) over the top surface of the semiconductor material layer 1112 and the STIs 1120A-1120H, and depositing a gate electrode material layer (e.g., polysilicon, silicon germanium, etc.) over the gate dielectric material layer (not shown). A patterned material layer is deposited over the gate electrode material layer and a pattern is transferred thereon, and then the exposed portions of the gate dielectric material layer and the gate electrode material layer are removed by an etching process to expose the semiconductor material layer 1112 and the STIs 1120A-1120H, leaving the gate electrodes 1114G1 and 1114G2. Gate electrode 1114G1 extends over a portion of the top surface of STI 1120D, over a top surface of P-doped drift region 1112B, and over a portion of the top surface of N-doped well 1112C. Gate electrode 1114G2 extends over a portion of the top surface of STI 1120F, over a top surface of N-doped drift region 1112E, and over a portion of the top surface of P-doped well 1112F.

[0091] Fig.11F is a cross-sectional view of an integrated circuit 1100 during a manufacturing process according to some embodiments of the present disclosure. Fig.11E compared to, Fig.11F Depicted is the formation of LDD regions 1115A, 1115B, and 1115C in the first cell 1101A, and LDD regions 1115D, 1115E, and 1115F in forming a gate electrode (see, for example, the above combination Fig.11DThe gate electrodes 1114G1 and 114G2 described above have been formed in the first unit 1101A. The LDD region promotes improving the carrier density of the transistor and serves as a landing position for the transistor contact. According to some embodiments, the addition of the LDD region of the integrated circuit corresponds to the execution of operation 156 in method 140. In some embodiments, multiple doping operations are used to add dopants to the semiconductor material layer, for example, a P-type dopant is added in a first dopant addition operation and an N-type dopant is added in a second dopant addition operation. In some embodiments, dopants are added by adjusting the energy of the dopant atoms in the implantation process. A lower implantation energy is used so as to retain the implanted dopant atoms to the upper part of the doped well where the LDD region is located. For example, the LDD region 1115A is located in the upper part of the P-doped well 1112A and is physically separated from the P-doped drift region 1112B. Similarly, the LDD regions 1115B and 1115C are located in the upper region of the N-doped well 1112C and are physically separated from the P-doped drift region 1112B. LDD region 1115A has a net P-type doping profile with a higher P-type dopant concentration than P-doped well 1112A. LDD 1115C has a net N-type doping profile with a greater N-type dopant concentration than N-doped well 1112C. LDD 1115B has a net P-type doping profile and abuts one side of LDD 1115C within N-doped well 1112C. LDD 1115B is proximate to gate 1114G1 but does not extend below gate 1114G1.

[0092] LDD 1115D is located in the upper region of N-doped well 1112D and has a higher N-type dopant concentration than N-doped well 1112D outside LDD region 1115D. LDD region 1115D is physically separated from N-doped drift region 1112E. N-doped drift region is physically separated from LDD region in P-doped well 1112F: LDD 1115E and 1115F. LDD 1115F is a P-doped LDD region in the upper region of P-doped well 1112F, and LDD 1115E is adjacent to LDD 1115F in the upper region of P-doped well 1112F. LDD 1115E has a net N-type doping profile and separates P-doped LDD 1115F from the portion of P-doped well 1112F under gate electrode 1114G2 and the P / N junction directly under gate electrode 1114G2.

[0093] When adding dopants to source / drain regions or one or more LDD regions in a semiconductor material layer, a patterned material layer is deposited over the top surface of the semiconductor material layer (and the DTI extending through the semiconductor material layer) to expose a portion of one or more doped wells within the footprint of the transistor. When adding an LDD region such as LDD region 1115A in well 1112A, the local density of P-type dopants is increased in the LDD region by adding additional P-type dopants during the implantation process. When forming LDD region 1115B in well 1112C, P-type dopants are added to first neutralize the net N-type dopant remaining in the top region of well 1112C, and then to produce a surplus or excess of P-type dopants in LDD region 1115B. Therefore, according to some embodiments, a first amount of P-type dopant is added to LDD region 1115A, and a second amount of P-type dopant is added to LDD region 1115B, wherein the second amount of P-type dopant is greater than the first amount of P-type dopant because the composition of the wells in which the LDD regions are located is different. In a similar manner, adding dopants to the LDD region 1115D located in the top region of the well 1112D requires a smaller total amount of N-type dopant than adding N-type dopant to form the LDD region 1115E in the well 1112F of the second transistor 1103B. The LDD region 1115C in the well 1112C is formed by adding N-type dopant to the top region of the well 1112C. Similarly, the LDD region 1115F in the well 1112F is formed by adding P-type dopant to the top region of the well 1112F.

[0094] Fig.11G is a cross-sectional view of an integrated circuit 1100 during a manufacturing process according to some embodiments of the present disclosure. Fig.11F compared to, Fig.11G A plurality of contacts that have been formed through the film stack of the integrated circuit 1100 are depicted. A first set of contacts (bias contacts 1118A, bias contacts 1118B, and bias contacts 1118C) extend through the first ILD film 1114, the semiconductor material layer 1112, and the second oxide layer 1110, down to the bias pad. Bias contact 1118A is electrically connected to bias pad 1108A. Bias contact 1118B is electrically connected to bias pad 1108B. Bias contact 1118C is electrically connected to bias pad 1108C. Bias pad 1108B is below the entire first transistor 1103A. Bias pad 1108C is below the entire second transistor.

[0095] The transistor contacts for the first transistor 1103A include a drain contact 1116D electrically connected to the LDD region 1115A, a gate contact 1116G electrically connected to the gate electrode 1114G1, and a source contact 1116S1 electrically connected to the LDD regions 1115B and 1115C in the well 1112C of the first transistor 1103A. The second transistor 1103B has a drain contact 1116D2 extending through the first ILD film 1114 and the LDD region 1115D in the N-doped well 1112D. The gate contact 1116G2 extends downward through the first ILD film to the electrode 1114G2. The source contact 1116S2 extends downward through the first ILD film 1114 to the LDD region 1115E and the LDD region 1115F in the well 1112F. According to some embodiments, the bias contacts are fabricated in separate operations for tilting the contact openings and filling the contact openings. The formation of transistor contacts and bias contacts corresponds to the performance of operation 164 in method 140 , as described above.

[0096] Fig.11H is a cross-sectional view of an integrated circuit 1100 according to some embodiments. Fig.11G compared to, Fig.11H A first portion of the interconnect structure between contacts is depicted. Conductive line 1124A extends from bias contact 1118B in first transistor 1103A to drain contact 1116D1 on the top surface of first ILD film 1117. Similarly, conductive line 1124B extends from source contact 1116S2 in second transistor 1103B to bias contact 1118C. Thus, the operation of the transistor triggers carriers to move through the channel region between the source transistor and the drain transistor, and when the transistor is in operation, a voltage or charge storage is applied in the bias pad below the transistor. Conductive lines 1124A and 1124B act as bridges to facilitate the operation of the bias pad without additional transistors or logic elements in the integrated circuit. Conductive lines 1124A and 1124B are located in an ILD layer 1119 deposited above ILD layer 1117.

[0097] Figures 12A-12D is a cross-sectional view of an integrated circuit during a manufacturing process according to some embodiments.

[0098] Fig. 12A1 is a cross-sectional view of an integrated circuit 1200 according to some embodiments of the present disclosure. In the integrated circuit 1200, a first oxide layer 1206 has been deposited over a substrate 1204. In the integrated circuit 1200, a first cell 1201A is undergoing first oxide layer thinning, while a second cell 1201B of the integrated circuit is protected from the first oxide layer thinning by a mask material layer 1205. The material 1205 must be deposited over a top surface of the first oxide layer 1206. In the first cell 1201A, a first top surface portion 1206T1 and a second top surface portion 1206T2 are exposed by an opening in the mask material 1205. The first top surface portion 1206T1 corresponds to the first transistor 1203A. The second top surface portion 1206T2 corresponds to a portion of the oxide layer below the second transistor 1203B. The first oxide layer thinning is performed by etching the first top surface portion 1206T1 and the second top surface portion 1206T2 using an etching process, as previously described in optional operation 144 of method 140.

[0099] Fig. 12B 1 is a cross-sectional view of an integrated circuit 1220 according to some embodiments. Fig. 12A Elements of the integrated circuit 1200 that are similar in structure and function have the same identification numbers. The differences between the integrated circuit 1220 and the integrated circuit 1200 are described below. In the integrated circuit 1220, according to operation 144 of the method 140, only the first transistor 1203A has exposed the first top surface portion 1206T1 for the first oxide thinning, as described above. The first oxide layer 1206 of the second transistor 1203B is protected from the first oxide thinning by the mask material 1205.

[0100] Fig. 12C 1 is a cross-sectional view of an integrated circuit 1240 according to some embodiments of the present disclosure. In the integrated circuit 1240, elements having similar structures and functions as the integrated circuit 1200 have the same identification numbers. A bias pad material 1208 layer has been deposited over the first oxide layer 1206. A mask material layer 1207 has been deposited over the bias pad material 1208 layer. The openings in the mask material layer 1207 correspond to the bias layer material portions 1208T1 and 1208T2 of the first transistor 1203A and the second transistor 1203B. Thinning of the bias pad material layer 1208 is performed according to the above-described optional operation 148 in the method 140. Typically, thinning of the bias pad material layer is performed by etching using an aqueous etchant, or a dry etching process, or a plasma etching process. More details about the chemical reactions and other considerations associated with the thinning of the bias layer are previously described in operation 148 of the method 140.

[0101] Fig.12D is a cross-sectional view of an integrated circuit 1260 according to some embodiments of the present disclosure. Elements of the integrated circuit 1260 having similar structures or functions as elements of the integrated circuit 1240 have the same identifying references. Mask material 1207 is over a bias pad material layer 1208. The mask material 1207 covers the bias pad material layer 1208 in the cross-sectional area at 1203B, but an opening in the mask material 1207 exposes a bias layer material portion 1208T1 in the footprint of the first transistor 1203A. According to some embodiments, the bias pad material layer under the PMOS transistor in the integrated circuit cell is exposed for thinning, while in most transistors it is protected by the mask material. In some embodiments, the bias pad material layer under the NMOS transistor is exposed for thinning, while the PMOS transistor is protected by the mask material.

[0102] Some aspects of the present disclosure relate to a semiconductor device, including: a buried oxide layer located above a substrate; a semiconductor material layer located above the buried oxide layer, the semiconductor material layer including a plurality of doped regions; a transistor, wherein the transistor includes a gate electrode and a plurality of doped regions; an isolation region located in the semiconductor material layer; an interlayer dielectric (ILD) material located above the semiconductor material layer and the gate electrode; a first bias contact extending through the ILD material and the isolation region to the buried oxide layer; and an interconnect structure electrically connected to the buried oxide layer through the first bias contact. In some embodiments, the semiconductor device further includes: a first bias pad located in the buried oxide layer, wherein the first bias pad includes a conductive material. In some embodiments, the first bias contact is isolated from the semiconductor material layer by an isolation structure extending through the semiconductor material layer. In some embodiments, the semiconductor device further comprises: a second bias pad located in the buried oxide layer, wherein the second bias pad is between the second transistor and the substrate, the second bias pad is electrically isolated from the first bias pad by a deep trench isolation structure (DTI) in the buried oxide layer, wherein the second bias pad is electrically connected to an interconnect structure of the integrated circuit through a second bias contact. In some embodiments, the semiconductor device further comprises: a second transistor, a bias pad located below the second transistor, and a second bias contact electrically connected to the second bias pad, wherein the first bias pad has a first bias pad thickness, and the second bias pad has a second bias pad thickness that is smaller than the first bias pad thickness. In some embodiments, in the semiconductor material layer, the first bias contact and the second bias contact are each separated from the semiconductor material layer by an isolation structure in the semiconductor material layer. In some embodiments, the semiconductor device further comprises: a second bias contact extending through the ILD material, the semiconductor material layer, and the buried oxide layer to the substrate, and electrically connected to the interconnect structure of the integrated circuit above the ILD material. In some embodiments of the semiconductor device, the second bias contact is separated from the semiconductor material layer by a deep trench isolation structure (DTI). In some embodiments, the semiconductor device further comprises: a plurality of columnar bias contacts extending through the isolation region. In some embodiments, the first bias contact further comprises: a stripe bias contact extending through the isolation region of the integrated circuit and electrically connected to the first bias pad. In some embodiments, the isolation region extends around the entire first transistor of the integrated circuit. In some embodiments, the first bias pad is electrically connected to a voltage source through an interconnect structure.

[0103] Some aspects of the present disclosure relate to a semiconductor device, including: a buried oxide layer located above a substrate; a semiconductor material layer located above the buried oxide layer; a transistor having a source well and a drain well located in the semiconductor material layer; a first bias pad located in the buried oxide layer between the source well and the substrate; a second bias pad located in the buried oxide layer between the drain well and the substrate; a first deep trench isolation structure (DTI) ring, wherein the first bias pad is surrounded by the first DTI ring in the buried oxide layer; and a second DTI ring, wherein the second bias pad is surrounded by the second DTI ring in the buried oxide layer, and the first DTI ring and the second DTI ring share a central DTI segment. In some embodiments, the first bias pad and the second bias pad are configured to receive different voltages. In some embodiments, the transistor is located between the central DTI segment and an interlayer dielectric (ILD) material.

[0104] Some aspects of the present disclosure relate to a method for manufacturing an integrated circuit, comprising the following operations: surrounding a first bias pad with a dielectric material of a buried oxide layer; adding dopants to a semiconductor material layer above the first bias pad; depositing a gate dielectric material and a gate electrode material above a top surface of the semiconductor material layer; etching the gate dielectric material and the gate electrode material to isolate the gate electrode above the semiconductor material layer; depositing an interlayer dielectric (ILD) material above the gate electrode and the semiconductor material layer; etching at least one bias contact opening, the at least one bias contact opening down to the first bias pad; filling the at least one bias contact opening with a bias contact material; and electrically connecting the at least one bias contact to an interconnect structure of the semiconductor device. In some embodiments of the method, surrounding the first bias pad with a dielectric material of the buried oxide layer further comprises: depositing a first oxide layer over the substrate; depositing a bias pad material layer over the first oxide layer; depositing a second oxide layer on the bias pad material layer; and isolating the first bias pad from the remainder of the bias pad material layer by etching a deep trench isolation structure opening through the second oxide layer and the bias pad material layer, and filling the deep trench isolation structure opening with a dielectric material, wherein the deep trench isolation structure extends around a portion of the semiconductor material layer. In some embodiments, adding dopants to the semiconductor material layer further comprises adding dopants to the source well and drain well of the transistor, and further comprises etching a substrate contact opening from the first ILD film down to the substrate, and filling the substrate contact opening with a conductive material. In some embodiments, the method further comprises: surrounding a second bias pad within the buried oxide layer with a dielectric material, the second bias pad being located under a different transistor than the first bias pad. In some embodiments, the first bias pad has a first bias pad thickness and the second bias pad has a second bias pad thickness, and the method further includes modifying the first bias pad thickness to be different from the second bias pad thickness.

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0106] Example 1 is a semiconductor device comprising: a buried oxide layer located above a substrate; a semiconductor material layer located above the buried oxide layer, the semiconductor material layer comprising a plurality of doped regions; a transistor, wherein the transistor comprises a gate electrode and the plurality of doped regions; an isolation region located in the semiconductor material layer; an interlayer dielectric (ILD) material located above the semiconductor material layer and the gate electrode; a first bias contact extending through the ILD material and the isolation region to reach the buried oxide layer; and an interconnect structure electrically connected to the buried oxide layer through the first bias contact.

[0107] Example 2 is the semiconductor device described in Example 1, further comprising: a first bias pad located in the buried oxide layer, wherein the first bias pad comprises a conductive material.

[0108] Example 3 is the semiconductor device described in Example 2, further including: a second bias pad located within the buried oxide layer, wherein the second bias pad is between the second transistor and the substrate, and the second bias pad is electrically isolated from the first bias pad by a deep trench isolation structure (DTI) within the buried oxide layer, and wherein the second bias pad is electrically connected to the interconnect structure of the semiconductor device through a second bias contact.

[0109] Example 4 is the semiconductor device of Example 3, wherein, in the semiconductor material layer, the first bias contact and the second bias contact are each separated from the semiconductor material layer by an isolation structure in the semiconductor material layer.

[0110] Example 5 is the semiconductor device of Example 2, wherein the first bias pad is electrically connected to a voltage source through the interconnect structure.

[0111] Example 6 is the semiconductor device of Example 1, wherein the first bias contact is isolated from the semiconductor material layer by an isolation structure, and the isolation structure extends through the semiconductor material layer.

[0112] Example 7 is the semiconductor device described in Example 1, further including: a second transistor, a bias pad located below the second transistor, and a second bias contact electrically connected to the second bias pad, wherein the first bias pad has a first bias pad thickness and the second bias pad has a second bias pad thickness that is smaller than the first bias pad thickness.

[0113] Example 8 is the semiconductor device described in Example 1, further comprising: a second bias contact extending through the ILD material, the semiconductor material layer and the buried oxide layer to reach the substrate and electrically connected to an interconnect structure of the semiconductor device above the ILD material.

[0114] Example 9 is the semiconductor device of Example 8, wherein the second bias contact is separated from the semiconductor material layer by a deep trench isolation structure (DTI).

[0115] Example 10 is the semiconductor device of Example 1, further comprising: a plurality of pillar-type bias contacts extending through the isolation region.

[0116] Example 11 is the semiconductor device of Example 10, wherein the isolation region extends around an entire first transistor of an integrated circuit of the semiconductor device.

[0117] Example 12 is the semiconductor device of Example 1, wherein the first bias contact further comprises: a stripe-type bias contact extending through an isolation region of the semiconductor device and electrically connected to the first bias pad.

[0118] Example 13 is a semiconductor device comprising: a buried oxide layer located above a substrate; a semiconductor material layer located above the buried oxide layer; a transistor having a source well and a drain well located in the semiconductor material layer; a first bias pad located within the buried oxide layer between the source well and the substrate; a second bias pad located within the buried oxide layer between the drain well and the substrate; a first deep trench isolation structure (DTI) ring, wherein the first bias pad is surrounded by the first DTI ring within the buried oxide layer; and a second DTI ring surrounding the second bias pad within the buried oxide layer, the first DTI ring and the second DTI ring sharing a central DTI segment.

[0119] Example 14 is a semiconductor device as described in Example 13, having a first voltage source and a second voltage source, wherein the first bias pad is electrically connected to the first voltage source and the second bias pad is electrically connected to the second voltage source, wherein the first voltage source and the second voltage source have different voltages.

[0120] Example 15 is the semiconductor device of Example 13, wherein the transistor is located between the central DTI segment and an interlayer dielectric (ILD) material.

[0121] Example 16 is a method for manufacturing a semiconductor device, comprising: surrounding a first bias pad with a dielectric material; adding dopants to a semiconductor material layer above the first bias pad; depositing a gate dielectric material and a gate electrode material above a top surface of the semiconductor material layer; etching the gate dielectric material and the gate electrode material to isolate a first gate electrode above the semiconductor material layer; depositing an interlayer dielectric (ILD) material above the first gate electrode and the semiconductor material layer; etching at least one bias contact opening that extends downward to the first bias pad; filling the at least one bias contact opening with a bias contact material; and electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.

[0122] Example 17 is the method described in Example 16, wherein surrounding the first bias pad with a dielectric material also includes: depositing a first oxide layer above the substrate; depositing a bias pad material layer above the first oxide layer; depositing a second oxide layer on the bias pad material layer; and isolating the first bias pad from the rest of the bias pad material layer by: etching a deep trench isolation structure opening through the second oxide layer and the bias pad material layer, and filling the deep trench isolation structure opening with a dielectric material, wherein the deep trench isolation structure extends around a portion of the semiconductor material layer.

[0123] Example 18 is the method described in Example 16, wherein adding dopants to the semiconductor material layer further includes: adding dopants to the source well and drain well of the transistor; etching a substrate contact opening, the substrate contact opening extending from the first ILD material downward to the substrate; and filling the substrate contact opening with a conductive material.

[0124] Example 19 is the method described in Example 16, wherein etching the gate dielectric material and the gate electrode material also includes isolating a second gate electrode above the semiconductor material layer, and the method also includes surrounding a second bias pad with dielectric material, wherein the second bias pad is located below the second gate electrode.

[0125] Example 20 is the method described in Example 19, wherein the first bias pad has a first bias pad thickness and the second bias pad has a second bias pad thickness, and the method further includes: modifying the first bias pad thickness to be different from the second bias pad thickness.

Claims

1. A semiconductor device, comprising: a buried oxide layer located above the substrate; a semiconductor material layer, located above the buried oxide layer, the semiconductor material layer comprising a plurality of doped regions; A transistor, wherein the transistor comprises a gate electrode and the plurality of doped regions; an isolation region, located in the semiconductor material layer; An interlayer dielectric ILD material is located above the semiconductor material layer and the gate electrode; a first bias contact extending through the ILD material and the isolation region to the buried oxide layer; and an interconnect structure electrically connected to the buried oxide layer through the first biasing contact, Wherein, the semiconductor device further comprises: a first bias pad located in the buried oxide layer, wherein the first bias pad comprises a conductive material, the first bias pad is located between the transistor and the substrate in a vertical direction, and the first bias pad corresponds to the transistor in a horizontal direction; and A second bias pad is located in the buried oxide layer, wherein the second bias pad is located between the second transistor and the substrate in a vertical direction, and corresponds to the second transistor in a horizontal direction, and the second bias pad is electrically isolated from the first bias pad by a deep trench isolation structure DTI in the buried oxide layer, wherein the second bias pad is electrically connected to the interconnection structure of the semiconductor device through a second bias contact.

2. The semiconductor device according to claim 1, wherein In the semiconductor material layer, the first bias contact and the second bias contact are each separated from the semiconductor material layer by an isolation structure in the semiconductor material layer.

3. The semiconductor device according to claim 1, wherein The first bias pad is electrically connected to a voltage source through the interconnect structure.

4. The semiconductor device according to claim 1, wherein: The first bias contact is isolated from the layer of semiconductor material by an isolation structure extending through the layer of semiconductor material.

5. The semiconductor device according to claim 1, further comprising: The second transistor, and the second bias contact electrically connected to the second bias pad, wherein the first bias pad has a first bias pad thickness and the second bias pad has a second bias pad thickness that is less than the first bias pad thickness.

6. The semiconductor device according to claim 1, further comprising: A third biasing contact extends through the ILD material, the semiconductor material layer and the buried oxide layer to the substrate and is electrically connected to an interconnect structure of the semiconductor device above the ILD material.

7. The semiconductor device according to claim 6, wherein: The third bias contact is separated from the semiconductor material layer by a deep trench isolation structure DTI.

8. The semiconductor device according to claim 1, further comprising: A plurality of post-type bias contacts extend through the isolation region.

9. The semiconductor device according to claim 8, wherein: The isolation region extends around an entire first transistor of an integrated circuit of the semiconductor device.

10. The semiconductor device according to claim 1, wherein The first bias contact further includes a stripe-type bias contact extending through an isolation region of the semiconductor device and electrically connected to the first bias pad.

11. A semiconductor device comprising: a buried oxide layer located above the substrate; a semiconductor material layer located above the buried oxide layer; a transistor having a source well and a drain well located in the semiconductor material layer; A first bias pad is located in the buried oxide layer between the source well and the substrate, and the first bias pad corresponds to the source well in a horizontal direction; A second bias pad is located in the buried oxide layer between the drain well and the substrate, and the second bias pad corresponds to the drain well in a horizontal direction; a first deep trench isolation structure DTI ring, wherein the first bias pad is surrounded by the first DTI ring within the buried oxide layer; as well as A second DTI ring surrounds the second bias pad within the buried oxide layer, the first DTI ring and the second DTI ring share a central DTI section.

12. The semiconductor device according to claim 11, comprising a first voltage source and a second voltage source, wherein: The first bias pad is electrically connected to the first voltage source, and the second bias pad is electrically connected to the second voltage source, wherein the first voltage source and the second voltage source have different voltages.

13. The semiconductor device according to claim 11, wherein The transistor is located between the central DTI segment and an interlayer dielectric ILD material.

14. A method for manufacturing a semiconductor device, comprising: surrounding the first bias pad with a dielectric material; adding a dopant to the semiconductor material layer above the first bias pad; depositing a gate dielectric material and a gate electrode material over a top surface of the layer of semiconductor material; etching the gate dielectric material and the gate electrode material to isolate a first gate electrode above the semiconductor material layer; depositing an interlayer dielectric ILD material over the first gate electrode and the semiconductor material layer; etching at least one bias contact opening down to the first bias pad; filling the at least one biasing contact opening with a biasing contact material; as well as electrically connecting at least one biasing contact to an interconnect structure of the semiconductor device, The first bias pad is located between the semiconductor material layer and the substrate in a vertical direction, and corresponds to the first gate electrode in a horizontal direction.

15. The method according to claim 14, wherein: Surrounding the first bias pad with a dielectric material further comprises: depositing a first oxide layer over the substrate; depositing a bias pad material layer over the first oxide layer; depositing a second oxide layer on the bias pad material layer; and The first bias pad is isolated from the rest of the bias pad material layer by: etching a deep trench isolation structure opening through the second oxide layer and the offset pad material layer, and The deep trench isolation structure opening is filled with a dielectric material, wherein the deep trench isolation structure extends around a portion of the semiconductor material layer.

16. The method according to claim 14, wherein: Adding a dopant to the semiconductor material layer further comprises: adding dopants to the source well and the drain well of the transistor; etching a substrate contact opening from the first ILD material down to the substrate; and The substrate contact opening is filled with a conductive material.

17. The method according to claim 14, wherein: Etching the gate dielectric material and the gate electrode material further includes isolating a second gate electrode above the layer of semiconductor material, and the method further includes surrounding a second bias pad with dielectric material, the second bias pad being located below the second gate electrode.

18. The method according to claim 17, wherein: The first bias pad has a first bias pad thickness and the second bias pad has a second bias pad thickness, and the method further includes modifying the first bias pad thickness to be different from the second bias pad thickness.

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