Apparatus for capturing 2D images and depth images of a scene

Abstract

The present specification relates to an apparatus for capturing 2D images and depth images, comprising: a first sensor (C1) formed inside and on top of a first semiconductor substrate (100) comprising a front surface and a back surface, the first sensor (C1) comprising a plurality of 2D image pixels (P1) and a plurality of transmission windows (F), each transmission window (F) comprising a portion (100F) of the first substrate and an amorphous silicon region (50) in contact with the back surface of the portion (100F) of the first substrate (100); and a second sensor (C2) formed inside and on top of a second semiconductor substrate (130) opposite to the first sensor (C1) on the back surface side of the first substrate and comprising a plurality of depth pixels (P2) arranged opposite to the transmission windows (F) of the first sensor (C1).

Description

Technical Field

[0001] This application relates to an image acquisition device, and more specifically, to an image acquisition device capable of acquiring 2D images and depth images of a scene. Background Technology

[0002] Image acquisition devices capable of acquiring depth information have already been provided. For example, a time-of-flight (ToF) detector works by emitting light signals into a scene and then detecting the reflected light signals from objects in the scene. By calculating the time of flight of the light signals, the distance between the acquisition device and objects in the scene can be estimated. As an example, the pixels of such a sensor can use SPAD-type photodiodes (single-photon avalanche diodes).

[0003] In some applications, it is best to be able to capture both a two-dimensional (2D) image of the scene and a corresponding depth image of the scene simultaneously.

[0004] While a solution to achieve this goal is to use separate image sensors to capture 2D and depth images, this is not optimal because the sensors will have different viewpoints on the scene, resulting in misalignment between pixels in the corresponding images. Furthermore, using two sensors increases the size and cost of the device.

[0005] Another solution is to integrate the 2D image pixels and depth pixels into the same detector array. However, the problem is that depth pixels typically have a much larger size and / or a much higher power supply voltage than 2D image pixels, which complicates this integration.

[0006] The applicant’s previously filed patent application EP3503192 describes an apparatus for acquiring 2D images and depth images of a scene. The apparatus includes a stacked first sensor and a second sensor. The first sensor includes a plurality of 2D pixels and a plurality of transmission windows, and the second sensor includes a plurality of depth pixels arranged opposite to the transmission windows of the first sensor.

[0007] There is a need for an apparatus for acquiring 2D and depth images of a scene, which at least partially overcomes one or more drawbacks of known apparatuses. Summary of the Invention

[0008] To this end, one embodiment provides an apparatus for acquiring 2D images and depth images, comprising:

[0009] A first sensor is formed inside and on top of a first semiconductor substrate including a front surface and a rear surface. The first sensor includes a plurality of 2D image pixels and a plurality of transmission windows, each transmission window including a portion of the first substrate and an amorphous silicon region in contact with the rear surface of the portion of the first substrate. A second sensor is formed inside and on top of a second semiconductor substrate in the opposite direction to the first sensor on the rear surface side of the first substrate, and includes a plurality of depth pixels arranged opposite to the transmission windows of the first sensor.

[0010] According to one embodiment, the first sensor includes an interconnect stack on the rear surface side of the first substrate, wherein electrical connection rails and / or terminals are formed in the interconnect stack.

[0011] According to one embodiment, in each transmission window of the first sensor, the amorphous silicon region is arranged in an opening through the interconnect stack of the first sensor.

[0012] According to one embodiment, in each transmission window of the first sensor, the amorphous silicon region extends through a thickness substantially equal to that of the interconnect stack of the first sensor and is flush with the surface of the interconnect stack of the first sensor opposite to the first semiconductor substrate.

[0013] According to one embodiment, in each transmission window of the first sensor, the amorphous silicon region is laterally defined along its periphery and its entire height by a dielectric material with a refractive index less than that of amorphous silicon.

[0014] According to one embodiment, in each transmission window of the first sensor, a portion of the first substrate is laterally defined along its periphery and its entire height by a wall made of a dielectric material with a refractive index less than that of the first semiconductor substrate.

[0015] According to one embodiment, in each transmission window of the first sensor, a portion of the first semiconductor substrate and the amorphous silicon region have substantially the same surface area in a top view.

[0016] According to one embodiment, the device further includes alternating dielectric layers with different refractive indices between each transmission window of the first sensor and the corresponding depth pixel of the second sensor to form an anti-reflective stack through which light passes through the transmission window toward the depth pixel.

[0017] According to one embodiment, the second sensor includes an interconnect stack on the rear surface side of the second semiconductor substrate, wherein electrical connection rails and / or terminals are formed in the interconnect stack.

[0018] According to one embodiment, each depth pixel of the second sensor includes a SPAD-type photodiode.

[0019] According to one embodiment, each depth pixel of the second sensor includes multiple storage areas connected to the same detection area and is capable of measuring the phase shift between an amplitude-modulated light signal emitted by the light source of the device and a light signal received by the photoelectric detection area of ​​the pixel after reflection on the scene where an image of it is to be acquired.

[0020] According to one embodiment, the first semiconductor substrate is made of single-crystal silicon. Attached Figure Description

[0021] The above-described features and advantages, as well as other advantages, will be described in detail in the following description of specific embodiments given by way of example rather than limitation, wherein:

[0022] Figure 1 This is a cross-sectional view schematically and partially illustrating an embodiment of a device for acquiring 2D and depth images;

[0023] Figures 2A to 2J This is a cross-sectional view, schematically illustrating the manufacturing process. Figure 1 The steps of an example manufacturing method for a 2D image and depth image acquisition device of the described type. Detailed Implementation

[0024] In the various figures, similar features have been indicated by similar reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0025] For clarity, only steps and components useful for understanding the embodiments described herein are shown and described in detail. In particular, the formation of photodiodes and circuitry for controlling 2D image pixels and depth pixels is not described in detail; based on the teachings of this specification, the formation of such pixels is within the capabilities of those skilled in the art.

[0026] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected, or that they can be coupled through one or more other elements.

[0027] In the following disclosure, unless otherwise specified, when referring to absolute positional qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative positional qualifiers such as the terms “up,” “down,” “above,” “below,” etc., or directional qualifiers such as “horizontal,” “vertical,” etc., please refer to the directions shown in the figure.

[0028] Unless otherwise specified, the expressions “approximately,” “about,” “generally,” and “roughly” indicate a percentage of 10%, and preferably 5%.

[0029] Figure 1 It is a cross-sectional view, schematically and partially illustrating an embodiment of the apparatus for acquiring 2D and depth images of a scene.

[0030] Figure 1 The apparatus shown includes:

[0031] A first sensor C1 is formed inside and on top of a first semiconductor substrate 100 (e.g., a single-crystal silicon substrate). The sensor C1 includes a plurality of 2D image pixels P1 and a plurality of windows F distributed across the entire sensor surface.

[0032] A second sensor C2 is formed inside and on top of a second semiconductor substrate 130 (e.g., a single-crystal silicon substrate). The second sensor C2 is disposed behind the sensor C1 and includes a plurality of pixels with a depth of P2. The plurality of pixels are arranged relative to the window F of the sensor C1, and each pixel with a depth of P2 includes a SPAD-type photodiode.

[0033] It should be noted that in this description, the front and rear sides of a component refer to the surface of the component intended to face the scene from which its image is to be acquired, and the component surface opposite to its front side. Figure 1 In the example, the front and rear sides of the acquisition device are its upper and lower surfaces, respectively.

[0034] In practice, Figure 1 The device is designed for use in conjunction with a light source (e.g., a laser source) that emits light at or within a defined wavelength range, preferably a narrow wavelength range, such as a range with a half-width of less than 3 nm, for example, a light source with a central emission wavelength of around 940 nm. As an example, the emission wavelength range of the light source is outside the visible light range, for example, in the near-infrared range, for example, in the range of 700 to 1000 μm. In operation, the light signal generated by the light source is emitted towards the scene in the form of light pulses, such as periodic pulses (e.g., through one or more lenses). The returned light signal reflected by the scene is captured by the depth pixel P2 of sensor C2 to measure the time of flight of the light signal at different points in the scene and thereby infer the distance between the different points in the scene and the acquisition device. Pixel P1 of sensor C1 is capable of acquiring the visible light emitted by the scene to form a 2D image of the scene. The window F of sensor C1 is transmissive within the emission range of the light source so that the depth pixel P2 of sensor C2 can detect the returned light signal. As an example, the transmittance of the window F of sensor C1 within the emission wavelength range of the light source is greater than 50%.

[0035] In the illustrated example, each pixel P1 of the sensor C1 includes a photodiode 101, which includes one or more locally implanted regions formed in the semiconductor substrate 100. In this example, the implanted regions of the photodiode 101 are arranged on the rear surface side of the substrate 100. Each pixel P1 may also include one or more additional elements (not shown), such as control transistors, formed on the rear surface side of the substrate 100, for example, in and on the rear surface side of the substrate 100. The sensor C1 also includes an interconnect stack 110 formed by alternating dielectric and conductive layers coated on the rear surface of the substrate 100, in which electrical connection tracks and / or terminals 111 are formed to connect the pixels P1 of the sensor to peripheral control and power circuitry (not shown).

[0036] In the example shown, sensor C1 includes a vertical insulating wall 103 that spans the entire thickness of substrate 100 and defines substrate portions 100F corresponding to different windows F of sensor C1. The vertical insulating wall 103 is particularly optically insulating and may further have electrical insulating properties. As an example, the vertical insulating wall 103 is made of a dielectric material, such as silicon oxide. Similar insulating walls may also be provided between pixels P1 of sensor C1.

[0037] In the example shown, the substrate 100 of sensor C1 includes an implant-free region located in the substrate portion 100F of the window F of sensor C1 to maximize the transparency of the substrate in the window F.

[0038] according to Figure 1 In one aspect of the embodiment, each transmission window F further includes an amorphous silicon region 50 on the rear surface side of the substrate 130, the region 50 being located opposite the substrate portion 100F of the window F. The region 50 contacts the rear surface of the substrate portion 100F through its front surface and extends substantially over the entire surface of the window F. In this example, the interconnect stack 110 is interrupted relative to each transmission window F. The amorphous silicon region 50 is located in the interrupted region of the interconnect stack 110. The amorphous silicon region 50 extends, for example, over substantially the entire thickness of the interconnect stack 110. The thickness of the amorphous silicon region 50 is, for example, substantially the same as the thickness of the interconnect stack 110, for example, in the range of 3 to 15 μm, or, for example, in the range of 5 to 10 μm.

[0039] Preferably, the amorphous silicon region 50 is in contact with a material (e.g., silicon oxide) with a refractive index less than that of amorphous silicon along its periphery and substantially its entire height. Therefore, light originating from the substrate portion 100F of window F is vertically directed toward the underlying pixel P2.

[0040] The thickness of the substrate 100 is, for example, in the range of 2 to 10 μm, or, for example, in the range of 3 to 5 μm.

[0041] For example, in a top view, the size of each window F is substantially the same as the size of pixel P1 of sensor C1. For example, in a top view, the maximum size of each pixel P1 or window F of sensor C1 is less than 10 μm, for example less than 5 μm, for example less than 2 μm, for example approximately 1 μm.

[0042] In the example shown, the front surface of substrate 100 is coated with a passivation layer 115, such as a silicon oxide layer, an HfO2 layer, an Al2O3 layer, or a stack of multiple different material layers capable of having functions other than passivation (anti-reflection, filtering, bonding, etc.), which extends substantially over the entire surface of the sensor. For example, layer 115 is disposed on and in contact with the front surface of substrate 100.

[0043] exist Figure 1 In the example, sensor C1 is a 2D color image sensor, meaning it includes different types of pixels P1 capable of measuring light intensity within different visible light wavelength ranges. For this purpose, each pixel P1 includes a color filter 118, such as a colored resin layer, disposed on the front surface side of substrate 100. As an example, sensor C1 includes three types of pixels P1: a first pixel P1 called a blue pixel, including a color filter 118 that preferably transmits blue light; a second pixel P1 called a red pixel, including a color filter 118 that preferably transmits red light; and a third pixel P1 called a green pixel, including a color filter 118 that preferably transmits green light. Figure 1 In the image, different types of pixels P1 are not distinguished.

[0044] exist Figure 1 In this example, each pixel P1 also includes an infrared bandstop filter 120, such as an interference filter. For example, the filter 120 is adapted to transmit light of all wavelengths except those centered on the emission wavelength range of the light source. In this example, the filter 120 is disposed on the front surface side of the substrate 100, for example, disposed above and in contact with the front surface of the passivation layer 115, and extends substantially across the entire surface of each pixel P1. For example, a color filter 118 is disposed above and in contact with the front surface of the filter 120. The filter 120 enables the prevention of light from the light source and reflected by the scene from being detected by the pixel P1, thus avoiding degradation of the quality of the 2D image acquired by the pixel P1. More generally, the filter 120 is capable of blocking infrared radiation to improve the color rendering of the 2D image.

[0045] As a variation, sensor C1 can be a monochrome 2D image sensor, in which case filter 118 can be omitted.

[0046] In the illustrated example, each window F of sensor C1 includes a filter 121, such as a resin filter and / or an interference filter, capable of transmitting light within the emission wavelength range of the light source. Preferably, the filter 121 is only capable of transmitting light in a relatively narrow band centered on the emission wavelength range of the system's light source, for example, a wavelength range with a full width at half maximum (FWHM) of less than 30 nm, less than 20 nm, or less than 10 nm. In this example, the filter 121 is disposed on the front surface side of the substrate 100, for example, inside and in contact with the front surface of the passivation layer 115, and extends substantially across the entire surface of window F. The filter 121 is able to prevent the photodiode of the underlying pixel P2 from unnecessarily activating under light radiation not from the system's light source. Figure 1 In this example, filter 121 is located only at the level of the sensor window F.

[0047] Each pixel P1 of sensor C1 may also include a microlens 122 disposed on the front surface side of substrate 100, for example above and in contact with the color filter 118 of the pixel, capable of focusing incident light onto the pixel photodiode 101.

[0048] Furthermore, each window F of the sensor C1 may include a microlens 122 disposed on the front surface side of the substrate 100, for example, above and in contact with the filter 120 of the window.

[0049] In this example, the rear surface of sensor C1 is bonded to the front surface of sensor C2 via molecular bonding. For this purpose, sensor C1 includes a layer 126a coated on its rear surface, for example, made of silicon oxide. Furthermore, sensor C2 includes a layer 126b coated on its front surface, having the same properties as, for example, the silicon oxide layer 126a. The rear surface of layer 126a contacts the front surface of layer 126b to achieve molecular bonding from sensor C2 to sensor C1. For example, layers 126a and 126b extend continuously over substantially the entire surface of sensors C1 and C2, respectively.

[0050] In the example shown, sensor C1 also includes a layer 128 on its rear surface side, between interconnect stack 110 and layer 126a. This layer 128 is formed of a material with a different refractive index than layers 126a and 126b, for example, a material with a higher refractive index than layers 126a and 126b, such as silicon nitride. As an example, layer 128 extends continuously over substantially the entire surface of sensor C1. Layer 126a contacts the rear surface of layer 128, for example, through its front surface.

[0051] Furthermore, in this example, sensor C2 also includes, on its front surface side, between substrate 130 and layer 126b, a layer 132 formed of a material with a refractive index different from that of layers 126a and 126b, for example, a layer made of the same material as layer 128 (e.g., silicon nitride). As an example, layer 132 extends continuously over substantially the entire surface of sensor C2. Layer 126a contacts the front surface of layer 132, for example, through its rear surface.

[0052] In this example, the stacking of layers 128-126a and 126b-132 forms an anti-reflective stack that facilitates light transmission from each transmission window F of sensor C1 to the photosensitive area of ​​the underlying pixel P2. The thicknesses of layers 128, 126a, 126b, and 132 can be selected based on the emission wavelength of the light source to enhance the anti-reflective function of the stack at the emission wavelength of the light source, for example, making the reflectivity of the stack at the emission wavelength of the light source less than 6%. As a non-limiting example, for an operating wavelength of 940 nm for the light source, and with layers 128 and 132 made of silicon nitride and layers 126a and 126b made of silicon oxide, layers 128 and 132 can each have a thickness of 119 nm, and the sum of the thicknesses of layers 126a and 126b can be approximately 200 nm.

[0053] Each pixel P2 of sensor C2 includes a SPAD-type photodiode 133 formed in substrate 130, opposite a corresponding window F of sensor C1. The photodiode 133 includes one or more semiconductor regions formed in the semiconductor substrate 130. Each pixel P2 may also include one or more additional elements (not shown), such as control transistors, formed on the back surface side of substrate 130, for example, in and on the back surface of substrate 130. Sensor C2 also includes an interconnect stack 140 formed by alternating dielectric and conductive layers coated on the back surface of substrate 130, in which electrical connection tracks and / or terminals 141 are formed to connect the pixels P2 of the sensor to peripheral control and power circuitry (not shown).

[0054] SPAD photodiodes are essentially formed by a reverse PN junction with a reverse bias voltage higher than or equal to their avalanche threshold. When there is no charge in the depletion region or space charge region of the PN junction, the photodiode is in a non-conductive pseudo-steady state. When photogenerated charge is injected into the depletion region, if the displacement velocity of that charge in the depletion region is large enough—that is, if the electric field in the depletion region is strong enough—the photodiode can avalanche. Therefore, a single photon can generate a measurable electrical signal, and this has a very short response time, making it particularly suitable for time-of-flight measurements. Most known SPAD photodiode structures are available for use with... Figure 1The sensor C2, for example, has a structure with a planar surface PN junction, a structure with a planar buried PN junction, or a structure with a planar vertical PN junction, as described, for example, in French patent application Nr. 16 / 58513 filed September 13, 2016, and the corresponding PCT application Nr. PCT / FR2017 / 052406 (B15154 / DD17140) filed September 11, 2017. For example, as described in the aforementioned French and PCT applications, a SPAD photodiode with a vertical PN junction advantageously limits the effective surface area for detection of pixel P2. This makes the size of pixel P2 and the corresponding window F relatively small in a top view, for example, the same size as pixel P1, thereby limiting the resolution loss of the 2D image due to the presence of window F.

[0055] In the example shown, in each pixel P2 of sensor C2, the photodiode 133 of the pixel is completely surrounded by a vertical insulating wall 135 extending through the entire thickness of a substrate 130. The wall 135 is particularly optically insulating and may further be electrically insulating. As an example, the vertical insulating wall 135 is made of a dielectric material, such as silicon oxide. As a variation, the vertical insulating wall 135 is a multilayer wall comprising an inner layer made of a dielectric material (e.g., silicon oxide), one or more intermediate layers comprising at least one metal layer, and an outer layer made of a dielectric material (e.g., silicon oxide).

[0056] In the example shown, the lateral dimension of the detection area of ​​pixel P2 (defined by wall 135) is larger than the lateral dimension of the transmission window F, which allows the alignment constraints on the assembly of sensors C1 and C2 to be lifted. However, the described embodiment is not limited to this specific case. As a variation, the lateral dimension of the photosensitive area of ​​the detection area of ​​pixel P2 is substantially the same as the lateral dimension of the transmission window F. In this case, the vertical insulating wall 135 can be located substantially perpendicularly to the vertical insulating wall 103 of the substrate portion 100 surrounding the corresponding window F of sensor C1 on the same straight line.

[0057] Walls 103 and 135, and the vertical guide through the amorphous silicon region 50, can limit the risk of light rays received by pixel P1 near window F activating the SPAD photodiode of the corresponding pixel P2, which could lead to erroneous depth measurements.

[0058] It should be noted that SPAD photodiodes are generally associated with secondary circuitry, particularly circuitry for biasing their PN junction to a voltage greater than their avalanche threshold, readout circuitry capable of detecting the onset of avalanche in the photodiode, and quenching circuitry capable of interrupting avalanche once it begins. Such secondary circuitry is not shown in the figures and will not be detailed. The described embodiments are compatible with secondary circuitry used with known SPAD photodiodes. For example, the secondary circuitry may be arranged at least partially inside and on top of the rear surface of the portion of substrate 130 located outside the vertical insulating wall 135 of the pixel.

[0059] Although Figure 1 This is not shown in the diagram, but as a variation, sensor C2 may also include a metal shielding layer that is substantially coated on the entire front surface of substrate 130, except for the portion of substrate 130 located within wall 135 (corresponding to the photodetector region of pixel P2). For example, the metal shielding layer is disposed between substrate 130 and dielectric layer 132. Here, the metal shielding layer functions as an optical insulator, designed to prevent light received by pixel P1 near window F from activating the SPAD photodiode of the corresponding pixel P2. As a variation, the metal shielding layer is not continuous, but is formed by multiple separate rings that, in top view, respectively surround the photodetector regions of different pixels P2 of the sensor. One advantage is that this limits parasitic light reflection from the metal shielding layer to pixel P1 of sensor C1.

[0060] The thickness of the substrate 130 is, for example, in the range of 5 to 50 μm, or, for example, in the range of 8 to 20 μm.

[0061] It should be pointed out that, Figure 1 The arrangement of sensors C1 and C2 in the illustrated device is advantageous because the interconnect stack 140 of sensor C2 is located on the side of sensor substrate 130 opposite to sensor C1. In fact, one difficulty encountered when integrating conventional photodiode pixels and SPAD photodiode pixels is that the power supply levels required by these two types of pixels differ significantly, necessitating relatively large electrically insulating elements between adjacent pixels of different types. Figure 1 In the example, sensors C1 and C2 are naturally electrically isolated at the level of their respective pixel arrays and at the level of their respective control / readout circuitry. Since the interconnect stack 140 of sensor C2 is arranged on the side of substrate 130 opposite to sensor C1, the risk of breakdown and / or parasitic coupling due to the potential difference between the conductive power tracks of the pixels of sensor C1 and the conductive power tracks of the pixels of sensor C2 is avoided. For example, in Figure 1 In the device, the power supply voltage of pixel P2 of sensor C2 is at least 5 times or even 10 times that of pixel P1 of sensor C1.

[0062] In the example shown, sensor C2 is bonded to a support substrate 150, such as a silicon substrate, via its rear surface. As a variation, for example, as described in the aforementioned patent application EP3503192... Figure 1 The supporting substrate may be replaced by additional control and processing circuitry (not shown) formed inside and on top of the third semiconductor substrate.

[0063] Figures 2A to 2J This is a simplified cross-sectional view, illustrating... Figure 1 The sequential steps of the manufacturing method of the device shown.

[0064] Figure 2A It shows Figure 1 An embodiment of the 2D image sensor C1 of the device shown.

[0065] To form the sensor, it begins with a relatively thick semiconductor substrate 100, for example, a substrate with a thickness of several hundred micrometers.

[0066] The implantation area for the photodiode 101 and the possible element for controlling the pixel P1 of the sensor is formed by the first surface of the substrate, i.e. Figure 2A The upper surface of the substrate 100 is formed in the direction shown. In the top view, the vertical insulating wall 103 that defines the sensor window F is also formed from the upper surface of the substrate 100.

[0067] Then, an interconnect stack 110 of the sensor C1 is formed on the upper surface of the substrate 100. In this example, as... Figure 2A As shown, the metal layer of the interconnect stack 110 does not extend relative to the transmission window F of the sensor C1.

[0068] In this example, an etch stop layer 201, for example made of silicon nitride, is further deposited on the upper surface of the interconnect stack 110.

[0069] Figure 2B The subsequent step is illustrated, namely, forming an opening 203 from the upper surface of the structure, which perpendicularly passes through layer 201 and interconnect stack 110 and appears on the upper surface of semiconductor substrate 100. The opening extends across the entire surface of the transmission window F of sensor C1. The opening 203 is formed, for example, by photolithography and etching.

[0070] Figure 2C , 2D Figures 2 and 2E illustrate an optional step of forming a dielectric coating, for example, made of silicon oxide, on the sidewall of opening 203.

[0071] Figure 2C More specifically, the deposition step of a silicon oxide layer 205 with a thickness greater than the height of the opening 203, completely filling the opening 203, is described.

[0072] Figure 2D The following step is illustrated, for example, planarizing the upper surface of layer 205 by CMP (“chemical-mechanical polishing”). Planarization is interrupted at the level of stop layer 201. Thus, at the end of this step, layer 205 is removed elsewhere except for the opposing transmission window F, with the portion of layer 205 remaining in the transmission window flush with the upper surface of stop layer 201.

[0073] Figure 2E The step of removing the central portion of layer portion 205 located within opening 203 at the level of each transmission window F is shown. At the end of this step, only the peripheral region of layer 205 covering the sidewalls of opening 203 is retained. As an example, the layer portion 205 retained in this step coats the sidewalls of opening 203 substantially along the entire height of opening 203. Removal of the central portion of layer portion 205 is performed, for example, by photolithography and etching. In this step, the pathway on the upper surface of the semiconductor substrate 100 opposite to the transmission window F is released. The layer portion 205 retained on the side of opening 203 is intended to form a vertical wall for optically guiding the amorphous silicon region 50 through the transmission window F. Figure 2D (Not shown in the image). For example, the guide wall 205 is located perpendicularly to the vertical wall 103 of the substrate portion 100F that defines the window F and is on the same straight line. As an example, in each transmission window F, the guide wall 205 contacts the upper surface of the wall 103 through its lower surface.

[0074] It should be noted that, Figure 2C , 2D The steps 2G and 2G can be omitted as a variant. In this case, the dielectric material forming the interconnect stack 50 ensures the guidance of light perpendicularly passing through each transmission window of the amorphous silicon region 50 around the amorphous silicon region 50.

[0075] In another variation, the vertical guide wall may comprise a stack of multiple layers capable of including one or more metal layers. Forming such a wall may include one or more steps of conformally depositing the layers onto the sidewalls and bottom of the opening 203, and one or more vertical anisotropic etching steps aimed at keeping the layers only on the sidewalls of the opening 203.

[0076] Figure 2F The subsequent deposition steps of the amorphous silicon layer 50, which is thicker than the height of the opening 203 and completely fills the opening 203, are shown.

[0077] Figure 2GThe following steps are illustrated, for example, planarizing the upper surface of layer 50 by CMP. Planarization is interrupted after the removal of stop layer 201. Thus, at the end of this step, layer 50 is removed everywhere except for the opposing transmission window F, and the portion of layer 50 remaining in the transmission window is flush with the upper surface of stop layer 101.

[0078] Figure 2H The following steps are illustrated: depositing a dielectric layer 128 on the upper surface side of the interconnect stack 110, followed by depositing a bonding layer 126a for the sensor C1. In this example, each of layers 128 and 126a extends continuously across the entire surface of the sensor C1. More specifically, in this example, layer 128 contacts the upper surface of the interconnect stack 110, the vertical guide wall 205, and the amorphous silicon region 50 via its lower surface. Layer 126a contacts the upper surface of layer 128 via its lower surface.

[0079] Figure 2I The parallel steps for forming the device sensor C2 are shown.

[0080] To form the sensor, it begins with a relatively thick semiconductor substrate 130, for example, a substrate with a thickness of several hundred micrometers.

[0081] The implantation area for photodiode 133 and possible elements for controlling sensor pixel P2 is formed by the first surface of the substrate, i.e. Figure 2I The upper surface of the substrate 130 is formed in the direction shown. A vertical insulating wall 135 that laterally defines the pixel P2 is further formed from the upper surface of the substrate 130.

[0082] For example, a SPAD photodiode can be formed as described in Figure 3 of the aforementioned application EP3503192, as well as in French application No. 16 / 58513 and PCT application No. PCT / FR2017 / 052406.

[0083] Interconnect stack 140 of sensor C2 is then formed on the upper surface of substrate 130.

[0084] Figure 2J The following steps are shown: thinning of the substrate 130 of sensor C2 from its surface opposite the interconnect stack 140.

[0085] For this purpose, a support substrate 150 is bonded to the surface of the interconnect stack 140 opposite to the substrate 130. Then, using the support substrate 150 as a handle, the substrate 130 is thinned from its surface opposite the interconnect stack 140, for example by grinding and / or CMP.

[0086] It should be noted that, in Figure 2J In the middle, the orientation of sensor C2 is relative to Figure 2I It's upside down.

[0087] Thinning is interrupted at the surface level of the vertical insulating wall 135 opposite the interconnect stack 140. In this example, at the end of the thinning step, the wall 135 is flush with the surface of the substrate 130 opposite the interconnect stack 140. Figure 2J The upper surface of substrate 130 in the indicated direction.

[0088] Figure 2J The following steps are also shown: depositing a dielectric layer 132 on the upper surface of the thinned substrate 130, followed by depositing a bonding layer 126a of the sensor C2. In this example, each of layers 132 and 126b extends continuously over the entire surface of the sensor C2. More specifically, in this example, layer 132 contacts the upper surface of the thinned substrate 130 and the vertical insulating wall 135 through its lower surface. Layer 126b contacts the upper surface of layer 132 through its lower surface.

[0089] The next steps of the method for manufacturing the apparatus are not shown; based on the instructions in this specification, these steps are within the capabilities of those skilled in the art. Sensor C1 can be flipped and bonded to the upper surface of sensor C2 by directly or molecularly bonding the surface of layer 126a opposite substrate 100 to the surface of layer 126b opposite substrate 130. Then, using a support substrate 150 as a handle, for example by grinding and / or CMP, substrate 100 of sensor C1 can be thinned from its surface opposite interconnect stack 110. For example, this thinning is interrupted at the surface level of the vertical insulating wall 103 opposite interconnect stack 110, so that at the end of the thinning step, wall 103 is flush with the surface of substrate 100 opposite interconnect stack 110. Then, Figure 1 The upper components of the device shown, particularly layer 115, filters 120, 118 and 121, and microlens 122, may be formed on one side of the surface of substrate 100 opposite to the interconnect stack 110.

[0090] In the top view, the arrangement of 2D pixel P1 and depth pixel P1 is the same as or similar to that in Figure 4 of the aforementioned patent application EP3503192.

[0091] exist Figure 1 In the device, the depth pixel P2 can be controlled individually to generate a depth image with a resolution equal to the number of pixels P2 of the sensor C2.

[0092] As a variation, pixel P2 can be composed of blocks of multiple adjacent pixels, for example, a block of three adjacent pixels P2 coupled together to form a photomultiplier of, for example, type SIPM. Then, it is specified that only relevant events within each block are retained. In other words, only events detected simultaneously by multiple pixels within a block are retained to construct a depth image. The resolution of the depth image is then less than the number of pixels P2 in sensor C2, but the noise immunity of the depth image sensor is thus improved.

[0093] Sensors C1 and C2 can be controlled independently. In particular, depending on the application under consideration, the rate at which sensor C1 acquires 2D images can differ from the rate at which sensor C2 acquires depth images.

[0094] Specific embodiments have been described. Various changes and modifications will occur to those skilled in the art. In particular, an embodiment in which each depth pixel P2 of sensor C2 comprises a SPAD-type photodiode has been described herein. However, the described embodiments are not limited to this particular case. As a variation, depth pixels can be formed using any other technique adapted to achieve the measurement of the time-of-flight of light signals emitted by a light source and reflected by the scene. For example, depth pixels can be locked pixels, as described in the applicant's previously filed French patent applications Nos. 16 / 62341 and 16 / 62340, i.e., pixels comprising multiple storage regions coupled to the same detection area, and the pixel being capable of measuring the phase shift between an amplitude-modulated light signal emitted by a light source and a light signal received by the photodetector area of ​​the pixel after reflection on the scene.

[0095] Furthermore, those skilled in the art are capable of adapting the provided solution to different examples of the apparatus described in the aforementioned patent application EP3503192 by replacing the optical elements 124, 124' or 124" of this document with the amorphous silicon region 50.

Claims

1. An apparatus for acquiring 2D images and depth images, comprising: A first sensor (C1) is formed inside and on top of a first semiconductor substrate (100) including a front surface and a rear surface. The first sensor (C1) includes a plurality of 2D image pixels (P1) and a plurality of transmission windows (F). Each transmission window (F) includes a portion (100F) of the first semiconductor substrate and an amorphous silicon region (50) in contact with the rear surface of the portion (100F) of the first semiconductor substrate (100). as well as The second sensor (C2) is formed inside and on top of the second semiconductor substrate (130) in the opposite direction to the first sensor (C1) on the rear surface side of the first semiconductor substrate, and includes a plurality of depth pixels (P2) arranged opposite to the transmission window (F) of the first sensor (C1). The first sensor (C1) includes an interconnect stack (110) on the rear surface side of the first semiconductor substrate (100), wherein electrical connection rails and / or terminals (111) are formed in the interconnect stack. In each transmission window (F) of the first sensor (C1), the amorphous silicon region (50) is arranged in an opening through the interconnect stack (110) of the first sensor (C1); In each transmission window (F) of the first sensor (C1), the amorphous silicon region (50) extends through a thickness substantially equal to that of the interconnect stack (110) of the first sensor (C1) and is flush with the surface of the interconnect stack (110) of the first sensor (C1) opposite to the first semiconductor substrate (100).

2. The apparatus of claim 1, wherein in each transmission window (F) of the first sensor (C1), the amorphous silicon region (50) is laterally defined along its periphery and along its entire height by a dielectric material with a refractive index less than that of amorphous silicon.

3. The apparatus of claim 1, wherein in each transmission window (F) of the first sensor (C1), the portion (100F) of the first semiconductor substrate is laterally defined along its periphery and along its entire height by a wall (103) made of a dielectric material with a refractive index less than that of the first semiconductor substrate (100).

4. The apparatus of claim 1, wherein in each transmission window (F) of the first sensor (C1), the portion (100F) of the first semiconductor substrate (100) and the amorphous silicon region (50) have substantially the same surface area in a top view.

5. The apparatus of claim 1, further comprising alternating dielectric layers (128, 126a-126b, 132) with different refractive indices between each transmission window (F) of the first sensor (C1) and the corresponding depth pixel (P2) of the second sensor (C2) to form an anti-reflective stack through which light passes through the transmission window (F) toward the depth pixel (P2).

6. The apparatus of claim 1, wherein the second sensor (C2) includes an interconnect stack (140) on the rear surface side of the second semiconductor substrate (130), wherein electrical connection rails and / or terminals (141) are formed in the interconnect stack.

7. The apparatus of claim 1, wherein each depth pixel (P2) of the second sensor (C2) comprises a SPAD-type photodiode (133).

8. The apparatus of claim 1, wherein each depth pixel (P2) of the second sensor (C2) includes a plurality of storage areas connected to the same detection area and is capable of measuring the phase shift between an amplitude-modulated light signal emitted by the light source of the apparatus and a light signal received by the pixel photoelectric detection area after reflection on the scene on which an image of it is to be acquired.

9. The apparatus of claim 1, wherein the first semiconductor substrate (100) is made of single-crystal silicon.

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