A power transistor

Abstract

The present application relates to a power transistor, comprising at least a substrate, a buffer layer and a barrier layer; and a gate, a source and a drain located above the barrier layer; wherein one or more insulating isolation structures are provided in a conductive channel below the gate and between the source and the drain. The present application also relates to an electronic device comprising the power transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power transistor with an isolation structure. Background Art

[0002] Power transistors such as high electron mobility transistors (HEMT) are widely used in high-frequency and high-power fields such as wireless communication base stations, radars, and automotive electronics. As an emerging semiconductor material, gallium nitride has the characteristics of wide bandgap and high electron mobility, and is particularly suitable for use in power semiconductor devices such as HEMT. GaN field-effect transistors show on-resistance and capacitance far lower than their silicon counterparts. GaN field-effect transistors have been proven to greatly reduce the size of power conversion systems, increase operating frequencies, and improve efficiency.

[0003] However, in actual use, power transistors inevitably have on-resistance. Even though the on-resistance of power transistors based on gallium nitride materials is smaller than that of silicon counterparts, it is not zero. The existence of this on-resistance causes the power transistor to heat up when current passes through it. The increase in temperature will in turn increase the on-resistance. Therefore, when the heat dissipation of the power transistor is not sufficient, it is possible to enter a vicious cycle of temperature increase, resistance increase, temperature increase again, resistance increase again, until the power transistor is burned out. Figure 1 The figure shows the curve of the on-resistance of the GaN power transistor as the temperature increases. It can be seen that when the temperature rises to 55 degrees Celsius, the on-resistance value and the rate of change of the power transistor increase significantly.

[0004] The method for solving the above problem in the prior art is to add an overheat protection element or module to the circuit, such as disclosed in US Pat. No. 20020171405A1, which uses a Zener diode and a heat dissipation radiator to ensure that the power transistor conducts a large current while achieving heat dissipation.

[0005] However, power transistors are usually large in area, and the temperature at each location is uneven. When the temperature is too high and the transistor burns out, it is often not the entire transistor that is burned out at all locations at the same time, but a few points form hot spots and burn out first. This situation limits the potential of power transistors such as HEMTs. Summary of the invention

[0006] In response to the technical problems existing in the prior art, the present application proposes a power transistor, which includes at least a substrate, a buffer layer and a barrier layer; and a gate, a source and a drain located above the barrier layer; wherein one or more insulating isolation structures are provided in the conductive channel below the gate and between the source and the drain.

[0007] Particularly, the isolation structure is formed in the barrier layer, or in the barrier layer and one or more layers of the structure thereunder.

[0008] Particularly, the isolation structure includes an insulating region formed by ion implantation.

[0009] Particularly, the isolation structure includes a hollow region formed by etching.

[0010] Particularly, the intervals between the isolation structures gradually increase from the center to the edge of the power transistor.

[0011] Particularly, the ion implantation material forming the isolation structure is hydrogen or helium.

[0012] Particularly, the width of the isolation structure is equal to the width of the gate.

[0013] Particularly, the width of the isolation structure is greater than or less than the width of the gate.

[0014] Particularly, the power transistor is a HEMT.

[0015] The present application also provides an electronic device, which includes one or more power transistors as described above.

[0016] The present application sets the isolation structure in the conductive channel of the power transistor, optimizes the conductive path by reducing the conductive path of the part with poor heat dissipation, makes the overall temperature distribution of the power transistor more uniform, reduces the possibility of hot spots, and improves the working stability of the power transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0018] Figure 1 Shown is a graph of the resistance and temperature relationship of a conventional GaN power transistor;

[0019] Figure 2 Shown is a cross-sectional view of a conventional HEMT power transistor;

[0020] Figure 3A The figure shows a local enlarged schematic diagram of a conventional HEMT power transistor;

[0021] Figure 3B Shown is an exemplary layout of a conventional HEMT power transistor;

[0022] Figure 4 FIG. 1 is a schematic layout diagram of a HEMT power transistor according to an embodiment of the present application;

[0023] Figure 5FIG. 1 is a schematic layout diagram of a HEMT power transistor according to another embodiment of the present application;

[0024] Figures 6A-6C Shown is a partial exemplary layout of a HEMT power transistor according to multiple embodiments of the present application;

[0025] Figure 7 It is a three-dimensional schematic diagram of a local structure of a HEMT power transistor according to an embodiment of the present application; and

[0026] Figure 8 FIG. 1 is a three-dimensional schematic diagram of a local structure of a HEMT power transistor according to another embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0029] The following is an introduction and explanation using HEMT as an example. Figure 2 FIG. 1 is a schematic cross-sectional view of a conventional HEMT. As shown in the figure, the HEMT includes at least a substrate 110, a buffer layer 120 and a barrier layer 140 from bottom to top. The substrate material may be gallium nitride, silicon, sapphire, silicon carbide, aluminum nitride, diamond, the buffer layer material may be gallium nitride, aluminum gallium nitride, aluminum nitride and a mixture thereof, and the barrier layer may be aluminum gallium nitride, aluminum nitride and the like. According to one embodiment, a source 150, a drain 170 and a gate 160 located between the source and the drain may also be provided above the barrier layer 140. The electrode materials may be metal or polycrystalline silicon. An electron potential well is formed at the HEMT heterojunction interface, and a two-dimensional electron gas is formed in the potential well, thereby forming a conductive channel 130 between the buffer layer 120 and the barrier layer 140 for directional migration of electrons from the source to the drain.

[0030] Figure 3A The following is a partial enlarged view of a conventional HEMT power transistor. Figure 3A As shown, a HEMT power transistor may include a plurality of sources 150 connected to each other, a plurality of drains 170 connected to each other, and a plurality of gates (not shown) distributed between the sources 150 and the drains 170 .

[0031] Figure 3B An exemplary layout of a conventional HEMT power transistor is shown. A corresponding gate (not shown) is distributed between each set of source 150 and drain 170 lines, and a channel region is located between the source and drain. Figure 3B The area 130 between the dotted lines in the figure represents the conductive channel area under the gate. During the operation of the power transistor, the temperature of the channel area will increase due to the presence of the on-resistance. In particular, the temperature will be higher at a location far from the edge of the transistor due to insufficient heat dissipation.

[0032] Figure 4 FIG. 1 is a schematic layout of a HEMT power transistor according to an embodiment of the present application. As shown in the figure, one or more insulating isolation structures 180 may be provided in the channel region between the source 150 and the drain 170. The channel region without the isolation structure 180 may still be conductive to form current. In some embodiments, a plurality of isolation structures 180 may be evenly distributed in the channel region, for example Figure 4 As shown, the distances between the isolation structures 180 in the channel region between a set of sources and drains may be the same.

[0033] Figure 5 The figure shows a schematic layout of a HEMT power transistor according to another embodiment of the present application. Since power transistors often have a certain area, the points with higher temperatures are often located near the central area of ​​the transistor, while the edge areas of the transistor can have more sufficient heat exchange with the environment, so the temperature is relatively lower than that of the central area. In view of this, as shown in the figure, in this embodiment, the spacing between the isolation structures 180 can gradually increase from the center to the edge of the power transistor. In other embodiments, the isolation structure 180 may not be set at the edge of the power transistor.

[0034] According to different embodiments, the distance between the isolation structures 180 or the distribution density of the isolation structures 180 may be designed and adjusted according to actual needs.

[0035] Figures 6A-6C FIG. 1 is a partial exemplary layout of a HEMT power transistor according to multiple embodiments of the present application. As shown in the figure, the area 130 between the dotted lines represents the channel area under the gate, which is only the middle part of the entire channel area between the source and the drain. Fig. 6AAs shown, the width of the isolation structure 180 can be substantially the same as the channel region below the gate or the gate width. Figure 6B As shown, the width of the isolation structure 180 may be smaller than the gate width. Figure 6C As shown, the width of the isolation structure 180 may be greater than the gate width, and the widest case of the isolation structure 180 may reach the dimension between the source and the drain.

[0036] Figure 7 The figure shows a three-dimensional schematic diagram of the local structure of a HEMT power transistor according to an embodiment of the present application. According to an embodiment, the isolation structure 180 may be an insulating region formed by ion implantation. Ion implantation can accurately control the concentration distribution and implantation depth of ions, and the lateral diffusion of ions is small, and the process conditions are easy to control. According to an embodiment of the present application, the implanted ions may be hydrogen or helium. According to an embodiment, the upper surface of the isolation structure 180 is the upper surface of the barrier layer 140, and the depth of the isolation structure 180, that is, the depth of the implantation, may involve part or all of the thickness of the barrier layer, for example, the depth of the isolation structure in the barrier layer 140 may reach 10-50 nm extending downward from the upper surface of the barrier layer 140. According to an embodiment of the present application, in addition to involving the barrier layer 140, the depth of the isolation structure 180 may also be implanted into part or all of the buffer layer 120, for example, the depth of the isolation structure 180 in the buffer layer 120 may reach 10-50 nm extending downward from the lower surface of the barrier layer 140. According to other embodiments, the HEMT may further include other layer structures, and the isolation structure 180 may at least involve or penetrate into a part or all of the barrier layer 140 , or involve or penetrate into the barrier layer 140 and one or more layers thereunder.

[0037] Figure 8 FIG. 1 is a schematic diagram of a partial structure of a HEMT power transistor according to another embodiment of the present application. As shown in the figure, the isolation structure 180 may be a hollow region formed by etching, wherein the hollow region is non-conductive. The etching method may be dry etching, wet etching, or a combination of the two methods.

[0038] In some embodiments, the width of the hollowed-out region formed by etching can also be less than, equal to, or greater than the width of the gate. The etching depth can involve part or all of the barrier layer 140, part or all of the buffer layer 120, or even part or all of the substrate 110 or other layer structures.

[0039] It is known to those skilled in the art that the above structure is not limited to GaN or any specific material, nor is it limited to the specific structure of HEMT devices.

[0040] The device structure provided by the present application can effectively alleviate the situation where the power device is heated due to the on-resistance, thereby causing the device to burn out. By effectively adjusting the isolation structure shape and distribution density, the heating problem of the device can be reduced while ensuring the electrical performance of the power device, thereby increasing the practical life of the device.

[0041] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A HEMT power transistor, comprising at least: Substrate, buffer layer and barrier layer; as well as, A gate, a source and a drain located above the barrier layer; Wherein, one or more insulating isolation structures are provided in the conductive channel below the gate and between the source and the drain; The isolation structure includes an insulating region formed by ion implantation. 2 . The HEMT power transistor according to claim 1 , wherein the isolation structure is formed in the barrier layer, or in one or more layers of the barrier layer and therebelow. 3 . The HEMT power transistor according to claim 1 , wherein the intervals between the isolation structures gradually increase from the center to the edge of the power transistor. 4 . The HEMT power transistor according to claim 1 , wherein the ion implantation material forming the isolation structure is hydrogen or helium. 5 . The HEMT power transistor according to claim 1 , wherein a width of the isolation structure is equal to a width of the gate. 6 . The HEMT power transistor according to claim 1 , wherein a width of the isolation structure is greater than or less than a width of the gate.

7. An electronic device comprising one or more HEMT power transistors according to any one of claims 1 to 6.

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