Light detection device and electronic device

Abstract

According to the present disclosure, the light detection device includes: a first pixel, which is capable of generating a first pixel signal; a reference signal generating unit, which generates a reference signal; and a first comparison unit, which includes a first power supply circuit and a first comparison circuit, the first power supply circuit is capable of generating a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node, and is capable of outputting the first power supply voltage from an output terminal, the first comparison circuit is capable of operating based on the first power supply voltage, and is capable of performing a comparison operation based on the first pixel signal and the reference signal.

Description

Technical Field

[0001] The present disclosure relates to a light detection device capable of detecting light and an electronic device including the light detection device. Background Art

[0002] In a light detection device, generally, a pixel generates a pixel signal corresponding to the amount of light received, and an AD (Analog to Digital) conversion circuit converts the pixel signal into a digital code. For example, Patent Document 1 discloses an imaging device that performs AD conversion based on a signal having a ramp waveform and a pixel signal.

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Laid-Open No. 2007-19682 Summary of the invention

[0006] Incidentally, in the light detecting device, the image quality is desired to be high, and further improvement of the image quality is desired.

[0007] It is desirable to provide a light detection device and an electronic device capable of improving image quality.

[0008] According to an embodiment of the present disclosure, a light detection device includes a first pixel, a reference signal generating unit, and a first comparing unit. The first pixel is configured to generate a first pixel signal. The reference signal generating unit is configured to generate a reference signal. The first comparing unit includes a first power supply circuit and a first comparing circuit. The first power supply circuit is capable of generating a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node, and is capable of outputting the first power supply voltage from an output terminal. The first comparing circuit operates based on the first power supply voltage, and is capable of performing a comparison operation based on the first pixel signal and the reference signal.

[0009] The electronic device according to the embodiment of the present disclosure includes the above-mentioned light detection device, and corresponds to, for example, a smartphone, a digital camera, a video camera, a notebook personal computer, or the like.

[0010] In the light detection device and the electronic device according to the embodiments of the present disclosure, the first pixel generates a first pixel signal, the reference signal generating unit generates a reference signal, the first power supply circuit generates a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node, and then, a first comparison circuit operable based on the first power supply voltage performs a comparison operation based on the first pixel signal and the reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a configuration example of an image pickup device according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A circuit diagram of a configuration example of a pixel shown.

[0013] Figure 3 It is shown Figure 1 A block diagram showing an example of the configuration of a readout unit shown.

[0014] Figure 4A It is shown Figure 3 A circuit diagram showing an example of the configuration of a comparison section is shown.

[0015] Figure 4B It is shown Figure 3 A circuit diagram of another configuration example of a comparison section shown.

[0016] Figure 5 It is shown Figure 3 A circuit diagram showing an example of the configuration of a readout section is shown.

[0017] Figure 6 It is shown Figure 1 An explanatory diagram of an embodiment of an imaging device shown in FIG.

[0018] Figure 7 It is shown Figure 1 An explanatory diagram of another embodiment of the imaging device shown.

[0019] Figure 8 It is shown Figure 1 A timing chart showing an example of the operation of the imaging device shown.

[0020] Fig. 9 It is shown Figure 1 A timing waveform diagram showing an example of the operation of the imaging device shown.

[0021] Fig. 10A is a circuit diagram showing a configuration example of a comparison section according to a modification.

[0022] Fig. 10B is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0023] Fig.11A is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0024] Fig. 11B is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0025] Fig. 12A is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0026] Fig. 12B is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0027] Fig.13 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0028] Fig.14 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0029] Fig.15 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0030] Fig.16 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0031] Fig.17 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0032] Fig.18 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0033] Fig.19 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0034] Fig. 20 is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0035] Fig.21 is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0036] Fig. 22 is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0037] Fig.23 It is shown Fig. 22 A circuit diagram showing an example of the configuration of a readout section is shown.

[0038] Fig.24 is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0039] Fig.25 is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0040] Fig.26 It is shown Fig.25 A circuit diagram showing an example of the configuration of a readout section is shown.

[0041] Fig. 27is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0042] Fig.28 is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0043] Fig.29 is a circuit diagram showing a configuration example of a readout section according to another modification example.

[0044] Fig. 30A is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0045] Fig. 30B is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0046] Fig.31A is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0047] Fig.31B is a circuit diagram showing a configuration example of a comparison section according to another modification example.

[0048] Fig.32 This is an explanatory diagram showing an example of use of the imaging device.

[0049] Fig.33 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0050] Fig.34 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0051] Fig.35 is a block diagram showing a configuration example of a distance measuring device according to an application example.

[0052] Fig.36 It is shown Fig.35 A block diagram of an example of the configuration of a light detection unit shown.

[0053] Fig.37 It is shown Fig.36 A circuit diagram of a configuration example of a pixel shown.

[0054] Fig.38 It is shown Fig.35 The waveform diagram of the operation example of the ranging device shown. DETAILED DESCRIPTION

[0055] Hereinafter, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0056] 1. Example

[0057] 2. Example of using the camera device

[0058] 3. Application examples for mobile objects

[0059] 4. Application examples of distance measuring devices

[0060] <1. Example>

[0061] [Construction example]

[0062] Figure 1 The configuration example of an image pickup device 1 to which the light detection device according to the embodiment is applied is shown. The image pickup device 1 includes a pixel array 11 , a drive section 12 , a reference signal generation section 13 , a readout section 20 , a signal processing section 14 , and an image pickup control section 15 .

[0063] The pixel array 11 includes a plurality of pixels P arranged in a matrix shape. The pixels P are respectively configured to generate a pixel voltage Vpix corresponding to the amount of received light.

[0064] Figure 2 FIG. 1 shows an example of the configuration of a pixel P. The pixel array 11 includes a plurality of control lines TGL, a plurality of control lines RSTL, a plurality of control lines SELL, and a plurality of signal lines VSL. The control lines TGL are respectively arranged in the horizontal direction ( Figure 2 The control lines RSTL extend in the horizontal direction and one end of them is connected to the driving section 12. The control signal SRST is provided to the control line RSTL by the driving section 12. The control lines SELL extend in the horizontal direction and one end of them is connected to the driving section 12. The control signal SSEL is provided to the control line SELL by the driving section 12. The signal lines VSL extend in the vertical direction ( Figure 2 The signal lines VSL extend in the longitudinal direction (in the horizontal direction) and one end thereof is connected to the readout section 20. The signal lines VSL transmit the signals SIG generated by the pixels to the readout section 20. Figure 1 and Figure 2 A plurality of pixels P arranged side by side in a row (in the horizontal direction) constitute a pixel line L.

[0065] Each pixel P includes a photodiode PD, a transistor TG, a floating diffusion FD, and transistors RST, AMP, and SEL. The transistors TG, RST, AMP, and SEL in this example are N-type MOS (Metal Oxide Semiconductor) transistors.

[0066] The photodiode PD is a photoelectric conversion unit that generates an amount of charge corresponding to the amount of received light and accumulates the charge therein. The anode of the photodiode PD is grounded, and the cathode is connected to the source of the transistor TG.

[0067] The transistor TG has a gate connected to the control line TGL, a source connected to the cathode of the photodiode PD, and a drain connected to the floating diffusion FD.

[0068] The floating diffusion FD is configured to accumulate charges transferred from the photodiode PD via the transistor TG. The floating diffusion FD is configured by using, for example, a diffusion layer formed on the front surface of a semiconductor substrate. Figure 2 In FIG. 1 , the floating diffusion FD is shown using the symbol of a capacitor.

[0069] The transistor RST has a gate connected to a control line RSTL, a drain supplied with a power supply voltage VDD, and a source connected to a floating diffusion FD.

[0070] The transistor AMP has a gate connected to the floating diffusion FD, a drain supplied with a power supply voltage VDD, and a source connected to the drain of the transistor SEL.

[0071] The gate of the transistor SEL is connected to the control line SELL, the drain is connected to the source of the transistor AMP, and the source is connected to the signal line VSL.

[0072] With this construction, in the pixel P, the transistor SEL is turned on based on the control signal SSEL supplied to the control line SELL, thereby electrically connecting the pixel P to the signal line VSL. This causes the transistor AMP to be connected to the constant current source CS (described later) of the readout section 20, and to operate as a so-called source follower. Then, the pixel P outputs a signal SIG to the signal line VSL, the signal SIG including a voltage corresponding to the voltage of the floating diffusion section FD. Specifically, as described later, the pixel P outputs a reset voltage Vreset in the P phase period TP of the two periods (P phase period TP and D phase period TD) in which the readout section 20 performs AD conversion, and outputs a pixel voltage Vpix corresponding to the amount of light received in the D phase period TD. The pixel P outputs a signal SIG including the reset voltage Vreset and the pixel voltage Vpix to the signal line VSL.

[0073] Driving unit 12( Figure 1 ) is configured to sequentially drive the plurality of pixels P in the pixel array 11 in units of pixel lines L based on instructions from the imaging control unit 15. Specifically, the driving unit 12 provides a plurality of control signals STG one-to-one to the plurality of control lines TGL in the pixel array 11, provides a plurality of control signals SRST one-to-one to the plurality of control lines RSTL, and provides a plurality of control signals SSEL one-to-one to the plurality of control lines SELL, thereby driving the plurality of pixels P in the pixel array 11 in units of pixel lines L.

[0074] The reference signal generating section 13 is configured to generate a reference signal RAMP based on an instruction from the imaging control section 15. The reference signal RAMP has a so-called ramp waveform in which a voltage level gradually changes with the passage of time in two periods (P-phase period TP and D-phase period TD) during which the readout section 20 performs AD conversion. The reference signal generating section 13 provides the reference signal RAMP to the readout section 20.

[0075] The readout section 20 is configured to generate an image signal DATA0 by performing AD conversion based on a signal SIG supplied from the pixel array 11 via a signal line VSL, based on an instruction from the imaging control section 15 .

[0076] Figure 3 FIG. 2 shows an example of the configuration of the readout section 20. It should be noted that, in addition to the readout section 20, Figure 3 Also shown are a reference signal generating unit 13, a signal processing unit 14, and an imaging control unit 15. The readout unit 20 includes a plurality of constant current sources CS (constant current sources CS[0], CS[1], CS[2], CS[3], ...), a plurality of AD converters ADC (AD converters ADC[0], ADC[1], ADC[2], ADC[3], ...), and a transmission scanning unit 29.

[0077] Multiple constant current sources CS are arranged corresponding to multiple signal lines VSL. Specifically, the 0th constant current source CS[0] is arranged corresponding to the 0th signal line VSL[0], the first constant current source CS[1] is arranged corresponding to the first signal line VSL[1], the second constant current source CS[2] is arranged corresponding to the second signal line VSL[2], and the third constant current source CS[3] is arranged corresponding to the third signal line VSL[3]. The same applies to the fourth and subsequent constant current sources CS. One end of each constant current source CS is connected to the corresponding signal line VSL, and the other end is grounded. Each of the multiple constant current sources CS is configured to apply a predetermined current to the corresponding signal line VSL.

[0078] A plurality of AD conversion units ADC are provided corresponding to a plurality of signal lines VSL. Specifically, the 0th AD conversion unit ADC[0] is provided corresponding to the 0th signal line VSL[0], the first AD conversion unit ADC[1] is provided corresponding to the first signal line VSL[1], the second AD conversion unit ADC[2] is provided corresponding to the second signal line VSL[2], and the third AD conversion unit ADC[3] is provided corresponding to the third signal line VSL[3]. The same applies to the fourth and subsequent AD conversion units ADC. Each of the plurality of AD conversion units ADC is configured to convert the voltage of the signal SIG into a digital code CODE by performing AD conversion based on the signal SIG provided from the pixel array 11. Each AD conversion unit ADC includes a comparison unit 21, a counter 24, and a latch 25.

[0079] The comparison section 21 is configured to generate a signal CMPO by performing a comparison operation based on a reference signal RAMP supplied from the reference signal generation section 13 and a signal SIG supplied from the pixel P via a signal line VSL. The comparison section 21 sets an operation point based on control signals AZSW and AXN supplied from the imaging control section 15, and then performs a comparison operation. The comparison section 21 includes a power supply circuit 22 and a comparison circuit 23.

[0080] Figure 4A 1 shows a configuration example of the comparison section 21. The comparison section 21 is provided with a power supply voltage VDD0, a ground voltage VSS0, and bias voltages VB1 and VB2. The power supply voltage VDD0 is provided from the camera control section 15 via a power supply line VDDL. The power supply circuit 22 of the comparison section 21 includes a transistor MN10. The comparison circuit 23 of the comparison section 21 includes capacitors C1 and C2, transistors MP11, MN11, MP12, and MN12, switches SW1 and SW2, and a capacitor C3. The transistors MP11 and MP12 are P-type MOS transistors, and the transistors MN10 to MN12 are N-type MOS transistors. In this example, although not shown, the back gates of the transistors MP11 and MP12 are provided with the power supply voltage VDD0, and the back gates of the transistors MN10 to MN12 are provided with the ground voltage VSS0.

[0081] The gate of the transistor MN10 is supplied with a bias voltage VB1, the drain is connected to the power supply line VDDL, and the source is connected to the sources of the transistors MP11 and MP12. The transistor MN10 operates as a so-called source follower, thereby outputting the power supply voltage VDD1 from the source.

[0082] Each of the capacitors C1 and C2 has one end (terminal T1) and the other end (terminal T2). One end of the capacitor C1 is connected to the reference signal generating unit 13, and the other end is connected to the other end of the capacitor C2, the gate of the transistor MP11, and one end of the switch SW1. One end of the capacitor C1 is provided with a reference signal RAMP generated by the reference signal generating unit 13. One end of the capacitor C2 is connected to the signal line VSL, and the other end is connected to the other end of the capacitor C1, the gate of the transistor MP11, and one end of the switch SW1. One end of the capacitor C2 is provided with a signal SIG generated by the pixel P.

[0083] The gate of transistor MP11 is connected to the other end of capacitors C1 and C2 and one end of switch SW1, the drain is connected to the drain of transistor MN11, the gate of transistor MP12 and the other end of switch SW1, and the source is connected to the source of transistors MN10 and MP12. The gate of transistor MN11 is provided with bias voltage VB2, the drain is connected to the drain of transistor MP11, the gate of transistor MP12 and the other end of switch SW1, and the source is provided with ground voltage VSS0. Transistor MN11 is a load of transistor MP11 and works as a constant current source. Switch SW1 is configured to be turned on and off based on control signal AZSW, and one end of switch SW1 is connected to the other end of capacitors C1 and C2 and the gate of transistor MP11, and the other end is connected to the drain of transistors MP11 and MN11 and the gate of transistor MP12. Transistors MP11 and MN11 and switch SW1 are included in the primary circuit 101 of comparison circuit 23.

[0084] The gate of transistor MP12 is connected to the drains of transistors MP11 and MN11 and the other end of switch SW1, the drain is connected to the drain of transistor MN12 and one end of switch SW2, and the source is connected to the sources of transistors MN10 and MP11. The gate of transistor MN12 is connected to one end of capacitor C3 and the other end of switch SW2, the drain is connected to the drain of transistor MP12 and one end of switch SW2, and the source is provided with ground voltage VSS0. Switch SW2 is configured to be turned on and off based on control signal AZN, and one end of switch SW2 is connected to the drains of transistors MP12 and MN12, and the other end is connected to the gate of transistor MN12 and one end of capacitor C3. One end of capacitor C3 is connected to the gate of transistor MN12 and the other end of switch SW2, and the other end is provided with ground voltage VSS0. It should be noted that capacitor C3 may be configured by MOS capacitor or the like, or may be configured by parasitic capacitance at the gate of transistor MN12, parasitic capacitance at switch SW2, or parasitic capacitance at wiring, for example. The transistors MP12 and MN12 , the switch SW2 , and the capacitor C3 are included in the subsequent-stage circuit 102 of the comparison circuit 23 .

[0085] With this configuration, in the comparison section 21, the power supply circuit 22 generates the power supply voltage VDD1, and the comparison circuit 23 operates based on the power supply voltage VDD1, thereby performing a comparison operation based on the signal SIG and the reference signal RAMP. Specifically, the current generated by the transistor MN11 operating as a constant current source flows through the transistor MN10, and the transistor MN10 operates as a so-called source follower. Therefore, the power supply circuit 22 generates the power supply voltage VDD1. In the comparison circuit 23, as described later, the operating point is set by turning on switches SW1 and SW2. Then, the comparison circuit 23 performs a comparison operation based on the reference signal RAMP and the reset voltage Vreset included in the signal SIG in the P-phase period TP, and performs a comparison operation based on the reference signal RAMP and the pixel voltage Vpix included in the signal SIG in the D-phase period TD.

[0086] It should be noted that in this example, the comparison section 21 is as follows Figure 4A The comparison unit 21 may also be configured as shown, but is not limited thereto. Figure 4B The comparison unit 21A shown in FIG. 1 is configured in the same manner as the comparison unit 21A shown in FIG. In this example, the ground voltage VSS0 is supplied from the imaging control unit 15 via the ground line VSSL. The comparison unit 21A includes a power supply circuit 22A and a comparison circuit 23A. The power supply circuit 22A includes a transistor MP20. The comparison circuit 23A includes capacitors C11 and C12, transistors MN21, MP21, MN22, and MP22, switches SW11 and SW12, and a capacitor C13. The transistors MP20 to MP22 are P-type MOS transistors, and the transistors MN21 and MN22 are N-type MOS transistors.

[0087] The transistor MP20 has a gate supplied with a bias voltage VB1, a drain connected to a ground line VSSL, and a source connected to sources of the transistors MN21 and MN22. The transistor MP20 operates as a so-called source follower, thereby outputting a ground voltage VSS1 from a source.

[0088] Each of the capacitors C11 and C12 has one end and the other end. One end of the capacitor C11 is connected to the reference signal generating section 13, and the other end is connected to the other end of the capacitor C12, the gate of the transistor MN21, and one end of the switch SW11. One end of the capacitor C11 is provided with a reference signal RAMP generated by the reference signal generating section 13. One end of the capacitor C12 is connected to the signal line VSL, and the other end is connected to the other end of the capacitor C11, the gate of the transistor MN21, and one end of the switch SW11. One end of the capacitor C12 is provided with a signal SIG generated by the pixel P.

[0089] The gate of transistor MN21 is connected to the other end of capacitors C11 and C12 and one end of switch SW11, the drain is connected to the drain of transistor MP21, the gate of transistor MN22 and the other end of switch SW11, and the source is connected to the source of transistors MP20 and MN22. The gate of transistor MP21 is provided with bias voltage VB2, the drain is connected to the drain of transistor MN21, the gate of transistor MN22 and the other end of switch SW11, and the source is provided with power supply voltage VDD0. Transistor MP21 is a load of transistor MN21 and operates as a constant current source. Switch SW11 is configured to be turned on and off based on control signal AZSW, and one end of switch SW11 is connected to the other end of capacitors C11 and C12 and the gate of transistor MN21, and the other end is connected to the drain of transistors MN21 and MP21 and the gate of transistor MN22. Transistors MN21 and MP21 and switch SW11 are included in the primary circuit 101 of comparison circuit 23A.

[0090] The gate of transistor MN22 is connected to the drain of transistors MN21 and MP21 and the other end of switch SW11, the drain is connected to the drain of transistor MP22 and one end of switch SW12, and the source is connected to the source of transistors MP20 and MN21. The gate of transistor MP22 is connected to one end of capacitor C13 and the other end of switch SW12, the drain is connected to the drain of transistor MN22 and one end of switch SW12, and the source is provided with power supply voltage VDD0. Switch SW12 is configured to be turned on and off based on control signal AZN, and one end of switch SW12 is connected to the drain of transistors MN22 and MP22, and the other end is connected to the gate of transistor MP22 and one end of capacitor C13. One end of capacitor C13 is connected to the gate of transistor MP22 and the other end of switch SW12, and the other end is provided with power supply voltage VDD0. Transistors MN22 and MP22, switch SW12, and capacitor C13 are included in the post-stage circuit 102 of comparison circuit 23A.

[0091] Figure 5 1 and 2 , and a connection example of the power supply line VDDL and the plurality of comparison sections 21 is shown. Note that in this figure, the transistor MN11 of the comparison circuit 23 is represented by the symbol of a constant current source, and the subsequent circuit 102 (transistors MP12 and MN12, switch SW2, and capacitor C3) of the comparison circuit 23 is represented by the symbol of an amplifier circuit.

[0092] like Figure 3 and Figure 5As shown, the imaging control section 15 supplies the power supply voltage VDD0 to the plurality of comparison sections 21 via the power supply line VDDL. In each of the plurality of comparison sections 21, the power supply circuit 22 (transistor MN10) generates the power supply voltage VDD1 based on the power supply voltage VDD0, and supplies the generated power supply voltage VDD1 to the comparison circuit 23. Then, the comparison circuit 23 performs a comparison operation based on the reference signal RAMP and the signal SIG, and generates a signal CMPO.

[0093] Counter 24( Figure 3 ) is configured to perform a counting operation based on the signal CMPO supplied from the comparison section 21 and the control signal CTL supplied from the imaging control section 15. In the counting operation, pulses of the clock signal CLK supplied from the imaging control section 15 are counted.

[0094] The latch 25 is configured to generate a digital code CODE based on the count value obtained by the counter 24 and to hold the digital code CODE. Specifically, the latch 25 generates a digital code CODE corresponding to the difference (CNTD-CNTP) between the count value CNTP obtained by the counter 24 in the P-phase period TP and the count value CNTD obtained by the counter 24 in the D-phase period TD. Then, the latch 25 outputs the digital code CODE to the bus wiring BUS based on the control signal provided from the transmission scanning section 29.

[0095] The transmission scanning section 29 is configured to control based on the control signal CTL2 supplied from the imaging control section 15 so that the latches 25 of the plurality of AD conversion sections ADC sequentially output the digital code CODE to the bus wiring BUS. The reading section 20 sequentially transmits the plurality of digital codes CODE supplied from the plurality of AD conversion sections ADC as the image signal DATA0 to the signal processing section 14 using the bus wiring BUS.

[0096] Signal processing unit 14 ( Figure 1 ) is configured to generate an image signal DATA by performing predetermined signal processing on the image signal DATA0 based on an instruction from the imaging control section 15, and output the image signal DATA.

[0097] The imaging control section 15 is configured to supply control signals to the driving section 12, the reference signal generating section 13, the readout section 20, and the signal processing section 14, and to control the operations of these circuits, thereby controlling the operation of the imaging device 1. Specifically, the imaging control section 15 supplies the control signal to the driving section 12, thereby performing control so that the driving section 12 sequentially drives the plurality of pixels P in the pixel array 11 in units of pixel lines L. In addition, the imaging control section 15 supplies the control signal to the reference signal generating section 13, thereby performing control so that the reference signal generating section 13 generates the reference signal RAMP. In addition, the imaging control section 15 supplies the power supply voltage VDD0 and the bias voltages VB1 and VB2 to the readout section 20, and supplies the control signals AZSW, AZN, CTL, and CTL2 and the clock signal CLK to the readout section 20, thereby performing control so that the readout section 20 generates the image signal DATA0 by performing AD conversion based on the signal SIG. In addition, the imaging control section 15 controls the operation of the signal processing section 14 by supplying the control signal to the signal processing section 14.

[0098] Next, the implementation of the imaging device 1 will be described. In the imaging device 1, for example, Figure 1 Each of the blocks shown may be formed in one semiconductor substrate, or may be formed in a plurality of semiconductor substrates.

[0099] Figure 6 An embodiment of the imaging device 1 in which each block is formed in one semiconductor substrate 200 is shown. In the semiconductor substrate 200, a pixel array 11 is provided, and a driving section 12 is provided on the left side of the pixel array 11. In addition, a readout section 20 is provided below the pixel array 11. In the readout section 20, a constant current source section 201 including a plurality of constant current sources CS, a comparison circuit section 202 including a plurality of comparison sections 21, a counter section 203 including a plurality of counters 24, a latch section 204 including a plurality of latches 25, and a transmission scanning section 29 are arranged in order from the top. A reference signal generating section 13 and an imaging control section 15 are provided on the left side of the readout section 20. In addition, a signal processing section 14 is provided on the right side of the pixel array 11 and the readout section 20.

[0100] Figure 7An embodiment of the imaging device 1 is shown in which each block is formed in two semiconductor substrates 211 and 212. For example, the pixel array 11 is provided in the semiconductor substrate 211, and the readout section 20, the drive section 12, the reference signal generating section 13, the signal processing section 14, and the imaging control section 15 are provided in the semiconductor substrate 212. The semiconductor substrates 211 and 212 are stacked on each other. Then, a plurality of signal lines VSL arranged in the semiconductor substrate 211 are electrically connected to the readout section 20 arranged in the semiconductor substrate 212 via, for example, TSV (Through Silicon Via), and a plurality of control lines TGL, a plurality of control lines RSTL, and a plurality of control lines SELL arranged in the semiconductor substrate 211 are electrically connected to the drive section 12 arranged in the semiconductor substrate 212 via, for example, TSV. The readout section 20 is provided in the semiconductor substrate 212, and the drive section 12, the reference signal generation section 13 and the imaging control section 15 are provided on the left side of the readout section 20, and the signal processing section 14 is provided on the right side of the readout section 20. In the readout section 20, a constant current source section 201 including a plurality of constant current sources CS, a comparison circuit section 202 including a plurality of comparison sections 21, a counter section 203 including a plurality of counters 24, a latch section 204 including a plurality of latches 25, and a transmission scanning section 29 are arranged in order from the top.

[0101] In each block, the above method ( Figure 7 ) is formed in two semiconductor substrates 211 and 212, by mainly providing the pixel array 11 in the semiconductor substrate 211, it is possible to manufacture the semiconductor substrate 211 by using a semiconductor manufacturing process specific to the pixel. That is, the semiconductor substrate 211 does not include a circuit other than the pixel array 11, and therefore, for example, even in the case where a specific manufacturing process is used to form the pixel, the manufacturing process does not affect the circuit other than the pixel array 11. Therefore, in the image pickup device 1, a semiconductor manufacturing process dedicated to pixel formation can be used, so that the image pickup characteristics of the image pickup device 1 can be improved.

[0102] Here, the pixel P corresponds to a specific example of a “first pixel” in the present disclosure. The comparison section 21 corresponds to a specific example of a “first comparison section” in the present disclosure. The power supply circuit 22 corresponds to a specific example of a “first power supply circuit” in the present disclosure. The comparison circuit 23 corresponds to a specific example of a “first comparison circuit” in the present disclosure. The transistor MN10 corresponds to a specific example of a “first power supply transistor” in the present disclosure. The capacitor C1 corresponds to a specific example of a “first capacitor” in the present disclosure. The capacitor C2 corresponds to a specific example of a “second capacitor” in the present disclosure. The transistor MP11 corresponds to a specific example of a “first transistor” in the present disclosure. The switch SW1 corresponds to a specific example of a “first switch” in the present disclosure. The transistor MN11 corresponds to a specific example of a “first current source” in the present disclosure. The transistor MP12 corresponds to a specific example of a “second transistor” in the present disclosure. The transistor MN12 corresponds to a specific example of a “third transistor” in the present disclosure. The switch SW2 corresponds to a specific example of a “second switch” in the present disclosure.

[0103] [Operation and function]

[0104] Next, the operation and effect of the image pickup apparatus 1 according to the present embodiment will be described.

[0105] (Overview of overall operation)

[0106] First, refer to Figure 1 The outline of the overall operation of the image pickup device 1 is described. The driving section 12 sequentially drives a plurality of pixels P in the pixel array 11 in units of pixel lines L based on an instruction from the image pickup control section 15. Each pixel P outputs a reset voltage Vrest as a signal SIG in a P-phase period TP, and outputs a pixel voltage Vpix corresponding to the amount of light received as a signal SIG in a D-phase period TD. The reference signal generating section 13 generates a reference signal RAMP based on an instruction from the image pickup control section 15. The readout section 20 generates an image signal DATA0 by performing AD conversion based on a signal SIG supplied from the pixel array 11 via a signal line VSL based on an instruction from the image pickup control section 15. The signal processing section 14 generates an image signal DATA by performing predetermined signal processing on the image signal DATA0 based on an instruction from the image pickup control section 15. The image pickup control section 15 supplies a control signal to the driving section 12, the reference signal generating section 13, the readout section 20, and the signal processing section 14, and controls the operations of these circuits, thereby controlling the operation of the image pickup device 1.

[0107] (Detailed operation)

[0108] In the image pickup device 1, the plurality of pixels P respectively accumulate charges corresponding to the amount of light received, and output a pixel voltage Vpix corresponding to the amount of light received as a signal SIG. Then, the readout section 20 performs AD conversion based on the signal SIG. This operation is described in detail below.

[0109] Figure 8 An example of an operation of scanning a plurality of pixels P in the pixel array 11 is shown.

[0110] In the period from time t0 to time t1, the camera device 1 sequentially exposes the pixel array 11 from the top in the vertical direction and starts driving D1. Specifically, the driving section 12 generates control signals STG and SRST, for example, so as to sequentially select the pixel line L, and sequentially turn on the transistors TG and RST in the pixel P for a predetermined length of time. Therefore, in each pixel P, the voltage of the floating diffusion FD and the voltage of the cathode of the photodiode PD are set to the power supply voltage VDD. Then, the transistors TG and RST are turned off, so that the photodiode PD starts to accumulate charges corresponding to the amount of light received. Therefore, in a plurality of pixels P, the exposure period T starts sequentially.

[0111] In the period from time t2 to time t3, the image pickup device 1 sequentially performs readout drive D2 on the pixel array 11 from the top in the vertical direction. Specifically, as described later, the drive section 12 sequentially selects the pixel lines L by generating control signals STG and SRST. Therefore, the pixel P outputs the reset voltage Vreset as the signal SIG in the P phase period TP, and outputs the pixel voltage Vpix as the signal SIG in the D phase period TD. The readout section 20 generates a digital code CODE by performing AD conversion based on the signal SIG.

[0112] The image pickup device 1 repeats the above-mentioned exposure start drive D1 and the above-mentioned readout drive D2. Thus, the image pickup device 1 obtains a captured image.

[0113] Next, the readout drive D2 will be described in detail. Next, focusing on a certain pixel P (pixel P1) among the plurality of pixels P, operations of the pixel P1 and the AD converter ADC (AD converter ADC1) connected to the pixel P1 will be described in detail.

[0114] Fig. 9An operation example of the readout driver D2 in the pixel of interest P1 is shown, wherein (A) represents the waveform of the control signal SSEL, (B) represents the waveform of the control signal SRST, (C) represents the waveform of the control signal STG, (D) represents the waveform of the signal SIG, (E) represents the waveform of the control signal AZSW, (F) represents the waveform of the reference signal RAMP, (G) represents the waveform of the gate voltage Vg of the transistor MP11 in the comparison section 21 of the AD conversion section ADC1, and (H) represents the waveform of the signal CMPO in the AD conversion section ADC1. The waveform of the control signal AZN is the same as that of the control signal AZSW.

[0115] In the image pickup device 1, within a certain horizontal period (H), first, the pixel P1 outputs the reset voltage Vrest by performing a reset operation, and the AD conversion section ADC1 performs AD conversion based on the reset voltage Vreset in the P phase period TP. Then, the pixel P1 performs a charge transfer operation to output the pixel voltage Vpix, and the AD conversion section ADC1 performs AD conversion based on the pixel voltage Vpix in the D phase period TD. This operation is described in detail below.

[0116] First, at time t11, when the horizontal period H starts, the driving section 12 changes the voltage of the control signal SSEL from a low level to a high level ( Fig. 9 (A)). Therefore, in the pixel P1, the transistor SEL is turned on, and the pixel P1 is electrically connected to the signal line VSL. In addition, at time t11, the driving unit 12 changes the voltage of the control signal SRST from a low level to a high level ( Fig. 9 (B)). Therefore, in the pixel P1, the transistor RST is turned on, and the voltage of the floating diffusion FD is set to the power supply voltage VDD (reset operation). Then, the pixel P1 outputs a voltage (reset voltage Vreset) corresponding to the voltage of the floating diffusion FD at this time. Therefore, the voltage of the signal SIG becomes the reset voltage Vreset ( Fig. 9 (D)).

[0117] In addition, at time t11, the reference signal generating unit 13 changes the reference signal RAMP to the voltage V1 ( Fig. 9 In addition, at time t11, the imaging control unit 15 changes the voltages of the control signals AZSW and AZN from low level to high level ( Fig. 9 (E)). Therefore, the two switches SW1 and SW2 in the comparison unit 21 of the AD conversion unit ADC1 are turned on. By turning on the switch SW1, the gate voltage Vg of the transistor MP11 becomes the same voltage (voltage V2) as the drain voltage of the transistor MP11 ( Fig. 9(G)) to set the voltages of the capacitors C1 and C2. In addition, by turning on the switch SW2, the gate voltage of the transistor MN12 becomes the same voltage as the drain voltage of the transistor MN12 to set the voltage of the capacitor C3. Therefore, the voltage of the signal CMPO becomes the voltage V3 ( Fig. 9 Therefore, the comparison section 21 performs the operation point setting operation.

[0118] Next, at time t12, the driving unit 12 changes the voltage of the control signal SRST from high level to low level ( Fig. 9 (B)). Therefore, in the pixel P1, the transistor RST is turned off.

[0119] Next, at time t13, the imaging control unit 15 changes the voltages of the control signals AZSW and AZN from high level to low level ( Fig. 9 (E)). Therefore, in the comparison section 21 of the AD conversion section ADC1, the two switches SW1 and SW2 are turned off, and the operation point setting operation ends. Thereafter, the comparison section 21 operates to compare the gate voltage Vg with the voltage V2.

[0120] Next, at time t14, the reference signal generating unit 13 reduces the voltage of the reference signal RAMP from the voltage V1 to the voltage V4 ( Fig. 9 Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 becomes a voltage lower than the voltage V2 ( Fig. 9 (G)), thereby reducing the voltage of the signal CMPO ( Fig. 9 In other words, the comparison section 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg is lower than the voltage V2, thereby changing the voltage of the signal CMPO to a low level.

[0121] Next, in the period from time t15 to time t17 (P phase period TP), the AD conversion unit ADC1 performs AD conversion based on the reset voltage Vreset. Specifically, first, at time t15, the reference signal generation unit 13 starts to increase the voltage of the reference signal RAMP from the voltage V4 at a predetermined rate of change ( Fig. 9 Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 starts to increase ( Fig. 9 (G)). In addition, at time t15, the imaging control section 15 starts generating the clock signal CLK. The counter 24 of the AD conversion section ADC1 performs a counting operation to count the pulses of the clock signal CLK.

[0122] Then, at time t16, the gate voltage Vg exceeds the voltage V2 ( Fig. 9Therefore, the comparison unit 21 of the AD conversion unit ADC1 changes the voltage of the signal CMPO from a low level to a high level ( Fig. 9 (H)). That is, the comparison unit 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg exceeds the voltage V2, thereby changing the voltage of the signal CMPO from a low level to a high level. The counter 24 of the AD conversion unit ADC1 stops the counting operation based on this transition of the signal CMPO. At this time, the count value of the counter 24 is CNTP. The latch 25 of the AD conversion unit ADC1 latches the count value CNTP as the count value in the P-phase period TP. Then, the counter 24 is reset.

[0123] Next, at time t17, the reference signal generation section 13 sets the voltage of the reference signal RAMP to the voltage V1 at the end of the P-phase period TP. In addition, at time t17, the imaging control section 15 stops generating the clock signal CLK.

[0124] Then, at time t17, the driving unit 12 changes the voltage of the control signal STG from the low level to the high level ( Fig. 9 (C)). Therefore, in the pixel P1, the transistor TG is turned on, and the charge generated in the photodiode PD is transferred to the floating diffusion FD (charge transfer operation). Then, the pixel P1 outputs a voltage (pixel voltage Vpix) corresponding to the voltage of the floating diffusion FD at this time. Therefore, the voltage of the signal SIG becomes the pixel voltage Vpix ( Fig. 9 (D)). Fig. 9 Two pixel voltages Vpix (pixel voltages Vpix1 and Vpix2) different from each other are shown as an example. The voltage of the signal SIG is reduced in the above manner, so that in the comparison section 21 of the AD conversion section ADC1, the gate voltage Vg of the transistor MP11 is reduced ( Fig. 9 The gate voltage Vg changes to a voltage corresponding to the pixel voltage Vpix. By reducing the gate voltage Vg in this way, the voltage of the signal CMPO decreases ( Fig. 9 That is, the comparison section 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg is lower than the voltage V2, thereby changing the voltage of the signal CMPO to a low level.

[0125] Next, at time t18, the driving unit 12 changes the voltage of the control signal STG from high level to low level ( Fig. 9 Therefore, in the pixel P1, the transistor TG is turned off.

[0126] Next, at time t19, the reference signal generating unit 13 reduces the voltage of the reference signal RAMP from the voltage V1 to the voltage V4 ( Fig. 9Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 decreases ( Fig. 9 (G)).

[0127] Next, in the period from time t20 to time t23 (D phase period TD), the AD conversion unit ADC1 performs AD conversion based on the pixel voltage Vpix. Specifically, first, at time t20, the reference signal generation unit 13 starts to increase the voltage of the reference signal RAMP from the voltage V4 at a predetermined rate of change ( Fig. 9 Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 starts to increase ( Fig. 9 (G)). In addition, at time t20, the imaging control section 15 stops generating the clock signal CLK. The counter 24 of the AD conversion section ADC1 performs a counting operation to count the pulses of the clock signal CLK.

[0128] When the pixel voltage Vpix is ​​the voltage Vpix1, at time t21, the gate voltage Vg exceeds the voltage V2 ( Fig. 9 Therefore, the comparison unit 21 of the AD conversion unit ADC1 changes the voltage of the signal CMPO from a low level to a high level ( Fig. 9 That is, the comparison unit 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg exceeds the voltage V2, thereby changing the voltage of the signal CMPO from a low level to a high level.

[0129] When the pixel voltage Vpix is ​​the voltage Vpix2, at time t22, the gate voltage Vg exceeds the voltage V2 ( Fig. 9 Therefore, the comparison unit 21 of the AD conversion unit ADC1 changes the voltage of the signal CMPO from a low level to a high level ( Fig. 9 (H)).

[0130] The counter 24 of the AD conversion section ADC1 stops the counting operation based on this transition of the signal CMPO. At this time, the count value of the counter 24 is CNTD. The latch 25 of the AD conversion section ADC1 latches the count value CNTD as the count value in the D phase period TD. Then, the counter 24 is reset.

[0131] Next, at time t23, the reference signal generating section 13 sets the voltage of the reference signal RAMP to the voltage V1 ( Fig. 9 (F)). In addition, at time t23, the camera control unit 15 stops generating the clock signal CLK. Then, at time t23, the drive unit 12 changes the voltage of the control signal SSEL from a high level to a low level ( Fig. 9(A)). Therefore, in the pixel P1, the transistor SEL is turned off, so that the pixel P1 is electrically separated from the signal line SGL.

[0132] Then, the latch 25 of the AD conversion section ADC1 generates a digital code CODE corresponding to a difference (CNTD−CNTP) between the count value CNTP obtained by the counter 24 in the P-phase period TP and the count value CNTD obtained by the counter 24 in the D-phase period TD.

[0133] As described above, in the image pickup device 1, the count value CNTP is obtained by performing a count operation based on the reset voltage Vreset in the P phase period TP, and the count value CNTD is obtained by performing a count operation based on the pixel voltage Vpix in the D phase period TD. Then, in the image pickup device 1, a digital code CODE corresponding to the difference (CNTD-CNTP) between the count values ​​CNTP and CNTD is generated. In the image pickup device 1, by performing such correlated double sampling, the noise component contained in the pixel voltage Vpix can be removed. Therefore, the image quality of the captured image can be improved.

[0134] As described above, in the camera device 1, each of the plurality of comparison units 21 includes a power supply circuit 22. Therefore, interference between the plurality of AD conversion units ADC can be suppressed. That is, for example, in the case where the power supply circuit 22 is not provided in each of the plurality of comparison units 21, when the comparison unit 21 in a certain AD conversion unit ADC causes the signal CMPO to change, a transient current may generate noise in the power supply voltage VDD0. In this case, the noise may affect the operation of other AD conversion units via the power supply line VDDL. In the camera device 1, since the power supply circuit 22 is provided in each of the plurality of comparison units 21, when the comparison unit 21 in a certain AD conversion unit ADC causes the signal CMPO to change, the possibility that the noise of the power supply voltage VDD0 generated by the transient current affects the operation of other AD conversion units can be reduced. Therefore, in the camera device 1, the possibility of, for example, stripes appearing in the captured image can be reduced. As a result, in the camera device 1, the image quality of the captured image can be improved.

[0135] [Effect]

[0136] As described above, in the present embodiment, since each of the plurality of comparing sections includes a power supply circuit, the image quality of the captured image can be improved.

[0137] [Modification 1]

[0138] In the above-described embodiment, for example, although Figure 4AThe comparison circuit 23 of the comparison unit 21 shown in FIG. 1 is provided with four transistors MP11, MN11, MP12 and MN12, but the present invention is not limited thereto. Fig. 10A Like the comparison circuit 23B of the comparison unit 21B shown in FIG. 1 , a transistor MN13 may also be provided. The transistor MN13 is an N-type MOS transistor, and its gate is provided with a signal CMPO, the drain is connected to the source of the transistors MN10, MP11 and MP12, and the source is connected to the drain of the transistors MP11 and MN11, the gate of the transistor MP12 and the other end of the switch SW1. Here, the transistor MN13 corresponds to a specific example of the "fourth transistor" in the present disclosure. The transistor MN13 performs control based on the voltage of the signal CMPO to prevent the drain voltage of the transistor MN11, which operates as a constant current source, from being too low. Therefore, for example, the constant current characteristic of the transistor MN11 can be maintained, and interference between multiple AD conversion units ADC can be suppressed.

[0139] In this example, although the present modification example is applied to the comparison section 21 ( Figure 4A ), but this modification example can also be applied to, for example, the comparison unit 21A ( Figure 4B ). Specifically, for example, Fig. 10B As shown in FIG. 2 , a transistor MP23 may be provided as in the comparison circuit 23C of the comparison section 21C shown in FIG. 2 . The transistor MP23 is a P-type MOS transistor, and its gate is provided with a signal CMPO, a drain is connected to the sources of the transistors MP20, MN21, and MN22, and a source is connected to the drains of the transistors MN21 and MP21, the gate of the transistor MN22, and the other end of the switch SW11. The transistor MP23 performs control based on the voltage of the signal CMPO to prevent the drain voltage of the transistor MP21 operating as a constant current source from being too high. Therefore, for example, the constant current characteristic of the transistor MP21 can be maintained, and interference between the multiple AD conversion sections ADC can be suppressed.

[0140] [Modification 2]

[0141] In the above embodiment, for example, Figure 4A In the power supply circuit 22 of the comparison unit 21 shown in FIG. 1 , the bias voltage VB1 is constantly supplied to the gate of the transistor MN10, but the present invention is not limited thereto. Alternatively, for example, a sample-and-hold circuit may be provided, and the bias voltage VB1 may be supplied to the gate of the transistor MN10 only during a predetermined period of time. Fig. 10A An example of the case of the comparison unit 21B is shown.

[0142] Fig.11AAn example of the configuration of the comparison section 21D according to the present modification is shown. The comparison section 21D includes a power supply circuit 22D and a comparison circuit 23B. The power supply circuit 22D includes a capacitor C4 and a switch SW3. One end of the capacitor C4 is connected to the gate of the transistor MN10 and one end of the switch SW3, and the other end is provided with a DC voltage VREF. The voltage VREF is generated by the imaging control section 15. It should be noted that, for example, the capacitor C4 may be configured by using a MOS capacitor or the like, or may be configured by using a parasitic capacitance at the gate of the transistor MN10, a parasitic capacitance at the switch SW3, or a parasitic capacitance at the wiring, etc. The switch SW3 is configured to be turned on and off based on a control signal SHSW, and one end of the switch SW3 is connected to the gate of the transistor MN10 and one end of the capacitor C4, and the other end is provided with a bias voltage VB1. The control signal SHSW is generated by the imaging control section 15. The sampling and holding circuit includes a capacitor C4 and a switch SW3. Here, the capacitor C4 corresponds to a specific example of the “fourth capacitor” in the present disclosure. The switch SW3 corresponds to a specific example of a “fourth switch” in the present disclosure.

[0143] For example, the switch SW3 is turned on during a period when the switches SW1 and SW2 are turned on, and is turned off during a period when the switches SW1 and SW2 are turned off. Fig. 9 In the readout driver D2 shown, the switch SW3 is turned on in the period from time t11 to time t13. Therefore, the gate voltage of the transistor MN10 is set to the bias voltage VB1. Then, the switch SW3 is turned on in the period from time t13 to time t23. Therefore, the gate voltage of the transistor MN10 is maintained at the bias voltage VB1. In the comparison unit 21D, the switch SW3 is disconnected in the P phase period TP and the D phase period TD. Therefore, when the comparison unit 21D causes the signal CMPO to change in a certain AD conversion unit ADC and generates noise in the gate of the transistor MN10, the possibility of the noise affecting the operation of other AD conversion units ADC can be reduced. As a result, interference between multiple AD conversion units ADC can be suppressed.

[0144] Likewise, for example, this modification example can be applied to the comparison unit 21A ( Figure 4B ), or this modification example may be applied to the comparison unit 21C ( Fig. 10B ). Fig. 11B The present modification example is applied to the comparison unit 21C ( Fig. 10B). The comparison section 21E includes a power supply circuit 22E and a comparison circuit 23C. The power supply circuit 22E includes a capacitor C14 and a switch SW13. One end of the capacitor C14 is connected to the gate of the transistor MP20 and one end of the switch SW13, and the other end is provided with a voltage VREF. The switch SW13 is configured to be turned on and off based on the control signal SHSW, and one end of the switch SW13 is connected to the gate of the transistor MP20 and one end of the capacitor C14, and the other end is provided with a bias voltage VB1. Therefore, as with the comparison section 21D, in the comparison section 21E, interference between the plurality of AD conversion sections ADC can also be suppressed.

[0145] [Variation 3]

[0146] In the above embodiment, for example, Figure 4A In the comparison circuit 23 of the comparison section 21 shown in FIG. 1 , the bias voltage VB2 is constantly supplied to the gate of the transistor MN11 operating as a current source, but the present invention is not limited thereto. Alternatively, for example, a sample-and-hold circuit may be provided, and the bias voltage VB2 may be supplied to the gate of the transistor MN11 only during a predetermined period of time. Fig.11A An example of the case of the comparison unit 21D is shown.

[0147] Fig. 12A An example of the configuration of the comparison section 21F according to the present modification is shown. The comparison section 21F includes a power supply circuit 22D and a comparison circuit 23F. The comparison circuit 23F includes a capacitor C5 and a switch SW4. One end of the capacitor C5 is connected to the gate of the transistor MN11 and one end of the switch SW4, and the other end is provided with a DC voltage VREF. The voltage VREF is generated by the imaging control section 15. It should be noted that, for example, the capacitor C5 may be configured by using a MOS capacitor or the like, or may be configured by using a parasitic capacitance at the gate of the transistor MN11, a parasitic capacitance at the switch SW4, or a parasitic capacitance at the wiring, etc. The switch SW4 is configured to be turned on and off based on the control signal SHSW2, and one end of the switch SW4 is connected to the gate of the transistor MN11 and one end of the capacitor C5, and the other end is provided with a bias voltage VB2. The control signal SHSW2 is generated by the imaging control section 15. The sample-hold circuit includes a capacitor C5 and a switch SW4. Here, the switch SW4 corresponds to a specific example of the “sixth switch” in the present disclosure.

[0148] For example, the switch SW4 is turned on during a period when the switches SW1 and SW2 are turned on, and is turned off during a period when the switches SW1 and SW2 are turned off. Fig. 9In the readout driver D2 shown, the switch SW4 is turned on in the period from time t11 to time t13. Therefore, the gate voltage of the transistor MN11 is set to the bias voltage VB2. Then, the switch SW4 is turned on in the period from time t13 to time t23. Therefore, the gate voltage of the transistor MN11 is maintained at the bias voltage VB2. In the comparison unit 21F, the switch SW4 is disconnected in the P phase period TP and the D phase period TD. Therefore, when the comparison unit 21F causes the signal CMPO to change in a certain AD conversion unit ADC and generates noise in the gate of the transistor MN11, the possibility of the noise affecting the operation of other AD conversion units ADC can be reduced. As a result, interference between multiple AD conversion units ADC can be suppressed.

[0149] Likewise, for example, this modification example can be applied to the comparison unit 21A ( Figure 4B ), this modification example can be applied to the comparison unit 21C ( Fig. 10B ), or this modification example may be applied to the comparison unit 21E( Fig. 11B ). Fig. 12B The present modification example is applied to the comparison unit 21E ( Fig. 11B ). The comparison unit 21G includes a power supply circuit 22E and a comparison circuit 23G. The comparison circuit 23G includes a capacitor C15 and a switch SW14. One end of the capacitor C15 is connected to the gate of the transistor MP21 and one end of the switch SW14, and the other end is provided with a voltage VREF. The switch SW14 is configured to be turned on and off based on the control signal SHSW2, and one end of the switch SW14 is connected to the gate of the transistor MP21 and one end of the capacitor C15, and the other end is provided with a bias voltage VB2. Therefore, as with the comparison unit 21F, in the comparison unit 21G, interference between the plurality of AD conversion units ADC can also be suppressed.

[0150] [Variation 4]

[0151] In the above embodiment, for example, Figure 4A As shown in the comparison section 21, the primary circuit 101 of the comparison circuit 23 is constituted by using two transistors MP11 and NM11, but is not limited thereto. Fig.13 The primary circuit 101 can be configured by using a plurality of transistors, as in the comparison unit 21H shown in FIG. The primary circuit 101 of the comparison unit 21H includes transistors MN11, MP11, MP13, and MN14.

[0152] The transistor MP13 is a P-type MOS transistor, and its gate is provided with a bias voltage VB3, the drain is connected to the drain of the transistor MN14, the input terminal of the subsequent circuit 102, and the other end of the switch SW1, and the source is connected to the drain of the transistor MP11. The bias voltage VB3 is generated by the imaging control section 15. The source of the transistor MP11 is grounded, and the gate of the transistor MP13 is grounded. Therefore, the transistor MP11 and the transistor MP13 are included in a cascade circuit.

[0153] The transistor MN14 is an N-type MOS transistor, and the gate of the transistor MN14 is provided with a bias voltage VB4, the drain is connected to the drain of the transistor MP13, the input terminal of the subsequent circuit 102, and the other end of the switch SW1, and the source is connected to the drain of the transistor MN11. The bias voltage VB4 is generated by the imaging control section 15. The transistors MN11 and MN14 are included in a cascade circuit.

[0154] By this configuration, in the comparison circuit 23H, the small signal gain can be improved, so that a more stable comparison operation can be achieved. In addition, by providing the transistors MP13 and MN14, the kickback noise from the subsequent stage circuit 102 can be reduced.

[0155] [Variation 5]

[0156] In the above embodiment, for example, Figure 4A As in the comparison section 21 shown in the figure, in the power supply circuit 22, the transistor MN10 operates as a source follower, but is not limited thereto. Alternatively, for example, a plurality of transistors may be provided, and the plurality of transistors may operate as a multi-stage source follower. This modification is described in detail with reference to some examples.

[0157] Fig.14 There is shown a configuration example of a comparison section 21J according to the present modification. The comparison section 21J includes a power supply circuit 22J and a comparison circuit 23. The power supply circuit 22J includes transistors MN10 and MN15, a capacitor C6, and a switch SW5.

[0158] The gate of the transistor MN10 is provided with a bias voltage VB1, the drain is connected to the power supply line VDDL, and the source is connected to the drain of the transistor MN15. The transistor MN15 is an N-type MOS transistor, and the gate of the transistor MN15 is connected to one end of the capacitor C6 and one end of the switch SW5, the drain is connected to the source of the transistor MN10, and the source is connected to the source of the transistor MP11 and the power supply terminal of the subsequent circuit 102. One end of the capacitor C6 is connected to the gate of the transistor MN15 and one end of the switch SW5, and the other end is provided with a DC voltage VREF. The voltage VREF is generated by the camera control section 15. The switch SW5 is configured to be turned on and off based on the control signal SHSW, and one end of the switch SW5 is connected to the gate of the transistor MN15 and one end of the capacitor C6, and the other end is provided with a bias voltage VB5. The control signal SHSW and the bias voltage VB5 are generated by the camera control section 15. The capacitor C6 and the switch SW5 are included in the sample-and-hold circuit. For example, the switch SW5 is turned on during the period when the switch SW1 is turned on, and is turned off during the period when the switch SW1 is turned off. Here, the transistor MN15 corresponds to a specific example of a "second power supply transistor" in the present disclosure. The switch SW5 corresponds to a specific example of a "fifth switch" in the present disclosure.

[0159] By this configuration, in the comparison section 21J, the current generated by the transistor MN11 operating as a constant current source is applied to the transistors MN10 and MN15, and the transistors MN10 and MN15 operate as two-stage source followers. Therefore, the power supply circuit 22J generates the power supply voltage VDD1. Therefore, in the comparison section 21J, by providing a two-stage source follower, the possibility that the noise of the power supply voltage VDD0 generated by the transient current when the comparison section 21J makes the signal CMPO transition in a certain AD conversion section ADC affects the operation of other AD conversion sections ADC can be reduced. As a result, interference between multiple AD conversion sections ADC can be suppressed.

[0160] Fig.15 A configuration example of a comparison section 21K according to the present modification is shown. The comparison section 21K includes a power supply circuit 22K and a comparison circuit 23. The power supply circuit 22K includes transistors MN10 and MN15, an operational amplifier OPA, a capacitor C6, and a switch SW5.

[0161] The gate of the transistor MN10 is connected to the output terminal of the operational amplifier OPA, the drain is connected to the power supply line VDDL, the source is connected to the drain of the transistor MN15 and the inverting input terminal of the operational amplifier OPA. The non-inverting input terminal of the operational amplifier OPA is provided with a bias voltage VB1, the inverting input terminal is connected to the source of the transistor MN10 and the drain of the transistor MN15, and the output terminal is connected to the gate of the transistor MN10.

[0162] The gate of the transistor MN15 is connected to one end of the capacitor C6 and one end of the switch SW5, the drain is connected to the source of the transistor MN10 and the inverting input terminal of the operational amplifier OPA, and the source is connected to the source of the transistor MP11 and the power supply terminal of the subsequent circuit 102. One end of the capacitor C6 is connected to the gate of the transistor MN15 and one end of the switch SW5, and the other end is provided with a DC voltage VREF. The voltage VREF is generated by the camera control unit 15. The switch SW5 is configured to be turned on and off based on the control signal SHSW, and one end of the switch SW5 is connected to the gate of the transistor MN15 and one end of the capacitor C6, and the other end is provided with a bias voltage VB5. The control signal SHSW and the bias voltage VB5 are generated by the camera control unit 15. The capacitor C6 and the switch SW5 are included in the sample-and-hold circuit. For example, the switch SW5 is turned on during the period when the switch SW1 is turned on, and is turned off during the period when the switch SW1 is turned off.

[0163] By this configuration, in the comparison section 21K, a negative feedback operation is performed so that the source voltage of the transistor MN10 is equal to the bias voltage VB1. Then, the current generated by the transistor MN1 operating as a constant current source is applied to the transistors MN10 and MN15, and the transistors MN10 and MN15 operate as a two-stage source follower. Then, the power supply circuit 22K generates the power supply voltage VDD1. Therefore, as with the comparison section 21J, in the comparison section 21K, interference between the plurality of AD conversion sections ADC can also be suppressed.

[0164] Fig.16 A configuration example of another comparison section 21L according to the present modification is shown. The comparison section 21L includes a power supply circuit 22L and a comparison circuit 23. The power supply circuit 22L includes transistors MN10 and MN15, capacitors C4 and C6, and switches SW3 and SW5.

[0165] The gate of the transistor MN10 is connected to one end of the capacitor C4 and one end of the switch SW3, the drain is connected to the power supply line VDDL, and the source is connected to the drain of the transistor MN15. One end of the capacitor C4 is connected to the gate of the transistor MN10 and one end of the switch SW3, and the other end is provided with a DC voltage VREF1. The voltage VREF1 is generated by the camera control section 15. The switch SW3 is configured to be turned on and off based on the control signal SHSW1, and one end of the switch SW3 is connected to the gate of the transistor MN10 and one end of the capacitor C4, and the other end is provided with a bias voltage VB1. The control signal SHSW1 and the bias voltage VB1 are generated by the camera control section 15. For example, the switch SW3 is turned on during a period when the switch SW1 is turned on, and is turned off during a period when the switch SW1 is turned off.

[0166] The gate of the transistor MN15 is connected to one end of the capacitor C6 and one end of the switch SW5, the drain is connected to the source of the transistor MN10, and the source is connected to the source of the transistor MP11 and the power supply terminal of the subsequent circuit 102. One end of the capacitor C6 is connected to the gate of the transistor MN15 and one end of the switch SW5, and the other end is provided with a DC voltage VREF2. The voltage VREF2 is generated by the imaging control section 15. The switch SW5 is configured to be turned on and off based on the control signal SHSW2, and one end of the switch SW5 is connected to the gate of the transistor MN15 and one end of the capacitor C6, and the other end is provided with a bias voltage VB5. The control signal SHSW2 and the bias voltage VB5 are generated by the imaging control section 15. For example, the switch SW5 is turned on during a period in which the switch SW1 is turned on, and is turned off during a period in which the switch SW1 is turned off.

[0167] By this configuration, in the comparison section 21L, the current generated by the transistor MN11 operating as a constant current source is applied to the transistors MN10 and MN15, and the transistors MN10 and MN15 operate as two-stage source followers. Then, the power supply circuit 22L generates the power supply voltage VDD1. Therefore, as with the comparison section 21J, in the comparison section 21L, interference between the plurality of AD conversion sections ADC can also be suppressed.

[0168] [Variation 6]

[0169] In the above embodiment, if Fig.17 As shown, the back gates of the transistors MN10 and MN11 are supplied with the ground voltage VSS0, and the back gate of the transistor MP11 is supplied with the power supply voltage VDD0, but it is not limited thereto. The present modification is described in detail below with reference to some examples.

[0170] Fig.18 1 shows a configuration example of a comparison section 21M according to the present modification. The comparison section 21M includes a power supply circuit 22M. In the power supply circuit 22M, the back gate of the transistor MN10 is connected to the source of the transistor MN10. The transistor MN10 is formed in a P-well electrically insulated from a P-type semiconductor substrate by a deep N-well. Therefore, for example, the gate-source voltage Vgs of the transistor MN10 can be reduced, so that the power supply voltage VDD0 can be further reduced and power consumption can be reduced.

[0171] Fig.192 shows an example of a configuration of another comparison section 21N according to this modification. The comparison section 21N includes a comparison circuit 23N. In the comparison circuit 23N, the back gate of the transistor MP11 is connected to the source of the transistor MP11. Therefore, for example, the absolute value of the gate-source voltage Vgs of the transistor MP11 can be reduced, so that the power supply voltage VDD0 can be further reduced and the power consumption can be reduced. The comparison section 21N is effective in the case of adopting a manufacturing process that cannot form a deep N well.

[0172] Fig. 20 An example of the construction of another comparison unit 21P according to this modification is shown. The comparison unit 21P includes a power supply circuit 22M and a comparison circuit 23N. That is, the back gate of the transistor MN10 is connected to the source of the transistor MN10, and the back gate of the transistor MP11 is connected to the source of the transistor MP11. Therefore, for example, the absolute value of the gate-source voltage Vgs of the transistors MN10 and MP11 can be reduced, so that the power supply voltage VDD0 can be further reduced and the power consumption can be reduced. In addition, in the comparison unit 21P, the back gates of both the transistors MP11 and MN10 are respectively connected to the sources of these transistors, so that these back gates are driven separately in units of the AD conversion unit ADC. Therefore, interference between multiple AD conversion units ADC can be suppressed.

[0173] [Variation 7]

[0174] In addition, the back gates of the transistors MN10 in the power supply circuits of the plurality of AD conversion units ADC may be connected to each other. Fig.21 An example of the construction of a readout section 20Q in an image pickup device 1Q according to this variation is shown. The readout section 20Q includes a plurality of comparison sections 21Q and a voltage generation section 16Q. Each of the plurality of comparison sections 21Q includes a power supply circuit 22Q. The back gates of the transistors MN10 of the plurality of power supply circuits 22Q are connected to each other. The back gates of these transistors MN10 are provided with a DC voltage VDC. The plurality of transistors MN10 are formed in a P well. The voltage generation section 16Q is configured to generate a voltage VDC. The voltage VDC is set to a voltage that causes a PN junction formed by the source of the transistor MN10 and the P well to become reverse biased.

[0175] Therefore, in the image pickup device 1Q, the voltage VDC is supplied to the back gates of the plurality of transistors MN10. For example, by appropriately setting the voltage VDC, the absolute value of the gate-source voltage Vgs of the transistor MN10 can be reduced, thereby further reducing the power supply voltage VDD0 and reducing power consumption. In addition, in the image pickup device 1Q, the plurality of transistors MN10 are provided in one P well, and therefore, compared with the case where the plurality of transistors MN10 are provided in a plurality of P wells, for example, the area of ​​the well contact can be reduced. Therefore, the layout area can be reduced.

[0176] [Variation 8]

[0177] In the above-described embodiment, in each comparison section 21 of the plurality of AD converters ADC, the output terminal of the power supply circuit 22 is connected to the comparison circuit 23, but this is not limited thereto. Alternatively, for example, the output terminals of the power supply circuits 22 of two or more AD converters ADC may be connected to each other, and these output terminals may be connected to the comparison circuits 23 of two or more AD converters ADC. This modified example is described in detail below.

[0178] Fig. 22 and Fig.23 An example of the configuration of the readout section 20R in the camera device 1R according to the present modification is shown. The readout section 20R includes a plurality of AD converters ADC. In this example, the output terminals of the power supply circuits 22 in the two AD converters ADC are connected to each other. Specifically, the output terminal of the power supply circuit 22 of the 0th AD converter ADC[0] and the output terminal of the power supply circuit 22 of the first AD converter ADC[1] are connected to each other. Therefore, the two power supply circuits 22 generate the power supply voltage VDD1. The comparison circuit 23 of the 0th AD converter ADC[0] and the comparison circuit 23 of the first AD converter ADC[1] perform operations based on the power supply voltage VDD1. In addition, the output terminal of the power supply circuit 22 of the second AD converter ADC[2] and the output terminal of the power supply circuit 22 of the third AD converter ADC[3] are connected to each other. Therefore, the two power supply circuits 22 generate the power supply voltage VDD1. The comparison circuit 23 of the second AD converter ADC[2] and the comparison circuit 23 of the third AD converter ADC[3] perform operations based on the power supply voltage VDD1. The same applies to the fourth and subsequent AD converters. Therefore, the two power supply circuits 22 generate the power supply voltage VDD1 , and the output impedance of the circuit generating the power supply voltage VDD1 can be reduced compared with the above-described embodiment, and the circuit noise included in the power supply voltage VDD1 can be reduced to 1 / √2.

[0179] It should be noted that in this example, the output terminals of the power supply circuits 22 in the two AD converters ADC are connected to each other, but it is not limited to this. Alternatively, the output terminals of the power supply circuits 22 in three or more AD converters ADC may be connected to each other. For example, in the case where the output terminals of the power supply circuits 22 in N AD converters ADC are connected to each other, the circuit noise contained in the power supply voltage VDD1 can be reduced to 1 / √N.

[0180] In addition, in this example, Fig.23 As shown, the subsequent circuit 102 performs operation based on the power supply voltage VDD1, but is not limited thereto. Fig.24The following circuit 102 can perform an operation based on the power supply voltage VDD0, as in the readout section 20S shown in the figure. The readout section 20S includes a plurality of comparison sections 21S. The plurality of comparison sections 21S respectively include a comparison circuit 23S. The following circuit 102 of the comparison circuit 23S performs an operation based on the power supply voltage VDD0. Therefore, in this modification, the influence of the operation of the following circuit 102 on the power supply voltage VDD1 can be suppressed.

[0181] [Variation 9]

[0182] In the above-described embodiment, the comparison section 21 of each of the plurality of AD conversion sections ADC includes the power supply circuit 22, however, another power supply circuit may be provided in addition to the power supply circuit 22. This modification example will be described in detail below.

[0183] Fig.25 and Fig.26 An example of the configuration of a readout section 20T in an image pickup device 1T according to the present modification is shown. The readout section 20T includes a plurality of AD conversion sections ADC and a plurality of power supply circuits 28T. The plurality of power supply circuits 28T are each configured to generate a power supply voltage VDD0 based on a power supply voltage VDDA supplied via a power supply line VDDL. Then, in this example, the power supply circuit 28T supplies the generated power supply voltage VDD0 to a comparison section 21T of two AD conversion sections ADC. The power supply circuit 28T includes a transistor MN0. The transistor MN0 is an N-type MOS transistor, and the gate of the transistor MN0 is supplied with a bias voltage VB0, the drain is connected to the power supply line VDDL, and the source is connected to two comparison sections 21T. The power supply voltage VDDA and the bias voltage VB0 are generated by the image pickup control section 15. The comparison section 21T includes a power supply circuit 22D and a comparison circuit 23S. The drain of the transistor MN10 of the power supply circuit 22D is connected to the source of the transistor MN0 of the power supply circuit 28T. The power supply circuit 28T and the power supply circuit 22D operate as two-stage source followers.

[0184] Therefore, in the readout section 20T, by providing a two-stage source follower, the possibility that the noise of the power supply voltage VDD0 generated by the transient current when the comparison section 21T in a certain AD conversion section ADC causes the signal CMPO to transition can be reduced to affect the operation of other AD conversion sections ADC. As a result, interference between multiple AD conversion sections ADC can be suppressed. In addition, in the readout section 20T, in this example, the power supply circuit 28T supplies the generated power supply voltage VDD0 to two comparison sections 21T, so that the number of power supply circuits 28T can be reduced. Therefore, the circuit area can be reduced.

[0185] Note that, in this example, the power supply circuit 28T supplies the generated power supply voltage VDD0 to two comparison sections 21T, but is not limited thereto. Alternatively, the power supply circuit 28T may supply the power supply voltage VDD0 to three or more comparison sections 21T.

[0186] In addition, in this example, Fig.26 As shown, the power supply circuit 28T is constituted by using a transistor MN0, but is not limited thereto. Fig. 27 As shown in the readout unit 20U, the power supply circuit 28U can be configured by using a transistor MN0 and an operational amplifier OPA0. The non-inverting input terminal of the operational amplifier OPA0 is provided with a bias voltage VB0, the inverting input terminal is connected to the source of the transistor MN0, and the output terminal is connected to the gate of the transistor MN0. Therefore, the power supply circuit 28U can generate a stable power supply voltage VDD0. As a result, in this modification, interference between multiple AD conversion units ADC can be suppressed.

[0187] [Variation 10]

[0188] In addition, a variable resistor may be provided between output terminals of the power supply circuits in two adjacent AD converters ADC among the plurality of AD converters ADC. This modification example will be described in detail below.

[0189] Fig.28 An example of the construction of a readout unit 20V in an image pickup device 1V according to this modification is shown. The readout unit 20V includes a plurality of comparison units 21T, a plurality of transistors 18V, and a voltage generating unit 17V. The transistor 18V is an N-type MOS transistor, and the transistor 18V is provided between the output terminals of a power supply circuit 22D of each two AD conversion units ADC adjacent to each other in a plurality of AD conversion units ADC. The source of the transistor 18V is connected to the output terminal of a certain power supply circuit 22D, the drain is connected to the output terminal of a power supply circuit 22D adjacent to a certain power supply circuit 22D, and the gate is provided with a control voltage Vctrl. The drain-source resistance value in the transistor 18V is changed according to the control voltage Vctrl. That is, the transistor 18V is used as a variable resistor. The voltage generating unit 17V is configured to generate a control voltage Vctrl.

[0190] With this configuration, for example, when the resistance value of the transistor 18V increases, the resistance value between the output terminals of the plurality of power supply circuits 22D increases, and thus, the readout section 20 ( Figure 5), for example, the possibility of generating streaks in the captured image can be reduced. As a result, the image quality of the captured image can be improved. In addition, when the resistance value of the transistor 18V is reduced, the resistance value between the output terminals of the plurality of power supply circuits 22D is reduced, and thus, compared with the readout unit 20S ( Fig.24 ), the output impedance can be reduced, and the circuit noise included in the power supply voltage VDD1 can be reduced.

[0191] It should be noted that in this example, the variable resistor is configured by using an N-type MOS transistor, but is not limited thereto. Alternatively, for example, the variable resistor may also be configured by using a P-type MOS transistor.

[0192] In addition, in this example, all of the multiple AD conversion units ADC are connected to each other via transistor 18V, but are not limited to this. As an alternative, for example, the multiple AD conversion units ADC can be divided into multiple groups each including two or more AD conversion units ADC, and the AD conversion units ADC belonging to the same group can be connected to each other via transistor 18V. In addition, multiple AD conversion units ADC of even numbers can be connected to each other via transistor 18V, and multiple AD conversion units ADC of odd numbers can be connected to each other via transistor 18V. Specifically, for example, the 0th AD conversion unit ADC [0] and the second AD conversion unit ADC [2] can be connected to each other via transistor 18V (transistor 18V1), and the second AD conversion unit ADC [2] and the fourth AD conversion unit ADC [4] can be connected to each other via transistor 18V (transistor 18V2). Similarly, the first AD conversion unit ADC[1] and the third AD conversion unit ADC[3] can be connected to each other via transistor 18V (transistor 18V3), and the third AD conversion unit ADC[3] and the fifth AD conversion unit ADC[5] can be connected to each other via transistor 18V (transistor 18V4).

[0193] In this example, one voltage generating section 17V is provided and controls the resistance values ​​of all transistors 18V, but the present invention is not limited thereto. Alternatively, for example, a plurality of voltage generating sections may be provided and control the resistance values ​​of different transistors 18V.

[0194] [Variation 11]

[0195] In addition, if Fig.29As shown in the readout section 20W, the output terminals of the power supply circuit 22 of two AD converters ADC that are not adjacent to each other can be connected to each other. In this example, the nth AD converter ADC [n], the (n+2)th AD converter ADC [n+2], the (n+3)th AD converter ADC [n+3] and the (n+5)th AD converter ADC [n+5] constitute a group (first group), and the output terminals of the power supply circuit 22 of the multiple AD converters ADC belonging to the first group are connected to each other. In addition, the (n+4)th AD converter ADC [n+4], the (n+6)th AD converter ADC [n+6], the (n+7)th AD converter ADC [n+7] and the (n+9)th AD converter ADC [n+9] constitute another group (second group), and the output terminals of the power supply circuit 22 of the multiple AD converters ADC belonging to the second group are connected to each other. That is, the power circuit 22 of the AD converter ADC[n+4] disposed between the AD converter ADC[n+3] and the AD converter ADC[n+5] (their power circuits 22 are connected to each other) is not connected to the power circuit 22 of the AD converter ADC[n+3] and the AD converter ADC[n+5]. Therefore, for example, even in the case where stripes appear in the captured image, the boundary of the image can be blurred, so that the stripes can be made less noticeable. Interference is generated between the multiple AD converters ADC belonging to the first group, and similarly, interference is generated between the multiple AD converters ADC belonging to the second group. The degree of interference between the multiple AD converters ADC belonging to the first group is different from the degree of interference between the multiple AD converters ADC belonging to the second group. Therefore, by disposing the AD converter ADC belonging to the second group between the multiple AD converters ADC belonging to the first group, the boundary of the image can be blurred based on the difference in the degree of interference.

[0196] [Variation 12]

[0197] In the above embodiment, if Figure 4A As shown, the comparison circuit 23 includes a single-ended circuit, but is not limited thereto. Alternatively, for example, the comparison circuit may include a differential circuit. The comparison sections 31A and 31B according to this modification are described in detail below.

[0198] Fig. 30A 2 shows a configuration example of a comparison section 31A. The comparison section 31A includes a power supply circuit 22 and a comparison circuit 33A. The comparison circuit 33A includes capacitors C31 to C33, transistors MN31 to MN33, switches SW31 and SW32, and transistors MP31 and MP32. The transistors MN31 to MN33 are N-type MOS transistors, and the transistors MP31 and MP32 are P-type MOS transistors.

[0199] Capacitors C31 and C32 have one end and the other end, respectively. One end of capacitor C31 is provided with a reference signal RAMP, and the other end is connected to the other end of capacitor C32, the gate of transistor MN31, and one end of switch SW31. One end of capacitor C32 is provided with a signal SIG, and the other end is connected to the other end of capacitor C31, the gate of transistor MN31, and one end of switch SW31. One end of capacitor C33 is provided with a DC voltage VREF, and the other end is connected to the gate of transistor MN32 and one end of switch SW32.

[0200] The gate of transistor MN31 is connected to the other end of capacitors C31 and C32 and one end of switch SW31, the drain is connected to the drain of transistor MP31, the gates of transistors MP31 and MP32 and the other end of switch SW31, and the source is connected to the source of transistor MN32 and the drain of transistor MN33. The gate of transistor MN32 is connected to the other end of capacitor C33 and one end of switch SW32, the drain is connected to the drain of transistor MP32, the other end of switch SW32 and the input terminal of the post-stage circuit 102, and the source is connected to the source of transistor MN31 and the drain of transistor MN33. The gate of transistor MN33 is provided with bias voltage VB2, the drain is connected to the sources of transistors MN31 and MN32, and the source is provided with ground voltage VSS0. Transistor MN33 operates as a current source, and transistors MN31 and MN32 operate as a differential pair.

[0201] The switch SW31 is configured to be turned on and off based on the control signal AZSW. One end of the switch SW31 is connected to the other end of the capacitors C31 and C32 and the gate of the transistor MN31, and the other end is connected to the drains of the transistors MN31 and MP31 and the gates of the transistors MP31 and MP32. The switch SW32 is configured to be turned on and off based on the control signal AZSW. One end of the switch SW32 is connected to the other end of the capacitor C33 and the gate of the transistor MN32, and the other end is connected to the drains of the transistors MN32 and MP32 and the input terminal of the subsequent circuit 102.

[0202] The gate of the transistor MP31 is connected to the gate of the transistor MP32, the drains of the transistors MP31 and MN31, and the other end of the switch SW31, the drain is connected to the gates of the transistors MP31 and MP32, the drain of the transistor MN31, and the other end of the switch SW31, and the source is connected to the sources of the transistors MN10 and MP32, and the power supply terminal of the subsequent stage circuit 102. The gate of the transistor MP32 is connected to the gate of the transistor MP31, the drains of the transistors MP31 and MN31, and the other end of the switch SW31, the drain is connected to the input terminal of the subsequent stage circuit 102, the drain of the transistor MN32, and the other end of the switch SW32, and the source is connected to the sources of the transistors MN10 and MP31, and the power supply terminal of the subsequent stage circuit 102. The transistors MP31 and MP32 operate as loads of the transistors MN31 and MN32 as a differential pair.

[0203] Here, transistor MN31 corresponds to a specific example of a “first transistor” in the present disclosure. Transistor MN32 corresponds to a specific example of a “fifth transistor” in the present disclosure. Capacitor C33 corresponds to a specific example of a “third capacitor” in the present disclosure. Switch SW32 corresponds to a specific example of a “third switch” in the present disclosure. Transistors MP31 and MP32 correspond to specific examples of a “load circuit” in the present disclosure. Transistor MN33 corresponds to a specific example of a “first current source” in the present disclosure.

[0204] Fig. 30B 2 shows a configuration example of a comparison section 31B. The comparison section 31B includes a power supply circuit 22A and a comparison circuit 33B. The comparison circuit 33B includes capacitors C41 to C43, transistors MP1 to MP43, switches SW41 and SW42, and transistors MN41 and MN42. The transistors MP41 to MP43 are P-type MOS transistors, and the transistors MN41 and MN42 are N-type MOS transistors. The capacitors C41 to C43 of the comparison section 31B correspond to the capacitors C31 to C33 of the comparison section 31A, respectively. The transistors MP41 to MP43 of the comparison section 31B correspond to the transistors MN31 to MN33 of the comparison section 31A, respectively. The switches SW41 and SW42 of the comparison section 31B correspond to the switches SW31 and SW32 of the comparison section 31A, respectively. The transistors MN41 and MN42 of the comparison section 31B correspond to the transistors MP31 and MP32 of the comparison section 31A, respectively.

[0205] [Variation 13]

[0206] In the above embodiment, for example, Figure 4AAs shown, the comparison circuit 23 combines the voltage of the signal SIG and the voltage of the reference signal RAMP using capacitors C1 and C2 and performs a comparison operation based on the voltage thus combined, but is not limited thereto. The comparison sections 51A and 51B according to this modification are described in detail below.

[0207] Fig.31A 1 shows a configuration example of a comparison section 51A. The comparison section 51A includes a power supply circuit 22 and a comparison circuit 53A. The comparison circuit 53A includes capacitors C51 and C52. One end of the capacitor C51 is provided with a reference signal RAMP, and the other end is connected to the gate of the transistor MN31 and one end of the switch SW31. One end of the capacitor C52 is provided with a signal SIG, and the other end is connected to the gate of the transistor MN32 and one end of the switch SW32. Here, the capacitor C51 corresponds to a specific example of a “first capacitor” in the present disclosure. The capacitor C52 corresponds to a specific example of a “second capacitor” in the present disclosure.

[0208] Fig.31B 2 shows a configuration example of a comparison section 51B. The comparison section 51B includes a power supply circuit 22A and a comparison circuit 53B. The comparison circuit 53B includes capacitors C61 and C62. One end of the capacitor C61 is provided with a reference signal RAMP, and the other end is connected to the gate of the transistor MP41 and one end of the switch SW41. One end of the capacitor C62 is provided with a signal SIG, and the other end is connected to the gate of the transistor MP42 and one end of the switch SW42.

[0209] [Other Modifications]

[0210] In addition, two or more of the above-described modifications may be combined.

[0211] <2. Example of use of the imaging device>

[0212] Fig.32 The use example of the imaging device 1 according to the above embodiment is shown. For example, as described below, the above imaging device 1 can be used for various situations of sensing light such as visible light, infrared light, ultraviolet light, and X-rays.

[0213] - Devices that capture images for viewing, such as digital cameras and mobile devices with camera functions

[0214] - Equipment for traffic use, for safe driving such as automatic stopping and recognition of the driver's status, for example, on-board sensors for capturing images of the front, rear, surroundings, and interior of a car; surveillance cameras for monitoring moving vehicles and roads; and distance measuring sensors for measuring the distance between vehicles, etc.

[0215] - Devices used in home appliances such as televisions, refrigerators, and air conditioners to capture images of user gestures and operate the appliances based on the gestures

[0216] - Equipment for medical care purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light

[0217] - Equipment for security purposes, such as surveillance cameras for crime prevention and cameras for personal identity verification

[0218] - Equipment for beauty purposes, such as skin measurement equipment that takes images of the skin and microscopes that take images of the scalp

[0219] - Equipment for sports use, such as action cameras and wearable cameras for sports applications, etc.

[0220] - Equipment for agricultural purposes, such as cameras used to monitor fields and crops

[0221] <3. Application examples of mobile objects>

[0222] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as: a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0223] Fig.33 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0224] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.33 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0225] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating the drive force of the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0226] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for each of the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, it is possible to input radio waves or signals of various switches sent from a mobile device that replaces the key to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, power window device, or lights, etc. of the vehicle.

[0227] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing on objects such as pedestrians, vehicles, obstacles, signs, or letters on the road surface.

[0228] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or can be non-visible light such as infrared rays.

[0229] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 for detecting the driver's state. The driver state detection unit 12041 includes, for example, a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0230] Based on the information outside or inside the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism, or the braking device, and can output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), including collision avoidance or collision mitigation of the vehicle, following driving based on the following distance, speed maintenance driving, vehicle collision warning, or lane departure warning of the vehicle.

[0231] In addition, the microcomputer 12051 is capable of controlling the driving force generating device, steering mechanism, or braking device, etc. based on the information outside the vehicle or inside the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing collaborative control of automatic driving aimed at achieving autonomous driving of the vehicle without relying on the driver's operation.

[0232] Furthermore, based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights and switch the high beam to the low beam, for example, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control aimed at achieving anti-glare.

[0233] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify passengers on the vehicle or the outside of the vehicle of information. Fig.33 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. The display portion 12062 may include, for example, at least one of an on-board display and a head-up display.

[0234] Fig.34 This is a diagram showing an example of the installation position of the camera unit 12031.

[0235] exist Fig.34 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0236] The camera units 12101, 12102, 12103, 12104 and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper and rear door of the vehicle 12100 and at the upper part of the windshield in the vehicle. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly acquire images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly acquire images from the side of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly acquires images from the rear of the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle is mainly used to detect the vehicle in front, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0237] By the way, Fig.34 Examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 seen from above is obtained.

[0238] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0239] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the change of the distance over time (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the following three-dimensional object as the leading vehicle: specifically, the three-dimensional object is closest to the vehicle 12100 on the driving road and is traveling at a predetermined speed (for example, greater than or equal to 0 km / h) in almost the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the leading vehicle, and can perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control such as automatic driving that enables the vehicle to travel autonomously without relying on the driver's operation can be performed.

[0240] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to see. Then, the microcomputer 12051 can determine a collision risk for indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collision.

[0241] At least one of the camera units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 is capable of identifying a pedestrian by determining whether the pedestrian exists in the image captured by the camera units 12101 to 12104. For example, such pedestrian recognition is performed by the following process: extracting feature points in the image captured by the camera units 12101 to 12104 as infrared cameras; and determining whether the object is a pedestrian by pattern matching a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a rectangular outline for emphasis is superimposed and displayed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon or the like for representing a pedestrian is displayed at a desired position.

[0242] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the camera unit 12031 in the above-mentioned components. Therefore, the image quality of the image captured in the vehicle control system 12000 can be improved. This enables the vehicle control system 12000 to improve the accuracy of collision avoidance or collision mitigation of the vehicle, following driving based on following distance, speed maintenance driving, vehicle collision warning, and lane departure warning of the vehicle.

[0243] <4. Application examples of distance measuring devices>

[0244] Next, an example in which the present technology is applied to a distance measuring device will be described in detail.

[0245] Fig.35 The configuration example of the distance measuring device 900 according to the present application example is shown. The distance measuring device 900 is configured to measure the distance to the measurement object OBJ by an indirect method. The distance measuring device 900 includes a light emitting section 901, an optical system 902, a light detecting section 910, and a control section 903.

[0246] The light emitting unit 901 is configured to emit a light pulse L0 toward the measuring object OBJ. The light emitting unit 901 emits the light pulse L0 by performing a light emitting operation of alternately repeating light emission and non-light emission based on an instruction from the control unit 903. The light emitting unit 901 includes, for example, a light source that emits infrared light. The light source is configured by using, for example, a laser light source or an LED (Light Emitting Diode).

[0247] The optical system 902 includes a lens that forms an image on the light receiving surface S of the light detection section 910. A light pulse (reflected light pulse L1) emitted from the light emitting section 901 and reflected on the measuring object OBJ enters the optical system 902.

[0248] The light detection section 910 is configured to generate a distance image PIC by detecting light based on an instruction from the control section 903. A plurality of pixel values ​​included in the distance image PIC respectively represent values ​​related to the distance D to the measuring object OBJ. Then, the light detection section 910 outputs the generated distance image PIC as an image signal DATA.

[0249] The control section 903 is configured to provide a control signal to the light emitting section 901 and the light detecting section 910 , and control the operations of the light emitting section 901 and the light detecting section 910 , thereby controlling the operations of the distance measuring device 900 .

[0250] Fig.36 An example of the configuration of the light detection unit 910 is shown. The light detection unit 910 includes a pixel array 911, a driving unit 912, a reference signal generating unit 913, a readout unit 919, a signal processing unit 914, and an imaging control unit 915. For example, the pixel array 911, the driving unit 912, the reference signal generating unit 913, the readout unit 919, the signal processing unit 914, and the imaging control unit 915 may be formed in one semiconductor substrate. In addition, the pixel array 911 may be formed in one semiconductor substrate, and the driving unit 912, the reference signal generating unit 913, the readout unit 919, the signal processing unit 914, and the imaging control unit 915 may be formed in another semiconductor substrate. The two semiconductor substrates may be stacked on each other.

[0251] The pixel array 911 includes a plurality of pixels 920 arranged in a matrix shape. The pixels 920 are respectively configured to generate a pixel voltage Vpix corresponding to the amount of received light.

[0252] Fig.37 2 shows a configuration example of the pixel 920. The pixel array 911 includes a plurality of control lines 931A, a plurality of control lines 931B, a plurality of control lines 932A, a plurality of control lines 932B, a plurality of control lines 933, a plurality of signal lines 939A, and a plurality of signal lines 939B.

[0253] The pixel 920 includes a photodiode 921, floating diffusions 923A and 923B, and transistors 922A, 922B, 924A, 924B, 925A, 925B, 926A, and 926B. The circuit including the photodiode 921, the floating diffusion 923A, and the transistors 922A, 924A, 925A, and 926A is also referred to as a tap A. In addition, the circuit including the photodiode 921, the floating diffusion 923B, and the transistors 922B, 924B, 925B, and 926B is also referred to as a tap B.

[0254] In the tap A, the gate of the transistor 922A is connected to the control line 931A, the source is connected to the photodiode 921, and the drain is connected to the floating diffusion 923A. The floating diffusion 923A is configured to accumulate the charge provided from the photodiode 921 via the transistor 922A. The gate of the transistor 924A is connected to the control line 932A, the drain is provided with the power supply voltage VDD, and the source is connected to the floating diffusion 923A. The gate of the transistor 925A is connected to the floating diffusion 923A, the drain is provided with the power supply voltage VDD, and the source is connected to the drain of the transistor 926A. The gate of the transistor 926A is connected to the control line 933, the drain is connected to the source of the transistor 925A, and the source is connected to the signal line 939A. The above description is made by taking the tap A as an example, and the same is true for the tap B.

[0255] With this configuration, in each pixel 920, the transistor 924A is turned on to reset the floating diffusion 923A, and the transistor 924B is turned on to reset the floating diffusion 923B. Then, one of the transistors 922A and 922B is alternately turned on to selectively accumulate the charge generated by the photodiode 921 in the floating diffusion 923A and the floating diffusion 923B. Then, the transistors 926A and 926B are turned on to cause the pixel 920 to output a pixel signal corresponding to the amount of charge accumulated in the floating diffusion 923A to the signal line 939A, and to output a pixel signal corresponding to the amount of charge accumulated in the floating diffusion 923B to the signal line 939B.

[0256] Driving unit 912 ( Fig.36) is configured to sequentially drive a plurality of pixels 920 in the pixel array 911 in units of pixel lines L based on an instruction from the imaging control section 915. The reference signal generating section 913 is configured to generate a reference signal RAMP based on an instruction from the imaging control section 915. The readout section 919 is configured to generate an image signal DATA0 by performing AD conversion based on a pixel signal provided from the pixel array 911 via signal lines 939A and 939B based on an instruction from the imaging control section 915. The signal processing section 914 is configured to generate a distance image PIC by performing predetermined signal processing on the image signal DATA0 based on an instruction from the imaging control section 915, and output an image signal DATA including the distance image PIC. The imaging control section 915 is configured to provide a control signal to the driving section 912, the reference signal generating section 913, the readout section 919, and the signal processing section 914, and control the operations of these circuits, thereby controlling the operation of the light detection section 910.

[0257] Fig.38 An operation example of the distance measuring device 900 is shown. Fig.38 (A) represents the waveform of the light pulse L0 emitted from the light emitting unit 901, Fig.38 (B) shows the waveform of the reflected light pulse L1 detected by the light detection unit 910 .

[0258] The light emitting unit 901 emits a light pulse L0 ( Fig.38 (A)). The light pulse L0 travels toward the measurement object OBJ. Then, the light pulse L0 is reflected on the measurement object OBJ, and the reflected light pulse L1 thus reflected travels toward the light detection unit 910. Then, the pixel 920 of the light detection unit 910 detects the reflected light pulse L1 ( Fig.38 (B)). The waveform of the reflected light pulse L1 detected by pixel 920 is relative to Fig.38 The waveform of the light pulse L0 shown in (A) is delayed by the delay time DL. The delay time DL is the time for the light to advance in the order of the light emitting unit 901, the object OBJ to be measured, and the light detecting unit 910, and corresponds to the flight time of the light. The flight time of the light corresponds to the distance between the distance measuring device 900 and the object OBJ to be measured.

[0259] In the indirect method, the floating diffusion 923A of the pixel 920 accumulates the signal charge Q1 corresponding to the amount of light received by the photodiode 921 in the period 941 when the light emitting section 901 emits light, and the floating diffusion 923B of the pixel 920 accumulates the signal charge Q2 corresponding to the amount of light received by the photodiode 921 in the period 942 when the light emitting section 901 does not emit light. Then, the signal processing section 914 determines the charge ratio between the signal charge Q1 and the signal charge Q2. The photodiode 921 detects light in the periods 951 and 952, so the charge amount of the signal charge Q1 is proportional to the length of the period 951, and the charge amount of the signal charge Q2 is proportional to the length of the period 952. In the case where the delay time DL is short, the signal charge Q1 increases and the signal charge Q2 decreases. In the case where the delay time DL is long, the signal charge Q1 decreases and the signal charge Q2 increases. Therefore, the charge ratio between the signal charge Q1 and the signal charge Q2 changes according to the delay time DL. In the indirect method, for example, by determining the charge ratio, the delay time DL can be determined with high accuracy. As a result, the distance to the measurement object OBJ can be measured with high accuracy. The present technology is applied to the readout section 919. Therefore, the image quality of the distance image can be improved.

[0260] An example of the distance measuring device 900 to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the above-mentioned distance measuring device 900. Therefore, in the distance measuring device 900, the image quality of the distance image can be improved.

[0261] Although the present technology has been described above with reference to some embodiments, modified examples, and specific application examples, the present technology is not limited to these embodiments and the like, and the present technology can be modified in various ways.

[0262] For example, in the above embodiment, the pixel P is Figure 2 The configuration shown is, but not limited to, this. Pixels having various configurations may be used.

[0263] It should be noted that the effects described herein are merely illustrative and not restrictive, and other effects may be provided.

[0264] It should be noted that the present technology may have the following configurations. According to the present technology having the following configurations, image quality can be improved. (1)

[0266] A light detection device, comprising:

[0267] a first pixel configured to generate a first pixel signal;

[0268] a reference signal generating section configured to generate a reference signal; and

[0269] A first comparison unit includes a first power supply circuit and a first comparison circuit, wherein the first power supply circuit is configured to generate a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node, and output the first power supply voltage from an output terminal, and the first comparison circuit is configured to operate based on the first power supply voltage and perform a comparison operation based on the first pixel signal and the reference signal. (2)

[0271] The light detection device according to (1), wherein the first comparison circuit includes a first current source connected to the second power supply node. (3)

[0273] The light detection device according to (2), wherein

[0274] The first pixel is configured to output the first pixel signal from an output terminal,

[0275] The reference signal generating section is configured to output the reference signal from an output terminal, and

[0276] The first comparison circuit comprises:

[0277] a first transistor having a gate, a drain and a source;

[0278] a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor,

[0279] a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the first transistor; and

[0280] A first switch connects the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch. (4)

[0282] The light detection device according to (3), wherein

[0283] The source of the first transistor is connected to the output terminal of the first power supply circuit, and

[0284] The drain of the first transistor is connected to the first current source. (5)

[0286] The light detection device according to (4), wherein

[0287] The first comparison circuit further includes:

[0288] a second transistor having a gate connected to the drain of the first transistor, a drain and a source;

[0289] a third transistor having a gate, a drain connected to the drain of the second transistor, and a source connected to the second power supply node; and

[0290] a second switch that connects the gate of the third transistor and the drain of the third transistor to each other by turning on the second switch. (6)

[0292] The light detection device according to (5), wherein the first comparison unit further includes a fourth transistor having a gate connected to the drain of the second transistor, a drain connected to the output terminal of the first power supply circuit, and a source connected to the drain of the first transistor. (7)

[0294] The light detection device according to (3), wherein

[0295] The source of the first transistor is connected to the first current source, and

[0296] The first comparison circuit comprises:

[0297] a fifth transistor having a gate, a drain, and a source connected to the first current source;

[0298] a third capacitor connected to the gate of the fifth transistor;

[0299] a third switch, connecting the gate electrode of the fifth transistor and the drain electrode of the fifth transistor to each other by turning on the third switch; and

[0300] A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor. (8)

[0302] The light detection device according to (2), wherein:

[0303] The first pixel is configured to output the first pixel signal from an output terminal,

[0304] The reference signal generating section is configured to output the reference signal from an output terminal, and

[0305] The first comparison circuit comprises:

[0306] a first transistor having a gate, a drain, and a source connected to the first current source;

[0307] a fifth transistor having a gate, a drain, and a source connected to the first current source;

[0308] a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor,

[0309] a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the fifth transistor;

[0310] a first switch, connecting the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch;

[0311] a third switch, connecting the gate electrode of the fifth transistor and the drain electrode of the fifth transistor to each other by turning on the third switch; and

[0312] A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor. (9)

[0314] The light detection device according to (7) or (8), wherein the load circuit comprises:

[0315] a first load transistor having a gate, a drain connected to the drain of the first transistor, and a source connected to the output terminal of the first power supply circuit; and

[0316] A second load transistor has a gate connected to the gate of the first load transistor, a drain connected to the drain of the fifth transistor, and a source connected to the output terminal of the first power supply circuit. (10)

[0318] The light detection device according to (2), wherein

[0319] The first pixel is configured to output the first pixel signal from an output terminal,

[0320] The reference signal generating section is configured to output the reference signal from an output terminal, and

[0321] The first comparison circuit comprises:

[0322] a first transistor having a gate, a drain, and a source connected to the output terminal of the first power supply circuit;

[0323] a sixth transistor having a gate, a drain connected to the first current source, and a source connected to the drain of the first transistor;

[0324] a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor;

[0325] a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the first transistor; and

[0326] a first switch, and connecting the gate of the first transistor and the drain of the sixth transistor to each other by turning on the first switch. (11)

[0328] The light detection device according to any one of (3) to (10), wherein:

[0329] The bias voltage includes a first bias voltage, and

[0330] The first power supply circuit includes a first power supply transistor having a gate supplied with the first bias voltage, a drain connected to the first power supply node, and a source connected to the source of the first transistor. (12)

[0332] The light detection device according to any one of (3) to (10), wherein:

[0333] The bias voltage includes a first bias voltage and a second bias voltage, and

[0334] The first power supply circuit comprises:

[0335] a first power supply transistor having a gate supplied with the first bias voltage, a drain connected to the first power supply node, and a source; and

[0336] A second power supply transistor has a gate supplied with the second bias voltage, a drain connected to the source of the first power supply transistor, and a source connected to the source of the first transistor. (13)

[0338] The light detection device according to (11) or (12), wherein the first power supply circuit further includes a fourth switch, and the first bias voltage is supplied to the gate of the first power supply transistor by turning on the fourth switch. (14)

[0340] The light detection device according to (13), wherein the first power supply circuit further includes a fourth capacitor connected to the gate of the first power supply transistor. (15)

[0342] A light detection device according to (11) or (12), wherein the first power supply circuit also includes an operational amplifier, a non-inverting input terminal of the operational amplifier is provided with the first bias voltage, an inverting input terminal is connected to the source of the first power supply transistor, and an output terminal is connected to the gate of the first power supply transistor. (16)

[0344] The light detection device according to (11) or (12), wherein the first power supply transistor further has a back gate connected to the source of the first power supply transistor. (17)

[0346] The light detection device according to (11) or (12), further comprising a voltage generating section configured to output a predetermined voltage from the output terminal, wherein

[0347] The first power supply transistor further has a back gate connected to the output terminal of the voltage generating section. (18)

[0349] The light detection device according to (12), wherein the first power supply circuit further includes a fifth switch, and the second bias voltage is supplied to the gate of the second power supply transistor by turning on the fifth switch. (19)

[0351] The light detection device according to any one of (3) to (6), wherein the first transistor further has a back gate connected to the source of the first transistor. (20)

[0353] The light detection device according to any one of (2) to (19), wherein the first current source includes a first current source transistor having a gate, a drain, and a source connected to the second power supply node. (twenty one)

[0355] The light detection device according to any one of (2) to (19), wherein:

[0356] The first current source comprises:

[0357] a first current source transistor having a gate, a drain, and a source connected to the second power supply node; and

[0358] A second current source transistor has a gate, a drain, and a source connected to the drain of the first current source transistor. (twenty two)

[0360] The light detection device according to (20), wherein the first current source further includes a sixth switch, and a third bias voltage is provided to the gate of the first current source transistor by turning on the sixth switch. (twenty three)

[0362] The light detection device according to any one of (1) to (22), further comprising:

[0363] a second pixel configured to generate a second pixel signal; and

[0364] A second comparing unit includes a second power supply circuit and a second comparing circuit, wherein the second power supply circuit is configured to generate a second power supply voltage based on the power supply voltage and the bias voltage provided from the first power supply node, and output the second power supply voltage from an output terminal, and the second comparing circuit is configured to operate based on the second power supply voltage and perform the comparing operation based on the second pixel signal and the reference signal. (twenty four)

[0366] The light detection device according to (23), wherein the output terminal of the second power supply circuit is connected to the output terminal of the first power supply circuit. (25)

[0368] The light detection device according to (24), further comprising:

[0369] a third pixel configured to generate a third pixel signal; and

[0370] a third comparison section, comprising a third power supply circuit and a third comparison circuit, wherein the third power supply circuit is configured to generate a third power supply voltage based on the power supply voltage supplied from the first power supply node and the bias voltage, and output the third power supply voltage from an output terminal, and the third comparison circuit is configured to operate based on the third power supply voltage and perform the comparison operation based on the third pixel signal and the reference signal, wherein:

[0371] The output terminal of the third power supply circuit is electrically insulated from the output terminal of the first power supply circuit and is electrically insulated from the output terminal of the second power supply circuit, and

[0372] The third comparing section is provided between the first comparing section and the second comparing section. (26)

[0374] The light detection device according to (23), further including a variable resistor having a first terminal connected to the output terminal of the first power supply circuit and a second terminal connected to the output terminal of the second power supply circuit. (27)

[0376] The light detection device according to (23), further including a fourth power supply circuit configured to generate the power supply voltage based on another power supply voltage supplied from a third power supply node and output the power supply voltage to the first power supply node. (28)

[0378] An electronic device, comprising:

[0379] a light detection device; and

[0380] a processing unit for controlling the operation of the light detection device,

[0381] The light detection device comprises:

[0382] a first pixel configured to generate a first pixel signal;

[0383] a reference signal generating section configured to generate a reference signal; and

[0384] A first comparison unit includes a first power supply circuit and a first comparison circuit, wherein the first power supply circuit is configured to generate a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node, and output the first power supply voltage from an output terminal, and the first comparison circuit is configured to operate based on the first power supply voltage and perform a comparison operation based on the first pixel signal and the reference signal.

[0385] This application claims the benefit of Japanese Priority Patent Application JP2019-068359 filed in the Japan Patent Office on Mar. 29, 2019, the entire contents of which are incorporated herein by reference.

[0386] Those skilled in the art should understand that various modifications, combinations, sub-combinations and changes may be made according to design requirements and other factors as long as these modifications, combinations, sub-combinations and changes are within the scope of the appended claims or the equivalents thereof.

Claims

1. A light detection device, include: a first pixel configured to generate a first pixel signal; a second pixel configured to generate a second pixel signal; a reference signal generating unit configured to generate a reference signal; a first comparing section including a first power supply circuit configured to generate a first power supply voltage based on a power supply voltage supplied from a first power supply node and a bias voltage and output the first power supply voltage from an output terminal and a first comparing circuit configured to operate based on the first power supply voltage and perform a comparing operation based on the first pixel signal and the reference signal; and A second comparing unit includes a second power supply circuit and a second comparing circuit, wherein the second power supply circuit is configured to generate a second power supply voltage based on the power supply voltage and the bias voltage provided from the first power supply node, and output the second power supply voltage from an output terminal, and the second comparing circuit is configured to operate based on the second power supply voltage and perform the comparing operation based on the second pixel signal and the reference signal.

2. The light detection device according to claim 1, in, The first comparison circuit includes a first current source connected to a second power supply node.

3. The light detection device according to claim 2, in, The first pixel is configured to output the first pixel signal from an output terminal, The reference signal generating section is configured to output the reference signal from an output terminal, and The first comparison circuit comprises: a first transistor having a gate, a drain and a source; a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor, a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the first transistor; and A first switch connects the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch.

4. The light detection device according to claim 3, in, The source of the first transistor is connected to the output terminal of the first power supply circuit, and The drain of the first transistor is connected to the first current source.

5. The light detection device according to claim 4, in, The first comparison circuit further includes: a second transistor having a drain, a source, and a gate connected to the drain of the first transistor; a third transistor having a gate, a drain connected to the drain of the second transistor, and a source connected to the second power supply node; and a second switch that connects the gate of the third transistor and the drain of the third transistor to each other by turning on the second switch.

6. The light detection device according to claim 5, in, The first comparing section further includes a fourth transistor having a gate connected to the drain of the second transistor, a drain connected to the output terminal of the first power supply circuit, and a source connected to the drain of the first transistor.

7. The light detection device according to claim 3, in, The source of the first transistor is connected to the first current source, and The first comparison circuit comprises: a fifth transistor having a gate, a drain, and a source connected to the first current source; a third capacitor connected to the gate of the fifth transistor; a third switch, connecting the gate electrode of the fifth transistor and the drain electrode of the fifth transistor to each other by turning on the third switch; and A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor.

8. The light detection device according to claim 2, in, The first pixel is configured to output the first pixel signal from an output terminal, The reference signal generating section is configured to output the reference signal from an output terminal, and The first comparison circuit comprises: a first transistor having a gate, a drain, and a source connected to the first current source; a fifth transistor having a gate, a drain, and a source connected to the first current source; a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor, a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the fifth transistor; a first switch, connecting the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch; a third switch, connecting the gate electrode of the fifth transistor and the drain electrode of the fifth transistor to each other by turning on the third switch; and A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor.

9. The light detection device according to claim 7, in, The load circuit comprises: a first load transistor having a gate, a drain connected to the drain of the first transistor, and a source connected to the output terminal of the first power supply circuit; and A second load transistor has a gate connected to the gate of the first load transistor, a drain connected to the drain of the fifth transistor, and a source connected to the output terminal of the first power supply circuit.

10. The light detection device according to claim 2, in, The first pixel is configured to output the first pixel signal from an output terminal, The reference signal generating section is configured to output the reference signal from an output terminal, and The first comparison circuit comprises: a first transistor having a gate, a drain, and a source connected to the output terminal of the first power supply circuit; a sixth transistor having a gate, a drain connected to the first current source, and a source connected to the drain of the first transistor; a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor; a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the first transistor; and a first switch, and connecting the gate of the first transistor and the drain of the sixth transistor to each other by turning on the first switch.

11. The light detection device according to claim 3, in, The bias voltage includes a first bias voltage, and The first power supply circuit includes a first power supply transistor having a gate provided with the first bias voltage, a drain connected to the first power supply node, and a source connected to the source of the first transistor.

12. The light detection device according to claim 3, in, The bias voltage includes a first bias voltage and a second bias voltage, and The first power supply circuit comprises: a first power supply transistor having a source, a gate supplied with the first bias voltage, and a drain connected to the first power supply node; and A second power supply transistor has a gate supplied with the second bias voltage, a drain connected to the source of the first power supply transistor, and a source connected to the source of the first transistor.

13. The light detection device according to claim 11, in, The first power supply circuit further includes a fourth switch, and the first bias voltage is provided to the gate of the first power supply transistor by turning on the fourth switch.

14. The light detection device according to claim 13, in, The first power supply circuit also includes a fourth capacitor connected to the gate of the first power supply transistor.

15. The light detection device according to claim 11, in, The first power supply circuit also includes an operational amplifier having a non-inverting input terminal provided with the first bias voltage, an inverting input terminal connected to the source of the first power supply transistor, and an output terminal connected to the gate of the first power supply transistor.

16. The light detection device according to claim 11, in, The first power supply transistor also has a back gate connected to the source of the first power supply transistor.

17. The light detecting device according to claim 11, further comprising a voltage generating section configured to output a predetermined voltage from an output terminal, in, The first power supply transistor further has a back gate connected to the output terminal of the voltage generating section.

18. The light detection device according to claim 12, in, The first power supply circuit further includes a fifth switch, and the second bias voltage is provided to the gate of the second power supply transistor by turning on the fifth switch.

19. The light detection device according to claim 3, in, The first transistor also has a back gate connected to the source of the first transistor.

20. The light detection device according to claim 2, in, The first current source includes a first current source transistor having a gate, a drain, and a source connected to the second power supply node.

21. The light detection device according to claim 2, in, The first current source comprises: a first current source transistor having a gate, a drain, and a source connected to the second power supply node; and A second current source transistor has a gate, a drain, and a source connected to the drain of the first current source transistor.

22. The light detection device according to claim 20, in, The first current source further includes a sixth switch, and a third bias voltage is provided to the gate of the first current source transistor by turning on the sixth switch.

23. The light detection device according to claim 1, in, The output terminal of the second power supply circuit is connected to the output terminal of the first power supply circuit.

24. The light detection device according to claim 23, further comprising: include: a third pixel configured to generate a third pixel signal; and a third comparison section, comprising a third power supply circuit and a third comparison circuit, wherein the third power supply circuit is configured to generate a third power supply voltage based on the power supply voltage supplied from the first power supply node and the bias voltage, and output the third power supply voltage from an output terminal, and the third comparison circuit is configured to operate based on the third power supply voltage and perform the comparison operation based on the third pixel signal and the reference signal, wherein: The output terminal of the third power supply circuit is electrically insulated from the output terminal of the first power supply circuit and is electrically insulated from the output terminal of the second power supply circuit, and The third comparing section is provided between the first comparing section and the second comparing section. 25 . The light detection device according to claim 1 , further comprising a variable resistor having a first terminal connected to the output terminal of the first power supply circuit and a second terminal connected to the output terminal of the second power supply circuit. 26 . The light detecting device according to claim 1 , further comprising a fourth power supply circuit configured to generate the power supply voltage based on another power supply voltage supplied from a third power supply node and output the power supply voltage to the first power supply node.

27. An electronic device, wherein include: Light detection device; and a processing unit for controlling the operation of the light detection device, The light detection device is the light detection device according to any one of claims 1 to 26.

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