Metal oxide semiconductor field effect transistor device and manufacturing method thereof

Abstract

The present disclosure provides a metal oxide semiconductor field effect transistor and a method for manufacturing the same. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be adjacent to the gate of the device and / or located above the source region or drain region of the device. Various embodiments may include different combinations of air gaps formed in one or more sidewall spacers. Various embodiments may include air gaps formed adjacent to the gate of the device and / or located above the source region or drain region of the device. The formation of air gaps may reduce unnecessary parasitic capacitance and / or fringe capacitance.

Description

Technical Field

[0001] The present disclosure relates to a metal oxide semiconductor field effect transistor device having an air gap in a spacer and a method of manufacturing the same. Background Art

[0002] Parasitic / overlap capacitance caused by capacitance effects generated by sidewall spacers and / or gate oxide dielectric layers degrades the performance of metal-oxide semiconductor field effect transistor (MOSFET) devices, especially MOSFET devices operating at radio frequency (RF). In particular, the magnitude of parasitic / overlap capacitance can significantly affect the switching speed of MOSFET devices. The larger the capacitance, the more charge must be consumed to switch the MOSFET device. Therefore, the switching speed is significantly slowed down.

[0003] Parasitic capacitance may include various junction capacitances and overlap capacitances. Junction capacitance depends on the depth of the junction. Overlap capacitance depends on the amount of overlap between the implanted regions (such as the source and drain regions) and the gate. In addition to junction capacitance and overlap capacitance, the inner edge capacitance caused by the charge interaction of the sides of the gate in the source and drain regions and the outer edge capacitance caused by the charge interaction of the bottom of the gate in the source and drain regions may also have an adverse effect on the performance of the MOSFET device. Further, the use of high-k gate and spacer materials can increase the size of the edge region and result in higher edge capacitance without achieving short channel performance. Summary of the invention

[0004] According to an aspect of the present disclosure, a metal oxide semiconductor field effect transistor (MOSFET) device is located on a substrate, including a source region, a drain region, and a channel region located between the source region and the drain region. A gate dielectric layer is located above the channel region. A gate layer is located above the gate dielectric layer. A first sidewall spacer is adjacent to the gate dielectric layer and the gate layer and is located above the source region or the drain region. A second sidewall spacer is adjacent to the gate dielectric layer and the gate layer and is located above the other of the source region or the drain region. A first pair of air gaps, including a first air gap and a second air gap, are located in the first sidewall spacer, wherein the first air gap is adjacent to the gate layer and the second air gap is located above the source region or the drain region, wherein the first air gap has a major axis parallel to the gate layer, and the second air gap has a major axis parallel to the major surface of the substrate.

[0005] According to another aspect of the present disclosure, an integrated circuit having a metal oxide semiconductor field effect transistor device is located on a substrate and includes a plurality of metal oxide semiconductor field effect transistor devices, wherein at least one of the metal oxide semiconductor field effect transistor devices includes a plurality of sidewall spacers having a plurality of air gaps.

[0006] According to one aspect of the present disclosure, a method for manufacturing a metal oxide semiconductor field effect transistor on a substrate includes forming a metal oxide semiconductor field effect transistor device including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located on the channel region, a metal or polysilicon gate layer located on the gate dielectric layer, a first sidewall spacer adjacent to the gate dielectric layer and the metal or polysilicon gate layer and located on one of the source region or the drain region, and a second sidewall spacer adjacent to the gate dielectric layer and the metal or polysilicon gate layer and located on the other of the source region or the drain region. Etching the first sidewall spacer to form a first pair of trenches in the first sidewall spacer, the first pair of trenches including a first trench adjacent to the metal or polysilicon gate layer and a second trench located on the source region or the drain region. Depositing an etch stop layer on the first sidewall spacer to form a first air gap and a second air gap, the first air gap adjacent to the metal or polysilicon gate layer, and the second air gap located on the source region or the drain region. The first air gap has a major axis parallel to the metal or polysilicon gate layer, and the second air gap has a major axis parallel to the major surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with the practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity, the size of the various features can be arbitrarily increased or reduced.

[0008] Figure 1 A vertical cross-sectional view illustrating steps of forming a continuous gate dielectric layer, a continuous gate layer and a photoresist on a substrate in a semiconductor manufacturing method according to some embodiments;

[0009] Figure 2 A vertical cross-sectional view illustrating a step of patterning a continuous gate dielectric layer and a continuous gate layer on a substrate in a semiconductor manufacturing method according to some embodiments;

[0010] Figure 3 A vertical cross-sectional view illustrating a step of forming a source extension region and a drain extension region in a substrate by ion implantation in a semiconductor manufacturing method according to some embodiments;

[0011] Figure 4A vertical cross-sectional view illustrating steps of forming a continuous first oxide layer and a continuous nitride layer in a semiconductor manufacturing method according to some embodiments;

[0012] Figure 5 A vertical cross-sectional view illustrating a step of forming a continuous second oxide layer on a continuous nitride layer in a semiconductor manufacturing method according to some embodiments;

[0013] Figure 6 A vertical cross-sectional view illustrating a step of etching a continuous first oxide layer, a nitride layer, and a second oxide layer to form a sidewall spacer in a semiconductor manufacturing method according to some embodiments;

[0014] Figure 7 A vertical cross-sectional view illustrating steps of forming a deep source region and a deep drain region in a substrate by ion implantation in a semiconductor manufacturing method according to some embodiments;

[0015] Figure 8 A vertical cross-sectional view of a silicided deep source region, a deep drain region and a gate in a semiconductor manufacturing method according to some embodiments is shown;

[0016] Fig. 9 A vertical cross-sectional view illustrating a step of forming a nitride layer on a sidewall in a semiconductor manufacturing method according to some embodiments;

[0017] Fig. 10A A vertical cross-sectional view illustrating a step of forming an air gap in a nitride layer on a sidewall by depositing a stop layer in a semiconductor manufacturing method according to some embodiments;

[0018] Fig. 10B For part Fig. 10A Close-up view of

[0019] Fig.11 A vertical cross-sectional view illustrating steps of forming an intermediate dielectric layer and source / drain electrodes in a semiconductor manufacturing method according to some embodiments;

[0020] Fig.12 A vertical cross-sectional view of a semiconductor device having an air gap in only one sidewall according to some embodiments is shown;

[0021] Fig.13 A vertical cross-sectional view of a semiconductor device is shown, wherein a first transistor structure has air gaps on all sidewalls, a second transistor structure has an air gap on one sidewall, and a third transistor structure has no air gap on the sidewall;

[0022] Fig.14 A flowchart of manufacturing a semiconductor device with an air gap according to some embodiments is shown;

[0023] Fig.15A A vertical cross-sectional view of a semiconductor device is shown in which an air gap is formed only in the sidewall above the source / drain extension region;

[0024] Fig. 15B To illustrate the use of Fig.15A The device shown in Figure 8 A vertical cross-sectional view of the steps of forming and patterning a photoresist layer on the structure shown;

[0025] Fig. 15C To illustrate the use of Fig.15A A vertical cross-sectional view of the device shown in , a step of forming a trench in the nitride layer of the sidewall;

[0026] Fig.16 To illustrate another semiconductor manufacturing method according to some embodiments, in Figure 8 A vertical cross-sectional view of a step of forming a photoresist layer on the structure shown;

[0027] Fig.17 A vertical cross-sectional view illustrating the steps of patterning a photoresist layer to form a first portion of a transistor structure having an air gap in a portion of a sidewall spacer next to a gate, and forming a second portion of a transistor structure having an air gap in a portion of a sidewall spacer above a source / drain region in a semiconductor manufacturing method according to some embodiments;

[0028] Fig.18 A vertical cross-sectional view illustrating steps of forming a trench in a first portion of a portion of a transistor structure to form an air gap in a portion of a sidewall spacer next to a gate, and forming a trench in a second portion of the portion of the transistor structure to form an air gap in a portion of the sidewall spacer above a source / drain region in another semiconductor manufacturing method according to some embodiments;

[0029] Fig.19 A vertical cross-sectional view illustrating steps of forming an air gap in a first portion of a transistor structure in a sidewall spacer next to a gate and forming an air gap in a second portion of the transistor structure in a portion of the sidewall spacer above a source / drain region in another semiconductor manufacturing method according to some embodiments;

[0030] Fig. 20 A vertical cross-sectional view illustrating a step of forming an intermediate dielectric layer and source / drain electrodes in another semiconductor manufacturing method according to some embodiments;

[0031] Fig.21A vertical cross-sectional view illustrating a semiconductor device according to some embodiments, wherein a first portion of a transistor structure may have a single air gap in a nitride layer adjacent to a sidewall of a patterned gate dielectric layer, and a second portion of the transistor structure may have a single air gap in a nitride layer on a sidewall above a source or drain extension region;

[0032] Fig. 22 A vertical cross-sectional view illustrating a semiconductor device according to some embodiments, a first portion of a transistor having a single air gap in a nitride layer adjacent to a patterned gate dielectric layer and a sidewall of a patterned gate layer, and an air gap in the nitride layer at the sidewall above source and drain extension regions; and a second portion of the transistor having a single air gap in a nitride layer at the sidewall above a source or drain extension region, and an air gap in the nitride layer adjacent to the sidewall of the patterned gate dielectric layer and the patterned gate layer;

[0033] Fig.23 FIG. 4 is a flow chart illustrating another method for manufacturing a semiconductor device with an air gap according to some embodiments.

[0034]

Explanation of symbols

[0035] 102:Substrate

[0036] 104: Patterning the gate dielectric layer

[0037] 104L: Continuous gate dielectric layer

[0038] 106: Patterned gate layer

[0039] 106L: Continuous gate layer

[0040] 108: Photoresist layer

[0041] 110: Source extension region

[0042] 112: Drain extension region

[0043] 113: Channel area

[0044] 114: First ion implantation step

[0045] 116: Patterning the first oxide layer

[0046] 116L: Continuous first oxide layer

[0047] 118: Patterned nitride layer

[0048] 118L: Continuous Nitride Layer

[0049] 120L: Continuous second oxide layer

[0050] 122L: Sandwich

[0051] 122A: first sidewall spacer

[0052] 122B: Second sidewall spacer

[0053] 124: Second ion implantation step

[0054] 126: Deep Source Region

[0055] 127: Source region

[0056] 128: Deep drain region

[0057] 129: Drain region

[0058] 130: Silicide layer

[0059] 131: Transistor Structure

[0060] 131A: Transistor Structure

[0061] 131B: Transistor Structure

[0062] 131C: Transistor Structure

[0063] 131D: Transistor Structure

[0064] 131E: Transistor Structure

[0065] 131F: First transistor structure

[0066] 131G: Second transistor structure

[0067] 131H: First transistor structure

[0068] 131I: Second transistor structure

[0069] 132a: first groove

[0070] 132b: third groove

[0071] 134a: second groove

[0072] 134b: Fourth groove

[0073] 136: Etching stop layer

[0074] 138a: first air gap

[0075] 138b: Third air gap

[0076] 140a: second air gap

[0077] 140b: Fourth air gap

[0078] 142: Intermediate dielectric layer

[0079] 144: Source / drain electrode

[0080] 100:Semiconductor device

[0081] 200:Semiconductor devices

[0082] 300:Semiconductor devices

[0083] 400:Method

[0084] 402-406: Steps

[0085] 500:Semiconductor devices

[0086] 600:Semiconductor devices

[0087] 700:Semiconductor device

[0088] 800:Semiconductor devices

[0089] 900: Method

[0090] 902-908: Steps

[0091] H A1 :high

[0092] H A2 :high

[0093] H G :Total gate height

[0094] T A1 :thickness

[0095] T A2 :thickness

[0096] T O1 :Patterned first oxide layer thickness

[0097] T O2 :Patterned second oxide layer thickness

[0098] T N :Patterned nitride layer thickness DETAILED DESCRIPTION

[0099] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, values, operations, materials, configurations, and the like are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, and the like are also considered. For example, in the following description, forming a first feature above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may repeat reference numbers and / or text in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0100] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "above," etc. may be used in the present disclosure to describe one element or feature relative to another element or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0101] Generally, the disclosed structures and methods can be used to form metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices, wherein at least some of the MOSFETs have an air gap in at least one sidewall spacer of the MOSFET. The capacitance of a parallel plate capacitor is described by the following equation (1).

[0102]

[0103] Where Q is the charge of the parallel plates, V is the voltage across the gap between the parallel plates, ε is the dielectric constant, A is the area of ​​the parallel plates, and d is the spacing between the parallel plates. Therefore, when the area and spacing are known, the capacitance can be reduced by using a material with a lower dielectric constant than air between the parallel plates. The dielectric constant of silicon oxide (SiO2) is 3.9, while the dielectric constant of silicon nitride (Si3N4) is 7.9. In contrast, the dielectric constant of air is 1.0. Therefore, by forming an air gap at the location of a dielectric spacer formed by a higher dielectric constant material such as silicon oxide or silicon nitride, the junction capacitance, overlap capacitance and / or edge capacitance in the MOSFET can be reduced, and thereby increase and / or maintain switching speed and / or enhance the performance of short channels affected by the capacitor dielectric.

[0104] In some embodiments, both sidewall spacers of the MOSFET have air gaps formed in them. In other embodiments, a first portion of the MOSFET has air gaps formed in both sidewall spacers of the MOSFET, and a second portion of the MOSFET has an air gap formed in only one spacer. In other embodiments, a first portion of the MOSFET has air gaps formed in both sidewall spacers of the MOSFET, a second portion of the MOSFET has an air gap formed in only one spacer, and a third portion of the MOSFET has no air gaps in the sidewall spacers.

[0105] refer to Figure 1 , a continuous gate dielectric layer 104L, a continuous gate layer 106L, and a photoresist layer 108 may be formed on a substrate 102. The substrate 102 may be made of any suitable material, such as silicon, silicon on insulator (SOI), or silicon on sapphire (SOS). The continuous gate dielectric layer 104L may be made of any suitable material, such as an oxide or a nitride, such as silicon oxide. Other suitable materials may also be included in the scope of the present disclosure. The continuous gate layer 106L may be made of a metal, such as tungsten, nickel, aluminum, or an alloy thereof, or the continuous gate layer 106L may be made of polysilicon. Other suitable materials may also be included in the scope of the present disclosure. The photoresist layer 108 may be a positive or negative photoresist. The continuous gate dielectric layer 104L and the continuous gate layer 106L may be made by any suitable method. For example, the continuous gate dielectric layer 104L and the continuous gate layer 106L may be formed by chemical vapor deposition, metal organic chemical vapor deposition, or atomic layer deposition.

[0106] refer to Figure 2 , the photoresist layer 108 may be lithographically patterned to form an etch mask to form the gate. The photoresist layer 108 may be formed of a positive photoresist material, where ultraviolet radiation makes the polymer more soluble and easier to remove, or a negative photoresist material, where exposure to ultraviolet radiation can cause the polymer to crosslink and be more difficult to remove. The photoresist layer 108 is exposed to ultraviolet radiation through a photolithographic mask, and the unwanted material is removed. An etching process may then be performed to form a patterned gate dielectric layer 104 and a patterned gate layer 106 by patterning the continuous gate dielectric layer 104L and the continuous gate layer 106L. The photoresist layer 108 may then be removed by an ashing process.

[0107] refer to Figure 3, a first ion implantation step 114 may be performed on the substrate 102 to form the source extension region 110 and the drain extension region 112 in the substrate 102. The patterned gate layer 106 may mask a portion of the substrate 102 between the source extension region 110 and the drain extension region 112. Therefore, the source extension region 110 and the drain extension region 112 may be self-aligned to the patterned gate layer 106. Specifically, when the continuous gate layer 106L is patterned and used as a mask to form the source extension region 110 and the drain extension region 112, rather than first forming the source extension region 110 and the drain extension region 112 and then depositing and patterning the continuous gate layer 106L, there is no need to align a separate gate mask to align the patterned gate layer 106 having the source extension region 110 and the drain extension region 112. That is, by using the patterned gate layer 106 as a mask, the source extension region 110 and the drain extension region 112 are automatically aligned (i.e., self-aligned) to the patterned gate layer 106. The source extension region 110 and the drain extension region 112 can be doped with p-type or n-type dopants as required. Example n-type dopants include, but are not limited to, antimony, arsenic, and phosphorus. Example p-type dopants include, but are not limited to, boron, aluminum, and gallium. The implanted ion concentration of the source extension region 110 and the drain extension region 112 can be 2x10 20 Up to 2x10 21 As mentioned above, the doping concentration may be higher or lower. The region between the source extension region 110 and the drain extension region 112 and below the patterned gate dielectric layer 104 and the patterned gate layer 106 may constitute a channel region 113 .

[0108] refer to Figure 4 , the continuous first oxide layer 116L can be conformally deposited on the substrate 102 and the sidewalls and tops of the patterned gate dielectric layer 104 and the patterned gate layer 106. The continuous first oxide layer 116L can be made of a suitable oxide, such as silicon dioxide, hafnium dioxide (HfO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), titanium dioxide (TiO2). The scope of the present disclosure may also include other materials suitable for forming the continuous first oxide layer 116L. The continuous first oxide layer 116L can be formed by any suitable method. For example, the continuous first oxide layer 116L can be formed by chemical vapor deposition, metal organic chemical vapor deposition, or atomic layer deposition.

[0109] Next, the continuous nitride layer 118L may be co-deposited on the continuous first oxide layer 116L. Similar to the continuous first oxide layer 116L, the nitride layer 118L may be formed by any suitable method. For example, the nitride layer 118L may be formed by chemical vapor deposition, metal organic chemical vapor deposition, or atomic layer deposition.

[0110] refer to Figure 5 , the continuous second oxide layer 120L can be conformally deposited on the nitride layer 118L. In this way, a continuous oxide / nitride / oxide sandwich 122L can be formed on the substrate 102 and the patterned gate dielectric layer 104 and the patterned gate layer 106. The continuous second oxide layer 120L can be made of the same or different material as the continuous first oxide layer 116L. Similar to the continuous first oxide layer 116L, the continuous second oxide layer 120L can be formed by any suitable method. For example, the continuous second oxide layer 120L can be formed by chemical vapor deposition, metal organic chemical vapor deposition, or atomic layer deposition.

[0111] refer to Figure 6 , the continuous first oxide layer 116L, the continuous nitride layer 118L and the continuous second oxide layer 120L, i.e., the continuous oxide / nitride / oxide (ONO) can be combined to form a sandwich 122L structure and patterned to form a first sidewall spacer 122A and a second sidewall spacer 122B adjacent to the patterned gate dielectric layer 104 and the patterned gate layer 106. In this step, a portion of the upper surface of the source extension region 110 and the drain extension region 112 above the first sidewall spacer 122A and the second sidewall spacer 122B will be exposed. The first sidewall spacer 122A and the second sidewall spacer 122B can be formed so that the patterned first oxide layer 116 has a thickness between to Thickness (T O1 ), the patterned nitride layer 118 has a thickness between to Thickness (T N ), and the patterned second oxide layer 120 has a thickness between to Thickness (T O2 ).

[0112] refer to Figure 7 , a second ion implantation step 124 is performed. In this step, ions are implanted into the exposed source extension region 110 and the drain extension region 112 to form a deep source region 126 adjacent to the source extension region 110 and a deep drain region 128 adjacent to the drain extension region 112. The ion implantation concentration of the deep source region 126 and the deep drain region 128 may be 2 x 1021 Up to 2x 10 22 Even so, higher or lower dopant concentrations may be used. The source extension region 110 and the deep source region 126 may be collectively referred to as the source region 127. The drain extension region 112 and the deep drain region 128 may be collectively referred to as the drain region 129. The ions implanted in the second ion implantation step 124 may be the same as or different from the ions implanted in the first ion implantation step 114.

[0113] refer to Figure 8 , a silicide layer 130 is formed on the upper surface of the deep source region 126 and the deep drain region 128. The silicide layer 130 can be formed by depositing a metal thin layer (not shown) on the deep source region 126 and the deep drain region 128 and heating the metal to react with silicon. As further shown in the figure, when the patterned gate layer 106 is made of polysilicon, the metal can be deposited on the upper surface of the patterned gate layer 106 and heated to form the silicide layer 130 on the upper surface of the patterned gate layer 106. In summary, the patterned gate dielectric layer 104, the patterned gate layer 106, the first sidewall spacer 122A, the second sidewall spacer 122B, the source extension region 110, the drain extension region 112, the channel region 113, the source region 127 and the drain region 129 include a transistor structure 131. In one embodiment, the transistor structure 131 can be a MOSFET. The silicide layer 130 formed on the gate layer 106 , the deep source region 126 and the deep drain region 128 can improve the conductivity of the subsequently formed metal channel, which can be coupled to the gate layer 106 and the deep source region 126 and the deep drain region 128 .

[0114] refer to Fig. 9, the patterned nitride layer 118 in the first sidewall spacer 122A and the second sidewall spacer 122B can be selectively etched corresponding to the patterned first oxide layer 116 and the patterned second oxide layer 120. In this way, the first trench 132a and the third trench 132b can be formed in the patterned nitride layer 118 adjacent to the patterned gate dielectric layer 104 and the patterned gate layer 106. Further, the second trench 134a and the fourth trench 134b can be formed on the source extension region 110 or the drain extension region 112. The first trench 132a, the second trench 134a, the third trench 132b and the fourth trench 134b can be selectively etched by a wet etching process, a dry etching process or a combination of wet and dry etching processes. Therefore, the first trench 132a and the second trench 134a will be formed in the first sidewall spacer 122A. The third trench 132b and the fourth trench 134b will be formed in the second sidewall spacer 122B. The first trench 132a and the second trench 134a may be referred to as a first pair of trenches. The third trench 132b and the fourth trench 134b may be referred to as a second pair of trenches. In various embodiments, the patterned nitride layer 118 may be etched so that the first trench 132a and the third trench 132b have the following shapes: Fig. 10B The depth shown is between the total gate height H G In some embodiments, the first trench 132a and the third trench 132b may have a depth between 0.001 and 0.7 of the total gate height H. G In various embodiments, the patterned nitride layer 118 may be etched so that the second trench 134a and the fourth trench 134b have a depth between the width T of the first sidewall spacer 122A and the width T of the second sidewall spacer 122B. SW 0.001 to 0.7, such as between 0.10 and 0.5, such as between 0.2 and 0.4.

[0115] refer to Fig. 10A and Fig. 10BA contact etch stop layer 136 may be formed on the substrate 102, the first sidewall spacer 122A, the second sidewall spacer 122B, and the patterned gate layer 106. The contact etch stop layer 136 may be made of any suitable material, such as silicon oxide. The scope of the present disclosure may also include other suitable materials. The contact etch stop layer 136 may cover the upper portion of the first trench 132a, the second trench 134a, the third trench 132b, and the fourth trench 134b, and will not fill the first trench 132a, the second trench 134a, the third trench 132b, and the fourth trench 134b. In this way, the first air gap 138a and the third air gap 138b and the second air gap 140a and the fourth air gap 140b may be formed in the patterned nitride layer 118 of the first sidewall spacer 122A and the second sidewall spacer 122B. The first air gap 138a and the second air gap 140a may be referred to as a first pair of air gaps. The third air gap 138b and the fourth air gap 140b may be referred to as a second pair of air gaps.

[0116] The sizes of the first air gap 138a, the second air gap 140a, the third air gap 138b, and the fourth air gap 140b are controlled by the thickness of the patterned nitride layer 118 and the etching time for selectively etching the patterned nitride layer 118. Fig. 10B As shown, the thickness of the patterned nitride layer 118 determines the thickness of the first air gap 138a, the third air gap 138b and the depth of the second air gap 140a, the fourth air gap 140b, which will be discussed in more detail below. The thickness of the patterned first oxide layer 116 can be between to The thickness of the patterned nitride layer 118 may be between to The thickness of the patterned second oxide layer 120 may be between to Similarly, the etching time for selectively etching the patterned nitride layer 118 is determined by the depth of the first air gap 138a, the third air gap 138b and the thickness of the second air gap 140a, the fourth air gap 140b. Therefore, the size of the first air gap 138a, the second air gap 140a, the third air gap 138b and / or the fourth air gap 140b can be selected based on the configuration of the manufacturing device. It should be noted that if the thickness of the patterned nitride layer 118 is too large, when the contact etching stop layer 136 is deposited, the first air gap 138a and the third air gap 138b are reduced or eliminated, then the first air gap 138a and the third air gap 138b will be filled with the material of the contact etching stop layer 136. If the thickness and / or height of the first air gap 138a, the second air gap 140a, the third air gap 138b and / or the fourth air gap 140b are too small, the first air gap 138a, the second air gap 140a, the third air gap 138b and / or the fourth air gap 140b may not be able to effectively reduce parasitic and / or fringe capacitance.

[0117] Also refer to Figure 6 and Fig. 10B , the total height of the gate H G The first sidewall spacer 122A and the second sidewall spacer 122B have a total spacer width T of 104, 106, and 130. SW The thickness T of the patterned first oxide layer 116 is O1 , the thickness T of the patterned nitride layer 118 N and the maximum thickness T of the patterned second oxide layer 120 O2 , as mentioned above Figure 6 As described above, the first sidewall spacer 122A and the second sidewall spacer 122B may be formed so that the patterned first oxide layer 116 has a thickness between to Thickness (T O1 ), the patterned nitride layer 118 has a thickness between to Thickness (T N ), and the patterned second oxide layer 120 has a thickness between to Thickness (T O2 ).

[0118] As described above, replacing a higher dielectric material such as silicon oxide or silicon nitride with a lower dielectric material (such as air) between charged plates can reduce unintentional parasitic capacitance and fringing capacitance. If a portion of the higher dielectric material is replaced by a lower dielectric material in a layer, the dielectric constant (and capacitance) of the mixed material is determined by the weighted average of the amount of higher and lower dielectric materials. Therefore, by increasing the size of the air gap, parasitic and fringing capacitance can be reduced. In an embodiment, the height H of the first air gap 138a (or the third air gap 138b) is 1 / 40. A1 Between the total gate height H G 0.001 to 0.7 of the total gate height H G 0.10 to 0.5 of the total gate height H G The thickness T of the first air gap 138a (or the third air gap 138b) is between 0.2 and 0.4. A1 The thickness T of the first air gap 138a (or the third air gap 138b) may be equal to, less than, or greater than the thickness of the patterned Si3N4 layer 118 (patterned nitride layer 118). A1 Can be between to The height H of the second air gap 140a (or the fourth air gap 140b) is A2The height H of the second air gap 140a (or the fourth air gap 140b) may be equal to, less than, or greater than the thickness of the patterned Si3N4 layer 118 (patterned nitride layer 118). A2 Can be between to The thickness T of the second air gap 140a (or the fourth air gap 140b) is A2 The width T between the first sidewall spacer 122A and the second sidewall spacer 122B may be SW In one embodiment, the size of the first pair of air gaps may be different from the size of the second pair of air gaps. For example, in one embodiment, the volume of the first air gap 138a and the third air gap 138b may be 10% to 90% of the volume of the second air gap 140a and the fourth air gap 140b.

[0119] refer to Fig.11 , an intermediate dielectric layer 142 may be deposited on the contact etch stop layer 136. Next, a photoresist layer (not shown) may be deposited through the apertures (not shown) in the intermediate dielectric layer 142 and the etch stop layer 136 and patterned into a top form, and filled with a metal such as tungsten, copper, cobalt, molybdenum, ruthenium, other metal elements or alloys or combinations thereof. Other suitable materials are also included within the scope of the present disclosure. In this way, a contact may be formed through a source / drain electrode 144 coupled to the source region 127 and the drain region 129 to complete the integrated semiconductor device 100. The integrated semiconductor device 100 thus produced includes a transistor structure 131A, wherein the first sidewall spacer 122A and the second sidewall spacer 122B both have a pair of air gaps (a first air gap 138a, a second air gap 140a, a third air gap 138b and a fourth air gap 140b).

[0120] In some device configurations, adjacent MOSFET pairs share a common gate. In these configurations, it is not necessary to manufacture one or more first air gaps 138a, second air gaps 140a, third air gaps 138b, or fourth air gaps 140b. Further, in other device configurations, the spacing between adjacent MOSFETs may be asymmetric. That is, the spacing between the source side of adjacent MOSFETs may be different from the spacing between the drain side of adjacent MOSFETs. In these configurations, it is not necessary to manufacture one or more first air gaps 138a, second air gaps 140a, third air gaps 138b, or fourth air gaps 140b. In yet other configurations, the capacitance between the patterned gate layer 106 and the source / drain electrode 144 may be small enough to make the first air gap 138a and the third air gap 138b non-essential. In other configurations, the capacitance between the patterned gate layer 106 and the source / drain regions 127 , 129 may be small enough that the second air gap 140 a and the fourth air gap 140 b are unnecessary. Fig.12 , 13 15 to 23 illustrate various embodiments, in which different combinations of various air gaps, such as one or more first air gaps 138a, second air gaps 140a, third air gaps 138b or fourth air gaps 140b and methods form these embodiments.

[0121] Fig.12 Another embodiment of an integrated semiconductor device 200 is shown, wherein the first air gap 138a and the second air gap 140a may be formed only on the source region 127, or the third air gap 138b and the fourth air gap 140b may be formed on the drain region 129, and not on the source region 127 and the drain region 129 of the same transistor structure 131b. For example, Fig.12 It is shown that the first air gap 138a and the second air gap 140a are formed only on the source region 127, and no air gap is formed on the drain region 129. Alternatively, the first air gap 138a and the second air gap 140a are formed only on the drain region 129, and no air gap is formed on the source region 127.

[0122] In order to form Fig.12 The embodiment structure shown in the figure, the above method can be carried out according to Figure 8 Next, the photoresist layer 108 may be deposited on the entire surface and patterned so that only the source region 127 or the drain region 129 is exposed. In this way, the photoresist layer 108 protects the covered first sidewall spacer 122A and the second sidewall spacer 122B, while etching the exposed first sidewall spacer 122A and the second sidewall spacer 122B. The manufacturing process may be as follows: Fig. 9 That is, the first trench 132a and the second trench 134a may be formed in the exposed first sidewall spacer 122A. In another embodiment, the third trench 132b and the fourth trench 134b may be formed in the exposed second sidewall spacer 122B. Then, the photoresist layer 108 may be removed and an etch stop layer 136 may be deposited. Fig. 10A and 10B , to effectively form the first air gap 138a and the second air gap 140a or the third air gap 138b and the fourth air gap 140b. The integrated semiconductor device 200 thus formed includes a transistor structure 131B, wherein one of the first sidewall spacer 122A or the second sidewall spacer 122B has a pair of air gaps (the first air gap 138a, the second air gap 140a, the third air gap 138b and the fourth air gap 140b), and the other of the first sidewall spacer 122A or the second sidewall spacer 122B does not have an air gap.

[0123] Fig.13Another embodiment of the integrated semiconductor device 300 is shown. The integrated semiconductor device 300 includes a transistor structure 131A, wherein both the first sidewall spacer 122A and the second sidewall spacer 122B have a pair of air gaps (first air gap 138a, second air gap 140a, third air gap 138b, and fourth air gap 140b). A transistor structure 131B, wherein one of the first sidewall spacer 122A or the second sidewall spacer 122B has a pair of air gaps (first air gap 138a, second air gap 140a, third air gap 138b, and fourth air gap 140b), and the other of the first sidewall spacer 122A or the second sidewall spacer 122B does not have an air gap. A transistor structure 131C, wherein both the first sidewall spacer 122A and the second sidewall spacer 122B do not have a pair of air gaps.

[0124] In order to form Fig.13 The embodiment structure shown in the figure, the above method can be carried out according to Figure 8 Follow the steps shown. Fig.12 Similar to the embodiment shown, the photoresist layer 108 can be deposited on the entire surface and patterned. In this embodiment, the first portion of the MOSFET has the exposed first sidewall spacer 122A and the second sidewall spacer, the second portion of the MOSFET has only one of the exposed first sidewall spacer 122A or the second sidewall spacer 122B, and the third portion of the MOSFET has no exposed sidewall spacer. The manufacturing process can be as follows Fig. 9 That is, the first trench 132a, the second trench 134a, the third trench 132b and the fourth trench 134b may be formed in the first sidewall spacer 122A and the second sidewall spacer 122B exposed in the first portion. In addition, the first trench 132a and the second trench 134a in the second portion may be formed in the first sidewall spacer 122A (or the third trench 132b and the fourth trench 134b may be formed in the second sidewall spacer 122B). Next, the photoresist layer 108 is removed and the etching stop layer 136 is deposited as shown. Fig. 10A and 10B shown.

[0125] refer to Fig.14, a flow chart of a general method 400 for fabricating semiconductor devices 100 , 200 , and 300 having a first air gap 138 a , a second air gap 140 a , a third air gap 138 b , and a fourth air gap 140 b according to some embodiments is shown. Referring to step 402, a transistor structure 131 may be formed including a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located on the channel region 113, a metal or polysilicon gate layer 106 located on the gate dielectric layer 104, a first sidewall spacer 122A adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and located on one of the source region 127 or the drain region 129, and a second sidewall spacer 122B adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and located on the other of the source region 127 or the drain region 129.

[0126] Referring to step 404, the nitride layer 118 of the first sidewall spacer 122A is selectively etched relative to the first oxide layer 116 and the second oxide layer 120 to form a first trench 132a and a second trench 134a in the first sidewall spacer 122A. The first trench 132a and the second trench 134a include a first trench 132a adjacent to the metal or polysilicon gate layer 106 and a second trench 134a located above the source region 127 or the drain region 129. The depth of the first trench 132a and the second trench 134a is controlled based on the etching time. The actual etching time for the required depth is determined by the etching solution used and the required depth of the trench. For example, when etching with phosphoric acid, the etching rate can be reduced by increasing the amount of water in the acid. However, the etching rate can be increased by increasing the temperature. Further, as described above, in order to make the following Fig.12 and 13 In the illustrated embodiment, one or all of the first sidewall spacers 122A or the second sidewall spacers 122B in a portion of the MOSFET may be protected by the photoresist layer 108, and the exposed spacers are etched to form the first trench 132a, the second trench 134a, the third trench 132b, and the fourth trench 134b.

[0127] Referring to step 406, an etch stop layer 136 may be deposited on the first sidewall spacer 122A to form a first air gap 138a adjacent to the metal or polysilicon gate layer 106 and a second air gap 140a located above the source region 127 or the drain region 129. The first air gap 138a has a major axis parallel to the metal or polysilicon gate layer 106, and the second air gap 140a has a major axis parallel to the major surface of the substrate 102.

[0128] Generally, the structures and methods disclosed herein can be used to form metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices, wherein at least some of the MOSFETs have air gaps in at least one of the sidewall spacers of the MOSFET. The air gaps can reduce the junction, overlap and / or edge capacitance of the MOSFET made of high dielectric materials by reducing the dielectric constant of the first sidewall spacer 122A and the second sidewall spacer 122B. And, thereby increasing the switching speed and / or improving the short channel performance affected by the dielectric of the capacitor. In some embodiments, the air gap is formed between the sidewall spacers of the MOSFET. In other embodiments, the first portion of the MOSFET has an air gap formed in the sidewall spacers of the MOSFET, while the second portion of the MOSFET has an air gap in only one sidewall spacer. In other embodiments, the first portion of the MOSFET has an air gap formed in the sidewall spacers of the MOSFET, while the second portion of the MOSFET has an air gap in only one sidewall spacer, and the third portion of the MOSFET does not have an air gap in the sidewall spacer.

[0129] One embodiment is about a MOSFET located on a substrate 102, including a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located on the channel region 113, a gate layer 106 located on the gate dielectric layer 104, a first sidewall spacer 122A adjacent to the gate dielectric layer 104 and the gate layer 106 and located on one of the source region 127 or the drain region 129, and a second sidewall spacer 122B adjacent to the gate dielectric layer 104 and the gate layer 106 and located on the other of the source region 127 or the drain region 129. Furthermore, the first air gap 138a and the second air gap 140a located in the first sidewall spacer 122A include the first air gap 138a adjacent to the patterned gate layer 106 and the second air gap 140a located above the source region 127 or the drain region 129, wherein the first air gap 138a has a main axis parallel to the gate layer 106, and the second air gap 140a has a main axis parallel to the main surface of the substrate 102.

[0130] Fig.15A Another embodiment of the integrated semiconductor device 500 is shown, wherein the second air gap 140a and the fourth air gap 140b can be formed in the first sidewall spacer 122A and the second sidewall spacer 122B and are located above the source extension region 110 and the drain extension region 112, but not adjacent to the gate layer 106. In the first embodiment of the method, the integrated semiconductor device 500 is fabricated by depositing a "thick" continuous nitride layer 118L. When the thickness T of the patterned nitride layer 118 is NAbove the threshold thickness, the first trench 132a and the third trench 132b formed therein may also have a thickness above the threshold thickness. As a result, when the contact etch stop layer 136 is formed on the first sidewall spacer 122A and the second sidewall spacer 122B, the first trench 132a and the third trench 132b are filled with the material of the contact etch stop layer 136. Therefore, in some embodiments, the first air gap 138a and the third air gap 138b may not be formed in the first sidewall spacer 122A and the second sidewall spacer 122B. However, in such an embodiment, the second trench 134a and the fourth trench 134b may not be filled because the second trench 134a and the fourth trench 134b are horizontally oriented. In such an embodiment, the transistor structure 131 may be formed in the first sidewall spacer 122A and the second sidewall spacer 122B and located above the source extension region 110 and the drain extension region 112. The integrated semiconductor device 500 thus formed includes a transistor structure 131D, wherein the first sidewall spacer 122A and the second sidewall spacer 122B both have an air gap (a second air gap 140 a and a fourth air gap 140 b ) above the source extension region 110 and the drain extension region 112 .

[0131] In the second embodiment, Fig. 15B and 15C A method of manufacturing an integrated semiconductor device 500 is shown. Fig. 15B In the method for manufacturing the integrated semiconductor device 500 in the second embodiment, the photoresist layer 108 may be as follows Figure 8 The photoresist layer 108 may then be patterned to expose the patterned silicon nitride layer 118 at the horizontal end.

[0132] refer to Fig. 15C , the selective etching of the silicon nitride layer is then Fig. 9 After the second trench 134a and the fourth trench 134b in the first sidewall spacer 122A and the second sidewall spacer 122B reach the desired thickness, as shown in FIG. Fig. 10A and 10B As shown and described above, the photoresist layer 108 may be removed and a contact etch stop layer 136 may be deposited. Fig.11 As shown and described above, an interlayer dielectric layer 142 is deposited and source / drain electrodes 144 are fabricated.

[0133] Figures 16 to 20 FIG. 6 is a diagram showing the steps of another method for manufacturing an integrated semiconductor device 600 according to an embodiment. Fig.16 The photoresist layer 108 may be Figure 8 Deposited on the structure as shown and described above. Fig.17, the photoresist layer 108 may be patterned to expose the first sidewall spacer 122A and the second sidewall spacer 122B. As shown in the figure, the upper surface of the silicide layer 130 of the patterned gate layer 106 is also exposed. Fig. 9 As shown and described above, the selective etching for selectively etching the patterned silicon nitride layer 118 does not significantly etch the silicide layer 130. In another embodiment of the method, when patterning the photoresist layer 108, only the first sidewall spacer 122A and the second sidewall spacer 122B are exposed.

[0134] refer to Fig.18 The patterned silicon nitride layer 118 adjacent to the patterned gate dielectric layer 104 and the patterned gate layer 106 can be selectively etched to form the first trench 132a and the third trench 132b. However, portions of the patterned silicon nitride layer 118 located above the source extension region 110 and the drain extension region 112 will not be etched because they are protected by the photoresist layer 108.

[0135] refer to Fig.19 , the photoresist layer 108 may be removed by any suitable method, such as ashing. Next, a contact etch stop layer 136 may be formed on the surface of the substrate 102, the first sidewall spacer 122A, the second sidewall spacer 122B, and the patterned gate layer 106. As described above, the contact etch stop layer 136 may be made of any suitable material. The contact etch stop layer 136 may cover the upper portion of the first trench 132a and the third trench 132b. In this way, the first air gap 138a and the third air gap 138b may be formed in the patterned nitride layer 118 of the first sidewall spacer 122A and the second sidewall spacer 122B, and the second air gap 140a and the fourth air gap 140b will not be formed on the source extension region 110 and the drain extension region 112.

[0136] refer to Fig. 20, the intermediate dielectric layer 142 may be deposited on the contact etch stop layer 136. Next, a photoresist layer (not shown) may be deposited through the intermediate dielectric layer 142 and the pores (not shown) in the etch stop layer 136 and patterned into a top form, and filled with a metal such as tungsten, copper, cobalt, molybdenum, ruthenium, other metal elements or alloys or combinations thereof. Other suitable materials are also included in the scope of the present disclosure. In this way, a contact may be formed through the source / drain electrode 144 coupled to the source region 127 and the drain region 129 to complete the integrated semiconductor device 600. The integrated semiconductor device 600 thus produced includes a transistor structure 131E, which includes a first air gap 138a and a third air gap 138b located in the patterned nitride layer 118 of the first sidewall spacer 122A and the second sidewall spacer 122B, and the second air gap 140a and the fourth air gap 140b are not formed on the source extension region 110 and the drain extension region 112.

[0137] Fig.21 The integrated semiconductor device 700 according to some embodiments, wherein the first transistor structure 131F has a single air gap 138a located in the patterned nitride layer 118 in one of the first sidewall spacer 122A or the second sidewall spacer 122B adjacent to the patterned gate dielectric layer 104 and the patterned gate layer 106. The second transistor structure 131G has a single air gap 140b located in the patterned nitride layer 118 in one of the first sidewall spacer 122A or the second sidewall spacer 122B above the source extension region 110 and the drain extension region 112. In another embodiment (not shown), all transistor structures have a single air gap 138a in the patterned nitride layer 118 in one of the first sidewall spacer 122A or the second sidewall spacer 122B adjacent to the patterned gate dielectric layer 104 and the patterned gate layer 106. In yet another embodiment (not shown), all transistor structures have a single air gap 140 b in the patterned nitride layer 118 in one of the first sidewall spacer 122A or the second sidewall spacer 122B over the source extension region 110 and the drain extension region 112 .

[0138] Fig. 22Another embodiment of the integrated semiconductor device 800 is shown. In this embodiment, the first transistor structure 131H may have a first sidewall spacer 122A with a pair of air gaps 138a, 140a, and a second sidewall spacer 122B, and only a single sidewall spacer 140b is provided above the source extension region 110 and the drain extension region 112. The second transistor structure 131I may have a first sidewall spacer 122A with a pair of air gaps 138a, 140a, and a second sidewall spacer 122B, and only a single sidewall spacer 138b is provided adjacent to the patterned gate dielectric layer 104 and the patterned gate layer 106. In another embodiment (not shown), the entire transistor structure has a pair of air gaps 138a, 140a or 138b, 140b in one of the first sidewall spacer 122A or the second sidewall spacer 122B, and has one air gap 138a, 140a, 138b or 140b in the other of the first sidewall spacer 122A or the second sidewall spacer 122B.

[0139] refer to Fig.23 , a flow chart of a general method 900 for fabricating integrated semiconductor devices 600, 700, and 800 according to some embodiments is shown, wherein at least one of the second air gap 140a or the fourth air gap 140b is missing from a portion of the transistor structure. Referring to step 902, a transistor structure 131 may be formed on a substrate 102, including a source region 127, a drain region 129, a channel region 113 between the source region 127 and the drain region 129, a gate dielectric layer 104 located above the channel region 113, a metal or polysilicon gate layer 106 located above the gate dielectric layer 104, a first sidewall spacer 122A adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and located above one of the source region 127 or the drain region 129, and a second sidewall spacer 122B adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and located above the other of the source region 127 or the drain region 129.

[0140] Referring to step 904 , the exposed portion of the transistor structure 131 and the substrate 102 may be covered by the photoresist layer 108 to protect a portion of the first sidewall spacer 122A or the second sidewall spacer 122B located above the source region 127 or the drain region 129 .

[0141] Referring to step 906, the nitride layer 118 of the first sidewall spacer 122A may be selectively etched relative to the first oxide layer 116 and the second oxide layer 120 to form a first trench 132a in the first sidewall spacer 122A. The first trench 132a may be adjacent to the metal or polysilicon gate layer 106. The depth of the first trench 132a may be controlled according to the etching time. That is, the longer the etching, the deeper the trench. Further, as described above, in order to form the first trench 132a, Figures 19 to 22 In the illustrated embodiment, one or both of the first sidewall spacer 122A or the second sidewall spacer 122B of the transistor structure are protected by the photoresist layer 108, and the exposed spacers are etched to form the first trench 132a, the second trench 134a, the third trench 132b and the fourth trench 134b.

[0142] Referring to step 908 , an etch stop layer 136 is deposited on the first sidewall spacer 122A to be formed adjacent to the metal or polysilicon controlled gate layer 106 , wherein the first sidewall spacer 122A has a major axis parallel to the metal or polysilicon controlled gate layer 106 .

[0143] According to one embodiment, a metal oxide semiconductor field effect transistor (MOSFET) device 131 is located on a substrate 102. The MOSFET device 131 includes a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located on the channel region 113, a gate layer 106 located on the gate dielectric layer 104, a first sidewall spacer 122A adjacent to the gate dielectric layer 104 and the gate layer 106 and located on one of the source region 127 or the drain region 129, and a second sidewall spacer 122B adjacent to the gate dielectric layer 104 and the gate layer 106 and located on the other of the source region 127 or the drain region 129. The MOSFET device 131 includes a first pair of air gaps, including a first air gap 138a and a second air gap 140a, located in the first sidewall spacer 122A, wherein the first air gap 138a is adjacent to the gate layer 106, and the second air gap 140a is located above the source region 127 or the drain region 129, wherein the first air gap 138a has a main axis parallel to the gate layer 106, and the second air gap 140a has a main axis parallel to the main surface of the substrate 102.

[0144] According to one embodiment, an integrated circuit 100, 200, and 300 having a MOSFET device on a substrate 102 includes a plurality of MOSFET devices 131, wherein at least one of the MOSFET devices 131 includes a first sidewall spacer 122A and a second sidewall spacer 122B having a first air gap 138a, a second air gap 140a, a third air gap 138b, and a fourth air gap 140b.

[0145] According to one embodiment, a method 400 for fabricating a MOSFET on a substrate 102 includes forming a MOSFET device 131, including a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located on the channel region 113, a metal or polysilicon gate layer 106 located on the gate dielectric layer 104, a first sidewall spacer 122A adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and located on one of the source region 127 or the drain region 129, and a second sidewall spacer 122B adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and located on the other of the source region 127 or the drain region 129. The method 400 also includes etching the first sidewall spacer 122A to form a first trench 132a in the first sidewall spacer 122A adjacent to the metal or polysilicon gate layer 106 and a second trench 134a located above the source region 127 (or a third trench 132b adjacent to the metal or polysilicon gate layer 106 and a fourth trench 134b located above the drain region 129). An etch stop layer 136 is deposited on the first sidewall spacer 122A to form a first air gap 138a and a second air gap 140a, wherein the first air gap 138a is adjacent to the metal or polysilicon gate layer 106, and the second air gap 140a is located above the source region 127 (or the third air gap 138b is adjacent to the metal or polysilicon gate layer 106, and the fourth air gap 140b is located above the drain region 129), wherein the first air gap 138a has a main axis parallel to the metal or polysilicon gate layer 106, and the second air gap 140a has a main axis parallel to the main surface of the substrate 102.

[0146] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same benefits as the embodiments introduced in the present disclosure. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0147] According to an aspect of the present disclosure, a metal oxide semiconductor field effect transistor (MOSFET) device is located on a substrate, including a source region, a drain region, and a channel region located between the source region and the drain region. A gate dielectric layer is located above the channel region. A gate layer is located above the gate dielectric layer. A first sidewall spacer is adjacent to the gate dielectric layer and the gate layer and is located above the source region or the drain region. A second sidewall spacer is adjacent to the gate dielectric layer and the gate layer and is located above the other of the source region or the drain region. A first pair of air gaps, including a first air gap and a second air gap, are located in the first sidewall spacer, wherein the first air gap is adjacent to the gate layer and the second air gap is located above the source region or the drain region, wherein the first air gap has a major axis parallel to the gate layer, and the second air gap has a major axis parallel to the major surface of the substrate. In one or more of the above and following embodiments, the metal oxide semiconductor field effect transistor further comprises a second pair of air gaps, the second pair of air gaps comprising a third air gap and a fourth air gap, located in the second sidewall spacer, wherein the third air gap is adjacent to the gate layer, and the fourth air gap is located above the source region or the drain region, wherein the third air gap has a major axis parallel to the gate layer, and the fourth air gap has a major axis parallel to the major surface of the substrate. In one or more of the above and following embodiments, in the metal oxide semiconductor field effect transistor, the first pair of air gaps comprises a size different from that of the second pair of air gaps. In one or more of the above and following embodiments, in the metal oxide semiconductor field effect transistor, the height of the first air gap is between 0.001-0.7 of the height of the gate layer and the gate dielectric layer. In one or more of the above and following embodiments, in the metal oxide semiconductor field effect transistor, the first sidewall spacer and the second sidewall spacer comprise a sandwich structure, the sandwich structure comprising a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer. In one or more of the above and following embodiments, in the MOSFET, the second oxide layer comprises a material different from the first oxide layer. In one or more of the above and following embodiments, in the MOSFET, the first air gap and the second air gap are located in the nitride layer.

[0148] According to another aspect of the present disclosure, an integrated circuit having a metal oxide semiconductor field effect transistor device is located on a substrate and includes a plurality of metal oxide semiconductor field effect transistor devices. At least one of the metal oxide semiconductor field effect transistor devices includes a plurality of sidewall spacers having a plurality of air gaps. In one or more of the above and following embodiments, in the integrated circuit, the plurality of metal oxide semiconductor field effect transistor devices include a first metal oxide semiconductor field effect transistor device and a second metal oxide semiconductor field effect transistor device. The first metal oxide semiconductor field effect transistor device includes a first sidewall spacer and a second sidewall spacer, wherein the first sidewall spacer and the second sidewall spacer both include a second air gap and a fourth air gap located above a source region and a drain region of the first metal oxide semiconductor field effect transistor device. The second metal oxide semiconductor field effect transistor device includes a first sidewall spacer, including a second air gap and a fourth air gap located above a source region or a drain region of the second metal oxide semiconductor field effect transistor device. In one or more of the above and following embodiments, in an integrated circuit, a first sidewall spacer of a first metal oxide semiconductor field effect transistor device and a second sidewall spacer of the first metal oxide semiconductor field effect transistor device include a first air gap and a third air gap. The first air gap and the third air gap are adjacent to a gate layer of the first metal oxide semiconductor field effect transistor device, and the first sidewall spacer of the second metal oxide semiconductor field effect transistor includes the first air gap or the third air gap, and the first air gap or the third air gap is adjacent to the gate layer of the second metal oxide semiconductor field effect transistor device. In one or more of the above and following embodiments, the integrated circuit further includes a dynamic random access memory (DRAM) or a static random access memory (SRAM). In one or more of the above and following embodiments, in an integrated circuit, the plurality of metal oxide semiconductor field effect transistor devices include a first metal oxide semiconductor field effect transistor device and a second metal oxide semiconductor field effect transistor device. The first metal oxide semiconductor field effect transistor device includes a first sidewall spacer, including a second air gap located above a source region of the first metal oxide semiconductor field effect transistor device. The second MOSFET device includes a first sidewall spacer including a fourth air gap located above a drain region of the second MOSFET device.

[0149] According to one aspect of the present disclosure, a method for manufacturing a metal oxide semiconductor field effect transistor on a substrate includes forming a metal oxide semiconductor field effect transistor device including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located on the channel region, a metal or polysilicon gate layer located on the gate dielectric layer, a first sidewall spacer adjacent to the gate dielectric layer and the metal or polysilicon gate layer and located on one of the source region or the drain region, and a second sidewall spacer adjacent to the gate dielectric layer and the metal or polysilicon gate layer and located on the other of the source region or the drain region. Etching the first sidewall spacer to form a first pair of trenches in the first sidewall spacer, the first pair of trenches including a first trench adjacent to the metal or polysilicon gate layer and a second trench located on the source region or the drain region. Depositing an etch stop layer on the first sidewall spacer to form a first air gap and a second air gap, the first air gap adjacent to the metal or polysilicon gate layer, and the second air gap located on the source region or the drain region. Wherein the first air gap has a main axis parallel to the metal or polysilicon gate layer, and the second air gap has a main axis parallel to the main surface of the substrate. In one or more of the above and following embodiments, the method further includes etching the second sidewall spacer in the second sidewall spacer to form a second pair of grooves. The second pair of grooves includes a third groove and a fourth groove, the third groove is adjacent to the metal or polysilicon gate layer and the gate dielectric layer, and the fourth groove is located above the source region or the drain region. An etch stop layer is deposited on the second sidewall spacer to form a third air gap and a fourth air gap, the third air gap is adjacent to the metal or polysilicon gate layer, and the fourth air gap is located above the source region or the drain region. Wherein the third air gap has a main axis parallel to the metal or polysilicon gate layer, and the fourth air gap has a main axis parallel to the main surface of the substrate. In one or more of the above and following embodiments, in the method, the first sidewall and the second sidewall are single-step etched, and the etch stop layer is deposited on the first sidewall and the second sidewall in a single step. In one or more of the above and following embodiments, in the method, the first sidewall spacer and the second sidewall spacer are formed by depositing a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. In one or more of the above and following embodiments, in the method, the first pair of trenches are formed by selectively etching the nitride layer relative to the first oxide layer and the second oxide layer. In one or more of the above and following embodiments, in the method, the selective etching includes wet etching and dry etching. In one or more of the above and following embodiments, in the method, the formation of the source region and the drain region includes performing a first ion implantation with a metal or polysilicon gate layer and a gate dielectric layer as a mask to form a source extension region and a drain extension region. Performing a second ion implantation with the first sidewall spacer and the second sidewall spacer as a mask to form a deep source region and a deep drain region.In one or more of the above and following embodiments, the method further comprises depositing metal on the deep source region, the deep drain region and the metal or polysilicon gate layer when the metal or polysilicon gate layer comprises polysilicon, and heating to form a metal silicide layer on the deep source region, the deep drain region and the polysilicon gate layer.

Claims

1. A metal oxide semiconductor field effect transistor device, located on a substrate, characterized in that: include: a source region; a drain region; a channel region located between the source region and the drain region; a gate dielectric layer located above the channel region; a gate layer, located on the gate dielectric layer; a first sidewall spacer, adjacent to the gate dielectric layer and the gate layer, and located on the source region or the drain region, wherein the first sidewall spacer comprises a first oxide layer contacting the sidewall of the gate layer and a nitride layer on the first oxide layer, the first oxide layer and the nitride layer exposing a portion of the source region or the drain region; a second sidewall spacer adjacent to the gate dielectric layer and the gate layer and located above the other of the source region or the drain region; a first pair of air gaps, including a first air gap and a second air gap, located in the first sidewall spacer, wherein the first air gap is adjacent to the gate layer and the second air gap is located above the source region or the drain region, wherein the first air gap has a major axis parallel to the gate layer and the second air gap has a major axis parallel to a major surface of the substrate; and An etch stop layer is on the first sidewall spacer and defines one end of the first air gap and one end of the second air gap, wherein the first air gap and the second air gap are formed in the nitride layer and are not filled by the etch stop layer.

2. The MOSFET device according to claim 1, wherein: Also included is a second pair of air gaps, the second pair of air gaps including a third air gap and a fourth air gap, located in the second sidewall spacer, wherein the third air gap is adjacent to the gate layer, and the fourth air gap is located above the source region or the drain region, wherein the third air gap has a major axis parallel to the gate layer, and the fourth air gap has a major axis parallel to the major surface of the substrate.

3. The MOSFET device according to claim 2, wherein: The first pair of air gaps comprises a different size than the second pair of air gaps.

4. The MOSFET device according to claim 1, wherein: The height of the first air gap is between 0.001 and 0.7 of the height of the gate layer and the gate dielectric layer.

5. The MOSFET device according to claim 1, wherein: The first sidewall spacer includes a second oxide layer, and the nitride layer is located between the first oxide layer and the second oxide layer.

6. The MOSFET device according to claim 5, wherein: The second oxide layer includes a material different from that of the first oxide layer.

7. An integrated circuit having a metal oxide semiconductor field effect transistor device, located on a substrate, characterized in that: include: A plurality of metal oxide semiconductor field effect transistor devices, wherein a first metal oxide semiconductor field effect transistor device among the plurality of metal oxide semiconductor field effect transistor devices comprises: a source region; a drain region; a channel region located between the source region and the drain region; a gate dielectric layer located above the channel region; a gate layer, located on the gate dielectric layer; a first sidewall spacer, adjacent to the gate dielectric layer and the gate layer, and located on the source region or the drain region, wherein the first sidewall spacer comprises a first oxide layer contacting the sidewall of the gate layer and a nitride layer on the first oxide layer, the first oxide layer and the nitride layer exposing a portion of the source region or the drain region; a second sidewall spacer adjacent to the gate dielectric layer and the gate layer and located above the other of the source region or the drain region; a first pair of air gaps, including a first air gap and a second air gap, located in the first sidewall spacer, wherein the first air gap is adjacent to the gate layer and the second air gap is located above the source region or the drain region, wherein the first air gap has a major axis parallel to the gate layer and the second air gap has a major axis parallel to a major surface of the substrate; and An etch stop layer is on the first sidewall spacer and defines one end of the first air gap and one end of the second air gap, wherein the first air gap and the second air gap are formed in the nitride layer and are not filled by the etch stop layer.

8. The integrated circuit according to claim 7, characterized in that A second metal oxide semiconductor field effect transistor device among the plurality of metal oxide semiconductor field effect transistor devices comprises: A first sidewall spacer includes a second air gap and a fourth air gap located above the source region or the drain region of the second MOSFET device.

9. The integrated circuit according to claim 8, characterized in that The first sidewall spacer of the second MOSFET in the first MOSFET device includes a first air gap or a third air gap, and the first air gap or the third air gap is adjacent to a gate layer of the second MOSFET device.

10. The integrated circuit according to claim 9, characterized in that The integrated circuit includes a dynamic random access memory or a static random access memory.

11. The integrated circuit according to claim 7, characterized in that: A second metal oxide semiconductor field effect transistor device among the plurality of metal oxide semiconductor field effect transistor devices comprises: A first sidewall spacer includes a fourth air gap located above a drain region of the second MOSFET device.

12. A method for manufacturing a metal oxide semiconductor field effect transistor device on a substrate, characterized in that: include: forming a metal oxide semiconductor field effect transistor device including a source region, a drain region, a channel region between the source region and the drain region, a gate dielectric layer on the channel region, a metal or polysilicon gate layer on the gate dielectric layer, a first sidewall spacer adjacent to the gate dielectric layer and the metal or polysilicon gate layer and located on one of the source region or the drain region, and a second sidewall spacer adjacent to the gate dielectric layer and the metal or polysilicon gate layer and located on the other of the source region or the drain region, wherein forming the first sidewall spacer comprises depositing a first oxide layer contacting a sidewall of the metal or polysilicon gate layer; depositing a nitride layer on the first oxide layer; and patterning the first oxide layer and the nitride layer to expose a portion of the source region or the drain region; Etching the nitride layer of the first sidewall spacer to form a first pair of trenches in the first sidewall spacer, the first pair of trenches including a first trench adjacent to the metal or polysilicon gate layer and a second trench located on the source region or the drain region; as well as An etch stop layer is deposited on the first sidewall spacer to form a first air gap and a second air gap in the etched nitride layer that are not filled by the etch stop layer, the first air gap being adjacent to the metal or polysilicon gate layer, and the second air gap being located above the source region or the drain region, wherein the first air gap has a major axis parallel to the metal or polysilicon gate layer, and the second air gap has a major axis parallel to a major surface of the substrate.

13. The method according to claim 12, characterized in that Also includes: Etching the second sidewall spacer to form a second pair of trenches in the second sidewall spacer, the second pair of trenches comprising a third trench and a fourth trench, the third trench being adjacent to the metal or polysilicon gate layer and the gate dielectric layer, the fourth trench being located above the source region or the drain region; and The etch stop layer is deposited on the second sidewall spacer to form a third air gap and a fourth air gap, the third air gap is adjacent to the metal or polysilicon gate layer, and the fourth air gap is located above the source region or the drain region, wherein the third air gap has a major axis parallel to the metal or polysilicon gate layer, and the fourth air gap has a major axis parallel to the major surface of the substrate.

14. The method according to claim 13, characterized in that The first sidewall spacer and the second sidewall spacer are etched in a single step, and the etching stop layer is deposited on the first sidewall spacer and the second sidewall spacer in a single step.

15. The method according to claim 12, characterized in that The second sidewall spacer is formed by depositing a first oxide layer, a nitride layer on the first oxide layer and a second oxide layer on the nitride layer.

16. The method according to claim 12, characterized in that The etching of the nitride layer of the first sidewall spacer includes wet etching and dry etching.

17. The method according to claim 12, characterized in that The formation of the source region and the drain region includes: Performing a first ion implantation by using the metal or polysilicon gate layer and the gate dielectric layer as masks to form a source extension region and a drain extension region; and A second ion implantation is performed by using the first sidewall spacer and the second sidewall spacer as masks to form a deep source region and a deep drain region.

18. The method according to claim 17, characterized in that Also includes: When the metal or polysilicon gate layer comprises polysilicon, depositing a metal on the deep source region, the deep drain region and the metal or polysilicon gate layer; as well as Heating is performed to form a metal silicide layer on the deep source region, the deep drain region and the polysilicon gate layer.

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