Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device, wherein the display substrate includes a plurality of display units, the display units include a display area and a transparent area, at least one display area includes a plurality of sub-pixels; the display area is provided with a first power line, a compensation signal line, and a second power line along a first direction, the compensation signal line is provided between the first power line and the second power line, at least one display area is provided with a compensation connection line in the middle along a second direction, and the compensation connection line and the compensation signal line are interconnected; the transparent area includes a plurality of auxiliary cathodes and a plurality of auxiliary connection electrodes, the auxiliary cathodes are interconnected with the second power line, the plurality of auxiliary connection electrodes are symmetrically arranged relative to the compensation connection line, a part of the auxiliary connection electrodes are connected with the second power line, and another part of the auxiliary connection electrodes are connected with the auxiliary cathode. The present disclosure increases the overlap success rate of the auxiliary connection electrodes, can effectively alleviate the voltage drop of a large-size transparent display, and ensures display uniformity.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of light emission, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, and extremely high response speed. According to the different driving methods, OLED can be divided into two types: passive matrix drive (PM) type and active matrix drive (AM) type. AMOLED is a current-driven device that uses an independent thin film transistor (TFT) to control each sub-pixel. Each sub-pixel can be driven to emit light continuously and independently.

[0003] With the continuous development of display technology, OLED technology is increasingly used in transparent displays. Transparent display is an important personalized display field of display technology. It refers to the display of images in a transparent state. Viewers can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR) and augmented reality (AR) and 3D display functions. Transparent display devices using AMOLED technology usually divide each pixel into a display area and a transparent area. The display area is equipped with a pixel driving circuit and a light-emitting element to realize image display, and the transparent area realizes light transmission. Summary of the invention

[0004] The embodiments of the present disclosure provide a display substrate and a method for preparing the same, and a display device, which can improve the display effect.

[0005] An embodiment of the present disclosure provides a display substrate, comprising a plurality of display units, at least one of the display units comprising a display area and a transparent area, at least one of the display areas comprising a plurality of sub-pixels; at least one of the display areas is provided with a first power line, a compensation signal line, and a second power line along a first direction, the first power line, the compensation signal line, and the second power line extend along a second direction, the compensation signal line is provided between the first power line and the second power line, at least one of the display areas is provided with a compensation connection line in the middle along the second direction, the compensation connection line extends along the first direction, the compensation connection line is connected to the compensation signal line, and the first direction intersects with the second direction; at least one of the transparent areas comprises a plurality of auxiliary cathodes and a plurality of auxiliary connection electrodes, the auxiliary cathodes are connected to the second power line, and the plurality of auxiliary connection electrodes are symmetrically arranged relative to the compensation connection line, wherein a portion of the auxiliary connection electrodes are connected to the second power line, and another portion of the auxiliary connection electrodes are connected to the auxiliary cathode.

[0006] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and in the first direction, the first sub-pixel and the second sub-pixel are alternately arranged to form a first row, and the third sub-pixel and the fourth sub-pixel are alternately arranged to form a second row; in the second direction, the first sub-pixel and the third sub-pixel are alternately arranged to form a first column, and the second sub-pixel and the fourth sub-pixel are alternately arranged to form a second column.

[0007] In an exemplary embodiment, in a direction perpendicular to the display substrate, the sub-pixel includes a substrate, a driving circuit layer disposed on the substrate, and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer;

[0008] The first conductive layer includes the compensation signal line, the compensation connection line and the first electrode plate, the semiconductor layer includes an active layer of multiple transistors, the second conductive layer includes a first scanning signal line, a second scanning signal line, a second electrode plate and gate electrodes of multiple transistors, the third conductive layer includes the auxiliary cathode, the first power line, the second power line, a data signal line and source electrodes and drain electrodes of multiple transistors, and an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate to form a first storage capacitor;

[0009] The light emitting structure layer includes an anode, and the auxiliary connection electrode is arranged in the same layer as the anode.

[0010] In an exemplary embodiment, the second conductive layer further includes a first scan connection line and a second scan connection line, and the third conductive layer further includes a third scan connection line, wherein:

[0011] The first scanning connection line and the second scanning connection line are located in the first sub-pixel and the second sub-pixel, the first scanning signal line and the second scanning signal line are located in the third sub-pixel and the fourth sub-pixel, and the second scanning connection line and the second scanning signal line are connected to each other to form an integrated structure;

[0012] The third scan connection line is connected to the first scan connection line and the first scan signal line through via holes.

[0013] In an exemplary embodiment, the second conductive layer further comprises a transverse power connection line and a longitudinal power connection line, wherein:

[0014] The longitudinal power connection line extends along the second direction, the orthographic projection of the longitudinal power connection line on the substrate is located within the range of the orthographic projection of the first power line on the substrate, and the first power line is connected to the longitudinal power connection line through a via hole to form a double-layer first power line;

[0015] The transverse power connection line extends along the first direction, and the first power line is connected to the transverse power connection line through a via.

[0016] In an exemplary embodiment, the second conductive layer further includes an auxiliary power line, which extends along the second direction. The orthographic projection of the auxiliary power line on the substrate is within the range of the orthographic projection of the second power line on the substrate. The second power line is connected to the auxiliary power line through a via to form a double-layer second power line.

[0017] In an exemplary embodiment, the third conductive layer further includes a third electrode plate, an orthographic projection of the third electrode plate on the substrate overlaps with an orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via.

[0018] In an exemplary embodiment, the driving circuit layer includes a first transistor, a second transistor and a third transistor, the gate electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the first electrode of an organic electroluminescent diode, the gate electrode of the third transistor is connected to the second scanning signal line, the first electrode of the third transistor is connected to the compensation line through a compensation connection line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line; the first electrode plate is connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.

[0019] In an exemplary embodiment, the auxiliary connecting electrode includes a first connecting electrode, a second connecting electrode located on a side of the first connecting electrode away from the substrate, and a third connecting electrode located on a side of the second connecting electrode away from the substrate, the anode includes a first anode, a second anode located on a side of the first anode away from the substrate, and a third anode located on a side of the second anode away from the substrate, the first anode is arranged on the same layer as the first connecting electrode, the second anode is arranged on the same layer as the second connecting electrode, the third anode is arranged on the same layer as the third connecting electrode, the first anode, the second anode and the third anode form an "I"-shaped structure, and the first connecting electrode, the second connecting electrode and the third connecting electrode form an "I"-shaped structure.

[0020] An embodiment of the present disclosure further provides a display device, comprising: the display substrate as described above.

[0021] The embodiment of the present disclosure also provides a method for preparing a display substrate, comprising: forming a plurality of display units on a substrate, at least one of the display units comprising a display area and a transparent area, at least one of the display areas being provided with a first power line, a compensation signal line, and a second power line along a first direction, the first power line, the compensation signal line, and the second power line extending along a second direction, the compensation signal line being provided between the first power line and the second power line, at least one of the display areas being provided with a compensation connection line in the middle along the second direction, the compensation connection line extending along the first direction, the compensation connection line and the compensation signal line being connected to each other, and the first direction intersecting with the second direction; at least one of the transparent areas comprising a plurality of auxiliary cathodes and a plurality of auxiliary connection electrodes, the auxiliary cathodes being connected to each other with the second power line, the plurality of auxiliary connection electrodes being symmetrically provided with respect to the compensation connection line, wherein a portion of the auxiliary connection electrodes are connected to the second power line, and another portion of the auxiliary connection electrodes are connected to the auxiliary cathode.

[0022] The display substrate and its preparation method and display device of the disclosed embodiment increase the success rate of the auxiliary connection electrode overlap by setting a plurality of auxiliary connection electrodes on the transparent area and the second power line, and the plurality of auxiliary connection electrodes are evenly distributed in the pixel, which can effectively alleviate the voltage drop of the large-size transparent display, ensure the display uniformity, and help simplify the structural layout of the display area, reduce the occupied space of each sub-pixel, increase the area ratio of the transparent area, and improve the resolution and transparency. In addition, the preparation process disclosed in the present invention can be well compatible with the existing preparation process, the process is simple to realize, easy to implement, high production efficiency, low production cost, and high yield rate.

[0023] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0025] Figure 1 is a structural schematic diagram of a display device;

[0026] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0027] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0028] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0029] Figure 5 A schematic diagram of the structure of a display panel according to an exemplary embodiment of the present disclosure;

[0030] Figure 6 for Figure 5 Schematic diagram of equivalent circuit of pixel driving circuit in four sub-pixels shown.

[0031] Figure 7 It is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0032] Figure 8 for Figure 7 Schematic diagram of the cross-sectional structure of the middle AA region;

[0033] Fig. 9 It is a schematic diagram of an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed;

[0034] Fig.10 for Fig. 9 Schematic diagram of the cross-sectional structure of the middle AA region;

[0035] Fig.11 It is a schematic diagram after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0036] Fig.12 for Fig.11 Schematic diagram of the cross-sectional structure of the middle AA region;

[0037] Fig.13 It is a schematic diagram after forming a third insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0038] Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure of the middle AA region;

[0039] Fig.15 It is a schematic diagram after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0040] Fig.16 for Fig.15 Schematic diagram of the cross-sectional structure of the middle AA region;

[0041] Fig.17 It is a schematic diagram of an exemplary embodiment of the present disclosure after a planar layer pattern is formed;

[0042] Fig.18 for Fig.17 Schematic diagram of the cross-sectional structure of the middle AA region;

[0043] Fig.19It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first transparent conductive layer pattern;

[0044] Fig. 20 for Fig.19 Schematic diagram of the cross-sectional structure of the middle AA region;

[0045] Fig.21 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming an anode layer pattern;

[0046] Fig. 22 for Fig.21 Schematic diagram of the cross-sectional structure of the middle AA region;

[0047] Fig.23 A schematic diagram of an exemplary embodiment of the present disclosure after forming a first pixel definition layer pattern;

[0048] Fig.24 for Fig.23 Schematic diagram of the cross-sectional structure of the middle AA region;

[0049] Fig.25 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming an organic light-emitting layer pattern;

[0050] Fig.26 FIG. 1 is a schematic diagram of an exemplary embodiment of the present disclosure after a cathode pattern is formed.

[0051] Description of reference numerals:

[0052] 10—substrate; 102—driving circuit layer; 103—light emitting structure layer;

[0053] 104—packaging layer; VDD—first power line; VSS—second power line;

[0054] G1—first scanning signal line; G2—second scanning signal line; S—compensation signal line;

[0055] D—data signal line; C—capacitor; N1~N2—nodes;

[0056] T1~T3—transistors; P1~P4, P—sub-pixels; 11, 21, 31—active layers; 41~43—plates; 45~48—openings; G line 1; -1—first scan connection G line 2; -1—second scan connection 12, 22, 32—gate electrodes; 51—vertical power connection line; 52—lateral power connection line; 53—auxiliary power line; 54—third scan connection line; V1~V18—vias; S1-1—compensation connection line; 13, 23, 33—source electrodes;

[0057] 14, 24, 34—drain electrode; 80—auxiliary cathode; 61-64—insulating layer;

[0058] 65—flat layer; 70-72, 74—anode; 81-83—connecting electrodes;

[0059] 84—auxiliary connection electrode; 91—pixel definition layer; K1—first pixel opening;

[0060] 92—organic light-emitting layer; 93—organic light-emitting block; 94—cathode;

[0061] 100—display area; 200—transparent area; K-hole 2;—second auxiliary electrode opening 701—first anode connection electrode 702—second anode connection electrode

[0062] Extreme; extreme. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0064] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0065] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0066] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0067] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0068] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0069] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0070] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0071] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0072] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0073] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0074] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0075] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array, the timing controller is respectively connected to the data signal driver and the scan signal driver, the data signal driver is respectively connected to a plurality of data signal lines (D1 to Dn), and the scan signal driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include at least one scan signal line, at least one data signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ..., and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver can sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver can sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be constructed in the form of a shift register, and can generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of a clock signal, where m can be a natural number.

[0076] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light, and the four sub-pixels may each include a circuit unit and a light-emitting device, the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line and the data signal line, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0077] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a green subpixel (G) that emits green light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a blue subpixel (B) that emits blue light.

[0078] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon. In an exemplary embodiment, four sub-pixels may be arranged in parallel horizontally to form a RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a square, a diamond, or in parallel vertically, which is not limited in the present disclosure.

[0079] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as a pixel row, a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0080] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of four sub-pixels of the display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display substrate may include a driving circuit layer 102 arranged on a substrate 10, a light-emitting structure layer 103 arranged on a side of the driving circuit layer 102 away from the substrate, and an encapsulation layer 104 arranged on a side of the light-emitting structure layer 103 away from the substrate.

[0081] In an exemplary embodiment, the substrate 10 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of a plurality of film layers, and the plurality of film layers may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0082] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer and the electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of all sub-pixels may be a common layer connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap. In some possible implementations, the display substrate may include other film layers, which are not limited in the present disclosure.

[0083] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4 As shown, the pixel driving circuit has a 3T1C structure and may include three transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C and six signal lines (a data signal line D, a first scanning signal line G1, a second scanning signal line G2, a compensation signal line S, a first power line VDD and a second power line VSS).

[0084] In an exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The first electrode of the storage capacitor C is coupled to the control electrode of the second transistor T2, the second electrode of the storage capacitor C is coupled to the second electrode of the second transistor T2, and the storage capacitor C is used to store the potential of the control electrode of the second transistor T2. The control electrode of the first transistor T1 is coupled to the first scan signal line G1, the first electrode of the first transistor T1 is coupled to the data signal line D, the second electrode of the first transistor T1 is coupled to the control electrode of the second transistor T2, and the first transistor T1 is used to receive the data signal transmitted by the data signal line D under the control of the first scan signal line G1, so that the control electrode of the second transistor T2 receives the data signal. The control electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, the second electrode of the second transistor T2 is coupled to the first electrode of the light-emitting device, and the second transistor T2 is used to generate a corresponding current at the second electrode under the control of the data signal received by its control electrode. The control electrode of the third transistor T3 is coupled to the second scanning signal line G2, the first electrode of the third transistor T3 is coupled to the compensation signal line S, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0085] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode), the first electrode of the OLED is coupled to the second electrode of the second transistor T2, the second electrode of the OLED is coupled to the second power line VSS, and the OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0086] In an exemplary embodiment, the signal of the first power line VDD continuously provides a high level signal, and the signal of the second power line VSS is a low level signal. The first transistor T1 to the third transistor T3 can be a P-type transistor, or can be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0087] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide. Low-temperature polysilicon thin film transistors have advantages such as high mobility and fast charging, and oxide thin film transistors have advantages such as low leakage current. In an exemplary embodiment, low-temperature polysilicon thin film transistors and oxide thin film transistors can be integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, can achieve high resolution (Pixel Per Inch, PPI), low-frequency driving, can reduce power consumption, and can improve display quality. In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0088] In an exemplary embodiment, taking the case where all three transistors are N-type transistors as an example, Figure 4 The working process of the exemplary pixel driving circuit may include:

[0089] In the first stage A1, the signals of the first scanning signal line G1 and the second scanning signal line G2 are high-level signals, the data signal line D outputs the data voltage, the compensation signal line S outputs the compensation voltage, the signal of the first power line VDD is high-level, and the signal of the second power line VSS is low-level. The signal of the first scanning signal line G1 is a high-level signal, which turns on the first transistor T1, and the data voltage output by the data signal line D is written into the first node N1, which pulls up the potential of the first node N1 and charges the storage capacitor C. At this time, the potential of the first node N1 is V1=V data The signal of the second scanning signal line G2 is a high level signal, which turns on the third transistor T3, and the compensation voltage output by the compensation signal line S is written into the second node N2. At this time, the potential V2 of the second node N2 = V s Since the potential difference between the first node N1 and the second node N2 is greater than the threshold voltage V th , the second transistor T2 is turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on second transistor T2, thereby driving the OLED to emit light.

[0090] In the second stage A2, the signals of the first scanning signal line G1 and the second scanning signal line G2 are low level signals, so that the first transistor T1 and the third transistor T3 are turned off, and the voltage in the storage capacitor C still makes the second transistor T2 in the on state, and the power supply voltage output by the first power line VDD continues to pull up the potential of the second node N2, and the OLED continues to emit light. When the potential of the second node N2 is equal to V data -V th When , the second transistor T2 is turned off and the OLED no longer emits light.

[0091] In an exemplary embodiment, in order to drive the OLED to emit light normally, the OLED and the second transistor T2 are both forward biased. In the first stage, the power voltage output by the first power line VDD is greater than the data voltage output by the data signal line D, the data voltage output by the data signal line D is greater than the compensation voltage output by the compensation signal line S, and the compensation voltage output by the compensation signal line S is greater than the power voltage output by the second power line VSS.

[0092] For OLED, from the writing of data in one frame to the writing of data in the next frame, the gate electrode voltage of the driving transistor is maintained by the storage capacitor. Due to the leakage current of the transistor, the voltage stored in the storage capacitor will gradually decrease, causing the gate electrode potential of the transistor to change, thereby affecting the current flowing through the organic electroluminescent diode and affecting the luminous brightness of the sub-pixel. For this reason, the plate of the storage capacitor is usually designed to be large enough to ensure the capacity of the storage capacitor. However, with the development of high-resolution (PPI) display technology, especially ultra-large-size high-resolution display, the pixel size is getting smaller and smaller. The larger plate reduces the pixel aperture ratio, which not only affects the development of high-resolution display, but also causes problems such as increased power consumption and life decay of luminescent materials.

[0093] According to the light emission direction, OLED display substrates can be divided into three types: bottom emission OLED, top emission OLED and double-sided emission OLED. Bottom emission OLED means light is emitted from the bottom of the substrate, top emission OLED means light is emitted from the top of the substrate, and double-sided emission OLED means light is emitted from both the bottom and top of the substrate. Compared with bottom emission OLED, top emission OLED has the advantages of large aperture ratio, high color purity, and easy realization of high resolution (Pixels per inch, PPI), and has been widely recognized.

[0094] For top-emitting OLEDs, since the light is emitted in the direction of the cathode, the cathode is required to have good light transmittance and conductivity, but it is difficult to meet the light transmittance and conductivity requirements at the same time. For example, in order to meet the conductivity requirement, the cathode thickness must be larger, but at this time the cathode transmittance is low, and the color deviation problem of viewing angle will occur. In order to meet the light transmittance requirement, the cathode thickness must be thinner, but at this time the cathode impedance is large, which will not only lead to the problem of voltage rise and increased power consumption, but also lead to uneven voltage distribution at various locations on the cathode, resulting in uneven brightness.

[0095] In a top-emitting OLED display substrate, in order to reduce the cathode voltage drop, an auxiliary electrode is set to reduce the cathode impedance, thereby reducing the cathode voltage drop. However, on the same column of sub-pixels, if the auxiliary electrodes are unevenly distributed, it will lead to different voltage drops; if the uniformity of the auxiliary electrode overlap point success rate is poor, there will be a nonlinear change trend of the voltage drop, which cannot be compensated by optical compensation or other voltage drop algorithms. Therefore, this structure and process cannot effectively reduce the cathode voltage drop, affecting the display effect.

[0096] An exemplary embodiment of the present disclosure provides a display substrate including a plurality of display units, at least one of which includes a display area and a transparent area, and at least one of which includes a plurality of sub-pixels.

[0097] At least one display area is provided with a first power line, a compensation signal line and a second power line along a first direction, the first power line, the compensation signal line and the second power line extend along a second direction, the compensation signal line is provided between the first power line and the second power line, at least one display area is provided with a compensation connection line in the middle of the second direction, the compensation connection line extends along the first direction, the compensation connection line and the compensation signal line are connected to each other, and the first direction intersects with the second direction.

[0098] At least one transparent area includes multiple auxiliary cathodes and multiple auxiliary connecting electrodes, the auxiliary cathodes are interconnected with the second power line, and the multiple auxiliary connecting electrodes are symmetrically arranged relative to the compensation connecting line, wherein a part of the auxiliary connecting electrodes are connected to the second power line, and another part of the auxiliary connecting electrodes are connected to the auxiliary cathodes.

[0099] The display substrate provided by the embodiment of the present disclosure increases the success rate of overlapping the auxiliary connection electrodes by arranging a plurality of auxiliary connection electrodes on the transparent area and the second power line, and the plurality of auxiliary connection electrodes are evenly distributed within the pixel, which can effectively alleviate the voltage drop of a large-size transparent display, ensure display uniformity, and is conducive to simplifying the structural layout of the display area, reducing the occupied space of each sub-pixel, increasing the area ratio of the transparent area, and improving resolution and transparency.

[0100] Figure 5 FIG. 1 is a schematic diagram of a display panel according to an exemplary embodiment of the present disclosure, illustrating the structure of four sub-pixels (one pixel unit). Figure 6 for Figure 5 The equivalent circuit diagram of the pixel driving circuit in the four sub-pixels is shown in FIG. Figure 5 and Figure 6 As shown, in a direction parallel to the display substrate, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged in sequence, and each sub-pixel includes a pixel driving circuit and a storage capacitor. In the following description, sub-pixels refer to areas where pixel driving circuits are set. In an exemplary embodiment, at least one pixel unit may also include a first scan signal line G1, a second scan signal line G2, a first power line VDD, a second power line VSS, four data signal lines D( Figure 6 In the figure, four data signal lines D are respectively the first data signal line D1 to the fourth data signal line D4, the first sub-pixel P1 is connected to the first data signal line D1, the second sub-pixel P2 is connected to the second data signal line D2, the third sub-pixel P3 is connected to the third data signal line D3, and the fourth sub-pixel P4 is connected to the fourth data signal line D4), a compensation signal line S and four pixel driving circuits.

[0101] In an exemplary embodiment, the first scan signal line G1 and the second scan signal line G2 may extend along the first direction D1 and be sequentially arranged along the second direction D2, and the first direction D1 intersects the second direction D2. The first power line VDD, the data signal line D, and the compensation signal line S may extend along the second direction D2 and be correspondingly arranged along the first direction D1.

[0102] In an exemplary embodiment, four data signal lines D and one compensation signal line S are disposed between a first power line VDD and a second power line VSS, two of the four data signal lines D are located between the compensation signal line S and the first power line VDD, and the other two of the four data signal lines D are located between the compensation signal line S and the second power line VSS. Thus, four sub-pixels are formed between the first power line VDD and the second power line VSS by disposing four data signal lines D and one compensation signal line S, and correspondingly, four sub-pixels are also formed between the two compensation signal lines S by disposing one first power line VDD, one second power line VSS, and four data signal lines D.

[0103] In an exemplary embodiment, a first power line VDD, two data signal lines D, a compensation signal line S, another two data signal lines D, and a second power line VSS may be sequentially arranged along a first direction D1. In the first direction D1, the first sub-pixel P1 and the second sub-pixel P2 are alternately arranged to form a first row, and the third sub-pixel P3 and the fourth sub-pixel P4 are alternately arranged to form a second row; in the second direction D2, the first sub-pixel P1 and the third sub-pixel P3 are alternately arranged to form a first column, and the second sub-pixel P2 and the fourth sub-pixel P4 are alternately arranged to form a second column.

[0104] In an exemplary embodiment, in the four sub-pixels of at least one pixel unit, the pixel driving circuit in each sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor. The first transistor T1 may include a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the second transistor T2 may include a second active layer, a second gate electrode, a second source electrode and a second drain electrode, the third transistor T3 may include a third active layer, a third gate electrode, a third source electrode and a third drain electrode, and the storage capacitor may include a first plate and a second plate.

[0105] In an exemplary embodiment, the first electrode plate and the second electrode plate are transparent conductive layers, forming a transparent storage capacitor.

[0106] In an exemplary embodiment, the first scan signal line G1 is connected to the gate electrode of the first transistor T1 in each sub-pixel, the second scan signal line G2 is connected to the gate electrode of the third transistor T3 in each sub-pixel, the data signal line D is connected to the first electrode of the first transistor T1 in each sub-pixel, the compensation signal line S is connected to the first electrode of the third transistor T3 in each sub-pixel, the first power line VDD is connected to the first electrode of the second transistor T2 in each sub-pixel, the second electrode of the first transistor T1 in each sub-pixel is connected to the gate electrode of the second transistor T2, the second electrode of the second transistor T2 in each sub-pixel is connected to the first electrode of the third transistor T3 and the anode of the light emitting device, the first electrode plate in each sub-pixel is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, and the second electrode plate in each sub-pixel is respectively connected to the second electrode of the first transistor T1 and the gate electrode of the second transistor T2.

[0107] In an exemplary embodiment, at least one pixel unit may include a plurality of connection lines, the plurality of connection lines including at least two lateral power connection lines extending along a first direction D1 and two compensation connection lines extending along the first direction D1 and in an opposite direction of the first direction D1, forming a one-to-four structure of first power lines and a one-to-four structure of compensation signal lines.

[0108] In an exemplary embodiment, a horizontal power connection line is provided between the first sub-pixel P1 and the second sub-pixel P2, one end of the horizontal power connection line is connected to the first power line VDD through a via hole, and the other end is connected to the second transistor T2 in the first sub-pixel P1 and the second sub-pixel P2 through a via hole. Another horizontal power connection line is provided between the third sub-pixel P3 and the fourth sub-pixel P4, one end of the horizontal power connection line is connected to the first power line VDD through a via hole, and the other end is connected to the second transistor T2 in the third sub-pixel P3 and the fourth sub-pixel P4 through a via hole. In this way, one first power line VDD can provide power signals to four sub-pixels.

[0109] In an exemplary embodiment, the compensation connection line is disposed in the middle of a pixel unit, the compensation connection line and the compensation signal line are interconnected as an integral structure, and the compensation connection line is connected to the third transistor T3 in each sub-pixel through a via hole. In this way, one compensation signal line S can provide compensation signals to four sub-pixels.

[0110] The embodiment of the disclosed embodiment saves the number of signal lines and reduces the occupied space through the one-to-four structure of the first power line and the one-to-four structure of the compensation signal line. It has a simple structure, a reasonable layout, fully utilizes the layout space, improves space utilization, and is conducive to improving resolution.

[0111] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving circuit layer of the sub-pixel may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer and a planar layer stacked on a substrate. The first conductive layer includes at least a first plate of a storage capacitor, a compensation signal line and a compensation connection line, the semiconductor layer includes at least an active layer of three transistors, the second conductive layer includes at least a first scanning signal line, a second scanning signal line, a lateral power connection line, a second plate of a storage capacitor and gate electrodes of three transistors, and the third conductive layer includes at least a first power line VDD, a second power line VSS, a data signal line D and first and second electrodes of three transistors. The orthographic projection of the first plate on the substrate and the orthographic projection of the second plate on the substrate at least have an overlapping area to form a storage capacitor.

[0112] In an exemplary embodiment, the second conductive layer may include a first scan connection line and a second scan connection line, the first scan connection line and the second scan connection line are located in the first sub-pixel P1 and the second sub-pixel P2, the first scan signal line and the second scan signal line are located in the third sub-pixel P3 and the fourth sub-pixel P4, and the second scan connection line and the second scan signal line are connected to each other into an integrated structure;

[0113] The third conductive layer may include a third scan connection line, and the third scan connection line is respectively connected to the first scan connection line and the first scan signal line through via holes.

[0114] In an exemplary embodiment, the second conductive layer may include a longitudinal power connection line and an auxiliary power line, the first power line VDD is connected to the longitudinal power connection line through a via to form a double-layer first power line, and the second power line VSS is connected to the auxiliary power line through a via to form a double-layer second power line.

[0115] In an exemplary embodiment, the third conductive layer may include an auxiliary cathode electrode, and the auxiliary cathode electrode and the second power line VSS are an integral structure connected to each other.

[0116] In an exemplary embodiment, in a direction perpendicular to the display substrate, the sub-pixel further includes a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light emitting structure layer includes an anode, and the auxiliary connection electrode is disposed in the same layer as the anode.

[0117] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0118] Figure 7 to Figure 26This is a schematic diagram of the preparation process of the display substrate of the present disclosure, which illustrates the layout structure of a display unit of the top-emitting OLED display substrate. Each display unit includes a display area 100 and a transparent area 200. The display area 100 includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. In an exemplary embodiment, the preparation process of the driving circuit layer may include the following operations:

[0119] (1) forming a first conductive layer pattern, including: depositing a first metal film on a substrate, patterning the first metal film by a patterning process, and forming a first conductive layer pattern on the substrate 10, wherein the first conductive layer pattern includes a first electrode 41 and a compensation signal line S, wherein each sub-pixel forms a first electrode 41, and the compensation signal line S is a stripe structure arranged between four sub-pixels, such as Figure 7 and Figure 8 As shown, Figure 8 for Figure 7 Cross-section view along the AA direction.

[0120] In an exemplary embodiment, the first electrode plate 41 serves as a electrode plate of the first storage capacitor, configured to form a first storage capacitor with a second electrode plate formed subsequently, and the first electrode plate 41 also serves as a shielding layer, configured to shield the transistor from light, reduce the intensity of light irradiating the transistor, reduce leakage current, and thus reduce the impact of light on transistor characteristics.

[0121] In an exemplary embodiment, the compensation signal line S extends in the second direction D2, and a compensation connection line S-1 is provided on the compensation signal line S, which protrudes in the first direction D1 and the opposite direction of the first direction D1. The compensation connection line S-1 is connected to the first electrode of the third transistor formed subsequently, and is used to provide a compensation signal to the third transistor in each sub-pixel.

[0122] In an exemplary embodiment, the first electrode 41 is a long rectangular strip. The first electrode 41 in the first sub-pixel P1 and the first electrode 41 in the second sub-pixel P2 are respectively provided with a first opening 45 at a position close to the middle of the pixel unit and away from the compensation signal line S. The first electrode 41 in the third sub-pixel P3 and the first electrode 41 in the fourth sub-pixel P4 are respectively provided with a second opening 46 at a position close to the middle of the pixel unit and close to the compensation signal line S.

[0123] In an exemplary embodiment, the first conductive layer pattern in the first subpixel P1 is mirror-symmetric to the first conductive layer pattern in the second subpixel P2 with respect to a vertical axis (the vertical axis may be the compensation signal line S), and the first conductive layer pattern in the third subpixel P3 is mirror-symmetric to the first conductive layer pattern in the fourth subpixel P4 with respect to the vertical axis.

[0124] After this patterning process, the first conductive layer pattern is formed in the display area 100 , and there is no corresponding film layer in the transparent area 200 .

[0125] (2) forming a semiconductor layer pattern, comprising: depositing a first insulating film and a semiconductor film in sequence on a substrate having the aforementioned pattern, patterning the semiconductor film by a patterning process to form a first insulating layer 61 covering the first conductive layer pattern, and forming a semiconductor layer pattern on the first insulating layer 61, wherein the semiconductor layer comprises a first active layer 11, a second active layer 21, and a third active layer 31 pattern arranged in each sub-pixel, such as Fig. 9 and Fig.10 As shown, Fig.10 for Fig. 9 The first active layer 11 is used as the active layer of the first transistor, the second active layer 21 is used as the active layer of the second transistor, and the third active layer 31 is used as the active layer of the third transistor.

[0126] In an exemplary embodiment, in the four sub-pixels, there is an overlapping area between the orthographic projection of the second active layer 21 on the substrate 10 and the orthographic projection of the first electrode 41 on the substrate 10, so that the first electrode 41 as a shielding layer can shield the channel area of ​​the second transistor, thereby preventing light from affecting the channel and preventing the channel from affecting the display effect due to the generation of photo-induced leakage.

[0127] In an exemplary embodiment, the first active layer 11 in the first and second subpixels P1 and P2 is disposed near the first opening 45 , and the first active layer 11 in the third and fourth subpixels P3 and P4 is disposed near the second opening 46 .

[0128] In an exemplary embodiment, in the four sub-pixels P1 to P4, the third active layer 31 is disposed near the compensation connection line S-1, and an orthographic projection of the third active layer 31 on the substrate 10 overlaps with an orthographic projection of the compensation connection line S-1 on the substrate 10. In an exemplary embodiment, the third active layer 31 in the first sub-pixel P1 and the third active layer 31 in the third sub-pixel P3 are interconnected as an integral structure, and the third active layer 31 in the second sub-pixel P2 and the third active layer 31 in the fourth sub-pixel P4 are interconnected as an integral structure.

[0129] In an exemplary embodiment, the semiconductor layer pattern in the first subpixel P1 is mirror-symmetric to the semiconductor layer pattern in the second subpixel P2 with respect to the vertical axis, and the semiconductor layer pattern in the third subpixel P3 is mirror-symmetric to the semiconductor layer pattern in the fourth subpixel P4 with respect to the vertical axis.

[0130] In an exemplary embodiment, the semiconductor layer may use a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0131] After this patterning process, a semiconductor layer pattern is formed in the display area 100 , and the transparent area 200 includes a substrate 10 and a first insulating layer 61 disposed on the substrate 10 .

[0132] (3) forming a second conductive layer pattern, comprising: depositing a second insulating film and a second metal film in sequence on a substrate having the aforementioned pattern, patterning the second insulating film and the second metal film by a patterning process to form a second insulating layer 62 pattern and a second conductive layer pattern disposed on the second insulating layer 62, wherein the second conductive layer pattern comprises a first scanning signal line G1, a second scanning signal line G2, a first scanning connection line G1-1, a second scanning connection line G2-1, a longitudinal power connection line 51, a transverse power connection line 52 and an auxiliary power line 53 formed in each display unit, and a second electrode plate 42, a first gate electrode 12, a second gate electrode 22 and a third gate electrode 32 formed in each sub-pixel, as shown in FIG. Fig.11 and Fig.12 As shown, Fig.12 for Fig.11 Cross-section view along the AA direction.

[0133] In an exemplary embodiment, an orthographic projection of the second electrode plate 42 on the substrate 10 overlaps with an orthographic projection of the first electrode plate 41 on the substrate 10 , and the first electrode plate 41 and the second electrode plate 42 form a first storage capacitor.

[0134] In an exemplary embodiment, the second electrode plate 42 is an elongated rectangle, and the second electrode plates 42 in the first sub-pixel P1 and the second sub-pixel P2 are respectively provided with third openings 47 at the middle positions near the pixel units, and the second electrode plates 42 in the third sub-pixel P3 and the fourth sub-pixel P4 are respectively provided with fourth openings 48 at the middle positions near the pixel units.

[0135] In an exemplary embodiment, the first scan signal line G1 and the second scan signal line G2 both extend along the first direction D1, the second scan connection line G2-1 is an inverted "U" shaped structure, the second scan connection line G2-1 and the second scan signal line G2 are interconnected to form an integral structure, the first scan connection line G1-1 is an "I" shaped structure, the first scan connection line G1-1 and the second scan connection line G2-1 are located in the first sub-pixel P1 and the second sub-pixel P2, and the first scan signal line G1 and the second scan signal line G2 are located in the third sub-pixel P3 and the fourth sub-pixel P4.

[0136] In an exemplary embodiment, the orthographic projection of the second scan signal line G2 on the substrate overlaps with the orthographic projection of the third active layer 31 in the third sub-pixel P3 and the fourth sub-pixel P4 on the substrate, and the area where the second scan signal line G2 overlaps with the third active layer 31 in the third sub-pixel P3 and the fourth sub-pixel P4 serves as the gate electrode 32 of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4. The orthographic projection of the second scan connection line G2-1 on the substrate overlaps with the orthographic projection of the third active layer 31 in the first sub-pixel P1 and the second sub-pixel P2 on the substrate, and the area where the second scan connection line G2-1 overlaps with the third active layer 31 in the first sub-pixel P1 and the second sub-pixel P2 serves as the gate electrode 32 of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2.

[0137] In an exemplary embodiment, the first scan signal line G1 includes a "U"-shaped bend portion, and an orthographic projection of the first scan signal line G1 on the substrate overlaps with an orthographic projection of the first active layer 11 in the third sub-pixel P3 and the fourth sub-pixel P4 on the substrate. The overlapping area between the first scan signal line G1 and the first active layer 11 in the third sub-pixel P3 and the fourth sub-pixel P4 serves as the gate electrode 12 of the first transistor T1 in the third sub-pixel P3 and the fourth sub-pixel P4. The orthographic projection of the first scan connection line G1-1 on the substrate overlaps with an orthographic projection of the first active layer 11 in the first sub-pixel P1 and the second sub-pixel P2 on the substrate. The overlapping area between the first scan signal line G1 and the first active layer 11 in the first sub-pixel P1 and the second sub-pixel P2 serves as the gate electrode 12 of the first transistor T1 in the first sub-pixel P1 and the second sub-pixel P2.

[0138] In an exemplary embodiment, the second gate electrode 22 is disposed across the second active layer 21 and is connected to the second electrode plate 42 to form an integrated structure.

[0139] In an exemplary embodiment, each display unit includes two longitudinal power connection lines 51, which are formed in the first sub-pixel P1 and the third sub-pixel P3 and are strip-shaped structures extending along the second direction D2. In the first sub-pixel P1, the longitudinal power connection line 51 is located on one side of the second electrode plate 42 in the opposite direction of the first direction D1. In the third sub-pixel P3, the longitudinal power connection line 51 is located on one side of the second electrode plate 42 in the opposite direction of the first direction D1. The longitudinal power connection line 51 is configured to be connected to the first power line VDD formed subsequently, forming a double-layer wiring, ensuring the reliability of power signal transmission, and reducing the resistance of the first power line.

[0140] In an exemplary embodiment, each display unit includes two transverse power connection lines 52, one of which is located on the upper side of the pixel unit, and the other transverse power connection line 52 is located on the lower side of the pixel unit. Each transverse power connection line 52 may be provided with a through hole, and the orthographic projection of the through hole on the substrate overlaps with the orthographic projection of the compensation signal line and the subsequently formed data signal line on the substrate, and the through hole is configured to reduce the parasitic capacitance between the transverse power connection line 52 and the data signal line and the compensation signal line.

[0141] In an exemplary embodiment, each display unit includes two auxiliary power lines 53, which are formed in the second sub-pixel P2 and the fourth sub-pixel P4 and are strip-shaped structures extending along the second direction D2. In the second sub-pixel P2, the auxiliary power line 53 is located on one side of the second electrode plate 42 along the first direction D1. In the fourth sub-pixel P4, the auxiliary power line 53 is located on one side of the second electrode plate 42 along the first direction D1. The auxiliary power line 53 is configured to be connected to the second power line formed subsequently to form a double-layer wiring, thereby ensuring the reliability of power signal transmission and reducing the resistance of the second power line.

[0142] In an exemplary embodiment, the pattern of the second insulating layer 62 may be the same as the pattern of the second conductive layer, that is, the second insulating layer 62 is located below the second conductive layer, and there is no second insulating layer 62 in the area outside the second conductive layer.

[0143] In an exemplary embodiment, the first subpixel P1 and the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 in the second subpixel P2 are mirror-symmetric with respect to the vertical axis, and the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 in the third subpixel P3 and the fourth subpixel P4 are mirror-symmetric with respect to the vertical axis.

[0144] In an exemplary embodiment, this process also includes a conductorization treatment. The conductorization treatment is to perform plasma treatment using the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as shielding after forming the second conductive layer pattern, and the semiconductor layer in the area shielded by the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 (i.e., the area where the semiconductor layer overlaps with the first gate electrode 12, the second gate electrode 22, and the third gate electrode) is used as the channel area of ​​the transistor, and the semiconductor layer in the area not shielded by the second conductive layer is processed into a conductorization layer to form a conductorized source and drain area.

[0145] After this patterning process, a second conductive layer pattern is formed in the display area 100 , and the transparent area 200 includes a substrate 10 and a first insulating layer 61 disposed on the substrate 10 .

[0146] (4) Forming a third insulating layer pattern. Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate having the aforementioned pattern, patterning the third insulating film through a patterning process to form a third insulating layer 63 pattern covering the aforementioned structure, and providing a plurality of via hole patterns on the third insulating layer 63, wherein the plurality of via hole patterns include: a first via hole V1 and a second via hole V2 located on both sides of the first gate electrode 12, a third via hole V3 and a fourth via hole V4 located on both sides of the second gate electrode 22, a fifth via hole V5 and a sixth via hole V6 located on both sides of the third gate electrode 32, a plurality of seventh via holes V7 located at the position where the auxiliary power line 53 is located, and a plurality of seventh via holes V8 located at the position where the auxiliary power line 53 is located. The eighth via hole V8 at the location of the compensation connection line S-1, the ninth via hole V9 located in the overlapping area of ​​the first drain electrode 14 and the second electrode plate 42 formed subsequently, the tenth via hole V10 located on the first electrode plate 41 and overlapping with the opening area on the second electrode plate 42, the plurality of eleventh via holes V11 located at the location of the longitudinal power connection line 51, the twelfth via hole V12 and the thirteenth via hole V13 located at the location of the transverse power connection line 52, the fourteenth via hole V14 located at the location of the first scan connection line G1-1, and the fifteenth via hole V15 located at the location of the first scan signal line G1, as shown in FIG. Fig.13 and Fig.14 As shown, Fig.14 for Fig.13 Cross-section view along the AA direction.

[0147] The third insulating layer 63 in the first via hole V1 and the second via hole V2 is etched away, exposing the surfaces of both ends of the first active layer 11. The third insulating layer 63 in the third via hole V3 and the fourth via hole V4 is etched away, exposing the surfaces of both ends of the second active layer 21. The third insulating layer 63 in the fifth via hole V5 and the sixth via hole V6 is etched away, exposing the surfaces of both ends of the third active layer 31. The seventh via hole V7 is located at the position where the auxiliary power line 53 is located, and multiple seventh via holes V7 are arranged at intervals. The third insulating layer 63 in the seventh via hole V7 is etched away, exposing the surface of the auxiliary power line 53. The eighth via hole V8 is located at the position where the third source electrode 33 formed subsequently overlaps with the compensation connection line S-1. The first insulating layer 61 and the third insulating layer 63 in the eighth via hole V8 are etched away, exposing the surface of the compensation connection line S-1. The ninth via hole V9 is formed on the second electrode plate 42, and the third insulating layer 63 in the ninth via hole V9 is etched away, exposing the surface of the second electrode plate 42. The tenth via hole V10 in the first sub-pixel P1 and the second sub-pixel P2 is located at the position of the third opening 47 of the second electrode plate 42, and the tenth via hole V10 in the third sub-pixel P3 and the fourth sub-pixel P4 is located at the position of the fourth opening 48 of the second electrode plate 42. The first insulating layer 61 and the third insulating layer 63 in the tenth via hole V10 are etched away, exposing the surface of the first electrode plate 41. The eleventh via hole V11 is located at the position of the longitudinal power connection line 51. A plurality of eleventh via holes V11 are arranged at intervals. The third insulating layer 63 in the eleventh via hole V11 is etched away, exposing the surface of the longitudinal power connection line 51. The twelfth via hole V12 is located at the position where the transverse power connection line 52 overlaps with the first power line VDD to be formed later. The third insulating layer 63 in the twelfth via hole V12 is etched away, exposing the surface of the transverse power connection line 52. The thirteenth via hole V13 is located at the position where the horizontal power connection line 52 overlaps with the second source electrode 23 to be formed subsequently, and the third insulating layer 63 in the twelfth via hole V12 and the thirteenth via hole V13 is etched away, exposing the surface of the horizontal power connection line 52. The fourteenth via hole V14 is located at the position where the first scan connection line G1-1 overlaps with the third scan connection line 54 to be formed subsequently, and the third insulating layer 63 in the fourteenth via hole V14 is etched away, exposing the surface of the first scan connection line G1-1. The fifteenth via hole V15 is located at the position where the first scan signal line G1 overlaps with the third scan connection line 54 to be formed subsequently, and the third insulating layer 63 in the fifteenth via hole V15 is etched away, exposing the surface of the first scan signal line G1.

[0148] After this patterning process, a plurality of via patterns are formed in the display area 100 , and the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10 .

[0149] (5) forming a third conductive layer pattern, including: depositing a third metal film on the substrate having the aforementioned pattern, patterning the third metal film by a patterning process, forming a third conductive layer pattern and an auxiliary cathode 80 pattern on the third insulating layer 63, wherein the third conductive layer is formed in the display area 100, and the auxiliary cathode 80 is formed in the transparent area 200. The third conductive layer of the display area 100 includes: a first power line VDD, a second power line VSS, four data signal lines D and two third scanning connection lines 54 formed in each display unit, and a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34 and a third electrode plate 43 pattern formed in each sub-pixel. The auxiliary cathode 80 and the second power line VSS of the transparent area 200 are an integrated structure connected to each other, such as Fig.15 and Fig.16 As shown, Fig.16 for Fig.15 Cross-section view along the AA direction.

[0150] In an exemplary embodiment, the first power line VDD, the second power line VSS, the compensation signal line S and the data signal line D are arranged in parallel and extend along the second direction D2. The second power line VSS is arranged on a side adjacent to the auxiliary cathode 80, the first power line VDD is arranged on a side away from the auxiliary cathode 80, the compensation signal line S is arranged between the first power line VDD and the second power line VSS, two data signal lines D are arranged between the second power line VSS and the compensation signal line S, and another two data signal lines D are arranged between the first power line VDD and the compensation signal line S.

[0151] In an exemplary embodiment, the first power line VDD is connected to the longitudinal power connection line 51 through multiple eleventh vias V11, the first power line VDD is connected to the transverse power connection line 52 through the twelfth via V12, the transverse power connection line 52 is connected to the second source electrode 23 of each sub-pixel through the thirteenth via V13, and the second source electrode 23 is connected to one end of the second active layer 21 through the third via V3, thereby realizing the connection between the second source electrode 23 and the first power line VDD, and the first power line VDD and the longitudinal power connection line 51 form a double-layer routing, which ensures the reliability of power signal transmission and reduces the resistance of the first power line VDD.

[0152] In an exemplary embodiment, the second power line VSS is connected to the auxiliary power line 53 through a plurality of seventh vias V7, and the second power line VSS and the auxiliary power line 53 form a double-layer routing, which ensures the reliability of power signal transmission and reduces the resistance of the second power line VSS. In some possible implementations, the widths of the first power line VDD and the second power line VSS along the first direction D1 are both greater than the width of the compensation signal line S along the first direction D1, and the widths of the first power line VDD and the second power line VSS along the first direction D1 are both greater than the width of the data signal line D along the first direction D1, which can further reduce the resistance of the first power line VDD and the second power line VSS.

[0153] In an exemplary embodiment, the compensation connection line S-1 is connected to the third source electrode 33 of each sub-pixel through the eighth via hole V8. Since the compensation connection line S-1 is arranged in the middle of the sub-pixels on the upper and lower sides of the display area 100, and the compensation signal line S is arranged in the middle of the sub-pixels on the left and right sides of the display area 100, the compensation connection line S-1 and the compensation signal line S are an integrated structure connected to each other, and the third transistors of the sub-pixels on the left and right sides are symmetrically arranged with respect to the compensation signal line S. This symmetrical design allows each display unit to use only one compensation signal line S, which can ensure that the RC delay of the compensation signal before writing into the transistor is substantially the same, thereby ensuring display uniformity.

[0154] In an exemplary embodiment, the third scan connection line 54 is a straight line or a folded line structure extending along the second direction D2, and is connected to the first scan connection line G1-1 through the fourteenth via hole V14, and is connected to the first scan signal line G1 through the fifteenth via hole V15.

[0155] In an exemplary embodiment, the data signal line D of the first subpixel P1 is arranged on a side of the first subpixel P1 close to the first power line VDD, the data signal line D of the second subpixel P2 is arranged on a side of the second subpixel P2 close to the second power line VSS, the data signal line D of the third subpixel P3 is arranged on a side of the third subpixel P3 close to the compensation signal line S, and the data signal line D of the fourth subpixel P4 is arranged on a side of the fourth subpixel P4 close to the compensation signal line S.

[0156] In the exemplary embodiment, the first source electrode 13 is an integral structure connected to the data signal line D, so that each data signal line D is respectively connected to the first source electrode 13 of the sub-pixel, the first source electrode 13 is connected to one end of the first active layer 11 through the first via hole V1, the first drain electrode 14 is connected to the other end of the first active layer 11 through the second via hole V2, and the first drain electrode 14 is also connected to the second gate electrode 22 and the second electrode plate 42 through the ninth via hole V9, so that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential. The second source electrode 23 is connected to one end of the second active layer 21 through the third via hole V3, and at the same time, is connected to the horizontal power connection line 52 through the thirteenth via hole V13, and the horizontal power connection line 52 is connected to the first power line VDD through the twelfth via hole V12, so that the second source electrode 23 is connected to the first power line VDD, and the second drain electrode 24 is connected to the other end of the second active layer 21 through the fourth via hole V4. The third source electrode 33 is connected to one end of the third active layer 31 through the fifth via hole V5, and is connected to the compensation connection line S-1 through the eighth via hole V8. The compensation connection line S-1 and the compensation signal line S are an integrated structure connected to each other, so that the third source electrode 33 is connected to the compensation signal line S. The third drain electrode 34 is connected to the other end of the third active layer 31 through the sixth via hole V6. The second drain electrode 24, the third drain electrode 34 and the third electrode plate 43 are an integrated structure connected to each other. The third electrode plate 43 is connected to the first electrode plate 41 through the tenth via hole V10, so that the second drain electrode 24 is connected to the first electrode plate 41 and the third electrode plate 43 at the same time, and the third drain electrode 34 is connected to the first electrode plate 41 and the third electrode plate 43 at the same time, so that the second drain electrode 24, the third drain electrode 34, the first electrode plate 41 and the third electrode plate 43 have the same potential. The orthographic projection of the third electrode plate 43 on the substrate 10 and the orthographic projection of the second electrode plate 42 on the substrate 10 have an overlapping area, and the third electrode plate 43 and the second electrode plate 42 form a second storage capacitor.

[0157] In an exemplary embodiment, the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34 and the third electrode plate 43 in the first subpixel P1 and the second subpixel P2 are mirror-symmetric with respect to the vertical axis, and the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34 and the third electrode plate 43 in the third subpixel P3 and the fourth subpixel P4 are mirror-symmetric with respect to the vertical axis.

[0158] In an exemplary embodiment, the auxiliary cathode 80 is configured to reduce the diffraction effect of the transparent area. By arranging the auxiliary cathode 80 in the transparent area 200, the transparent area 200 is changed from a regular rectangle to an irregular shape, and different positions of the transparent area 200 have different slit widths. When light passes through the irregularly shaped transparent area 200, due to the different positions where the diffraction fringes are generated and the different directions in which the diffraction fringes are generated, the diffraction fringes generated by the light do not diffuse in one direction, but diffuse in multiple directions, which greatly weakens the diffraction effect, avoids the blurring phenomenon of objects behind the screen, and improves the transparent display effect.

[0159] In some possible implementations, the auxiliary cathode 80 of the transparent area 200 includes an electrode block 801 and a connecting bar 802, the electrode block 801 is connected to the second power line VSS through the connecting bar 802, the electrode block 801 may include any one or more of a circular, elliptical, rectangular, trapezoidal, pentagonal, hexagonal and dumbbell shape, the connecting bar 802 may be any one or more of a straight line, a folded line and an arc line, and the present disclosure does not make specific limitations here. In some possible implementations, the width of the electrode block 801 along the second direction D2 is greater than the width of the connecting bar 802, and the length of the connecting bar 802 along the first direction D1 is greater than the length of the electrode block 801.

[0160] In some possible implementations, the transparent region 200 may be provided with one auxiliary cathode 80 , or may be provided with two or more auxiliary cathodes 80 , and the area of ​​the electrode block 801 may be 5% to 20% of the area of ​​the transparent region 200 , which is not specifically limited in the present disclosure.

[0161] After this patterning process, the third conductive layer pattern is formed in the display area 100 , and the transparent area 200 includes the first insulating layer 61 and the third insulating layer 63 stacked on the substrate 10 , and the auxiliary cathode 80 disposed on the third insulating layer 63 .

[0162] (6) forming a fourth insulating layer and a planar layer pattern, comprising: first depositing a fourth insulating film on the substrate having the aforementioned pattern, then coating a planar film, etching the fourth insulating film through masking, exposure and development of the planar film to form a fourth insulating layer 64 pattern covering the aforementioned structure, and a planar (PLN) layer 65 pattern arranged on the fourth insulating layer 64, wherein a plurality of via hole patterns are provided on the fourth insulating layer 64 and the planar layer 65, and the plurality of via hole patterns at least include: a sixteenth via hole V16 located at a position of the third electrode plate 43 in each sub-pixel of the display area 100, a seventeenth via hole V17 on the second power line VSS, and an eighteenth via hole V18 located at a position of the auxiliary cathode 80 in the transparent area 200, as shown in FIG. Fig.17 and Fig.18 As shown, Fig.18 for Fig.17 Cross-section view along the AA direction.

[0163] In an exemplary embodiment, the sixteenth via hole V16 is located in the middle of the third electrode plate 43, the fourth insulating layer 64 and the planar layer 65 in the thirteenth via hole V13 are etched away to expose the surface of the third electrode plate 43, the fourth insulating layer 64 and the planar layer 65 in the seventeenth via hole V17 are etched away to expose the surface of the second power line VSS, and the fourth insulating layer 64 and the planar layer 65 in the eighteenth via hole V18 are etched away to expose the surface of the auxiliary cathode 80.

[0164] After this patterning process, the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10, an auxiliary cathode 80 arranged on the third insulating layer 63, a fourth insulating layer 64 and a planar layer 65 covering the auxiliary cathode 80, and an eighteenth via hole V18 exposing the auxiliary cathode 80 is opened on the fourth insulating layer 64 and the planar layer 65.

[0165] (7) forming a first transparent conductive layer pattern, comprising: depositing a first transparent conductive film on a substrate having the aforementioned pattern, patterning the first transparent conductive film by a patterning process, and forming a first transparent conductive layer pattern on a flat layer 65, wherein the first transparent conductive layer comprises a first anode 70 and a first connecting electrode 81, wherein the first anode 70 is formed in each sub-pixel of the display region 100, wherein the first anode 70 in each sub-pixel is connected to the drain electrode of the second transistor T2 through a sixteenth via hole V16 in the corresponding sub-pixel, wherein the first connecting electrode 81 is formed at a position where a seventeenth via hole V17 on the second power line VSS in the display region 100 is located and at a position where an auxiliary cathode 80 is located in the transparent region 100, wherein the first connecting electrode 81 is connected to the second power line VSS through the seventeenth via hole V17 and is connected to the auxiliary cathode 80 through an eighteenth via hole V18, as shown in FIG. Fig.19 and Fig. 20 As shown, Fig. 20 for Fig.19 The cross-sectional view is taken along the AA direction in the middle. Since the drain electrode of the second transistor T2 in each sub-pixel, the drain electrode of the third transistor T3 and the third electrode plate 43 are interconnected as an integral structure, the connection between the first anode 70 and the drain electrode of the second transistor T2 in each sub-pixel is achieved. In an exemplary embodiment, four first anodes 70 can form a red light emitting unit, a green light emitting unit, a blue light emitting unit and a white light emitting unit.

[0166] In an exemplary embodiment, the first anode 70 may include two separately disposed sub-anode blocks, and the two sub-anode blocks are connected to each other via a connection structure. Fig.19As shown, the connection structure may include: a first anode connection electrode 701, which is in a "U" shape, and its two ends are respectively connected to one of the two sub-anode blocks; a second anode connection electrode 702, one end of which is connected to the driving transistor, and the other end is connected to the first anode connection electrode 701, so that the two sub-anode blocks are interconnected through the connection structure.

[0167] If dark spots or bright spots appear in any sub-pixel of the display panel, a portion of the first anode connection electrode 701 in the connection structure can be laser cut, so that one of the two sub-anode blocks from one sub-pixel can be electrically connected to the driving transistor and the other sub-anode block is floated, thereby driving the sub-pixel normally.

[0168] In an exemplary embodiment, four first anodes 70 are arranged in a square, the upper left first anode 70 is connected to the third electrode plate 43 of the first sub-pixel P1 through the sixteenth via hole V16 of the first sub-pixel P1, the upper right first anode 70 is connected to the third electrode plate 43 of the second sub-pixel P2 through the sixteenth via hole V16 of the second sub-pixel P2, the lower left first anode 70 is connected to the third electrode plate 43 of the third sub-pixel P3 through the sixteenth via hole V16 of the third sub-pixel P3, and the lower right first anode 70 is connected to the third electrode plate 43 of the fourth sub-pixel P4 through the sixteenth via hole V16 of the fourth sub-pixel P4. In some possible implementations, the arrangement of the first anodes 70 in the display area 100 can be adjusted according to actual needs, and the present disclosure does not specifically limit it here.

[0169] After this patterning process, the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10, an auxiliary cathode 80 arranged on the third insulating layer 63, a fourth insulating layer 64 and a flat layer 65 covering the auxiliary cathode 80, and a first connecting electrode 81 arranged on the flat layer 65, and the first connecting electrode 81 is connected to the auxiliary cathode 80 through the eighteenth via hole V18.

[0170] (8) Forming anode and auxiliary connection electrode patterns. In an exemplary embodiment, forming the anode and auxiliary electrode patterns may include: sequentially depositing a fourth metal film and a second transparent conductive film on the substrate on which the aforementioned patterns are formed, patterning the fourth metal film and the second transparent conductive film through a patterning process to form a second anode 71, a third anode 72, a second connection electrode 82, and a third connection electrode 83 pattern, wherein the second anode 71 is disposed on a side of the first anode 70 away from the substrate and connected to the first anode 70, the third anode 72 is disposed on a side of the second anode 71 away from the substrate and connected to the second anode 71, the second connection electrode 82 is disposed on a side of the first connection electrode 81 away from the substrate and connected to the first connection electrode 81, and the third connection electrode 83 is disposed on a side of the second connection electrode 82 away from the substrate and connected to the second connection electrode 82. The stacked first anode 70, the second anode 71, and the third anode 72 constitute an anode 74, and the stacked first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 constitute an auxiliary connection electrode 84, as shown in FIG. Fig.21 and Fig. 22 As shown, Fig. 22 for Fig.21 Cross-section view along the AA direction.

[0171] In an exemplary embodiment, in a plane parallel to the display substrate, the shapes of the second anode 71 and the third anode 72 are similar to the shape of the first anode 70, and the orthographic projection of the second anode 71 on the substrate may be located within the range of the orthographic projection of the first anode 70 on the substrate, and the orthographic projection of the second anode 71 on the substrate may be located within the range of the orthographic projection of the third anode 72 on the substrate. In a plane parallel to the display substrate, the shapes of the second connection electrode 82 and the third connection electrode 83 are similar to the shape of the first connection electrode 81, and the orthographic projection of the second connection electrode 82 on the substrate may be located within the range of the orthographic projection of the first connection electrode 81 on the substrate, and the orthographic projection of the second connection electrode 82 on the substrate may be located within the range of the orthographic projection of the third connection electrode 83 on the substrate.

[0172] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first connecting electrode 81 located on the side of the second connecting electrode 82 adjacent to the substrate (lower side) has an edge protruding from the outline of the second connecting electrode 82, forming a "roof" structure, and the third connecting electrode 83 located on the side of the second connecting electrode 82 away from the substrate (upper side) has an edge protruding from the outline of the second connecting electrode 82. The first connecting electrode 81 and the third connecting electrode 83 form an "eaves" structure, so that the stacked first connecting electrode 81, the second connecting electrode 82 and the third connecting electrode 83 form an "I" shape.

[0173] In an exemplary embodiment, the first anode 70 located on the side of the second anode 71 adjacent to the substrate (lower side) has an edge protruding from the contour of the second anode 71 to form a "roof" structure, and the third anode 72 located on the side of the second anode 71 away from the substrate (upper side) has an edge protruding from the contour of the second anode 71 to form an "eaves" structure, so that the stacked first anode 70, second anode 71 and third anode 72 form an "I" shape.

[0174] In an exemplary embodiment, during the patterning process of the fourth metal film and the second transparent conductive film, the first etching solution and the second etching solution can be used for etching respectively, and the "I"-shaped structure of the auxiliary electrode and the anode can be formed by drilling. In an exemplary embodiment, the first etching solution can be an etching solution for etching transparent conductive materials (ITO etching solution), and the second etching solution can be an etching solution for etching metal materials (Metal etching solution). In an exemplary embodiment, after the photoresist pattern is formed through masking, exposure and development of the photoresist, the etching process may include: firstly etching the second transparent conductive film not covered by the photoresist with the ITO etching solution, so that the area not covered by the photoresist exposes the fourth metal film, and forms the third anode 72 and the third connecting electrode 83 pattern. Subsequently, the exposed fourth metal film is etched with the Metal etching solution to form the second anode 71 and the second connecting electrode 82 pattern. Since the rate at which the Metal etching solution etches the fourth metal film is greater than the rate at which the first transparent conductive film and the second transparent conductive film are etched, the side surfaces of the second anode 71 and the second connecting electrode 82 are etched into pits. The first anode 70 below the second anode 71 and the third anode 72 above the second anode 71 both protrude a distance from the second anode 71 , and the first connection electrode 81 below the second connection electrode 82 and the third connection electrode 83 above the second connection electrode 82 protrude a distance from the second connection electrode 82 , forming an “I” shaped structure.

[0175] In an exemplary embodiment, the auxiliary electrode formed on a plane perpendicular to the display substrate has a plurality of exposed surfaces, and these exposed surfaces respectively include: a first upper surface of the first connection electrode 81 protruding from the second connection electrode 82 portion away from the substrate, a second side surface of the second connection electrode 82 side, a third upper surface of the third connection electrode 83 upper side (away from the substrate side), a third side surface of the third connection electrode 83 side, and a third lower surface of the third connection electrode 83 lower side (adjacent to the substrate side), the third lower surface refers to the surface of the third connection electrode 83 protruding from the second connection electrode 82 portion adjacent to the substrate side. In an exemplary embodiment, the aforementioned side surfaces refer to a plurality of circumferential surfaces whose normal direction is parallel or nearly parallel to the substrate plane, for example, in a plane parallel to the substrate, the second side surface of the rectangular second connection electrode 82 includes four circumferential surfaces.

[0176] In an exemplary embodiment, the fourth metal film material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, and the second transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO), etc.

[0177] (9) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film through a patterning process to form a pixel definition (PDL) layer 91 pattern, a first pixel opening K1 and a second auxiliary electrode opening K2 being opened on the pixel definition layer 91, the pixel definition layer 91 in the first pixel opening K1 being removed to expose a portion of the surface of the third anode 72 in the anode, and the pixel definition layer 91 in the second auxiliary electrode opening K2 being removed to expose the entire surface of the second connection electrode 82 and the third connection electrode 83 in the auxiliary connection electrode, as shown in FIG. Fig.23 and Fig.24 As shown, Fig.24 for Fig.23 Sectional view along AA direction.

[0178] In an exemplary embodiment, the orthographic projection of the first pixel opening K1 on the substrate is located within the range of the orthographic projection of the third anode 72 on the substrate, the orthographic projection of the second auxiliary electrode opening K2 on the substrate is located within the range of the orthographic projection of the first connection electrode 81 on the substrate, and the orthographic projections of the second connection electrode 82 and the third connection electrode 83 on the substrate are located within the range of the orthographic projection of the second auxiliary electrode opening K2 on the substrate. The second auxiliary electrode opening K2 exposes the entire surface of the second connection electrode 82 and the third connection electrode 83, which means that the second auxiliary electrode opening has a second lower opening adjacent to a side of the substrate and a second upper opening away from a side of the substrate, and the orthographic projections of the second connection electrode 82 and the third connection electrode 83 on the substrate are located within the range of the orthographic projection of the second lower opening on the substrate.

[0179] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. In a plane parallel to the display substrate, the shape of the first pixel opening K1 may be similar to the shape of the plurality of anode blocks, and the shape of the second auxiliary electrode opening K2 may be a rectangle. In a plane perpendicular to the display substrate, the cross-sectional shape of the first pixel opening K1 and the second auxiliary electrode opening K2 may be a rectangle or a trapezoid, etc.

[0180] (10) Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming the organic light-emitting layer pattern may include: evaporating an organic light-emitting material on the substrate formed with the aforementioned pattern to form an organic light-emitting layer 92 and an organic light-emitting block 93 pattern, wherein the organic light-emitting layer 92 is disposed in an area outside the third connection electrode 83, the organic light-emitting layer 92 is connected to the third anode 72 in the anode 74 through the first pixel opening K1, the organic light-emitting block 93 is disposed on a surface of the third connection electrode 83 away from the substrate, and the organic light-emitting block 93 is isolated from the organic light-emitting layer 92, such as Fig.25 shown.

[0181] In the exemplary embodiment, due to the "I"-shaped structure of the auxiliary electrode, the third connection electrode 83 protrudes a distance from the second connection electrode 82, so that the organic light-emitting material is disconnected at the side edge of the third connection electrode 83, and an organic light-emitting block 93 is formed on the second upper surface of the third connection electrode 83, and an organic light-emitting layer 92 is formed in the area outside the third connection electrode 83, so that the organic light-emitting layer 92 and the organic light-emitting block 93 are isolated from each other. In the exemplary embodiment, the orthographic projection of the organic light-emitting block 93 on the substrate can be approximately equal to the orthographic projection of the third connection electrode 83 on the substrate. The organic light-emitting layer is separated by the auxiliary electrode of the "I"-shaped structure to form an isolated and isolated organic light-emitting block, which effectively avoids the interference of the organic light-emitting block on the emitted light, improves the quality of the emitted light, and is conducive to improving the display quality.

[0182] In an exemplary embodiment, the organic light emitting layer 92 is connected to the third anode 72 through the first pixel opening K1, thereby realizing the connection between the organic light emitting layer 92 and the anode 74. The organic light emitting layer 92 located in the second auxiliary electrode opening K2 region covers the sidewall of the second auxiliary electrode opening K2 in part, and covers part of the bottom surface of the second auxiliary electrode opening K2 in another part, and forms a slope on the bottom surface of the second auxiliary electrode opening K2. In an exemplary embodiment, the organic light emitting layer 92 located on the bottom surface of the second auxiliary electrode opening K2 is at a certain distance from the second connection electrode 82, and the area between the organic light emitting layer 92 and the second connection electrode 82 exposes the first connection electrode 81.

[0183] In an exemplary embodiment, the organic light emitting layer may include an emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or by inkjet technology.

[0184] In an exemplary embodiment, the organic light-emitting layer may be prepared by the following preparation method. First, an open mask is used to sequentially evaporate a hole injection layer and a hole transport layer to form a common layer of the hole injection layer and the hole transport layer on a display substrate. Subsequently, a fine metal mask is used to evaporate an electron blocking layer and a red light-emitting layer in a red sub-pixel, an electron blocking layer and a green light-emitting layer in a green sub-pixel, and an electron blocking layer and a blue light-emitting layer in a blue sub-pixel. The electron blocking layer and the light-emitting layer of adjacent sub-pixels may have a small amount of overlap (for example, the overlapping portion occupies less than 10% of the area of ​​each light-emitting layer pattern), or may be isolated. Subsequently, an open mask is used to sequentially evaporate a hole blocking layer, an electron transport layer, and an electron injection layer to form a common layer of the hole blocking layer, the electron transport layer, and the electron injection layer on a display substrate.

[0185] In an exemplary embodiment, the electron blocking layer can be used as a microcavity adjustment layer of the light-emitting device. By designing the thickness of the electron blocking layer, the thickness of the organic light-emitting layer between the cathode and the anode can meet the design of the microcavity length. In some exemplary embodiments, the hole transport layer, the hole blocking layer or the electron transport layer in the organic light-emitting layer can be used as the microcavity adjustment layer of the light-emitting device, which is not limited in the present disclosure.

[0186] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, and the doping ratio of the guest material in the light-emitting layer is 1% to 20%. Within the doping ratio range, on the one hand, the host material of the light-emitting layer can effectively transfer the exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light, and on the other hand, the host material of the light-emitting layer "dilutes" the guest material of the light-emitting layer, effectively improving the mutual collision between the molecules of the guest material of the light-emitting layer, and the fluorescence quenching caused by the mutual collision between the energy, thereby improving the luminous efficiency and the life of the device. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage. In an exemplary embodiment, the host material and the guest material can be co-evaporated by a multi-source evaporation process, so that the host material and the guest material are uniformly dispersed in the light-emitting layer, and the doping ratio can be regulated by controlling the evaporation rate of the guest material during the evaporation process, or by controlling the evaporation rate ratio of the host material and the guest material. In an exemplary embodiment, the thickness of the light-emitting layer can be about 10nm to 50nm.

[0187] In an exemplary embodiment, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or may be made of a p-type dopant of a strong electron-withdrawing system and a dopant of a hole transport material. In an exemplary embodiment, the hole injection layer may have a thickness of about 5 nm to 20 nm.

[0188] In an exemplary embodiment, in an exemplary embodiment, the hole transport layer may be made of a material with high hole mobility, such as an aromatic amine compound, and its substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer may be about 40 nm to 150 nm.

[0189] In an exemplary embodiment, the hole blocking layer and the electron transport layer may be made of aromatic heterocyclic compounds, such as imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazolephenanthridine derivatives; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; compounds containing nitrogen-containing six-membered ring structures such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives (including compounds having phosphine oxide-based substituents on heterocyclic rings), etc. In an exemplary embodiment, the thickness of the hole blocking layer may be about 5nm to 15nm, and the thickness of the electron transport layer may be about 20nm to 50nm.

[0190] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg) or calcium (Ca), or a compound of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5 nm to 2 nm.

[0191] (11) Forming a cathode pattern. In an exemplary embodiment, forming a cathode pattern may include: evaporating a cathode material on the substrate on which the aforementioned pattern is formed to form a cathode 94 pattern, wherein the cathode 94 is connected to the organic light-emitting layer 92, and a large-area contact connection with the auxiliary connection electrode 84 is achieved by wrapping the organic light-emitting block 93 and the auxiliary connection electrode 84, as shown in FIG26.

[0192] In an exemplary embodiment, the cathode 94 may be an integral structure connected together. In the area outside the auxiliary connection electrode 84, the cathode 94 is disposed on the organic light-emitting layer 92. In the area where the auxiliary connection electrode 84 is located, the cathode 94 is disposed on the exposed surface of the organic light-emitting block 93 on the one hand, and on the exposed surface of the auxiliary connection electrode on the other hand, forming a structure that wraps the auxiliary connection electrode 84 and the organic light-emitting block 93.

[0193] like Fig.26 As shown, for the organic light-emitting block 93, a portion of the cathode 94 covers or partially covers the surface of the organic light-emitting block 93 on the side away from the substrate, and another portion of the cathode 94 covers or partially covers or partially covers the side surface of the organic light-emitting block 93. For the third connection electrode 83, the organic light-emitting block 93 covers or partially covers the surface of the third connection electrode 83 on the side away from the substrate, a portion of the cathode 94 covers or partially covers the second side surface of the third connection electrode 83, and another portion of the cathode 94 covers or partially covers the second lower surface of the lower side of the third connection electrode 83, that is, the cathode 94 covers or partially covers the lower surface of the third connection electrode 83 protruding from the second connection electrode 82. In this way, not only the connection between the cathode 94 and the third connection electrode 83 is achieved, but also the encapsulation of the organic light-emitting block 93 is achieved. Since the cathode 94 is connected to the third connection electrode 83 through the third side surface and the third bottom surface, the cathode 94 on the upper side of the organic light-emitting block 93 and the third connection electrode 83 on the lower side of the organic light-emitting block 93 have the same potential, that is, the potentials of the upper and lower sides of the organic light-emitting block 93 are equal, which ensures that the organic light-emitting block 93 does not emit light, and avoids the flickering phenomenon caused by the light emission of the organic light-emitting block 93. For the second connection electrode 82, the cathode 94 covers or partially covers the second side surface of the side of the second connection electrode 82. For the first connection electrode 81, the cathode 94 covers or partially covers the first connection electrode 81 exposed between the organic light-emitting layer 92 and the second connection electrode 82.

[0194] In the exemplary embodiment of the present disclosure, the cathode is connected to the side surface of the second auxiliary electrode through contact, which effectively increases the contact area between the cathode and the auxiliary electrode, effectively reduces the resistance at the contact interface, and improves the display effect.

[0195] At this point, the light-emitting structure layer pattern is prepared on the driving circuit layer. The light-emitting structure layer includes an anode, an auxiliary connection electrode, a pixel definition layer, an organic light-emitting layer and a cathode. The organic light-emitting layer is connected to the anode and the cathode, respectively, the cathode is connected to the auxiliary connection electrode, and the auxiliary connection electrode is connected to the second power line through the auxiliary cathode.

[0196] In an exemplary embodiment, the preparation process of the display substrate may further include forming an encapsulation layer pattern, and the formation of the encapsulation layer pattern may include: first using an open mask plate to deposit a first inorganic thin film by plasma enhanced chemical vapor deposition (PECVD) to form a first encapsulation layer. Subsequently, an organic material is inkjet printed on the first encapsulation layer by an inkjet printing process, and after curing into a film, a second encapsulation layer is formed. Subsequently, a second inorganic thin film is deposited using an open mask plate to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation layer. In an exemplary embodiment, the first encapsulation layer and the third encapsulation layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The second encapsulation layer may be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material, and the organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0197] In an exemplary embodiment, after the encapsulation layer is prepared, a color filter layer and a black matrix can be formed on another substrate by a patterning process to form a color filter cover plate, a frame sealant is applied on the surface of the color filter cover plate, and the color filter cover plate is pressed together with the above-mentioned display substrate to form a color filter cover plate. Figure 5 The OLED display panel shown, Figure 5 Only the black matrix BM is shown, and the color filter layer is not shown. The black matrix has a plurality of opening areas arranged in a matrix, and the color filter layer is filled in the opening areas.

[0198] In other exemplary embodiments, the color filter layer and the black matrix can also be prepared on the display substrate. In this case, the color filter layer and the black matrix can be prepared after the cathode is formed and before the encapsulation layer is formed. By providing the black matrix, light crosstalk between adjacent sub-pixels can be effectively prevented, color mixing can be avoided, and the display effect can be improved.

[0199] Combination Figure 5 to Figure 26In each sub-pixel, the first active layer 11, the first gate electrode 12, the first source electrode 13 and the first drain electrode 14 constitute a first transistor T1, the second active layer 21, the second gate electrode 22, the second source electrode 23 and the second drain electrode 24 constitute a second transistor T2, the third active layer 31, the third gate electrode 32, the third source electrode 33 and the third drain electrode 34 constitute a third transistor T3, the first electrode plate 41 and the second electrode plate 42 constitute a first storage capacitor, the second electrode plate 42 and the third electrode plate 43 constitute a second storage capacitor, and the first storage capacitor and the second storage capacitor are in a parallel structure to store the potential of the second gate electrode 22 of the sub-pixel. The first transistor T1, the second transistor T2, the third transistor T3, the first storage capacitor and the second storage capacitor in the first sub-pixel P1 and the second sub-pixel P2 are mirror-symmetrical with respect to the compensation signal line S, and the first transistor T1, the second transistor T2, the third transistor T3, the first storage capacitor and the second storage capacitor in the third sub-pixel P3 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the compensation signal line S.

[0200] In each sub-pixel, the first gate electrode 12 is connected to the first scanning signal line G1, the first source electrode 13 is connected to the data signal line D, and the first drain electrode 14 is connected to the second gate electrode 22 of the sub-pixel. The second gate electrode 22 is connected to the first drain electrode 14 of the sub-pixel, the second source electrode 23 is connected to the first power line VDD through the horizontal power connection line 52, and the second drain electrode 24 is connected to the anode of the sub-pixel. The third gate electrode 32 is connected to the second scanning signal line G2, the third source electrode 33 is connected to the compensation signal line S, and the third drain electrode 34 is connected to the second drain electrode 24 of the sub-pixel. The first electrode plate 41 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel, the second electrode plate 42 is connected to the second gate electrode 22 and the first drain electrode 14 of the sub-pixel, and the third electrode plate 43 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel. The anode 74 is connected to the second drain electrode 24 of the sub-pixel where it is located, and the cathode 94 covering all sub-pixels is connected to the second power line VSS through the auxiliary cathode 80 of the transparent area 200 and the auxiliary connecting electrode 84, so that the organic light-emitting layer 92 between the anode 74 and the cathode 94 responds to the current of the second drain electrode 24 of the sub-pixel where it is located and emits light of corresponding brightness.

[0201] In an exemplary embodiment, the first conductive layer, the second conductive layer and the third conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer is called a gate insulating (GI) layer, the third insulating layer is called an interlayer insulating (ILD) layer, and the fourth insulating layer is called a passivation (PVX) layer. The thickness of the second insulating layer is less than the thickness of the third insulating layer, and the thickness of the first insulating layer is less than the sum of the thickness of the second insulating layer and the third insulating layer, so as to improve the capacity of the storage capacitor while ensuring the insulation effect. The planar layer may be made of organic materials, the transparent conductive film may be made of indium tin oxide ITO or indium zinc oxide IZO, and the pixel definition layer may be made of polyimide, acrylic or polyethylene terephthalate. The cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0202] In some possible implementations, the thickness of the first insulating layer is 3000 angstroms to 5000 angstroms, the thickness of the second insulating layer is 1000 angstroms to 2000 angstroms, the thickness of the third insulating layer is 4500 angstroms to 7000 angstroms, and the thickness of the fourth insulating layer is 3000 angstroms to 5000 angstroms. The thickness of the first conductive layer is 80 angstroms to 1200 angstroms, the thickness of the second conductive layer is 3000 angstroms to 5000 angstroms, and the thickness of the third conductive layer is 3000 angstroms to 9000 angstroms.

[0203] In an exemplary embodiment, the semiconductor layer may adopt an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0204] like Figure 5 to Figure 26 As shown, the display substrate provided by the present disclosure includes:

[0205] Base 10;

[0206] A first conductive layer is provided on the substrate 10, and the first conductive layer includes a first electrode plate 41 and a compensation signal line S;

[0207] A first insulating layer 61, covering the first conductive layer;

[0208] A semiconductor layer disposed on the first insulating layer 61, the semiconductor layer comprising a first active layer 11, a second active layer 21 and a third active layer 31;

[0209] A second insulating layer 62 and a second conductive layer disposed on the second insulating layer 62, the second conductive layer comprising: a first scanning signal line G1, a second scanning signal line G2, a second electrode plate 42, a longitudinal power connection line 51, a transverse power connection line 52, an auxiliary power line 53, a first gate electrode 12, a second gate electrode 22 and a third gate electrode 32, the second insulating layer 62 has the same pattern as the second conductive layer; an orthographic projection of the second electrode plate 42 on the substrate 10 and an orthographic projection of the first electrode plate 41 on the substrate 10 have an overlapping area, and the second electrode plate 42 and the first electrode plate 41 form a first storage capacitor;

[0210] A third insulating layer 63 covering the second conductive layer, with a plurality of via holes respectively formed thereon;

[0211] The third conductive layer and the auxiliary cathode 80 are arranged on the third insulating layer 63, and the third conductive layer includes a first power line VDD, a second power line VSS, a data signal line D, a third scan connection line 54, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34 and a third electrode plate 43. The first power line VDD is connected to the longitudinal power connection line 51 through the eleventh via hole V11, and is connected to the transverse power connection line 52 through the twelfth via hole V12. The second power line VSS is connected to the auxiliary power line 53 through the seventh via hole V7, and the first source electrode 13 is connected to the data signal line D is an integrated structure, the second source electrode 23 is connected to one end of the second active layer 21 through the third via hole V3, the third source electrode 33 is connected to the compensation signal line S through the eighth via hole V8, the first drain electrode 14 is connected to the second gate electrode 22 and the second electrode plate 42 through the ninth via hole V9, the second drain electrode 24, the third drain electrode 34 and the third electrode plate 43 are an integrated structure connected to each other, the third electrode plate 43 is connected to the first electrode plate 41 through the tenth via hole V10, the orthographic projection of the third electrode plate 43 on the substrate 10 and the orthographic projection of the second electrode plate 42 on the substrate 10 have an overlapping area, and the second electrode plate 42 and the third electrode plate 43 form a second storage capacitor;

[0212] A fourth insulating layer 64 and a planar layer 65 covering the third conductive layer, each of which has a plurality of via holes;

[0213] An anode 74 and an auxiliary connection electrode 84 are provided on the flat layer 65, wherein the anode 74 includes a first anode 70, a second anode 71 and a third anode 72 stacked together, and the auxiliary connection electrode 84 includes a first connection electrode 81, a second connection electrode 82 and a third connection electrode 83 stacked together, wherein the first anode 70 is connected to the drain electrode of the second transistor through a sixteenth via hole V16, and the first connection electrode 81 is connected to the auxiliary cathode 80 through an eighteenth via hole V18;

[0214] A pixel definition layer 91 is disposed on the planar layer 65, wherein the pixel definition layer 91 defines a first pixel opening exposing the anode in each sub-pixel, and the pixel definition layer 91 defines a second auxiliary electrode opening exposing the auxiliary connection electrode 84 in the second power line VSS and the transparent area;

[0215] An organic light-emitting layer 92 is disposed in the first pixel opening region and an organic light-emitting block 93 is disposed in the second auxiliary electrode opening region, the organic light-emitting layer 92 is connected to the anode, and the organic light-emitting block 93 is isolated from the organic light-emitting layer 92;

[0216] The cathode 94 of the display area 100 is connected to the organic light emitting layer 92 , and the second power line VSS and the cathode 94 of the transparent area 200 are connected to the auxiliary cathode 80 through the auxiliary connection electrode 84 ;

[0217] An encapsulation layer covers the above structure.

[0218] The structure and preparation process shown in the present disclosure are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the display area can include 3 sub-pixels. For another example, the pixel driving circuit can be 5T1C or 7T1C. For another example, other electrodes or leads can be provided in the film structure, which is not specifically limited in the present disclosure.

[0219] It can be seen from the structure and preparation process of the display substrate described above that the display substrate provided by the present disclosure increases the success rate of overlapping of the auxiliary connection electrodes by setting multiple auxiliary connection electrode nodes on the transparent area and the second power line, and the multiple auxiliary connection electrode nodes are evenly distributed in the pixel, thereby ensuring that the voltage drop of the cathode meets the product requirements.

[0220] In addition, by setting a plurality of auxiliary connection electrode nodes in the transparent area, the transparent area is changed into an irregular shape. When the light passes through the irregular transparent area, the diffraction stripes are generated in different directions due to the different positions of the diffraction stripes. Therefore, the diffraction stripes generated by the light will not diffuse in one direction, but in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect. Simulations show that when the auxiliary connection electrodes are not set, the brightness uniformity of the sub-pixels of different colors on the display substrate is poor. After the auxiliary connection electrodes are set according to the method disclosed in the present invention, the brightness uniformity of the sub-pixels of different colors on the display substrate is significantly improved.

[0221] The display substrate provided by the present disclosure can also effectively alleviate the voltage drop of large-size transparent display by setting an auxiliary connection electrode connected to the cathode of the light-emitting element in the transparent area, thereby ensuring display uniformity, simplifying the structural layout of the display area, reducing the occupied space of each sub-pixel, increasing the area ratio of the transparent area, and improving resolution and transparency.

[0222] The display substrate provided by the present disclosure adopts a second electrode plate made of a metal oxide material as the electrode plate of the storage capacitor. The second electrode plate forms a storage capacitor with the first electrode plate in the first conductive layer and the third electrode plate in the third conductive layer respectively. The first electrode plate and the third electrode plate have the same potential, and the second electrode plate has a potential different from that of the first electrode plate and the third electrode plate. Therefore, two parallel storage capacitors are formed between the first electrode plate, the second electrode plate and the third electrode plate, which effectively increases the capacity of the storage capacitor and is conducive to achieving high-resolution display.

[0223] The preparation process disclosed in the present invention can be realized by using existing mature preparation equipment, with little improvement on the existing process, and can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0224] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0225] The exemplary embodiments of the present disclosure further provide a method for preparing a display substrate, wherein the display substrate may include a plurality of sub-pixels; the preparation method may include:

[0226] A plurality of display units are formed on a substrate, at least one of the display units comprises a display area and a transparent area, at least one of the display areas is provided with a first power line, a compensation signal line, and a second power line along a first direction, the first power line, the compensation signal line and the second power line extend along a second direction, the compensation signal line is provided between the first power line and the second power line, at least one of the display areas is provided with a compensation connection line in the middle along the second direction, the compensation connection line extends along the first direction, the compensation connection line and the compensation signal line are connected to each other, and the first direction intersects with the second direction; at least one of the transparent areas comprises a plurality of auxiliary cathodes and a plurality of auxiliary connection electrodes, the auxiliary cathodes are connected to each other with the second power line, and the plurality of auxiliary connection electrodes are symmetrically arranged relative to the compensation connection line, wherein a part of the auxiliary connection electrodes are connected to the second power line, and another part of the auxiliary connection electrodes are connected to the auxiliary cathode.

[0227] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: The device comprises a plurality of display units, at least one of the display units comprises a display area and a transparent area, at least one of the display areas comprises a plurality of sub-pixels, each sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises a third transistor; At least one of the display areas is provided with a first power line, a compensation signal line, and a second power line along a first direction, the first power line, the compensation signal line, and the second power line extend along a second direction, the compensation signal line is provided between the first power line and the second power line, at least one of the display areas is provided with a compensation connection line in the middle along the second direction, the compensation connection line extends along the first direction, the compensation connection line and the compensation signal line are connected to each other, the first direction intersects with the second direction, and the compensation connection line is connected to a first electrode of a third transistor in each sub-pixel of the display area; At least one of the transparent areas includes multiple auxiliary cathodes and multiple auxiliary connecting electrodes, the auxiliary cathodes are interconnected with the second power line, and the multiple auxiliary connecting electrodes are symmetrically arranged relative to the compensation connecting line, wherein a part of the auxiliary connecting electrodes are connected to the second power line, and another part of the auxiliary connecting electrodes are connected to the auxiliary cathodes.

2. The display substrate according to claim 1, characterized in that: The multiple sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel. In the first direction, the first sub-pixel and the second sub-pixel are alternately arranged to form a first row, and the third sub-pixel and the fourth sub-pixel are alternately arranged to form a second row; in the second direction, the first sub-pixel and the third sub-pixel are alternately arranged to form a first column, and the second sub-pixel and the fourth sub-pixel are alternately arranged to form a second column.

3. The display substrate according to claim 1, characterized in that: In a direction perpendicular to the display substrate, the sub-pixel includes a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer; The first conductive layer includes the compensation signal line, the compensation connection line and the first electrode plate, the semiconductor layer includes an active layer of multiple transistors, the second conductive layer includes a first scanning signal line, a second scanning signal line, a second electrode plate and gate electrodes of multiple transistors, the third conductive layer includes the auxiliary cathode, the first power line, the second power line, a data signal line and source electrodes and drain electrodes of multiple transistors, and an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate to form a first storage capacitor; The light emitting structure layer includes an anode, and the auxiliary connection electrode is arranged in the same layer as the anode.

4. The display substrate according to claim 3, characterized in that: The second conductive layer further includes a first scanning connection line and a second scanning connection line, and the third conductive layer further includes a third scanning connection line, wherein: The first scanning connection line and the second scanning connection line are located in the first sub-pixel and the second sub-pixel, the first scanning signal line and the second scanning signal line are located in the third sub-pixel and the fourth sub-pixel, and the second scanning connection line and the second scanning signal line are connected to each other to form an integrated structure; The third scan connection line is connected to the first scan connection line and the first scan signal line through via holes.

5. The display substrate according to claim 3, characterized in that: The second conductive layer further comprises a horizontal power connection line and a vertical power connection line, wherein: The longitudinal power connection line extends along the second direction, the orthographic projection of the longitudinal power connection line on the substrate is located within the range of the orthographic projection of the first power line on the substrate, and the first power line is connected to the longitudinal power connection line through a via hole to form a double-layer first power line; The transverse power connection line extends along the first direction, and the first power line is connected to the transverse power connection line through a via.

6. The display substrate according to claim 3, characterized in that: The second conductive layer also includes an auxiliary power line, which extends along the second direction. The orthographic projection of the auxiliary power line on the substrate is within the range of the orthographic projection of the second power line on the substrate. The second power line is connected to the auxiliary power line through a via to form a double-layer second power line.

7. The display substrate according to claim 3, characterized in that: The third conductive layer further includes a third electrode plate, an orthographic projection of the third electrode plate on the substrate overlaps with an orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via.

8. The display substrate according to claim 3, characterized in that: The driving circuit layer includes a first transistor, a second transistor and a third transistor, the gate electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the first electrode of the organic electroluminescent diode, the gate electrode of the third transistor is connected to the second scanning signal line, the first electrode of the third transistor is connected to the compensation signal line through a compensation connection line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line; the first electrode plate is connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.

9. The display substrate according to claim 3, characterized in that: The auxiliary connecting electrode includes a first connecting electrode, a second connecting electrode located on a side of the first connecting electrode away from the substrate, and a third connecting electrode located on a side of the second connecting electrode away from the substrate. The anode includes a first anode, a second anode located on a side of the first anode away from the substrate, and a third anode located on a side of the second anode away from the substrate. The first anode is arranged on the same layer as the first connecting electrode, the second anode is arranged on the same layer as the second connecting electrode, and the third anode is arranged on the same layer as the third connecting electrode. The first anode, the second anode and the third anode form an "I"-shaped structure, and the first connecting electrode, the second connecting electrode and the third connecting electrode form an "I"-shaped structure.

10. A display device, characterized in that: include: A display substrate as claimed in any one of claims 1 to 9.

11. A method for preparing a display substrate, characterized in that: include: A plurality of display units are formed on a substrate, at least one of the display units comprises a display area and a transparent area, at least one of the display areas comprises a plurality of sub-pixels, each sub-pixel comprises a pixel driving circuit, the pixel driving circuit comprises a third transistor, at least one of the display areas is provided with a first power line, a compensation signal line, and a second power line along a first direction, the first power line, the compensation signal line, and the second power line extend along a second direction, the compensation signal line is provided between the first power line and the second power line, at least one of the display areas is provided with a compensation connection line in the middle of the second direction, the compensation connection line extends along the first direction, the compensation connection line is connected to the compensation signal line, the first direction intersects with the second direction, and the compensation connection line is connected to the first electrode of the third transistor in each sub-pixel of the display area; at least one of the transparent areas comprises a plurality of auxiliary cathodes and a plurality of auxiliary connection electrodes, the auxiliary cathodes are connected to the second power line, and the plurality of auxiliary connection electrodes are symmetrically arranged relative to the compensation connection line, wherein, A portion of the auxiliary connection electrodes is connected to the second power line, and another portion of the auxiliary connection electrodes is connected to the auxiliary cathode.

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