Trenches having different cross-sectional widths

Abstract

A semiconductor device includes a trench in a semiconductor material, the trench having a device section and a termination section. A gate structure is located in the trench. In some embodiments, the termination section has a cross-sectional width that is wider than a cross-sectional width of the device section.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more specifically, to transistors having a gate structure in a trench. Background Technology

[0002] Some types of transistors include transistor structures located in trenches within a substrate. For example, some types of transistors include gate structures and field plate structures located in trenches. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device includes:

[0004] A substrate, the substrate comprising a semiconductor material and trenches located in the semiconductor material;

[0005] A source region, located in the semiconductor material relative to a first side of the trench;

[0006] A gate structure located in the trench;

[0007] The trench area includes a portion positioned along a first vertical component sidewall of the trench, the first vertical component sidewall being positioned relative to a first side of the trench.

[0008] The trench includes a device segment, wherein the gate structure is located at least in the device segment, and the trench has a first cross-sectional width at a first location in the device segment;

[0009] The trench includes a terminal section, wherein the trench has a second cross-sectional width at a second location in the terminal section that is wider than the first cross-sectional width.

[0010] Optionally, the terminal section of the trench has a curved shape.

[0011] Optionally, the semiconductor device includes a drift region, the drift region including at least a portion located directly below the trench.

[0012] Optionally, the width of the second cross section is at least 10% wider than the width of the first cross section.

[0013] Optionally, the width of the second cross section is wider than the width of the first cross section by a ratio, wherein the ratio is in the range of 10%-200% of the width of the first cross section.

[0014] Optionally, the semiconductor device further includes:

[0015] Drain region, the drain region including a portion of a second side of the semiconductor material located on the upper surface of the trench opposite to the first side.

[0016] Optionally, the first cross-sectional width has a first orientation, and the second cross-sectional width has a second orientation orthogonal to the first orientation.

[0017] Optionally, the trench includes a second device segment, wherein a second gate structure is located at least in the second device segment, and the termination segment is positioned along the trench between the device segment and the second device segment.

[0018] Optionally, the trench has a third cross-sectional width at a third location in the second device segment.

[0019] Optionally, the trench includes a second terminal section, wherein the trench has a fourth cross-sectional width at a fourth position in the second terminal section that is wider than the third cross-sectional width.

[0020] Optionally, the device segment of the trench extends in a first orientation, and the second device segment extends in an orientation parallel to the first orientation.

[0021] Optionally, the terminal section of the trench has a curved shape.

[0022] Optionally, the semiconductor device further includes a field plate structure located in the trench at the first and second positions.

[0023] Optionally, the gate structure is not located at the second position.

[0024] Optionally, the field plate structure includes an upper portion in the second position, the upper portion being laterally positioned relative to the gate structure in the first position.

[0025] Optionally, in the first position, the gate structure is located directly above the field plate structure.

[0026] Optionally, the field plate structure is positioned closer to the first vertical component sidewall of the trench than to the second vertical component sidewall opposite to the trench.

[0027] Optionally, the semiconductor device further includes a dielectric that physically separates the gate structure from the field plate structure at the first location.

[0028] Optionally, the gate structure is positioned closer to the first vertical component sidewall of the trench than to the second vertical component sidewall opposite to the trench.

[0029] Optionally, the width of the second cross section is wider than the width of the first cross section by a ratio, wherein the ratio is in the range of 40%-60% of the width of the first cross section.

[0030] Optionally, the gate structure is not located at the second position.

[0031] In one or more embodiments, a semiconductor device includes:

[0032] A substrate, the substrate comprising a semiconductor material and trenches located in the semiconductor material;

[0033] A source region, located in the semiconductor material relative to a first side of the trench;

[0034] Drain region, the drain region including at least a portion of a second side of the trench that is opposite to the first side of the trench located in the semiconductor material;

[0035] A gate structure located in the trench;

[0036] A field plate structure, wherein the field plate structure is located in the trench;

[0037] The trench area includes a portion positioned along a first vertical component sidewall of the trench, the first vertical component sidewall being positioned relative to a first side of the trench.

[0038] The trench includes a device segment, wherein the gate structure is located at least in the device segment, and the trench has a first cross-sectional width at a first location in the device segment;

[0039] The trench includes a terminal section, wherein the trench has a second cross-sectional width at a second location in the terminal section that is at least 10% wider than the first cross-sectional width, the gate structure is not located at the second location, and the field plate structure is located at the second location. Attached Figure Description

[0040] The invention will be better understood by referring to the accompanying drawings, and many of its objectives, features and advantages will become apparent to those skilled in the art.

[0041] Figure 1 , 2 Partial cross-sectional side views of various stages in the manufacture of a semiconductor device according to an embodiment of the present invention are illustrated in 4-11, 13, 14, 16, 17 and 19-22.

[0042] Figure 3 , 12 Pages 15, 18, and 23 illustrate partial top views of various stages in the manufacture of a semiconductor device according to an embodiment of the present invention.

[0043] Figure 24-25 A partial cross-sectional side view illustrating various stages of manufacturing a semiconductor device according to another embodiment of the present invention is provided.

[0044] Figure 26-27 A partial cross-sectional side view illustrating various stages of manufacturing a semiconductor device according to another embodiment of the present invention is provided.

[0045] Unless otherwise specified, the same reference numerals are used in different figures to refer to the same objects. The figures are not necessarily drawn to scale. Detailed Implementation

[0046] The following provides a detailed description of the modes used to carry out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0047] As disclosed in some embodiments herein, a semiconductor device includes a trench in a semiconductor material having a device segment and a termination segment. In some embodiments, the cross-sectional width of the termination segment is wider than the cross-sectional width of the device segment. In some embodiments, a trench with a larger cross-sectional width in the termination segment can improve the breakdown voltage by compensating for different doping levels caused by curved surfaces in the termination. Because drift regions are formed by implanting ions at an angle through trench openings in a self-aligned manner, higher or lower levels of dopant can accumulate due to the geometry of the trench layout. Without such compensation, deviations from the target doping concentration can result in lower breakdown voltages in the termination regions. The target doping concentration is determined by optimizing the performance of the internal device.

[0048] In some embodiments, the methods described herein can provide a simplified process for forming a transistor having a gate structure and a field plate structure located in a trench, wherein the gate structure and the field plate structure are positioned closer to one sidewall of the trench than to one sidewall of the trench. In some embodiments, more dielectric material can be positioned between the gate and field plate and the drain sidewall of the trench than to the source sidewall of the trench to accommodate a larger potential difference between the drain and the source or gate connected to the field plate.

[0049] Figure 1 , 2 Tables 4-11, 13, 14, 16, 17, and 19-22 illustrate partial cross-sectional side views of various stages in the manufacture of a semiconductor device according to one embodiment, and Figure 3 , 12Pages 15, 18, and 23 illustrate partial top views of various stages in the manufacture of a semiconductor device according to one embodiment. Figure 1 , 4 6, 8, 10, 13, 16, 19 and 21 are partial cross-sectional side views at one location of wafer 101. Figure 2 , 5 Photos 7, 9, 11, 14, 17, 20, and 22 are partial cross-sectional side views at a second location on wafer 101. See also the images showing both locations. Figure 3 , 12 15, 18, and 23. As shown in the figure, in the top view, the two positions are orthogonal to each other.

[0050] Figure 1 and 2 This is a partial cross-sectional side view showing the top portion of the wafer 101 in which the trench 117 is formed. Figure 3 This is a partial top view of chip 101, showing... Figure 1 and 2 The location of the cross-sectional view. For example... Figure 3 As shown, Figure 1 and 2 The cross-sectional views are orthogonal to each other.

[0051] In one embodiment, wafer 101 includes a semiconductor substrate 105. In one embodiment, substrate 105 is made of single-crystal silicon, but in other embodiments, it may be made of other semiconductor material types (e.g., silicon-germanium, germanium, silicon carbide, gallium nitride, gallium arsenide, other group III-V semiconductor materials, or combinations thereof). In some embodiments, a portion of the shown substrate 105 may be epitaxially grown from a base substrate (not shown). In one embodiment, a portion of the shown substrate 105 is doped with boron and has a net p-type conductivity concentration of about 2e15 cm⁻³, but in other embodiments, the portion may be doped with other types of dopants and / or may be at other concentrations. In some embodiments, the epitaxially grown portion may be in-situ doped. In other embodiments, the top portion of substrate 105 is doped by ion implantation. In some embodiments, substrate 105 may include different layers of different semiconductor material types, may include different doped regions (not shown), and / or may include, for example, a buried dielectric layer (not shown) having a semiconductor-on-insulator (SOI) wafer.

[0052] A hard mask that will subsequently define trench openings is formed on substrate 105 using appropriate materials and processes. Figure 1 and 2In one embodiment shown, the hard mask may consist of a pad oxide layer 107, a nitride layer 109, and an oxide layer 111. In one embodiment, the oxide layer 107 has a thickness of 0.1 μm, the nitride layer 109 has a thickness of 0.1 μm, and the oxide layer has a thickness of 0.1 μm, but in other embodiments these layers may have other thicknesses.

[0053] After forming layers 107, 109, and 111, trench 117 is formed in wafer 101. In one embodiment, trench 117 has a depth of 4 μm, but in other embodiments it may have other depths. In one embodiment, trench 117 is formed by forming a patterned mask (not shown) on wafer 101 and then etching hard mask layers 111, 109, and 107 according to the pattern using appropriate etching chemicals. In one embodiment, the etching is anisotropic dry etching. In other embodiments, other types of hard mask layers may be used to form trench 117. After etching the hard mask openings, substrate 105 is etched to form trench 117. In one embodiment, the etching is reactive ion etching. Figure 1 and 2 As shown, the trench 117 includes a vertical component sidewall 130 and a vertical component sidewall 132.

[0054] In the illustrated embodiment, Figure 2 In the cross-sectional view, the cross-sectional width of the groove 117 is 122, for example... Figure 1 The cross-sectional width shown in the view is 120 mm. As used herein, the cross-sectional width of a trench location is the minimum cross-sectional width at the widest portion of the trench at said location, generally parallel to any direction of the main sidewall of the wafer. In the illustrated embodiment, the widest portion of trench 117 is at the top surface, where the trench narrows towards the bottom. When the trench is at a certain location (e.g., at...), Figure 1 When the cross-section has an orientation that extends in a straight line, the cross-sectional width is at an angle that is perpendicular to the direction of the trench extension (at other angles, the cross-sectional width will be wider). Figure 1 and 2 The cross-sectional widths of 120 and 122 at these locations are shown respectively.

[0055] like Figure 3 As shown in the embodiment, the groove 117 has an elliptical annular shape, wherein the cross-sectional width of the groove 117 at the terminal regions 301 and 303 is wider than the cross-sectional width at the device regions 305 and 307. In one embodiment, at device regions 305 and 307, the width is 120 (see...). Figure 1 The value is 1.0 μm, and at the end regions 301 and 303, the width is 122 (see...). Figure 2The width is 1.5 μm. In some embodiments, the width 122 is at least 10% larger than the width of the cross-sectional width 120. In other embodiments, the width 122 is at least 30% larger than the width of the cross-sectional width 120. In other embodiments, the width 122 is in the range of 10% to 200% larger than the width of the cross-sectional width 120. In other embodiments, the width 122 is in the range of 40% to 60% larger than the width of the cross-sectional width 120.

[0056] In other embodiments, the trench can have different shapes (e.g., circular, open horseshoe, line segment). In the illustrated embodiment, trench 117 surrounds the source post 119 of substrate 105. As shown in subsequent embodiments, the source region of the transistor ( Figure 21 2133) will be formed in pillar 119, and drain region 2135 will be formed outside trench 117.

[0057] After forming region 117, wafer 101 undergoes an oxidation process to form an oxide layer 125 on the sidewalls of trench 117. In one embodiment, layer 125 has a thickness of 0.01 μm, but in other embodiments it may have other thicknesses.

[0058] After trench 117 is formed, wafer 101 is implanted with an N-type ion dopant to form the drift region 121 of an n-type LDMOS transistor. In other embodiments, wafer 101 is implanted with a P-type dopant to form the drift region of a p-type LDMOS transistor. In one embodiment, region 121 is doped with an N-type dopant, such as phosphorus, at a dose of about 1e13 cm⁻² and an energy of 80 keV, and with a P-type dopant, such as boron, at a dose of 1e12 cm⁻² and an energy of 20 keV, but in other embodiments, other dopants may be used at other energies and / or other concentrations. In the illustrated embodiment, layers 107, 109, and 111 act as implantation masks to prevent ion implantation into other regions of substrate 105. In one embodiment, ions are implanted at a 35-degree angle, but in other embodiments, ions may be implanted at other angles. After implantation, wafer 101 is annealed to drive ions into the illustrated region of the ions.

[0059] from Figure 3It is understandable that, since the volume of each trench surface area is smaller than that in the internal device regions 305 and 307, if dopant is uniformly injected along the trench sidewalls, the dopant density on the convex surfaces of pillars 119 in terminal regions 301 and 303 will be excessively high, resulting in higher doping density after diffusion. In contrast, since the volume of each trench surface area is larger than that in device regions 305 and 307, the concave trench surface on the outer side of trench 117 will produce a lower doping density after diffusion. It is desirable that the dopant density on the inner and outer regions of device regions 305 and 307 be similar. The effect of uneven doping in terminal regions 301 and 303 on breakdown voltage can be offset by increasing the trench width in the terminal regions.

[0060] Figure 4 and 5 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 4 and 5 Wafer 101 is shown with an oxide conformal layer 401, followed by a field plate material conformal layer 403 deposited on top of wafer 101. In one embodiment, oxide layer 401 has a thickness of 0.3 μm and is deposited by chemical vapor deposition. However, in other embodiments, layer 401 may be formed by other processes (e.g., oxidation processes) or combinations thereof, have other thicknesses, and / or be made of other materials (e.g., another dielectric material). In one embodiment, layer 401 has a thickness to accommodate the subsequently formed field plate structure (e.g., Figure 6 Sufficient spacing is provided between the substrate 105 in the bottom portion of the trench (e.g., 117) and the sidewall 130 of the substrate 105, thereby providing a field dielectric thickness that can be optimized for breakdown voltage (BV) and on-resistance (RonA).

[0061] Layer 403 is a conductive field plate material layer, which in one embodiment is doped with polycrystalline silicon, but in other embodiments may be other materials. In one embodiment, layer 403 is formed by chemical vapor deposition and has a thickness of about 0.25 μm, but in other embodiments it may be formed by other methods and / or have other thicknesses.

[0062] Figure 6 and 7 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 6 and 7The illustration shows a wafer 101 after layer 403 has been anisotropically etched to separate layer 403 in trench 117 into field structure structures 603 and 607. In one embodiment, layer 403 is etched with an etching chemical that is selective to the material of layer 403 (e.g., polysilicon) and selective to the material of layer 401 (e.g., oxide), such that the oxide is etched at a negligible rate. In the illustrated embodiment, layer 403 is etched for a period of time such that material of layer 403 is removed from outside the trench 117 above the top surface of layer 401. The etching removes a portion of layer 403 located at the bottom of trench 117 to physically separate layer 403 into two trench structures. Etching may also cause the top portions of structures 603 and 607 to be recessed.

[0063] Figure 8 and 9 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 8 and 9 The diagram shows a partial side view after trench 117 is filled with a dielectric material (e.g., oxide) and wafer 101 has been planarized to remove layer 111. The planarization forms a dielectric material structure 801 between field plate structures 603 and 607.

[0064] Figure 10 and 11 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 10 and 11 This is a partial side view showing trench 1001 formed in a selective region of trench 117 within a portion of dielectric material structure 801, the top portion of structure 603, and a portion of layer 401. It should be noted that... Figure 11 In the view, trench 1001 is not formed. Figure 11 In one embodiment, a trench 1001 is formed by forming a mask (not shown) over a wafer 101, the wafer 101 having an opening above the trench 1001. The wafer 101 is then subjected to anisotropic plasma etching with an etching chemical that etches both polysilicon and oxide. However, in other embodiments, the wafer 101 is subjected to two separate etching processes, one with an etching chemical that etches oxide and the other with an etching chemical that etches polysilicon. After the trench 1001 is formed, the mask is removed.

[0065] Figure 12 This is a partial top view of wafer 101, showing the same stage. Figure 11 and 12 The location of the cross-sectional view. For example... Figure 12 As shown, trench 1001 and trench 1003, similar to trench 1001, are formed only in device regions 307 and 305, respectively. In most cases, they are not located in terminal regions 301 and 303.

[0066] Figure 13 and 14 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 13 and Figure 14 The diagram shows a wafer 101 after a gate structure 1305 has been formed in a trench 1001. In one embodiment, the gate structure 1305 is formed by planarizing the wafer 101 by forming a gate material (e.g., doped polysilicon) layer over the wafer 101 and utilizing layer 109 as a planarization stop layer. Prior to depositing the gate material, the wafer 101 undergoes an oxidation process, wherein a gate dielectric 1031 is formed on the sidewall 130 and a dielectric 1303 is formed on the top portion of structure 603 to provide dielectric separation from the gate structure 1305. In some embodiments, dielectrics 1301 and 1303 are formed by depositing dielectric layers (not shown) on the wafer 101 included in the trench 1001.

[0067] Figure 15 This is a partial top view of wafer 101, showing the same stage. Figure 13 and 14 The location of the cross-sectional view. For example... Figure 15 As shown, a gate structure 1305 is formed in a trench 1001, and a second gate structure 1501 is formed in a trench 1003.

[0068] Figure 16 and 17 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 16 and 17 The diagram shows a wafer 101 after the conductive structure 607 has been removed and a dielectric structure 1601 has been formed in its place. In one embodiment, a patterned mask (not shown) is formed over the wafer 101, which has openings for exposing structure 601 but not gate structure 1305 or structure 603. Structure 607 is then removed with appropriate etch chemicals, leaving oxide structure 801 intact. In one embodiment, a dielectric material layer is deposited over the wafer 101, which fills or at least partially fills the openings left by the removal of structure 607. Layer 109 is then used as an etch stop layer to planarize the wafer 101, thereby forming the dielectric structure 1601.

[0069] Figure 18 This is a partial top view of wafer 101, showing the same stage. Figure 16 and 17 The location of the cross-sectional view. Figure 18 The location of dielectric structure 1601 is shown.

[0070] Figure 19 and 20 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 19 and 20 The image shows wafer 101 after the nitride layer 109 and oxide pad layer 107 have been stripped using appropriate etch chemicals to remove these layers. During the removal of layer 107, the top portion of oxide structure 801 and dielectric structure 1601 are also removed from the oxide etching. Wafer 101 is then subjected to an oxidation process to form oxide layer 1901 on the exposed silicon structure. Nitride spacers 1905 and 1907 are then formed on wafer 101 to isolate the gate contacts from other contacts.

[0071] Figure 21 and 22 They are in Figure 1 and 2 A partial cross-sectional side view of the wafer 101 at the location. Figure 21 and 22 The image shows a wafer 101 after a P-well region 2137 has been formed in a substrate 105 by implanting P-type dopant (e.g., boron) ions into the substrate 105. In one embodiment, boron is selectively implanted at an energy of 180 keV and a dose of 1.0e13 cm⁻², but in other embodiments, other energies and / or other doses may be implanted. In one embodiment, an annealing step follows implantation.

[0072] Subsequently, source region 2133 and drain region 2135 are formed by selectively implanting N-type dopant ions into substrate 105. The N-type dopant ions are implanted through a patterned implantation mask (not shown) formed on wafer 101. In one embodiment, arsenic ions are implanted at a dose of 5e¹⁵ cm⁻² at 120 keV and phosphorus ions at a dose of 1.5e¹⁵ cm⁻² at 55 keV. In other embodiments, other N-type dopant ions may be implanted at other doses and / or other energies. Body contact region 2131 is formed by implanting P-type dopant ions into P-well region 2137. In one embodiment, boron ions are implanted at a dose of 1.5e¹⁵ cm⁻² and an energy of 25 keV through a patterned implantation mask (not shown) formed on wafer 101 to form body contact region 2131. Implantation is followed by an annealing step, such as rapid thermal annealing (RTA).

[0073] After forming the source region 2133, drain region 2135, and body contact region 2131, a silicide process is performed on wafer 101 to form silicide structures 2143, 2145, 2147, and 2149 on the exposed silicon sites. In some embodiments, wafer 101 is etched with an oxide to remove layer 1901 before forming the silicide structures. Then, a metal (e.g., tungsten titanate) layer is formed over wafer 101. Wafer 101 is then annealed to form a metal silicide and remove unreacted metal.

[0074] An interlayer dielectric material layer 2101 is formed on wafer 101. In one embodiment, layer 2101 is an oxide formed by a TEOS process, but in other embodiments it can be a different material. Openings are then formed in layer 2101 for forming metal contacts to electrically contact the transistor structure. In the illustrated embodiment, contact 2103 contacts both source region 2133 and body contact region 2131. Contact 2105 contacts drain region 2135. In other embodiments, the source region and body contact region can have different contacts to be individually biased to different voltages. Contact 2017 contacts field plate structure 603. Figure 21 The partial cross-sectional view does not show the location located in Figure 21 The contacts (2323 and 2327) of the gate structure 1305 are outside the view.

[0075] If possible Figure 21 As shown, the transistor includes a source region 2133, a drain region 2135, a channel region 2141 located in a well region 2137, a drift region 121, a gate structure 1305, and a field plate structure 603, wherein the channel region includes a portion positioned along a sidewall 130.

[0076] Figure 23 A top view of wafer 101 before the formation of oxide layer 2101 is shown. Figure 23 In the diagram, the boxes marked with "X" indicate the locations of the contacts to be formed in layer 2101. For simplicity, Figure 23 Sidewall spacers 1905 and 1907 are not shown. (See example...) Figure 23 As shown, contacts 2323 and 2327 will be formed to contact the silicide 2145 of the gate structure 1305. Contacts 2321 and 2325 will be formed to contact the gate silicide 2138 of the gate structure 1501. Contacts 2303, 2105, 2301, 2317, 2313, and 2311 will be formed to contact the drain silicide 2147, and contacts 2319, 2315, 2313, 2305, 2103, and 2307 will be formed to contact the source silicide 2143 (which also contacts the body region 2131). Contacts 2107 and 2309 will be formed to contact the field plate silicide 2149 in the termination region.

[0077] like Figure 21 As shown in the embodiment, the field plate structure 603 is positioned further away from the vertically forming trench sidewall 130 compared to the gate structure 1305. Similarly, the field plate structure 603 is positioned closer to the sidewall 130 compared to the sidewall 132. In one embodiment, employing the field plate structure in this manner can increase the BV by extending the equipotential lines so that the electric field does not peak at the gate corner.

[0078] exist Figure 21 and 22 Following the stages shown, other processes can be performed on wafer 101, such as forming additional interconnect layers. For example, interconnects can be formed to electrically couple gate structures 1305 and 1501 together. Then, for example, the outer ends of bonding pads are formed on wafer 101. Wafer 101 is then diced into multiple dies, each die including at least one transistor device having… Figure 21 and 22 The structure is shown. The die is then encapsulated in a semiconductor packaging material to form an integrated circuit package, which is then shipped to an end-use manufacturer for inclusion in an end-use product, such as an automotive, battery control system, or industrial equipment. In other embodiments, the transistor may include other structures and / or may be formed by other processes. Furthermore, additional process steps may be added to form other components on the same substrate. In some embodiments, field plate contacts 2107 may be electrically coupled to source contacts 2103 so that they are biased to the same potential during operation. In other embodiments, field plate structure 603 may be electrically coupled to gate structures 1305 and 1501 so that they are biased to the same potential during operation.

[0079] Figure 24 and 25 A partial cross-sectional side view of a transistor according to another embodiment is illustrated. Figure 24 and 25 Objects with the same reference numerals in the accompanying drawings Figure 21 and 22 The objects in the embodiments are similar. Figure 24 and 25 transistors and Figure 21 and 22 Similar to transistors, but Figure 24 and 25 The transistor has the ability to replace Figure 21 and 22 The transistor's dielectric structure 1601 has a gas cavity 2403. In one embodiment, in Figure 13 and 14Following the initial stage, when the conductive structure 607 is removed, a dielectric sealing layer (not shown) is formed over the wafer 101 to seal the opening, thereby forming a cavity 2403. The wafer 101 is then planarized using a layer 109 with a planarization stop layer. In one embodiment, the sealing layer is formed by forming a plug on top of a region of the cavity 2403. However, in other embodiments, the cavity can be formed using other processes. In one embodiment, the cavity 2403 provides a lower dielectric constant for the trench to improve the breakdown voltage.

[0080] Figure 26 and 27 A partial cross-sectional side view of a transistor according to another embodiment is illustrated. Figure 26 and 27 Objects with the same reference numerals in the accompanying drawings Figure 21 and 22 The objects in the embodiments are similar. Figure 26 and 27 In one embodiment, the field gate structure 607 is not removed from the wafer 101, but is retained in the wafer 101. The field gate structure 607 is floating and not electrically coupled to any external terminal of the integrated circuit including the transistor.

[0081] One advantage of at least some of the processes described herein is that transistors with gates and field plates closer to one edge of the trench can be fabricated more efficiently. Similarly, since forming a second trench allows for a larger gate structure 1305, a reliable electrical coupling can be formed between the gate structure 1305 and the silicide 2145.

[0082] For some devices, due to the geometry of the trench, higher-than-desirable levels of drift region dopant can accumulate in the termination region, which may reduce the breakdown voltage in these regions. In some embodiments, one advantage of providing a wider trench in the termination region than in the device region is that less drift region dopant can accumulate in the termination region, thereby improving the breakdown voltage.

[0083] although Figure 21 , 24 Sections 26 and 27 illustrate three different embodiments of a transistor, but other embodiments of a transistor may have other structures, features, regions, configurations, or doping concentrations. For example, although a transistor is shown as a P-type FET, it can be formed as an N-type FET by switching the doping conductivity type.

[0084] Additionally, in other embodiments, other types of transistors can be implemented using trenches that are wider in the termination region than in the device region. In other embodiments, the trenches may include combined gate / field plate structures or multiple field plate structures. Similarly, in other embodiments, the gate and / or field plate structures may be symmetrically located within the trenches.

[0085] As disclosed herein, if the first structure is located above the second structure on a line having a direction perpendicular to the main side surface of the generally planar surface of the wafer, then the first structure is "directly above" the second structure. For example, in Figure 21 In this configuration, contact 2103 is directly above region 2137. Contact 2103 is not directly above region 2135. As disclosed herein, if the first structure is located below the second structure on a line having a direction perpendicular to the main side surface of the generally planar surface of the wafer, then the first structure is "directly below" the second structure. For example, in Figure 21 In the middle, zone 2131 is directly below contact 2103. Zone 2131 is not directly below contact 2105. If two structures are located on opposite sides of one structure on a line, then one structure is "right in the middle" of two other structures on the same line. For example, in Figure 21 In Figure 21 In the cross-sectional side view, gate structure 1305 is located precisely midway between regions 2131 and 2135 along a line. Field plate structure 603 is not located precisely midway between regions 2131 and 2135 along a line. If two structures are located on opposite sides of one structure along a line parallel to the main side surface of the generally flat surface of the wafer, then one structure is "laterally positioned between the two other structures." For example, the gate structure is laterally positioned between regions 2133 and 2135. A "vertical component sidewall" of a trench is a portion of a trench sidewall with a profile, generally speaking, most of the components of said portion are vertical, although it may also have horizontal components or minor horizontal discontinuities within the sidewall portion. For example, a portion of a sidewall inclined at 70 degrees can be considered a vertical component sidewall portion.

[0086] Features shown or described herein with respect to one embodiment may be implemented in other embodiments shown or described herein.

[0087] In one embodiment, a semiconductor device includes a substrate comprising a semiconductor material. A trench is located in the semiconductor material. The semiconductor device includes a source region located in the semiconductor material relative to a first side of the trench and a gate structure located in the trench. The semiconductor device includes a channel region including a portion positioned along a first vertical component sidewall of the trench. The first vertical component sidewall is positioned relative to the first side of the trench. The trench includes a device segment, wherein the gate structure is located at least in the device segment. The trench has a first cross-sectional width at a first location in the device segment. The trench includes a termination segment, wherein the trench has a second cross-sectional width at a second location in the termination segment that is wider than the first cross-sectional width.

[0088] In another embodiment, a semiconductor device includes a substrate comprising a semiconductor material. A trench is located in the semiconductor material. The semiconductor device includes: a source region located in the semiconductor material relative to a first side of the trench; a drain region including at least a portion of a second side of the trench opposite to the first side of the trench located in the semiconductor material; a gate structure located in the trench; a field plate structure located in the trench; and a channel region including a portion positioned along a first vertical component sidewall of the trench. The first vertical component sidewall is positioned relative to the first side of the trench. The trench includes a device segment, wherein the gate structure is located at least in the device segment. The trench has a first cross-sectional width at a first location in the device segment. The trench includes a termination segment. The trench has a second cross-sectional width at a second location in the termination segment that is at least 10% wider than the first cross-sectional width, and the gate structure is not located at the second location. The field plate structure is located at the second location.

[0089] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, other changes and modifications may be made without departing from the invention and its broader aspects, and therefore the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a semiconductor material and trenches located in the semiconductor material; A source region, located in the semiconductor material relative to a first side of the trench; A gate structure located in the trench; The trench area includes a portion positioned along a first vertical component sidewall of the trench, the first vertical component sidewall being positioned relative to a first side of the trench. The trench includes a device segment, wherein the gate structure is located at least in the device segment, and the trench has a first cross-sectional width at a first location in the device segment; The trench includes a terminal section, wherein the trench has a second cross-sectional width at a second location in the terminal section that is wider than the first cross-sectional width; as well as The trench includes a second device segment, wherein a second gate structure is located at least in the second device segment, and the terminal segment is positioned along the trench between the device segment and the second device segment.

2. The semiconductor device according to claim 1, characterized in that, The width of the second cross section is wider than the width of the first cross section by a ratio, wherein the ratio is in the range of 10%-200% of the width of the first cross section.

3. The semiconductor device according to claim 1, characterized in that, In addition, including: Drain region, the drain region including a portion of a second side of the semiconductor material located on the upper surface of the trench opposite to the first side.

4. The semiconductor device according to claim 1, characterized in that, The first cross-sectional width has a first orientation, and the second cross-sectional width has a second orientation orthogonal to the first orientation.

5. The semiconductor device according to claim 1, characterized in that, The trench has a third cross-sectional width at a third location within the second device segment.

6. The semiconductor device according to claim 1, characterized in that, The device segment of the trench extends in a first orientation, and the second device segment extends in an orientation parallel to the first orientation.

7. The semiconductor device according to claim 1, characterized in that, Additionally, a field plate structure is included, which is located in the trench at the first and second positions.

8. The semiconductor device according to claim 1, characterized in that, The gate structure is positioned closer to the first vertical component sidewall of the trench than to the second vertical component sidewall of the trench.

9. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a semiconductor material and trenches located in the semiconductor material; A source region, located in the semiconductor material relative to a first side of the trench; Drain region, the drain region including at least a portion of a second side of the trench that is opposite to the first side of the trench located in the semiconductor material; A gate structure located in the trench; A field plate structure, wherein the field plate structure is located in the trench; The trench area includes a portion positioned along a first vertical component sidewall of the trench, the first vertical component sidewall being positioned relative to a first side of the trench. The trench includes a device segment, wherein the gate structure is located at least in the device segment, and the trench has a first cross-sectional width at a first location in the device segment; The trench includes a terminal section, wherein the trench has a second cross-sectional width at a second location in the terminal section that is at least 10% wider than the first cross-sectional width, the gate structure is not located at the second location, and the field plate structure is located at the second location; and The trench includes a second device segment, wherein a second gate structure is located at least in the second device segment, and the terminal segment is positioned along the trench between the device segment and the second device segment.

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