Coprocessor with bypass optimization, variable grid architecture, and fused vector operations
CN113490913BActive Publication Date: 2026-07-07APPLE INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- APPLE INC
- Filing Date
- 2020-02-23
- Publication Date
- 2026-07-07
AI Technical Summary
Technical Problem
In the existing technology, the performance and power efficiency optimization of coprocessors are difficult to be compatible with general-purpose processors, and there is a lack of implementation methods for dedicated hardware instructions.
Method used
By introducing optimization techniques such as bypass indication, mesh processing elements, and vector mode operation fusion into the coprocessor, a dedicated hardware circuit is designed to execute a subset of instructions, thereby improving processing efficiency.
Benefits of technology
It achieves high performance and low power consumption when the coprocessor executes a subset of instructions, improving the efficiency of the processing element and the system performance.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN113490913B_ABST
Abstract
In one embodiment, the coprocessor can include a bypass indication that identifies execution circuitry that is not used by a given processor instruction and thus can be bypassed. The corresponding circuitry can be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor can implement a grid of processing elements in rows and columns, where a given coprocessor instruction can specify an operation that causes at most all of the processing elements to operate on a vector of input operands to produce a result. The implementation of the coprocessor can implement a portion of the processing elements. Coprocessor control circuitry can be designed to operate with a full grid or a local grid, reissuing the instruction to perform the requested operation in the local grid case. In yet another embodiment, the coprocessor can be capable of fusing vector mode operations.
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