Accelerating access to memory banks in a data storage system

Abstract

A first host receives a first virtual address in a virtual memory, the first virtual address in the virtual memory corresponding to a first physical address of a first physical memory set to be accessed by the first host according to a mapping function. The first host accesses the first physical address to perform a first storage operation in the first physical memory set. A second host receives a second virtual address in the virtual memory, the second virtual address in the virtual memory corresponding to a second physical address of a second physical memory set to be accessed by the second host according to the mapping function. The second host accesses the second physical address to perform a second storage operation in the second physical memory set concurrently with the first host accessing the first physical address.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to U.S. Provisional Application No. 62 / 810,227, filed February 25, 2019, entitled “Method and apparatus for accelerating access to memory,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a data storage system that accelerates access to memory banks within the data storage system to improve the throughput of the data storage system and / or reduce the latency of accessing the data storage system. Background Technology

[0004] The background description provided herein is intended to provide a general overview of the context of this disclosure. The work of the currently named inventors, the scope of work described in this background section, and descriptions that may not conform to the prior art at the time of filing are neither intended nor implied as prior art relative to this disclosure.

[0005] Data storage systems facilitate the storage and retrieval of data in the form of volatile or non-volatile memory. The read / write performance of a data storage system is measured in terms of throughput and latency. Throughput limits the rate at which data is read from or written to the data storage system, while latency is the delay in accessing data from the data storage system. Conventional solutions for increasing throughput and reducing latency in data storage systems typically lead to a substantial increase in the power consumption and cost of the data storage system. Summary of the Invention

[0006] This disclosure relates to a data storage system that accelerates access to memory banks within the data storage system to improve the throughput of the data storage system and / or reduce the latency of accessing the storage system.

[0007] This disclosure provides a method for improving memory access in a data storage system. The method includes: receiving a first virtual address in virtual memory at a first host, the first virtual address in virtual memory corresponding to a first physical address of a first physical memory group to be accessed by the first host according to a mapping function; accessing the first physical address through the first host to perform a first read operation to read a first portion of a data unit stored in the first physical memory group at the first physical address, or performing a first write operation to write the first portion of the data unit to the first physical memory group at the first physical address; receiving a second virtual address in virtual memory at a second host, the second virtual address in virtual memory corresponding to a second physical address of a second physical memory group to be accessed by the second host according to a mapping function; and simultaneously with the first host accessing the first physical address, the second host accessing the second physical address to perform a second read operation to read a second portion of a data unit stored in the second physical memory group at the second physical address, or performing a second write operation to write the second portion of the data unit to the second physical memory group at the second physical address.

[0008] In one example, the mapping function maps a first virtual address associated with a first portion of a data cell in virtual memory to a first physical address associated with the first portion of a data cell in a first physical memory group, and maps a second virtual address associated with a second portion of a data cell in virtual memory to a second physical address associated with the second portion of a data cell in a second physical memory group. In another example, the first virtual address associated with the first portion of a data cell in virtual memory and the second virtual address associated with the second portion of a data cell in virtual memory are associated with consecutive rows in virtual memory, and the first physical address in the first physical memory group and the first physical address in the second physical memory group identify consecutive memory groups. In yet another example, the mapping function maps the first virtual address associated with the first portion of a data cell in virtual memory to a first physical address based on a logical XOR operation on the bits of the first virtual address associated with the first portion of a data cell in virtual memory, and the output of the logical XOR operation identifies the first physical memory group associated with the first portion of the data cell. In another example, the data unit is 32 bytes, and the first virtual address associated with the first portion of the data unit in virtual memory is a 23-bit variable address, where the 22nd bit is the most significant bit and the 0th bit is the least significant bit. A logical XOR operation is performed by XORing bits 12 through 9 with bits 8 through 5 of the address to identify the first physical memory group associated with the first portion of the data unit. In yet another example, a first host accesses a portion of the first physical memory group based on the first physical address, or a second host accesses a portion of the second physical memory group based on the second physical address. In another example, the first and second physical memory groups are the same memory group, and the method further includes arbitrating access to the first and second physical memory groups by the first and second hosts. In yet another example, the first and second physical memory groups are each single-port memory groups. In yet another example, the mapping function is a mapping table that maps virtual addresses in virtual memory to physical addresses in physical memory groups, and the mapping table is shared by the first and second hosts. In yet another example, concurrent access by the first and second hosts occurs within one clock cycle.

[0009] This disclosure provides a storage system comprising: a first memory group; a second memory group; a first host configured to: receive a first virtual address in a virtual memory, the first virtual address in the virtual memory corresponding to a first physical address of a first physical memory group to be accessed by the first host according to a mapping function; access the first physical address to perform a first read operation to read a first portion of a data unit stored in the first physical memory group at the first physical address, or perform a first write operation to write the first portion of the data unit to the first physical memory group at the first physical address; and a second host configured to: receive a second virtual address in a virtual memory, the second virtual address in the virtual memory corresponding to a second physical address of a second physical memory group to be accessed by the second host according to a mapping function; and simultaneously with accessing the first physical address by the first host, access the second physical address to perform a second read operation to read a second portion of a data unit stored in the second physical memory group at the second physical address, or perform a second write operation to write the second portion of the data unit to the second physical memory group at the second physical address. Attached Figure Description

[0010] Figure 1 An example storage system is shown that distributes access from the host to the memory group.

[0011] Figure 2 An example mapping of addresses in virtual memory to addresses in memory groups is shown to distribute access via the host to memory groups in an example storage system.

[0012] Figure 3 An example access to a memory group via a host is shown, based on mapping addresses in virtual memory to addresses in a sample memory system.

[0013] Figure 4 This is a flowchart of the functionality associated with host access to a memory group by mapping addresses in virtual memory to addresses in a sample storage system.

[0014] The accompanying drawings are for illustrative purposes only; however, it should be understood that the embodiments are not limited to the arrangements and means shown in the drawings. Detailed Implementation

[0015] This disclosure relates to a data storage system having multiple hosts and multiple memory groups, and the data storage system improves access to multiple memory groups by multiple hosts. The memory groups store data and facilitate the retrieval of stored data. Furthermore, in one embodiment, the memory group is a single-port memory group, which allows only one host to access the memory group at a time, given a specific period of time. Memory access is distributed across multiple physical memory groups to increase the probability that each host can successfully access the memory group, while avoiding conflicts caused by concurrent access by another host within a given period of time. By enabling multiple different hosts to access the memory group simultaneously with a reduced probability of conflict, the throughput of the storage system is increased and the latency of the storage system is reduced. In some examples, particularly when using single-port memory groups, the benefits of increased memory group access speed and reduced latency are achieved while maintaining low power consumption and reduced cost of the data storage system.

[0016] Overview

[0017] A data storage system has multiple hosts and multiple memory banks. Multiple hosts seek to access multiple memory banks to perform read or write operations on multiple memory banks. Each physical memory bank is a single-port memory that can be accessed by a host during a time period such as a clock cycle.

[0018] In some examples, two or more hosts want to access the same memory group within a time period. To ensure each host can access the same group, the data store has an arbitrator to fairly arbitrate access. The arbitrator grants access to host 1, then to host 2 in another time period, then to host 3 in another time period, and so on. Furthermore, each host can access a maximum number of bytes of data in the memory group, known as a data burst. For example, if the time period is a clock cycle, host 1 can access up to 64 bytes of data in a burst over two consecutive clock cycles. As another example, host 2 can access up to 512 bytes of data in a burst over 16 consecutive clock cycles. As yet another example, host 3 can access up to 1024 bytes of data in a burst over 32 consecutive clock cycles. Burst access allows efficient access to data in a memory group, but if two or more hosts want to access data in the same memory group, all but one host will have to wait until the other host completes its burst access. To increase the throughput and reduce latency of data storage systems, common practices include increasing the width of the data path to the data storage system, allowing more bits or bytes to be carried at a time, or increasing the clock rate of the clock that provides timing for the storage system, enabling more data to be read from or written to the memory bank over time. Both increasing the data path width and increasing the clock rate increase the cost of the data storage system and cause it to consume more power.

[0019] Systems, devices, methods, and techniques are described to improve access to multiple memory groups by distributing access among multiple hosts across memory groups. Hosts access multiple memory groups based on virtual memory within the memory groups. The virtual memory has multiple addresses, where addresses in the virtual memory of a memory group are associated with corresponding portions of data to be read from or stored in the memory group. For example, a first address in the virtual memory is associated with a first portion of data, and a second address in the virtual memory is associated with a second portion of data. In one embodiment, the memory group is a single-port memory group that allows access by a host over a period of time, such as a clock cycle. The host uses the address in the virtual memory of the memory group associated with a portion of data to access the memory group as a physical memory group to read portions of data from the memory group and write portions of data to the memory group. For example, a first host among multiple hosts determines an address in a first memory group to store or retrieve a first portion of data from the first memory group over a period of time based on a mapping between the first address and addresses in the first memory group. The first host then accesses the address in the first memory group. As another example, a second host among multiple hosts determines an address in a second memory group to store or retrieve a second portion of data from the second memory group during a given time period, based on a mapping between a first address in virtual memory and an address in the first memory group. The second host then accesses the address in the second memory group. This mapping distributes access across different memory groups for different portions of the data, enabling each host to successfully access a memory group with increased probability without conflicting with another host during the same time period, thereby increasing the throughput and reducing latency of the storage system.

[0020] The following description includes example systems, apparatuses, and methods that embody aspects of this disclosure. However, it should be noted that this disclosure can be practiced without these specific details. In other instances, well-known examples of instructions, structures, and techniques have not been shown in detail to avoid obscuring the description.

[0021] Example System

[0022] Figure 1A block diagram of an example storage system 100 facilitating the storage and retrieval of data in volatile or non-volatile memory is shown. In the example, storage system 100 may be such as a computing system, network device, or storage enclosure, or specifically, part of a larger system such as a personal computer, server, mainframe, smartphone, gaming system, set-top box, communication device, etc. Depending on the nature of the larger system, the data may take various forms, including but not limited to data packets, code, or data structures. Storage system 100 includes multiple memory banks 102, shown as 1…N, multiple hosts 104, and an arbiter 106, shown as 1…M. The multiple memory banks 102, multiple hosts 104, and arbiter 106 may be communicatively coupled together via a bus 110. Bus 110 may conform to Peripheral Component Interconnect (PCI), Industry Standard Architecture (ISA), PCI-Express, NuBus, Advanced Distributable Bus (AXI), Ethernet, or other standards.

[0023] A memory group, shown as one of a plurality of memory groups 102, is a unit containing multiple memory locations implemented in one or more semiconductor memory chips or in one or more memory drives, such as random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), zero-capacitance RAM, dual-transistor RAM, embedded DRAM (eDRAM), distributed data output RAM (EDORAM), double data rate RAM (DDRRAM), and flash memory; and the memory drives, such as solid-state drives, hard disks, etc. Although each memory group is depicted as a single block, in some configurations, a memory group comprises multiple different physical memories. Memory groups can be individual on-chip memory groups within the same integrated circuit, or they can be disposed on different solid-state devices or different integrated circuits.

[0024] In the example, memory locations can be organized as rows in a memory group. For example, a memory group can have 16,384 rows, and each row has 32 memory locations, with each memory location storing one byte of data. Each memory location can be associated with an address that uniquely identifies a memory location within the memory group. Each row can be associated with a row number or a memory address that uniquely identifies the row, such as the first or last byte of the memory location within that row. As an example, storage system 100 is shown as having N memory groups, identified as one of memory groups 1 to N. In some examples, N = 16. In other examples, storage system 100 can have more or fewer memory groups. Furthermore, each memory group in the plurality of memory groups 102 can have the same number of memory locations or a different number of memory locations. Additionally, each memory group can also be associated with non-overlapping address ranges, such that each memory location and row in each memory group is uniquely identifiable across the plurality of memory groups 102. As described below, each memory group can be accessed independently in parallel, but cannot be accessed by two or more hosts simultaneously. In the example, each memory group may be a single-port memory that allows access through one host at a time. Furthermore, in one embodiment, a portion of the memory group may be accessed via a single access channel (or port), which provides access to the corresponding portion of the memory group through a single host.

[0025] Each of the multiple hosts 104 is an integrated circuit that performs read or write access to the memory group. In some examples, the multiple hosts 104 and the multiple memory groups may be located on the same integrated circuit (IC) or solid-state device. In other examples, the multiple memory groups 102 and the multiple hosts 104 may be located on multiple integrated circuits or multiple other suitable solid-state devices.

[0026] Storage system 100 is shown as having M hosts, labeled host 1 to host M. While M = 6 in some examples, there are more or fewer hosts in other examples. Hosts can access memory banks. To facilitate such read and write access, a bus 110 facilitating communication between the multiple hosts 104 and the multiple memory banks 102 defines one or more paths among control paths, address paths, and data paths. The control path indicates whether data is being written to or read from a memory location. The address path carries the memory address indicating the memory location to be read or written. The data path carries the data to be stored in or read from the memory location. A host asserts one or more signals on the control path to indicate a read or write operation, on the address path to indicate data to be accessed, or on the data path to indicate data to be written. In the example, the signals can be voltage levels applied to the control path or the address path. Illustratively, a host can specify a read or write operation on the control line by placing a high (or low) voltage signal on the control path. The host then designates a memory location within the memory bank to be accessed by applying one or more signals indicating a unique memory address along the address path that identifies the memory location. For write access, the host applies one or more signals indicating data to be stored along the data path, causing the data to be stored in the identified memory location. For read access, the memory bank may apply one or more signals along the data path indicating data to be retrieved from the identified memory location within the memory bank and provided to the host. Other variations are also possible.

[0027] Storage system 100 may include a clock 114. Clock 114 is configured to generate a periodic signal referenced by a plurality of hosts 104, and it defines a time period or clock cycle when a host attempts to access a memory bank. Specifically, storage system 100 may be arranged such that, for each clock cycle, one or more hosts may attempt to access memory banks among a plurality of memory banks 102. For example, a host may access data in a row of a memory bank, such as 32 bytes of data. Furthermore, each host may be able to access a maximum amount of data in one or more memory banks at a time as a burst of continuous data. For example, host 1 may access up to 64 bytes of data at a time in 2 clock cycles. As another example, host 2 may access up to 512 bytes at a time in 16 clock cycles. As yet another example, host 3 may access up to 1024 bytes of data at a time in 32 clock cycles. Maximum access amounts allow for efficient access to data in the memory banks.

[0028] A memory group provides access to only one host per clock cycle. If two or more hosts attempt to access the same memory group or a portion of the same memory group (such as memory group 1) via a single access port or channel within the same clock cycle, a conflict occurs, and neither host is granted access without further intervention. Arbitrator 106 may be an integrated circuit that intercepts access to one or more memory groups from two or more hosts, detects whether access to the same memory group by two or more hosts would result in a conflict, and arbitrates the access by two or more hosts to the same memory group. If two or more hosts seek access to the same memory group within a clock cycle, arbitrator 106 can fairly grant access to the same memory group to both hosts. Fair access allows each host to complete its memory operations, enabling each host to meet individual throughput and latency criteria. For example, the arbitrator can grant access to the first host in a first clock cycle and then to the second host in a second clock cycle, based on an access scheme such as round-robin or weighted round-robin, by alternating access between two competing hosts. In this way, each host can be able to access the same memory group in a timely manner. Otherwise, if two hosts access data in the same memory group, one host may need to wait up to the number of clock cycles associated with the maximum access by the other host before it can access the same memory group.

[0029] In one embodiment, memory group 102 is physical memory. A host accesses multiple memory groups of virtual memory based on the memory groups. The virtual memory has one or more addresses associated with data, which, for example, may be frames, packets, blocks, or other suitable data units. Data may be associated with a single address in the virtual memory. Alternatively, data may be divided into portions, and addresses in the virtual memory of the memory group may be associated with corresponding portions of data. Furthermore, multiple portions of data may be consecutive addresses in the virtual memory. For example, a first address in the virtual memory may be associated with a first portion of data, and a second address in the virtual memory may be associated with a second portion of data. In this example, each address in the virtual memory maps to an address in the memory group. This mapping determines the memory group where the corresponding portion of data is stored or where the corresponding portion of data is retrieved from. Each host 104 may have a corresponding memory group access distributor (“access distributor”) 120 to perform the mapping. Access distributor 108 is an integrated circuit configured to map virtual addresses in the virtual memory to physical addresses in the memory group. This mapping enables host access to memory bank 102, such as reading or writing different portions of data distributed across different physical memory banks, so that each host will be able to successfully access the memory bank with increased probability without conflicting with another host, thereby increasing the throughput of the storage system and reducing the latency of the storage system in some examples.

[0030] Illustratively, two hosts can attempt to read or write different portions of data associated with different addresses in virtual memory within a clock cycle. A first portion of the data can be associated with a first address in virtual memory, and a second portion of the data can be associated with a second address in virtual memory. An access distributor associated with the first host can map the first address in virtual memory to an address in a first memory group, allowing one host to access the first memory group. An access distributor associated with the second host can map the second address in virtual memory to an address in a second memory group, allowing the second host to access the second memory group within the same clock cycle. The mapping function maps addresses in virtual memory to addresses in the memory group, enabling each host to successfully access the memory group for read or write operations, and the arbitrator 106 does not need to frequently arbitrate accesses to the same memory group.

[0031] In the example storage system 100 where M=6 and N=16, based on the access distributor distributing host accesses across different memory groups, a host has an 85.6% probability of successfully accessing a memory group within one clock cycle (i.e., another host will not simultaneously attempt to access the same memory group). This 85.6% probability is based on the premise that the probability of a memory group being accessed is 1 / 6 and the probability of no group being accessed is given as (1-1 / 6). 6 = 0.679. Then, the probability of accessing any one of the multiple memory groups 102 is given as 1 - 0.679 = 0.321, and the probability of a host successfully accessing a memory group is given as 0.321 * 16 / 6 = 0.856 or 85.6%. The probability of successful access indicates that if accesses to the multiple memory groups 102 by the host are uniformly distributed over clock cycles, and accesses to the memory groups by each host are independent, then the probability of a host successfully accessing a memory group without conflicting with another host is close to one. This probability can be increased or decreased based on the number of memory groups N and / or the number of hosts M. Because in some examples, the distribution of host accesses to memory groups is consistent, the throughput of the data storage system 100 is increased and the latency of the data storage system 100 is reduced.

[0032] Figure 2 An example process 200 is illustrated, performed by access distributor 108, distributing host access to memory groups 204, 206, and 208. Access distributor 108 can distribute access to the three memory groups 204, 206, and 208 based on address distribution within virtual memory 202 provided by the host. Virtual memory 202 can be defined within a single linear address space, having a start memory address and an end memory address. Virtual memory 202 can have multiple rows, an example of which is shown as row 250. In the example, each row can correspond to 32 bytes of data or a portion of data to be read or written. Memory groups 204, 206, and 208 can also be arranged in rows, for example, an example of which is shown as row 252. Row 252 can also correspond to 32 bytes of data, but in other examples, rows 250 and 252 can correspond to different sizes. Each memory bank and each row within a memory bank can be addressable, and each memory bank can have multiple rows, shown as 16584 rows in this example. Memory banks 204, 206, and 208 can collectively define memory pages. Access distributor 108 can define a mapping function that performs the mapping from addresses associated with addresses in virtual memory to addresses in the memory banks, which is a one-to-one mapping in this example.

[0033] The mapping function can instruct the addresses of consecutive rows in virtual memory 202 to be mapped to addresses of consecutive memory groups. In the example, multiple consecutive rows can represent data, and the addresses of consecutive rows can be associated with portions of the data. Memory groups can be contiguous as the address range of each subsequent memory group increases (or decreases). Illustratively, labels 10-15 are the addresses of rows in virtual memory 202. The addresses of rows in virtual memory 202 are mapped to addresses of memory groups, with each address uniquely identifying the memory group and the row within it. For example, address 10 in virtual memory 202 can be mapped to an address in the memory group associated with the row illustrated in memory group 204, address 11 in virtual memory 202 can be mapped to an address in the memory group associated with the row illustrated in memory group 206, and address 12 in virtual memory 202 can be mapped to an address in the memory group associated with the row illustrated in memory group 208. Addresses in the memory bank are represented by BR, where B is a variable indicating the memory bank and R is the row of the memory bank. As shown, 1-1 corresponds to the address of the first row in memory bank 1, 1-2 corresponds to the address of the second row in memory bank 1, 2-2 corresponds to the address of the first row in memory bank 2, and so on. Because there are three memory banks in this example, additional addresses in virtual memory 202 can be mapped to the same memory bank. Illustratively, addresses 13, 14, and 15, all associated with virtual memory 202, can be mapped, respectively, to addresses in memory banks associated with another row in memory banks 204, 206, and 208, based on a mapping function. The mapping function can be a hash function that provides a one-to-one mapping between addresses in virtual memory and addresses in memory banks. The mapping function maps addresses in virtual memory to addresses in memory banks, enabling each host to successfully access the memory banks for read or write operations.

[0034] In another example, access distributor 108 can indicate that an address in virtual memory 202 is mapped to a memory bank based on the bits of the address in virtual memory 202. Illustratively, consider addresses in virtual memory 202 represented by variable addresses. For example, a variable address can be 23 bits and represented as address [22:0], which is a shorthand notation identifying the values ​​of bits 22 through 0, where bit 22 is the most significant bit and bit 0 is the least significant bit. Address [22:0] can be the address that uniquely identifies a byte in virtual memory 202. Address [22:5] can indicate the values ​​of bits 22 through 5 of the address, and address [4:0] can indicate the values ​​of bits 4 through 0 of the address. A row of 32 bytes in virtual memory 202 can be uniquely identified by address [22:5], and address [4:0] uniquely addresses the bytes of the row. Access distributor 108 can map addresses in virtual memory 202 to addresses in a memory bank based on logical operations. The 8th to 5th bits of the address [8:5] correspond to four bits representing one of 16 values. The 12th to 9th bits of the address [12:9] can be the upper part. The logical operation can be:

[0035] Address [12:9] XOR address [8:5]

[0036] This is a logical XOR operation on two 4-bit numbers to produce a four-bit pattern indicating one of 16 memory banks associated with an address. The address can be mapped to the address of the indicated memory bank. Then, addresses [22:9] indicate the address of the row within the identified memory bank, and addresses [4:0] indicate the number of bytes in the row. The XOR operation causes rows in virtual memory with the same address [8:5] to be mapped to different memory banks in different pages. The XOR operation maps the address of virtual memory to the address of the memory bank, enabling each host to successfully access the memory bank for read or write operations.

[0037] Example function

[0038] Figure 3An example of multiple hosts 104 accessing multiple memory banks 102 is illustrated. Host 1, host 2, and host 3 can each access a portion of data based on addresses associated with portions of data in virtual memory. A mapping function indicates the mapping between addresses associated with portions of data in virtual memory and addresses in the memory banks where the portions of data are stored or can be written. In this example, the mapping function is represented as mapping table 320. Mapping table 320 distributes the accesses of the multiple hosts across the multiple memory banks 102 in the data storage system 100. The addresses associated with portions of data that the hosts attempt to access in virtual memory are shown as 302, 304, and 306, respectively, for hosts 1, 2, and 3. For example, host 1 can attempt to access portions of data associated with addresses 10, 11, 20, and 21 in virtual memory; host 2 can attempt to access portions of data associated with addresses 10, 11, 12, and 13 in virtual memory; and host 3 can attempt to access portions of data associated with addresses 10, 11, 12, 13, 14, 15, and 16 in virtual memory. Addresses in the range 10-21 can be mapped to addresses in memory groups. In this example, addresses N and N+10 can be in the same memory group. Illustratively, in this example, addresses 10 and 20 can be in the same memory group, while addresses 11 and 12 can be in different memory groups. The host number (e.g., 1, 2, or 3) in the lower right corner of block 308 can also indicate which host (e.g., host 1, host 2, or host 3) is attempting to access the portion of data associated with the address in the memory group. Arbitrator 106 can also arbitrate when two or more hosts attempt to access the same memory group within the same time period, such as the same clock cycle. In the event of a conflict, arbitrator 106 can allow the first host to access a memory group, then grant access to the second host, and then grant access to any additional hosts that wish to access that memory group. In this example, host 1 can have a maximum access limit of 2 blocks, while host 2 and host 3 can have maximum access limits of 16 blocks and 32 blocks, respectively.

[0039] In the example, the host can use mapping table 320 to map virtual addresses associated with a portion of data in virtual memory to physical addresses in the memory group. A portion of the data could be a block of data, a portion of a data packet, or some other part of a data unit that will be read from or stored in the memory group as part of a memory operation. Based on the mapped addresses in the memory group, the host can then read a portion of data in the memory group or write a portion of data to the memory group. For example, virtual address 10 in virtual memory 202 can be mapped to a physical address in memory group 1. As another example, virtual address 11 in virtual memory 202 can be mapped to a physical address in memory group 2. The host can then access the mapped addresses in the memory groups to perform memory operations associated with a portion of data in the memory groups, such as read or write.

[0040] As shown, in clock cycle 1, hosts 1, 2, and 3 attempt to access a portion of the data associated with virtual address 10 in virtual memory. Hosts may be attempting to access the same physical memory group based on mapping table 320. Arbitrator 106 can allow host 1 to access the physical memory group. Because each physical memory group allows access to one host per clock cycle, hosts 2 and 3 can be denied access.

[0041] As shown, in clock cycle 2, the arbitrator allows host 2 to access the portion of data associated with virtual address 10 in virtual memory. Host 1 may wish to access the portion of data associated with virtual address 11, which is located in a different memory group based on mapping table 120 and the portion of data associated with virtual address 10. Access to the portion of data associated with virtual address 11 is allowed because the portion of data associated with virtual address 10 is located in a different physical memory group based on mapping table 320 and the portion of data associated with virtual address 11. Because host 2 is allowed to access the data in clock cycle by the arbitrator, host 3 cannot access the portion of data associated with virtual address 10.

[0042] As shown, during clock cycle 3, the arbitrator allows host 3 to access the portion of data associated with virtual address 10. Host 2 is allowed to access the portion of data associated with virtual address 11, which is located in a different physical memory bank based on mapping table 320 and the portion of data associated with virtual address 10. Because host 1 has already performed a maximum access of two blocks of its maximum burst access length, host 1 is not allowed to access the portion of data associated with virtual address 10.

[0043] As shown, in clock cycle 4, host 1 accesses the portion of data associated with virtual address 20. Host 3 accesses the portion of data associated with virtual address 11, which is located in a different physical memory group based on mapping table 320 and the portion of data associated with virtual address 20. Because the portion of data associated with address 12 is not located in the same physical memory group as the portion of data associated with virtual address 20 or virtual address 11, host 2 accesses the portion of data associated with virtual address 12.

[0044] As shown, in clock cycle 5, host 1 accesses the portion of data associated with virtual address 21. Host 3 accesses the portion of data associated with virtual address 12, which is located in a different physical memory group based on mapping table 320 and the portion of data associated with virtual address 21. Because host 2 is not associated with the same physical memory group as the portion of data associated with virtual address 21 or the portion of data associated with virtual address 12 based on mapping table 320, host 2 accesses the portion of data associated with virtual address 13.

[0045] This process can continue until the host completes its access. The mapping table maps the addresses associated with portions of data in virtual memory to addresses in different memory groups to provide higher throughput and lower latency compared to a scenario where the data accessed by each host is in the same memory group. If the accesses are in the same memory group, host 1 will burst access to both blocks only based on its maximum access volume. Arbitrator 106 can then allow host 2 and then host 3 to burst access before allowing host 1 to complete its burst access. This could result in host 1 requiring 13 clock cycles to access the data, compared to 5 cycles in the example.

[0046] Figure 4 This is a flowchart 400 illustrating the functionality associated with distributing host access across multiple memory groups 102. In this example, these functions can be achieved through... Figure 1 The example uses storage system 100 to perform these functions. These functions begin at 402 and proceed to 412.

[0047] At 402, the address associated with the first portion of the data in the virtual memory is received by the first host. The first host may need to read or write the first portion of the data. In the example, storage system 100 may be part of a larger system such as a computing system, network device, or storage enclosure, or specifically a personal computer, server, mainframe, smartphone, gaming system, set-top box, communication equipment, etc. The first host may receive the address from a subsystem within the larger system.

[0048] At address 404, the address associated with the first portion of data in the virtual memory is mapped to the address associated with the first portion of data in the first memory bank. The first memory bank can be a physical single-port memory. The address can be mapped using a mapping function defined by the access distributor 108, enabling the host to successfully access the first memory bank for read or write operations. The mapping function can take the form of a hash function, logical operation, or mapping table, etc.

[0049] At address 406, the first host accesses an address in the first memory bank associated with a first portion of data within a time period. This access can be reading a portion of the data from an address in the memory bank or writing a portion of the data to an address in the memory bank. In this example, the time period can be a clock cycle.

[0050] At address 408, the address associated with the second portion of the data in virtual memory is received by the second host. The second host may need to read or write the second portion of the data. The second host may receive the address from a subsystem within a larger system.

[0051] At 410, the address associated with the second portion of data in the virtual memory is mapped to the address associated with the second portion of data in the second memory bank. The second memory bank may be a physical single-port memory separate from the first memory bank. The address can be mapped using a mapping function defined by the second host via access distributor 108, enabling the second host to successfully access the second memory bank for read or write operations. This mapping function may be the same as the mapping function used by the first host. In some examples, the mapping function may be shared between the first and second hosts, for example, in shared memory accessed by access distributor 108.

[0052] At 412, the second host accesses an address in the second memory bank associated with a second portion of the data for that time period. This access can be reading a portion of the data from the address in the memory bank or writing a portion of the data to the address in the memory bank. In the example, the access via the second host and the access via the first host can be concurrent, for example, within the same clock cycle.

[0053] In the example, access can be distributed across the memory bank based on a mapping function, allowing portions of the data to be accessed by multiple hosts with high throughput and low latency, while reducing conflicts between hosts. Depending on the access, the distribution can be uniform or non-uniform across the memory bank.

[0054] While aspects of this disclosure have been described in conjunction with specific embodiments presented as examples, alternatives, modifications, and variations may be made to the examples. Therefore, the embodiments set forth herein are intended to be illustrative rather than restrictive. Changes may be made without departing from the scope of the claims set forth below.

Claims

1. A method for accessing memory in a data storage system, the method comprising: A first virtual address in a virtual memory is received at a first host, wherein the first virtual address in the virtual memory corresponds to a first physical address of a first physical memory group to be accessed by the first host according to a mapping function. The mapping function is implemented at the first host to distribute memory access across multiple physical memory groups via the first host, wherein the multiple physical memory groups include the first physical memory group and the second physical memory group. Access the first physical memory group at the first physical address via the first host to perform: The first read operation reads a first portion of a data cell stored in the first physical memory group at the first physical address, or A first write operation is performed to write the first portion of the data unit to the first physical memory group at the first physical address; A second virtual address is received at the second host, and the second virtual address corresponds to the second physical address of the second physical memory group to be accessed by the second host according to the mapping function; The mapping function is implemented at the second host to distribute memory access across the plurality of physical memory groups via the second host, and Simultaneously with the first host accessing the first physical memory group at the first physical address, the second host accesses the second physical memory group at the second physical address to perform: The second read operation reads a second portion of the data unit stored in the second physical memory group at the second physical address, or The second write operation is to write the second portion of the data unit to the second physical memory group at the second physical address.

2. The method according to claim 1, wherein the mapping function is: Map the first virtual address to the first physical address, and Map the second virtual address to the second physical address.

3. The method according to claim 1, wherein: The first virtual address and the second virtual address are associated with consecutive rows in the virtual memory, and The first physical address and the second physical address identify contiguous memory groups.

4. The method according to claim 1, wherein: The mapping function maps the first virtual address to the first physical address based on a logical XOR operation on the bits of the first virtual address in the virtual memory. as well as The output of the logical XOR operation identifies the first physical memory group.

5. The method according to claim 4, wherein: The data unit is 32 bytes; The first virtual address is a 23-bit representation of a variable address, wherein the 22nd bit of the 23 bits is the most significant bit and the 0th bit of the 23 bits is the least significant bit. The logical XOR operation is performed by XORing the 12th to 9th bits of the variable address with the 8th to 5th bits of the variable address to identify the first physical memory group.

6. The method of claim 1, further comprising: Arbitration is made for access to one of the plurality of physical memory groups by the first host and the second host.

7. The method according to claim 1, wherein the first physical memory group and the second physical memory group are both single-port memory groups.

8. The method of claim 1, wherein the mapping function includes the use of a mapping table that maps virtual addresses of virtual memory to physical addresses of the plurality of physical memory groups; and The mapping table is shared by the first host and the second host.

9. The method of claim 1, wherein concurrent access by the first host and the second host occurs within one clock cycle.

10. A storage system, comprising: Multiple physical memory groups, including a first physical memory group and a second physical memory group; The first host is configured as follows: Receive a first virtual address in a virtual memory, wherein the first virtual address in the virtual memory corresponds to a first physical address of the first physical memory group to be accessed by the first host according to a mapping function; Implement the mapping function to distribute memory access across the plurality of physical memory groups via the first host; Access the first physical memory group at the first physical address to perform: The first read operation reads a first portion of a data cell stored in the first physical memory group at the first physical address, or A first write operation is performed to write the first portion of the data unit to the first physical memory group at the first physical address; The second host is configured as follows: Receive a second virtual address, which corresponds to a second physical address of the second physical memory group to be accessed by the second host according to the mapping function; Implement the mapping function to distribute memory access across the plurality of physical memory groups via the second host; as well as Simultaneously with the first host accessing the first physical memory group at the first physical address, the second physical memory group at the second physical address is accessed to perform: The second read operation reads a second portion of the data unit stored in the second physical memory group at the second physical address, or The second write operation is to write the second portion of the data unit to the second physical memory group at the second physical address.

11. The storage system of claim 10, wherein the virtual memories of the first virtual address and the second virtual address, and the plurality of physical memory groups, are configured with contiguous addresses.

12. The storage system according to claim 10, wherein: The first virtual address and the second virtual address are associated with consecutive rows in the virtual memory, and The first physical address and the second physical address are associated with a contiguous group of physical memory.

13. The storage system according to claim 10, wherein: The first host is configured to map the first virtual address to the first physical address based on a logical XOR operation on the bits of the first virtual address in the virtual memory; as well as The output of the logical XOR operation identifies the first physical memory group.

14. The storage system according to claim 13, wherein: The data unit is 32 bytes; The first virtual address is a 23-bit representation of a variable address, wherein the 22nd bit of the 23 bits is the most significant bit and the 0th bit of the 23 bits is the least significant bit. The logical XOR operation is performed by XORing the 12th to 9th bits of the variable address with the 8th to 5th bits of the variable address to identify the first physical memory group.

15. The storage system of claim 10, wherein simultaneously within a single clock cycle, the first host is configured to access the first physical address, and the second host is configured to access the second physical address.

16. The storage system of claim 10, further comprising an arbitrator configured to arbitrate access to one of the plurality of physical memory groups.

17. The storage system of claim 10, wherein the first physical memory group and the second physical memory group are single-port memory groups.

18. The storage system according to claim 10, wherein: The mapping function includes the use of a mapping table that maps virtual addresses of virtual memory to physical addresses of the plurality of physical memory groups; and The mapping table is shared by the first host and the second host.

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