Method and system for synchronizing computers

Abstract

The invention relates to a method and a system for synchronizing computers. The system comprises: a computing module (2) computing bits by each computer (A) and (B); an exchanging module (3) exchanging the computed bits; a signal pair determining module (4) determining a bit signal pair comprising the computed bits; a product pair determining module (5) determining a bit product pair indicating which bit equal to 1 in the bit signal pair of the computer (A, B) can be combined with the bit in the bit signal pair determined in iteration n-1 for the other computer (A, B); a remainder pair determining module (6) determining a bit remainder pair indicating which bit equal to 1 in the bit signal pair of the computer (A, B) is different from the bit in the bit signal pair of the other computer (A, B) in iteration n-1; a synchronization signal determining module (7) determining a synchronization signal based on the bit product pair and the bit remainder pair.

Description

Technical Field

[0001] This invention relates to computer synchronization. In particular, it relates to methods and systems for synchronizing two computers, specifically designed to control the control surfaces of an aircraft. Background Technology

[0002] Modern aircraft, especially transport aircraft, include a set of flight control computers that calculate control commands for the actuators of the aircraft's control surfaces. These flight control computers are distinct and redundant, making the flight control system robust to failures that could affect some of the computers. Furthermore, more generally, some of these computers operate in control mode (COM), while others operate in monitor mode (MON). The computer in monitor mode monitors the operation of the computer in control mode. Thus, the computers are distributed as COM / MON pairs.

[0003] Document EP 19206101.8 describes a flight control system for an aircraft. This flight control system includes a set of flight control command computing units and a set of aircraft control actuators. These computing units comprise two similar modules. One module corresponds to the computer operating in control mode, and the other module corresponds to the computer operating in monitoring mode. These two computers must be synchronized to allow robust implementation of automatic piloting laws. Summary of the Invention

[0004] The present invention aims to overcome this problem by proposing a system and method for synchronizing a first computer and a second computer.

[0005] Therefore, the present invention relates to a method for synchronizing a first computer and a second computer, each of which is configured to calculate control commands for controlling the control surface actuators of an aircraft according to the same flight rules, each of which includes a clock synchronized with each other, the first computer having an advance or delay relative to the second computer, the advance or delay being unknown and finite in terms of time.

[0006] According to the present invention, the method comprises a set of steps implemented iteratively, wherein the set of steps implemented in each iteration n includes:

[0007] - The calculation steps implemented by the calculation module are as follows: each of the computers calculates a bit, and if the control instruction calculated by each of the computers in iteration n is equal to the control instruction calculated in iteration n-1, then the bit is equal to 0; otherwise, the bit is equal to 1.

[0008] - The switching steps implemented by the switching module consist of: each bit calculated by the switching module in the computer;

[0009] - The signal pair determination step implemented by the signal pair determination module is characterized in that: each bit signal pair in the computer is determined, the bit signal pair including bits calculated by each of the computers;

[0010] - The product pair determination step implemented by the product pair determination module is characterized in that: each determined bit product pair in the computer indicates which bit equal to 1 in one determined bit signal pair in the computer in iteration n is equal to a bit in another determined bit signal pair in the computer in iteration n-1.

[0011] - The remainder pair determination step implemented by the remainder pair determination module is characterized in that: each determined bit remainder pair in the computer indicates which bit equal to 1 in a determined bit signal pair in the computer in iteration n is different from the bit in another determined bit signal pair in the computer in iteration n-1.

[0012] - The synchronization signal determination step implemented by the synchronization signal determination module is that each of the computers determines the synchronization signal based on bit product pairs and bit remainder pairs.

[0013] Therefore, this method enables the synchronization of control commands calculated by the two computers.

[0014] In addition, the calculation steps include the following sub-steps:

[0015] - The first computational sub-step implemented by the first computational submodule of the first computer is as follows: Calculate the first bit, if the control instruction calculated by the first computer in iteration n... Ia ( n The control command calculated in iteration n-1 is equal to the control command. Ia ( n If -1), then the first bit is equal to 0; otherwise, the first bit is equal to 1.

[0016] - The second computational sub-step, implemented by the second computational submodule of the second computer, involves: calculating the second bit, if the control instruction calculated by the second computer in iteration n... Ib ( n The control command calculated in iteration n-1 is equal to the control command. Ib ( n If -1), then the second bit is equal to 0; otherwise, the second bit is equal to 1.

[0017] In addition, the exchange step includes the following sub-steps:

[0018] - The first transmission sub-step implemented by the first transmission sub-module of the first computer is to: transmit the first bit to the second computer;

[0019] - The second transmission sub-step implemented by the second transmission sub-module of the second computer is to transmit the second bit to the first computer.

[0020] In addition, the signal pair determination step includes the following sub-steps:

[0021] - The first determining sub-step, implemented by the first determining sub-module of the first computer, involves: determining the first bit signal pair. Sa ( n ) = ,in sa 0 is equal to the specific bit calculated in iteration n-1, and sa 1 is equal to the opposite bit of the second bit calculated in iteration n-1.

[0022] - The second determining sub-step, implemented by the second determining submodule of the second computer, involves: determining the second bit signal pair. Sb ( n ) = ,in sb 0 is equal to a specific bit of the second bit calculated in iteration n-1, and sb 1 is equal to the opposite bit of the first bit calculated in iteration n-1.

[0023] Based on a specific feature, the product pair determination step includes the following sub-steps:

[0024] - The third determining sub-step, implemented by the third determining sub-module of the first computer, involves: determining the first bit product pair. Pa ( n ) = ,in pa 0 is a specific bit and pa 1 is the opposite bit.

[0025] • if( Ra ( n -1) = or Ra ( n -1) = )and Sa ( n ) = ,but Pa ( n) = , Ra ( n -1) corresponds to the bit remainder pair determined in iteration n-1.

[0026] • if( Ra ( n -1) = and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n ) = ,

[0027] • if( Ra ( n -1) = and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n ) = ,

[0028] Otherwise, Pa ( n ) = ;

[0029] - The fourth determining sub-step, implemented by the fourth determining sub-module of the second computer, involves: determining the second bit product pair. Pb ( n ) = ,in pb 0 is a specific bit and pb 1 is the opposite bit.

[0030] • if( Rb ( n -1) = or Rb ( n -1) = )and Sb ( n ) = ,but Pb (n ) = , Rb ( n -1) corresponds to the bit remainder pair determined in iteration n-1.

[0031] • if( Rb ( n -1) = and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n ) = ,

[0032] • if( Rb ( n -1) = and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n ) = ,

[0033] Otherwise, Pb ( n ) = .

[0034] Based on another specific characteristic, the remainder pair determination step includes the following sub-steps:

[0035] - The fifth determining sub-step, implemented by the fifth determining sub-module of the first computer, involves: determining the first bit remainder pair. Ra ( n ) = ,in ra 0 is a specific bit. ra 1 is the opposite bit, and Ra ( n ) = Sa ( n XOR Pa ( n );

[0036] - The sixth determining sub-step, implemented by the sixth determining sub-module of the second computer, involves: determining the second bit remainder pair. Rb ( n ) = ,in rb 0 is a specific bit. rb 1 is the opposite bit, and Rb ( n ) = Sb ( n XOR Pb ( n ).

[0037] In addition, the synchronization signal determination step includes the following sub-steps:

[0038] - The seventh determining sub-step, implemented by the seventh determining sub-module of the first computer, involves: determining the first synchronization signal. Oa ( n ),

[0039] • if Pa ( n ) = Then the first synchronization signal Oa ( n ) equals the first synchronization signal in iteration n-1. Oa ( n -1),

[0040] • if Pa ( n )≠ And if ra If 0 = 0, then the first synchronization signal Oa ( n This is equal to the control instructions calculated by the first computer in iteration n-1. Ia ( n -1),

[0041] • if Pa ( n )≠ And if ra 0 = 1, then the first synchronization signal Oa ( n This is equal to the control command calculated by the first computer in iteration n-2. Ia ( n -2);

[0042] - The eighth determining sub-step, implemented by the eighth determining sub-module of the second computer, involves: determining the second synchronization signal. Ob ( n ),

[0043] • if Pb ( n ) = Then the second synchronization signal Ob ( n ) equals the second synchronization signal in iteration n-1. Ob ( n -1),

[0044] • if Pb ( n )≠ And if rb If 0 = 0, then the second synchronization signal Ob ( n This is equal to the control instructions calculated by the second computer in iteration n-1. Ib ( n -1),

[0045] • if Pb ( n )≠ And if rb 0 = 1, then the second synchronization signal [[ID=]]Ob ( n This is equal to the control command calculated by the second computer in iteration n-2. Ib ( n -2).

[0046] The invention also relates to a system for synchronizing a first computer and a second computer, each of which is configured to calculate control commands for controlling the control surface actuators of an aircraft according to the same flight rules, each of which includes a clock synchronized with each other, the first computer having an advance or delay relative to the second computer, the advance or delay being unknown and finite in terms of time.

[0047] According to the present invention, the system includes a set of modules implemented iteratively, wherein the set of modules implemented at each iteration n includes:

[0048] - A computing module configured such that each of the computers computes a bit, whereby the bit is 0 if the control instruction computed by each of the computers in iteration n is equal to the control instruction computed in iteration n-1, otherwise the bit is 1.

[0049] - A switching module configured to cause each of the calculated bits in the computer to be switched;

[0050] - A signal pair determination module, configured such that each bit signal pair in the computer determines a bit signal pair, the bit signal pair including bits calculated by each of the computers;

[0051] - A product pair determination module, configured such that each determined bit product pair in the computer indicates which bit equal to 1 in one determined bit signal pair in the computer in iteration n is equal to a bit in another determined bit signal pair in the computer in iteration n-1.

[0052] - A remainder pair determination module, configured such that each determined bit remainder pair in the computer indicates which bit equal to 1 in one determined bit signal pair in the computer in iteration n is different from the bit in another determined bit signal pair in the computer in iteration n-1.

[0053] - A synchronization signal determination module, which is configured such that each of the computers determines a synchronization signal based on bit product pairs and bit remainder pairs.

[0054] In addition, the calculation module includes the following sub-modules:

[0055] - The first computing submodule of the first computer is configured to compute the first bit, if the control instruction computed by the first computer in iteration n... Ia ( n The control command calculated in iteration n-1 is equal to the control command. Ia ( n If -1), then the first bit is equal to 0; otherwise, the first bit is equal to 1.

[0056] - The second computing submodule of the second computer is configured to compute the second bit, if the control instruction computed by the second computer in iteration n... Ib ( n The control command calculated in iteration n-1 is equal to the control command. Ib ( n If -1), then the second bit is equal to 0; otherwise, the second bit is equal to 1.

[0057] In addition, the switching module includes the following sub-modules:

[0058] - A first transmission submodule of a first computer, configured to transmit a first bit to a second computer;

[0059] - A second transmission submodule of the second computer, configured to transmit the second bit to the first computer.

[0060] In addition, the signal pair determination module includes the following sub-modules:

[0061] - A first determining submodule of the first computer, configured to determine a first bit signal pair Sa ( n) = ,in sa 0 is equal to the first specific bit of the first bit calculated in iteration n-1, and sa 1 is equal to the second inverse bit of the second bit calculated in iteration n-1;

[0062] - The second determining submodule of the second computer is configured to determine the second bit signal pair. Sb ( n ) = ,in sb 0 is equal to the second specific bit calculated in iteration n-1, and sb 1 is equal to the first opposite bit of the first bit calculated in iteration n-1.

[0063] Based on a specific feature, the product pair determination module includes the following sub-modules:

[0064] - The third determining submodule of the first computer, configured to determine the first bit product pair Pa ( n ) = ,in pa 0 is a specific bit and pa 1 is the opposite bit.

[0065] • if( Ra ( n -1) = or Ra ( n -1) = )and Sa ( n ) = ,but Pa ( n ) = , Ra ( n -1) corresponds to the bit remainder pair determined in iteration n-1.

[0066] • if( Ra ( n -1) = and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n ) = ,

[0067] • if( Ra ( n -1) = and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n ) = ,

[0068] Otherwise, Pa ( n ) = ;

[0069] - The fourth determining submodule of the second computer, configured to determine the second bit product pair Pb ( n ) = ,in pb 0 is a specific bit and pb 1 is the opposite bit.

[0070] • if( Rb ( n -1) = or Rb ( n -1) = )and Sb ( n ) = ,but Pb ( n ) = , Rb ( n -1) corresponds to the bit remainder pair determined in iteration n-1.

[0071] • if( Rb ( n -1) = and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n ) = ,

[0072] • if( Rb ( n -1) = and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n ) = ,

[0073] Otherwise, Pb ( n ) = .

[0074] Based on another specific characteristic, the remainder pair determination module includes the following sub-modules:

[0075] - The fifth determining submodule of the first computer, which is configured to determine the first bit remainder pair Ra ( n ) = ,in ra 0 is a specific bit. ra 1 is the opposite bit, and Ra ( n ) = Sa ( n XOR Pa ( n );

[0076] - The sixth determining submodule of the second computer, which is configured to determine the second bit remainder pair Rb ( n ) = ,in rb 0 is a specific bit. rb 1 is the opposite bit, and Rb ( n ) = Sb ( n XOR Pb ( n ).

[0077] In addition, the synchronization signal determination module includes the following sub-modules:

[0078] - The seventh determining submodule of the first computer is configured to determine the first synchronization signal. Oa ( n ),

[0079] • if Pa ( n ) = Then the first synchronization signal Oa ( n ) equals the first synchronization signal in iteration n-1. Oa ( n -1),

[0080] • if Pa ( n )≠ And if ra If 0 = 0, then the first synchronization signal Oa ( n This is equal to the control instructions calculated by the first computer in iteration n-1. Ia ( n -1),

[0081] • if Pa ( n )≠ And if ra 0 = 1, then the first synchronization signal Oa ( n This is equal to the control command calculated by the first computer in iteration n-2. Ia ( n -2);

[0082] - The eighth determining submodule of the second computer, which is configured to determine the second synchronization signal. Ob ( n ),

[0083] • if Pb ( n ) = Then the second synchronization signal Ob ( n ) equals the second synchronization signal in iteration n-1. Ob ( n -1),

[0084] • if Pb ( n )≠ And if rb If 0 = 0, then the second synchronization signal Ob ( n This is equal to the control instructions calculated by the second computer in iteration n-1. Ib ( n -1),

[0085] • if Pb ( n )≠ And if rb 0 = 1, then the second synchronization signal Ob ( n This is equal to the control command calculated by the second computer in iteration n-2. Ib ( n -2).

[0086] The present invention also relates to a flight control system for an aircraft, comprising at least one system as described above for synchronizing a first computer and a second computer.

[0087] The present invention also relates to aircraft, particularly transport aircraft, which include the flight control system described above. Attached Figure Description

[0088] The invention, its features and advantages will become more apparent upon reading the description provided with reference to the accompanying drawings, in which:

[0089] Figure 1 A schematic depiction of a synchronization system is shown.

[0090] Figure 2 A schematic depiction of the synchronization method is shown.

[0091] Figure 3 An example illustrating the operation of a synchronization system is shown.

[0092] Figure 4 The bit exchange sequence between two computers is shown.

[0093] Figure 5 An aircraft with an airborne flight control system including the synchronization system is shown. Detailed Implementation

[0094] Figure 1 System 1 for synchronizing computer A and computer B is shown. In the remainder of the specification, this synchronization system will be referred to as System 1.

[0095] System 1 is designed to be airborne and housed on the aircraft AC, within the flight control system 11, such as Figure 5 As shown.

[0096] Each of computers A and B is configured to calculate control commands for the control surface actuators of the aircraft AC according to the same flight rules. Each of computers A and B includes a clock, which is synchronized with each other. Computer A is ahead or behind computer B. The advance or delay of computer A or B relative to another computer B or A is unknown. However, this advance or delay is finite in terms of time. This means that the advance or delay is less than the maximum time difference. Tsync The maximum time difference is defined below in this description.Tsync .

[0097] System 1 comprises a set of modules implemented iteratively.

[0098] The set of modules implemented for iteration n includes at least:

[0099] - Calculation module CALC 2,

[0100] - Switching module SH 3,

[0101] - Signal pair determination module DET1 4,

[0102] - Product pair determination module DET2 5,

[0103] - Remainder pairs determine module DET3 6, and

[0104] - Synchronization signal determination module DET4 7.

[0105] Calculation module 2 is configured such that each of computers A and B calculates a bit (or a Boolean value). If the control instruction calculated by each of computers A and B in iteration n is equal to the control instruction calculated in iteration n-1, then the bit is equal to 0. Otherwise, the bit is equal to 1.

[0106] Preferably, the bit is calculated before the control command is calculated.

[0107] Computing module 2 may include computing submodule CALC1 2A contained in computer A and computing submodule CALC2 2B contained in computer B.

[0108] Computer A's computational submodule 2A is configured to compute the first bit. If, in iteration n, computer A computes the control instruction... Ia ( n The control command calculated in iteration n-1 is equal to the control command. Ia ( n If the first bit is -1), then the first bit is equal to 0; otherwise, the first bit is equal to 1. Computer B's computation submodule 2B is configured to compute the second bit. If the control instruction computed by computer B in iteration n... Ib ( n The control command calculated in iteration n-1 is equal to the control command. Ib ( n If -1), then the second bit is equal to 0; otherwise, the second bit is equal to 1.

[0109] The switching module 3 is configured to cause each of computers A and B to exchange the calculated bits.

[0110] Switching module 3 may include transmission submodule SH1 3A contained in computer A and transmission submodule SH2 3B contained in computer B.

[0111] Computer A's transmission submodule 3A is configured to transmit the first bit calculated by the calculation submodule 2A to computer B.

[0112] Computer B's transmission submodule 3B is configured to transmit the second bit calculated by the calculation submodule 2B to computer A.

[0113] The first bit corresponds to a specific bit in computer A and its opposite bit in computer B. The second bit corresponds to the opposite bit in computer A and its specific bit in computer B.

[0114] Each of computers A and B has a sampling period. Tc The clocks can have the largest time difference between them. Tsync . Figure 4 The clock sequences C(n), C(n+1), and C(n+2) of two computers A and B are shown. In iteration n, the clock of computer A is delayed relative to the clock of computer B. Tsync The delay decreases in iteration n+1 and disappears in iteration n+2. Ls 1 represents the minimum waiting time for a bit transfer from one computer A, B to another computer B, A. Ls 2 represents the maximum latency for bit transfer from one computer A, B to another computer B, A. This latency is calculated by computer A in iteration n so that the bits calculated by computer B, A can be used by computer B, A in iteration n+1. Ls 1 should be greater than the maximum time difference Tsync ( Ls 1> Tsync and less than the sampling period Tc With the maximum time difference Tsync difference ( Ls 2 < Tc - 2 Tsync ).

[0115] Furthermore, it is preferable to select a sampling period Tc that satisfies the following relationship: > 3, of which Ts This corresponds to the transmission cycle of the data items to be synchronized collected by two computers, A and B. Ls This corresponds to the waiting time caused by transmitting the data item to each of computers A and B.

[0116] Signal pair determination module 4 is configured such that each of computers A and B determines a bit pair, referred to as a "bit signal pair". The bit signal pair includes bits calculated by each of computers A and B.

[0117] The signal pair determination module 4 includes determination submodules DET11 4A and DET12 4B.

[0118] Computer A's determining submodule 4A is configured to determine the first bit signal pair. Sa ( n ) = ,in sa 0 is a specific bit equal to the first bit calculated by computation submodule 2A in iteration n-1, and sa 1 is equal to the opposite bit of the second bit calculated by the computation submodule 2B in iteration n-1.

[0119] Computer B's determining submodule 4B is configured to determine the second bit signal pair. Sb ( n ) = ,in sb 0 is equal to a specific bit of the second bit calculated by computation submodule 2B in iteration n-1, and sb 1 is equal to the opposite bit of the first bit calculated by the computation submodule 2A in iteration n-1.

[0120] The product pair determination module 5 is configured such that each of computers A and B determines a bit pair called a "bit product pair". The bit product pair indicates which bit equal to 1 in a determined bit signal pair for one of computers A and B in iteration n is equal to a bit in another determined bit signal pair for computers A and B in iteration n-1.

[0121] The product pair determination module 5 may include determination submodules DET21 5A and DET22 5B.

[0122] Computer A's determining submodule 5A is configured to determine the first bit product pair. Pa ( n ) = ,in pa 0 is a specific bit and pa 1 is the opposite bit.

[0123] Pa ( n The following is determined:

[0124] if( Ra ( n -1) = or​ ( n -1) = )and ​ ( n ) = ,but ​ ( n ) = .

[0125] if( ​ ( n -1) = and ​ ( n ) = )or( ​ ( n -1) = and ​ ( n ) = ),but ​ ( n ) = .

[0126] if( ​ ( n -1) = and ​ ( n ) = )or( ​ ( n -1) = and ​ ( n ) = ),but ​ ( n ) = .

[0127] In other cases, ​ ( n ) = .

[0128] ​ ( n -1) corresponds to the bit pair called the "bit remainder pair" determined in iteration n-1. This will be explained below in this description. ​ ( n The determination of ).

[0129] Computer B's determining submodule 5B is configured to determine the second bit product pair. ​ ( n ) = ,in ​ 0 is a specific bit and ​ 1 is the opposite bit.

[0130] ​ ( n The following is determined:

[0131] if( ​ ( n -1) = or ​ ( n -1) = )and ​ ( n ) = ,but ​ ( n ) = .

[0132] if( ​ ( n -1) = and ​ ( n ) = )or( ​ ( n -1) = and ​ ( n ) = ),but ​ ( n ) = .

[0133] if( ​ ( n -1) = and ​ ( n ) = )or( ​ ( n -1) = and ​ ( n ) = ),but ​ ( n ) = .

[0134] In other cases, ​ ( n ) = .

[0135] ​ ( n -1) corresponds to the bit remainder pair determined in iteration n-1. This is explained below in this description. ​ ( n The determination of ).

[0136] The remainder pair determination module 6 is configured such that each of computers A and B determines a bit pair called a "bit remainder pair". The bit remainder pair indicates which bit equal to 1 in a determined bit signal pair for one of computers A and B in iteration n is different from the bit in another determined bit signal pair for computers A and B in iteration n-1.

[0137] The remainder pair determination module 6 may include determination submodules DET31 6A and DET32 6B.

[0138] Computer A's determining submodule 6A is configured to determine the first bit remainder pair. ​ ( n ) = ,in ra 0 is a specific bit and ra 1 is the opposite bit.

[0139] The first bit remainder pair is determined using the following relationship: ​ ( n ) = ​ ( n XOR ​ ( n ).

[0140] Computer B's determining submodule 6B is configured to determine the second bit remainder pair. ​ ( n ) = ,in rb 0 is a specific bit and rb 1 is the opposite bit.

[0141] The second bit remainder pair is determined using the following relationship: ​ ( n ) = ​ ( n XOR ​ ( n ).

[0142] The synchronization signal determination module 7 is configured such that each of computers A and B determines the synchronization signal based on bit product pairs and bit remainder pairs.

[0143] The synchronization signal determination module 7 may include determination submodule DET41 7A and determination submodule DET42 7B.

[0144] Computer A's determining submodule 7A is configured to determine the first synchronization signal. ​ ( n ).

[0145] The first synchronization signal is determined as follows.​ ( n ).

[0146] if ​ ( n ) = Then the first synchronization signal ​ ( n ) equals the synchronization signal in iteration n-1. ​ ( n -1).

[0147] if ​ ( n )≠ And if ra If 0 = 0, then the first synchronization signal ​ ( n This is equal to the control instructions calculated by computer A in iteration n-1. ​ ( n -1).

[0148] if ​ ( n )≠ And if ra 0 = 1, then the first synchronization signal ​ ( n This is equal to the control command calculated by computer A in iteration n-2. ​ ( n -2).

[0149] Computer B's determining submodule 7B is configured to determine the second synchronization signal. ​ ( n ).

[0150] The second synchronization signal is determined as follows. ​ ( n ).

[0151] if ​ ( n ) = Then the second synchronization signal ​ ( n ) equals the second synchronization signal in iteration n-1. ​ ( n -1).

[0152] if ​ ( n )≠ And if rb If 0 = 0, then the second synchronization signal ​ ( n This is equal to the control instructions calculated by computer B in iteration n-1. ​ (n -1).

[0153] if ​ ( n )≠ And if rb 0 = 1, then the second synchronization signal ​ ( n This is equal to the control instructions calculated by computer B in iteration n-2. ​ ( n -2).

[0154] Furthermore, it is assumed that in the first iteration n = N, the following bit pairs are set in iteration N-1 as follows: ​ ( N -1) = ​ ( N -1) = ​ ( N -1) = ​ ( N -1) = .

[0155] ​ An exemplary implementation of System 1 is illustrated.

[0156] The right-hand column relates to computer A, and the left-hand column relates to computer B. The first row shows the control instructions calculated by computer A and computer B, respectively. ​ , ​ The example diagram. Note the control commands. ​ Relative to control commands ​ It was delayed by one iteration.

[0157] The last line shows the synchronization signal determined by System 1. ​ , ​ The chart. Note these signals. ​ and ​ It is synchronized.

[0158] The determination of various bit pairs is shown between the two rows of charts.

[0159] The letter F stands for "false" and corresponds to a bit equal to 0. The letter T stands for "true" and corresponds to a bit equal to 1. Parentheses are not used to avoid overwhelming the reader with too much information.

[0160] ​ (Not shown), synchronization is not performed. Therefore, ​ (1) = ​ (1) and ​ (1) = ​ (1).

[0161] ​ :

[0162] ​ (2) = ​ (2) = ​ (2) = ​ (2) = Therefore, synchronization is not performed.

[0163] therefore, ​ (2) = ​ (1) and ​ (2) = ​ (1).

[0164] ​ :

[0165] For computer A, ​ (2) different from ​ (1), but ​ (2) equals ​ (1). Therefore, ​ (3) = and ​ (2) = .therefore, ​ (3) = .

[0166] therefore, ​ (3) = ​ (2).

[0167] For computer B, ​ (2) equals ​ (1), but ​ (2) different from ​ (1). Therefore, ​ (3) = and ​ (2) = .therefore, ​ (3) = .

[0168] therefore, ​ (3) = ​ (2).

[0169] ​ :

[0170] For computer A, ​ (3) equals ​ (2) ​ (3) different from ​ (2). Therefore, ​ (4) = and ​ (3)= .therefore, ​ (4) = .

[0171] therefore, ​ (4) = ​ (3).

[0172] For computer B, ​ (3) different from ​ (2) ​ (3) equals ​ (2). Therefore, ​ (4) = and ​ (3)= .therefore, ​ (4) = .

[0173] therefore, ​ (4) = ​ (3).

[0174] ​ :

[0175] For computer A, ​ (4) equals ​ (3) and ​ (4) equals ​ (3). Therefore, ​ (5) = and ​ (4)= .therefore, ​ (5) = .

[0176] therefore, ​ (5) = ​ (4).

[0177] For computer B, ​ (4) equals ​ (3) and ​ (4) equals ​ (3). Therefore, ​ (5) = and ​ (4)= .therefore, ​ (5) = .

[0178] therefore, ​ (5) = ​ (4).

[0179] ​ :

[0180] For computer A, ​ (5) different from ​ (4), but ​ (5) equals ​ (4). Therefore, ​ (6) = and ​ (5) = .therefore, ​ (6) = .

[0181] therefore, ​ (6) = ​ (5).

[0182] For computer B, ​ (5) equals ​ (4), but ​ (5) different from ​ (4). Therefore, ​ (6) = and ​ (5) = .therefore, ​ (6) = .

[0183] therefore, ​ (6) = ​ (5).

[0184] ​ :

[0185] For computer A, ​ (6) different from ​ (5) and ​ (6) different from ​ (5). Therefore, ​ (7) = and ​ (6) = .therefore, ​ (7) = .

[0186] therefore, ​ (7) = ​ (5).

[0187] For computer B, ​ (6) different from ​ (5) and ​ (6) different from ​(5). Therefore, ​ (7) = and ​ (6) = .therefore, ​ (7) = .

[0188] therefore, ​ (7) = ​ (6).

[0189] ​ :

[0190] For computer A, ​ (7) equals ​ (6), but ​ (7) different from ​ (6). Therefore, ​ (8) = and ​ (7) = .therefore, ​ (8) = .

[0191] therefore, ​ (8) = ​ (7).

[0192] For computer B, ​ (7) different from ​ (6) But ​ (7) equals ​ (6). Therefore, ​ (8) = and ​ (7)= .therefore, ​ (8) = .

[0193] therefore, ​ (8) = ​ (7).

[0194] ​ :

[0195] For computer A, ​ (8) equals ​ (7) and ​ (8) equals ​ (7). Therefore, ​ (9) = and ​ (8)= .therefore, ​ (9) = .

[0196] therefore, ​ (9) = ​ (8).

[0197] For computer B, ​ (8) equals ​ (7) and ​ (8) equals ​ (7). Therefore, ​ (9) = and ​ (8)= .therefore, ​ (9) = .

[0198] therefore, ​ (9) = ​ (8).

[0199] The present invention also relates to a method for synchronizing computer A and computer B. ​ ).

[0200] The method comprises a set of steps implemented iteratively.

[0201] The set of steps implemented in each iteration n includes:

[0202] - The calculation step E1 implemented by the calculation module 2 is as follows: each of computers A and B calculates a bit. If the control instruction calculated by each of computers A and B in iteration n is equal to the control instruction calculated in iteration n-1, then the bit is equal to 0; otherwise, the bit is equal to 1.

[0203] - The switching step E2 implemented by the switching module 3 is as follows: each of the computers A and B switches the calculated bits;

[0204] - The signal pair determination step E3 implemented by the signal pair determination module 4 is characterized in that: each of computers A and B determines a bit signal pair, the bit signal pair including bits calculated by each of computers A and B;

[0205] - The product pair determination step E4, implemented by the product pair determination module 5, is that: each determined bit product pair in computers A and B indicates which bit equal to 1 in a determined bit signal pair for computers A and B in iteration n is equal to a bit in another determined bit signal pair for computers A and B in iteration n-1.

[0206] - The remainder pair determination step E5, implemented by the remainder pair determination module 6, is that: each determined bit remainder pair in computers A and B indicates which bit equal to 1 in a determined bit signal pair for computers A and B in iteration n is different from the bit in another determined bit signal pair for computers A and B in iteration n-1.

[0207] - The synchronization signal determination step E6, implemented by the synchronization signal determination module 7, is that each of computers A and B determines the synchronization signal based on bit product pairs and bit remainder pairs.

[0208] Calculation step E1 may include the following sub-steps:

[0209] - The computational sub-step E1A implemented by computational submodule 2A of computer A is as follows: Calculate the first bit, if the control instruction calculated by computer A in iteration n... ​ ( n This is equal to the control instructions calculated by computer A in iteration n-1. ​ ( n If -1), then the first bit is equal to 0; otherwise, the first bit is equal to 1.

[0210] - The computational sub-step E1B implemented by computational submodule 2B of computer B is as follows: Calculate the second bit if the control instruction calculated by computer B in iteration n... ​ ( n This is equal to the control command calculated by computer B in iteration n-1. ​ ( n If -1), then the second bit is equal to 0; otherwise, the second bit is equal to 1.

[0211] The exchange step E2 may include the following sub-steps:

[0212] - The transmission sub-step E2A implemented by the transmission sub-module 3A of computer A is to transmit the first bit calculated by computer A to computer B;

[0213] - The transmission sub-step E2B implemented by the transmission sub-module 3B of computer B is to transmit the second bit calculated by computer B to computer A.

[0214] Signal pair determination step E3 may include the following sub-steps:

[0215] - The determining sub-step E3A, implemented by the determining sub-module 4A of computer A, is to: determine the first bit signal pair ​ ( n ) = ,in ​0 is equal to a specific bit calculated in iteration n-1, and ​ 1 is equal to the opposite bit of the second bit calculated in iteration n-1;

[0216] - The determining sub-step E3B, implemented by the determining submodule 4B of computer B, involves: determining the second bit signal pair. ​ ( n ) = ,in ​ 0 is equal to a specific bit of the second bit calculated in iteration n-1, and ​ 1 is equal to the opposite bit of the first bit calculated in iteration n-1.

[0217] Step E4, which determines the product pair, may include the following sub-steps:

[0218] - The determining sub-step E4A, implemented by the determining submodule 5A of computer A, is to: determine the first bit product pair. ​ ( n ) = ,in ​ 0 is a specific bit and ​ 1 is the opposite bit.

[0219] • if( ​ ( n -1) = or ​ ( n -1) = )and ​ ( n ) = ,but ​ ( n ) = , ​ ( n -1) corresponds to the bit remainder pair determined in iteration n-1.

[0220] • if( ​ ( n -1) = and ​ ( n ) = )or( ​ ( n -1) = and ​ ( n ) = ),but ​ ( n ) = ,

[0221] • if( ​ ( n -1) = and ​ ( n ) = )or( ​ ( n -1) = and ​ ( n ) = ),but ​ ( n ) = ,

[0222] Otherwise, ​ ( n ) = ;

[0223] - The determining sub-step E4B, implemented by the determining submodule 5B of computer B, involves: determining the second bit product pair. ​ ( n ) = ,in ​ 0 is a specific bit and ​ 1 is the opposite bit.

[0224] • if( ​ ( n -1) = or ​ ( n -1) = )and ​ ( n ) = ,but Pb ( n ) = , Rs ( n -1) corresponds to the bit remainder pair determined in iteration n-1.

[0225] • if( Rs ( n -1) = and Sb ( n ) = )or( Rs ( n -1) = and Sb ( n ) = ),but Pb ( n ) = ,

[0226] • if( Rs ( n -1) = and Sb ( n ) = )or( Rs ( n -1) = and Sb ( n ) = ),but Pb ( n ) = ,

[0227] Otherwise, Pb ( n ) = .

[0228] The remainder pair determination step E5 may include the following sub-steps:

[0229] - The determining sub-step E5A, implemented by the determining submodule 6A of computer A, involves: determining the first bit remainder pair. Sun ( n ) = ,in ra 0 is a specific bit. ra 1 is the opposite bit, and Sun ( n ) = Sat ( n XOR Pa ( n );

[0230] - The determining sub-step E5B, implemented by the determining submodule 6B of computer B, involves: determining the second bit remainder pair. Rs ( n ) = ,in rb 0 is a specific bit. rb 1 is the opposite bit, and Rs ( n ) = Sb ( n XOR Pb ( n ).

[0231] Synchronization signal determination step E6 may include the following sub-steps:

[0232] - The determining sub-step E6A, implemented by the determining sub-module 7A of computer A, involves: determining the first synchronization signal. Yes ( n ),

[0233] • if Pa ( n ) = Then the first synchronization signal Yes ( n ) equals the first synchronization signal in iteration n-1. Yes ( n -1),

[0234] • if Pa ( n )≠ And if ra If 0 = 0, then the first synchronization signal Yes ( n This is equal to the control instructions calculated by computer A in iteration n-1. It ( n -1),

[0235] • if Pa ( n )≠ And if ra 0 = 1, then the first synchronization signal Yes ( n This is equal to the control command calculated by computer A in iteration n-2. It ( n -2);

[0236] - The determining sub-step E6B, implemented by the determining submodule 7B of computer B, involves: determining the second synchronization signal. Ob ( n ),

[0237] • if Pb ( n ) = Then the second synchronization signal Ob ( n ) equals the second synchronization signal in iteration n-1. Ob ( n -1),

[0238] • if Pb ( n )≠ And if rb If 0 = 0, then the second synchronization signal Ob ( n This is equal to the control instructions calculated by computer B in iteration n-1. Ib ( n -1),

[0239] • if Pb (n )≠ And if rb 0 = 1, then the second synchronization signal Ob ( n This is equal to the control instructions calculated by computer B in iteration n-2. Ib ( n -2).

Claims

1. A method for synchronizing a first computer (A) and a second computer (B), each of the computers (A, B) being configured to calculate control commands for control surface actuators of an aircraft (AC) according to the same flight rules, each of the computers (A, B) including a clock synchronized with each other, the first computer (A) having an advance or delay relative to the second computer (B), the advance or delay being unknown and finite in terms of time; Its features are, It comprises a set of steps implemented iteratively, wherein the set of steps implemented in each iteration n includes: - The calculation step (E1) implemented by the calculation module (2) is as follows: each of the computers (A, B) calculates a bit if the control instruction calculated by each of the computers (A, B) in iteration n... , Equal to the control command calculated in iteration n-1 , If the value is 0, then the bit is equal to 0; otherwise, the bit is equal to 1. - The switching step (E2) implemented by the switching module (3) is that each bit calculated by the switching module (A, B) is switched; - The signal pair determination step (E3) implemented by the signal pair determination module (4) is characterized in that: each determined bit signal pair in the computers (A, B) , Bit signal pair , This includes bits calculated by each of the computers (A, B); - The product pair determination step (E4) implemented by the product pair determination module (5) is characterized in that: each bit product pair in the computers (A, B) is determined. , Bit product pairs , Indicates a specific bit signal pair for one of the computers (A, B) in iteration n. , Which bit in the sequence equals 1 is equal to another specific bit signal pair in the computers (A, B) in iteration n-1? , bits in; - The remainder pair determination step (E5) implemented by the remainder pair determination module (6) is characterized in that: each determined bit remainder pair in the computers (A, B) , Bit remainder pair , Indicates a specific bit signal pair for one of the computers (A, B) in iteration n. , Which bit in the sequence equal to 1 is different from another specific bit signal pair in the computers (A, B) in iteration n-1? , bits in; - The synchronization signal determination step (E6) implemented by the synchronization signal determination module (7) is characterized in that: each bit-product pair in the computers (A, B) is used for... , Bit remainder pair , To determine the synchronization signal, The synchronization signal determination step (E6) includes the following sub-steps: - The first determining sub-step (E6A) implemented by the first determining sub-module (7A) of the first computer (A) is to: determine the first synchronization signal. Oa ( n ), • if Pa ( n )= Then the first synchronization signal Oa ( n ) equals the first synchronization signal in iteration n-1. Oa ( n -1), • if Pa ( n )≠ And if ra If 0 = 0, then the first synchronization signal Oa ( n The control instructions calculated by the first computer (A) in iteration n-1 are equal to the control instructions calculated by the first computer (A). Ia ( n -1), • if Pa ( n )≠ And if ra 0 = 1, then the first synchronization signal Oa ( n The control instructions calculated by the first computer (A) in iteration n-2 are equal to the control instructions calculated by the first computer (A). Ia ( n -2); - The second determining sub-step (E6B) implemented by the second determining sub-module (7B) of the second computer (B) is to: determine the second synchronization signal. Ob ( n ), • if Pb ( n )= Then the second synchronization signal Ob ( n ) equals the second synchronization signal in iteration n-1. Ob ( n -1), • if Pb ( n )≠ And if rb If 0 = 0, then the second synchronization signal Ob ( n The control instructions calculated by the second computer (B) in iteration n-1 are equal to the control instructions calculated by the second computer (B). Ib ( n -1), • if Pb ( n )≠ And if rb 0 = 1, then the second synchronization signal Ob ( n This is equal to the control command calculated by the second computer (B) in iteration n-2. Ib ( n -2).

2. The method according to claim 1, Its features are, The calculation step (E1) includes the following sub-steps: - The first computational sub-step (E1A) implemented by the first computational submodule (2A) of the first computer (A) is as follows: Calculate the first bit if the control instruction calculated by the first computer (A) in iteration n... Ia ( n The control command calculated in iteration n-1 is equal to the control command. Ia ( n If -1), then the first bit is equal to 0; otherwise, the first bit is equal to 1. - The second computational sub-step (E1B) implemented by the second computational submodule (2B) of the second computer (B) is as follows: Calculate the second bit if the control instruction calculated by the second computer (B) in iteration n... Ib ( n The control command calculated in iteration n-1 is equal to the control command. Ib ( n If -1), then the second bit is equal to 0; otherwise, the second bit is equal to 1.

3. The method according to any one of claims 1 and 2, Its features are, The swap step (E2) includes the following sub-steps: - The first transmission sub-step (E2A) implemented by the first transmission sub-module (3A) of the first computer (A) is to transmit the first bit to the second computer (B). - The second transmission sub-step (E2B) implemented by the second transmission sub-module (3B) of the second computer (B) is to transmit the second bit to the first computer (A).

4. The method according to any one of claims 1 and 2, Its features are, The signal pair determination step (E3) includes the following sub-steps: - The third determining sub-step (E3A) implemented by the third determining sub-module (4A) of the first computer (A) is to: determine the first bit signal pair Sa ( n )= ,in sa 0 is equal to a specific bit calculated in iteration n-1, and sa 1 is equal to the opposite bit of the second bit calculated in iteration n-1; - The fourth determination sub-step (E3B) implemented by the fourth determination sub-module (4B) of the second computer (B) is as follows: determining the second bit signal pair Sb ( n )= ,in sb 0 is equal to a specific bit of the second bit calculated in iteration n-1, and sb 1 is equal to the opposite bit of the first bit calculated in iteration n-1.

5. The method according to any one of claims 1 and 2, Its features are, The product pair determination step (E4) includes the following sub-steps: - The fifth determining sub-step (E4A) implemented by the fifth determining sub-module (5A) of the first computer (A) is to: determine the first bit product pair Pa ( n )= ,in pa 0 is a specific bit and pa 1 is the opposite bit. • if( Ra ( n -1)= or Ra ( n -1) = )and Sa ( n ) = ,but Pa ( n ) = , Ra ( n -1) corresponds to the bit remainder pair determined in iteration n-1. • if( Ra ( n -1)= and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n )= , • if( Ra ( n -1)= and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n ) = , Otherwise, Pa ( n )= ; - The sixth determining sub-step (E4B) implemented by the sixth determining sub-module (5B) of the second computer (B) is to: determine the second bit product pair Pb ( n )= ,in pb 0 is a specific bit and pb 1 is the opposite bit. • if( Rb ( n -1)= or Rb ( n -1) = )and Sb ( n ) = ,but Pb ( n ) = , Rb ( n -1) corresponds to the bit remainder pair determined in iteration n-1. • if( Rb ( n -1)= and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n )= , • if( Rb ( n -1)= and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n ) = , Otherwise, Pb ( n )= .

6. The method according to any one of claims 1 and 2, Its features are, The remainder pair determination step (E5) includes the following sub-steps: - The seventh determining sub-step (E5A) implemented by the seventh determining sub-module (6A) of the first computer (A) is as follows: determining the first bit remainder pair Ra ( n )= ,in ra 0 is a specific bit. ra 1 is the opposite bit, and Ra ( n ) = Sa ( n XOR Pa ( n ); - The eighth determining sub-step (E5B) implemented by the eighth determining sub-module (6B) of the second computer (B) is as follows: determining the second bit remainder pair Rb ( n )= ,in rb 0 is a specific bit. rb 1 is the opposite bit, and Rb ( n ) = Sb ( n XOR Pb ( n ).

7. A system (1) for synchronizing a first computer (A) and a second computer (B), each of the computers (A, B) being configured to calculate control commands for control surface actuators of an aircraft (AC) according to the same flight rules, each of the computers (A, B) including a clock synchronized with each other, the first computer (A) having an advance or delay relative to the second computer (B), the advance or delay being unknown and finite in terms of time; Its features are, System (1) includes a first computer (A), a second computer (B), and a set of modules implemented iteratively, the set of modules implemented at each iteration n including: - Calculation module (2), which is configured such that each of the computers (A, B) calculates a bit if a control instruction is calculated by each of the computers (A, B) in iteration n. , Equal to the control command calculated in iteration n-1 , If the value is 0, then the bit is equal to 0; otherwise, the bit is equal to 1. - A switching module (3) configured to cause each of the computers (A, B) to exchange the calculated bits; - Signal pair determination module (4), which is configured such that each determined bit signal pair in the computers (A, B) , Bit signal pair , This includes bits calculated by each of the computers (A, B); - Product pair determination module (5), which is configured to determine each bit product pair in the computers (A, B) , Bit product pairs , Indicates a specific bit signal pair for one of the computers (A, B) in iteration n. , Which bit in the sequence equals 1 is equal to another specific bit signal pair in the computers (A, B) in iteration n-1? , bits in; - Remainder Pair Determination Module (6), which is configured to determine each bit remainder pair in the computers (A, B) , Bit remainder pair , Indicates a specific bit signal pair for one of the computers (A, B) in iteration n. , Which bit in the sequence equal to 1 is different from another specific bit signal pair in the computers (A, B) in iteration n-1? , bits in; - A synchronization signal determination module (7) is configured such that each bit-product pair in the computers (A, B) , Bit remainder pair , To determine the synchronization signal, The synchronization signal determination module (7) includes the following sub-modules: - A first determining submodule (7A) of a first computer (A) is configured to determine a first synchronization signal. Oa ( n ), • if Pa ( n )= Then the first synchronization signal Oa ( n ) equals the first synchronization signal in iteration n-1. Oa ( n -1), • if Pa ( n )≠ And if ra If 0 = 0, then the first synchronization signal Oa ( n The control instructions calculated by the first computer (A) in iteration n-1 are equal to the control instructions calculated by the first computer (A). Ia ( n -1), • if Pa ( n )≠ And if ra 0 = 1, then the first synchronization signal Oa ( n The control instructions calculated by the first computer (A) in iteration n-2 are equal to the control instructions calculated by the first computer (A). Ia ( n -2); - The second determining submodule (7B) of the second computer (B) is configured to determine the second synchronization signal. Ob ( n ), • if Pb ( n )= Then the second synchronization signal Ob ( n ) equals the second synchronization signal in iteration n-1. Ob ( n -1), • if Pb ( n )≠ And if rb If 0 = 0, then the second synchronization signal Ob ( n The control instructions calculated by the second computer (B) in iteration n-1 are equal to the control instructions calculated by the second computer (B). Ib ( n -1), • if Pb ( n )≠ And if rb 0 = 1, then the second synchronization signal Ob ( n This is equal to the control command calculated by the second computer (B) in iteration n-2. Ib ( n -2).

8. The system according to claim 7, Its features are, The calculation module (2) includes the following sub-modules: - A first computing submodule (2A) of a first computer (A), configured to compute a first bit, if the first computer (A) computes a control instruction in iteration n. Ia ( n The control command calculated in iteration n-1 is equal to the control command. Ia ( n If -1), then the first bit is equal to 0; otherwise, the first bit is equal to 1. - The second computing submodule (2B) of the second computer (B) is configured to compute the second bit if the control instruction computed by the second computer (B) in iteration n... Ib ( n The control command calculated in iteration n-1 is equal to the control command. Ib ( n If -1), then the second bit is equal to 0; otherwise, the second bit is equal to 1.

9. The system according to any one of claims 7 and 8, Its features are, The switching module (3) includes the following sub-modules: - A first transmission submodule (3A) of a first computer (A) is configured to transmit a first bit to a second computer (B). - The second transmission submodule (3B) of the second computer (B) is configured to transmit the second bit to the first computer (A).

10. The system according to any one of claims 7 and 8, Its features are, The signal pair determination module (4) includes the following sub-modules: - A third determining submodule (4A) of the first computer (A), configured to determine the first bit signal pair Sa ( n )= ,in sa 0 is equal to the first specific bit of the first bit calculated in iteration n-1, and sa 1 is equal to the second inverse bit of the second bit calculated in iteration n-1; - The fourth determining submodule (4B) of the second computer (B), which is configured to determine the second bit signal pair Sb ( n )= ,in sb 0 is equal to the second specific bit calculated in iteration n-1, and sb 1 is equal to the first opposite bit of the first bit calculated in iteration n-1.

11. The system according to any one of claims 7 and 8, Its features are, The product pair determination module (5) includes the following sub-modules: - The fifth determining submodule (5A) of the first computer (A), which is configured to determine the first bit product pair Pa ( n )= ,in pa 0 is a specific bit and pa 1 is the opposite bit. • if( Ra ( n -1)= or Ra ( n -1) = )and Sa ( n ) = ,but Pa ( n ) = , Ra ( n -1) corresponds to the bit remainder pair determined in iteration n-1. • if( Ra ( n -1)= and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n )= , • if( Ra ( n -1)= and Sa ( n ) = )or( Ra ( n -1) = and Sa ( n ) = ),but Pa ( n ) = , Otherwise, Pa ( n )= ; - The sixth determining submodule (5B) of the second computer (B), which is configured to determine the second bit product pair Pb ( n )= ,in pb 0 is a specific bit and pb 1 is the opposite bit. • if( Rb ( n -1)= or Rb ( n -1) = )and Sb ( n ) = ,but Pb ( n ) = , Rb ( n -1) corresponds to the bit remainder pair determined in iteration n-1. • if( Rb ( n -1)= and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n )= , • if( Rb ( n -1)= and Sb ( n ) = )or( Rb ( n -1) = and Sb ( n ) = ),but Pb ( n ) = , Otherwise, Pb ( n )= .

12. The system according to any one of claims 7 and 8, Its features are, The remainder pair determination module (6) includes the following sub-modules: - The seventh determining submodule (6A) of the first computer (A), which is configured to determine the first bit remainder pair Ra ( n )= ,in ra 0 is a specific bit. ra 1 is the opposite bit, and Ra ( n ) = Sa ( n XOR Pa ( n ); - The eighth determining submodule (6B) of the second computer (B), which is configured to determine the second bit remainder pair Rb ( n )= ,in rb 0 is a specific bit. rb 1 is the opposite bit, and Rb ( n ) = Sb ( n XOR Pb ( n ).

13. Flight control systems for aircraft. It includes at least one system (1) for synchronizing a first computer (A) and a second computer (B) according to any one of claims 7 to 12.

14. Airplane It includes the flight control system according to claim 13.

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