Barrier layer formation method and method for manufacturing semiconductor device

Abstract

A method for forming a barrier layer is provided that enables uniform distribution of dopant within a three-dimensional substrate, even when the substrate has a high aspect ratio. In this method, a barrier layer is formed on the substrate before forming a dopant-containing layer on the substrate having a three-dimensional structure. At this time, an atomic layer deposition (ALD) process is used to control at least one of the film thickness, film quality, and film type of the barrier layer in the height direction of the three-dimensional structure.

Description

Technical Field

[0001] This invention relates to a barrier layer formation method and a method for manufacturing a semiconductor device, and particularly to a barrier layer formation method used in the case of doping a substrate layer during the manufacturing process of a semiconductor device such as a FinFET. Background Technology

[0002] Previously, with the increasing integration of semiconductor chips, planar transistors such as MOSFETs have gradually become smaller, faster, and lower in power consumption. However, in existing planar transistors, even with miniaturization of the channel length, the so-called short-channel effect, which cannot be controlled by the gate voltage, cannot be suppressed, thus limiting the miniaturization of planar transistors. Therefore, research and development of three-dimensional transistors, primarily FinFETs, is actively underway.

[0003] Three-dimensional transistors have a three-dimensional structure in which the gate electrode surrounds the channel portion, thus exhibiting superior control over the channel region by the gate electrode compared to existing planar transistors, making them more suitable for miniaturization. Furthermore, this superior controllability enables high-speed operation and low-power consumption characteristics exceeding those of planar transistors, thereby also facilitating the reduction of pattern area.

[0004] On the other hand, three-dimensional transistors have a more complex structure compared to planar transistors, thus leading to increased sophistication, complexity, and cost in manufacturing. However, recent advancements in microfabrication technology have enabled the manufacture of three-dimensional transistors with significantly reduced manufacturing costs, raising expectations for their future application in various system LSIs across various industrial sectors.

[0005] As an example of a three-dimensional transistor, a FinFET has one or more fins formed in a channel region between the source and drain electrodes and disposed on a silicon substrate. The gate electrode is formed across these one or more fins, resulting in a so-called dual-gate structure. Utilizing this dual-gate structure, the aforementioned controllability of the FinFET is superior to that of a single-gate MOSFET.

[0006] Furthermore, for the purpose of forming extended electrodes for FinFETs, a method has been proposed to form a dopant-containing layer for doping the upper surface and sides of one or more fins using atomic layer deposition (ALD) (Patent Document 1). ALD is a film deposition method that forms an atomic film on the substrate surface in one-atom-unit increments through self-control, enabling the formation of extremely thin films. Therefore, when trenches with high aspect ratios (depth dimension / width dimension) are formed in the channel region due to the increasing complexity of the fin structure, it is superior to other film deposition methods such as CVD and PVD in that it can uniformly form a dopant-containing layer on the upper surface and sides of the fin.

[0007] In recent years, to meet the demands for higher performance and density in devices, there has been a desire to form three-dimensional structures with higher aspect ratios in the channel region. However, with high aspect ratios, such as... Figure 10 As shown, in the upper region 100a of the substrate 100 with a three-dimensional structure, the thickness of the doped layer 120A tends to be thicker, while in the lower region 100b, the thickness of the doped layer 120A tends to be thinner. Alternatively, in the upper region 100a containing the upper surface of the substrate 100, the dopant concentration of the doped layer 120B tends to be higher, while in the lower region 100b, the dopant concentration of the doped layer 120B tends to be lower. As a result, there is a problem that the distribution of dopant within the drive-in substrate 100 becomes non-uniform in the height direction of the substrate. That is, this non-uniformity is considered to be caused by the non-uniformity of the coverage of the doped layer itself and the non-uniformity of the dopant concentration within the doped layer.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0249013 Summary of the Invention

[0011] The technical problem that the invention aims to solve

[0012] The purpose of this invention is to provide a method for forming a barrier layer and a method for manufacturing a semiconductor device that enables the dopant to be uniformly distributed within the substrate layer even when the substrate layer has a three-dimensional structure with a high aspect ratio.

[0013] Technical solutions for solving technical problems

[0014] To achieve the above objectives, the present invention provides the following solutions.

[0015] [1] A method for forming a barrier layer, wherein a barrier layer is formed on a substrate layer having a three-dimensional structure before forming a dopant layer thereon, characterized in that,

[0016] Using atomic layer deposition (ALD) technology, at least one of the film thickness, film quality, and film type of the barrier layer is controlled in the height direction of the three-dimensional structure.

[0017] [2] According to the barrier layer formation method described in [1] above, the atomic layer deposition process is plasma enhanced atomic layer deposition process, i.e., PEALD process.

[0018] [3] According to the barrier layer formation method described in [2] above, the film thickness of the barrier layer formed on the side of the three-dimensional structure is controlled by adjusting the application time of the RF power.

[0019] [4] According to the barrier layer formation method described in [2] above, the film thickness of the barrier layer formed on the upper surface of the three-dimensional structure is controlled by adjusting the RF power and the application time of the RF power.

[0020] [5] According to the barrier layer formation method described in [2] above, the film quality of the barrier layer is controlled by adjusting the RF power and the application time of the RF power.

[0021] [6] According to the barrier layer formation method described in [2] above, the barrier layer is composed of SiN with regional selectivity or SiON, and the film species of the barrier layer is controlled by adjusting the concentration of N element.

[0022] [7] According to the barrier layer forming method described in [1] above, the three-dimensional structure includes a trench, wherein the aspect ratio of the trench, i.e., the height dimension / width dimension, is 10 to 100.

[0023] [8] A method for manufacturing a semiconductor device, comprising:

[0024] Step (A) to form a base layer with a three-dimensional structure;

[0025] Step (B) of forming a barrier layer on the substrate layer;

[0026] Step (C) involves forming a doped layer on the barrier layer using atomic layer deposition (ALD) technology.

[0027] The heat treatment step (D);

[0028] In step (B), an atomic layer deposition process is used to control at least one of the film thickness, film quality, and film type of the barrier layer in the height direction of the three-dimensional structure.

[0029] In step (D), the dopant contained in the dopant layer diffuses to the substrate layer via the barrier layer.

[0030] [9] In the semiconductor device manufacturing method described in [8] above, in step (B), the atomic layer deposition process is a plasma enhanced atomic layer deposition process, i.e., PEALD process.

[0031]

[10] In the method for manufacturing a semiconductor device according to [8] above, in step (B), the thickness of the barrier layer formed on the side of the three-dimensional structure is controlled by adjusting the application time of the RF power.

[0032]

[11] In the method for manufacturing a semiconductor device according to [8] above, in step (B), the thickness of the barrier layer formed on the upper surface of the three-dimensional structure is controlled by adjusting the RF power and the application time of the RF power.

[0033]

[12] In the method for manufacturing a semiconductor device according to [8] above, in step (B), the film quality of the barrier layer is controlled by adjusting the RF power and the application time of the RF power.

[0034]

[13] According to the semiconductor device manufacturing method described above [8], in step (B), the barrier layer is formed by SiN with regional selectivity or by SiON, and the film type of the barrier layer is controlled by adjusting the concentration of N element.

[0035]

[14] In the semiconductor device manufacturing method described in [8] above, in step (C), the atomic layer deposition process is a plasma enhanced atomic layer deposition process, i.e., PEALD process.

[0036]

[15] In the method for manufacturing a semiconductor device according to [8] above, in step (C), the concentration of the dopant in the dopant-containing layer is controlled in the height direction of the three-dimensional structure.

[0037]

[16] In the method of manufacturing a semiconductor device according to

[15] above, the concentration of the dopant in the dopant layer is reduced along the direction from the upper region of the three-dimensional structure toward the lower region.

[0038]

[17] In the method for manufacturing a semiconductor device according to

[16] above, the dopant is either element B or element P.

[0039]

[18] In the method for manufacturing a semiconductor device according to [8] above, the three-dimensional structure includes a trench, wherein the aspect ratio of the trench, i.e., the height dimension / width dimension, is 10 to 100.

[0040] The effects of the invention

[0041] According to the present invention, even in the case of a three-dimensional structure with a high aspect ratio in the substrate layer, the dopant can be uniformly distributed within the substrate layer. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating the barrier layer formation method and the semiconductor device manufacturing method according to embodiments of the present invention.

[0043] Figures 2A to 2D They are respectively for Figure 1 A schematic diagram illustrating an example of steps (A) to (D) in the diagram.

[0044] Figure 3 yes Figure 1 A timing diagram of the manufacturing process of a semiconductor device.

[0045] Figures 4A to 4C These are electron microscope images of the barrier layers formed in the upper, central, and lower regions of the basal layer when the RF power is applied for a time of 1.0 sec.

[0046] Figures 5A to 5C These are electron microscope images of the barrier layers formed in the upper, central, and lower regions of the basal layer when the RF power is applied for a time of 0.05 sec.

[0047] Figure 6 It is a graph showing the relationship between the thickness of the barrier layer and the concentration of dopant (P) in the dopant diffusion layer of the substrate.

[0048] Figure 7A and Figure 7B Yes Figure 2B and Figure 2C A schematic diagram illustrating a variation of the steps shown.

[0049] Figures 8A to 8D This is a schematic diagram illustrating another example of the manufacturing method of the semiconductor device shown in Figure 2.

[0050] Figure 9A and Figure 9B Yes Figure 8B and Figure 8C A schematic diagram illustrating a variation of the steps shown.

[0051] Figure 10 This is a schematic diagram illustrating the manufacturing method of existing semiconductor devices.

[0052] Explanation of reference numerals in the attached figures

[0053] 10 Substrate layer; 10a Upper region; 10b Lower region; 10c Side layer; 11A Barrier layer; 11B Barrier layer; 12A Doped layer; 12B Doped layer; 20 Trench; 30 Doped diffusion layer; 100 Substrate layer; 100a Upper region; 100b Lower region; 120A Doped layer; 120B Doped layer. Detailed Implementation

[0054] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings used in the following description, the feature parts will be enlarged for ease of understanding, and the shape, size, and proportions of each component are not limited to the content shown in the drawings.

[0055] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2A to 2D They are respectively for Figure 1 A schematic diagram illustrating an example of steps (A) to (D) in the diagram.

[0056] like Figure 1 As shown, the semiconductor device manufacturing method according to an embodiment of the present invention includes: a step (A) of forming a substrate layer having a three-dimensional structure; a step (B) of forming a barrier layer on the substrate layer; a step (C) of forming a dopant layer on the barrier layer using atomic layer deposition (ALD); and a step (D) of performing heat treatment. Although the manufacturing method of this embodiment includes steps (A) to (D), it is not limited to these steps and may include other steps. Hereinafter, each of steps (A) to (D) will be described.

[0057] <Step (A)>

[0058] First, by performing etching such as deep etching on the substrate, a three-dimensional substrate layer 10 is formed, which becomes the object of dopant diffusion. Figure 2A The substrate 10 is not particularly limited, for example, it is a channel region formed between the source and drain electrodes. The three-dimensional structure provided in the substrate 10 is formed, for example, by convex patterns and concave patterns.

[0059] The aforementioned three-dimensional structure, as a recessed pattern, may include grooves 20 having opposing sides and a bottom surface. When the aforementioned three-dimensional structure includes grooves, the depth-to-width ratio (height dimension / width dimension) of the grooves is not particularly limited, but is preferably 10 to 100, more preferably 50 to 100, and even more preferably 70 to 100.

[0060] The substrate 10 may be made of silicon (Si), but is not limited to this, and may also be made of a material with Si as the main component. A material with silicon as the main component refers to a material with a silicon content of more than 50% by mass.

[0061] <Step (B)>

[0062] Next, using the ALD process, at least one of the film thickness, film quality, and film type of the barrier layer is controlled in the height direction (also called the depth direction) of the aforementioned three-dimensional structure. Preferably, the ALD process in step (B) is plasma-enhanced atomic layer deposition (PEALD) (hereinafter also referred to as PEALD process). This allows for control of film density, film stress, etc., and compared to the thermal ALD process, it achieves simplicity in the gas supply for the active material and a shorter cycle time.

[0063] It should be noted that the "layer" in barrier layer refers to a thick structure formed on the surface of the substrate layer, synonymous with "film." The same applies to the doped layer discussed later. Barrier layers will be explained in detail below.

[0064] In this embodiment, the film thickness of the barrier layer 11A can be controlled in the height direction of the three-dimensional structure using the PEALD process. Figure 2B For example, by adjusting the application time of the RF power, the film thickness of the barrier layer 11A formed on the side of the three-dimensional structure can be controlled.

[0065] Furthermore, the thickness of the barrier layer 11A can be controlled in the width direction (lateral direction) of the three-dimensional structure using the PEALD process. For example, by adjusting the RF power and the application time of the RF power, the thickness of the barrier layer 11A formed in the lateral direction of the three-dimensional structure of the substrate layer 10, i.e., on the upper surface of the three-dimensional structure, can be controlled. After a certain period of time, the barrier layer 11A formed on the upper surface of the three-dimensional structure reaches a saturation state, and the film formation reaction becomes a bottleneck. Therefore, even if the RF power and the application time of the RF power are increased, the film thickness will not increase further. Thus, in the upper region 10a of the three-dimensional structure, the difference in thickness between the barrier layer 11A formed on the upper surface of the three-dimensional structure and the barrier layer 11A formed on the side can be controlled within a certain range.

[0066] As a specific example of step (B), for example, Figure 3As shown, a barrier layer forming gas and a reactant gas for generating reactive substances are pulsedly supplied to the reaction space containing the substrate layer 10. After purging or venting, RF power is pulsedly applied to the reaction space for a predetermined time, thereby generating a barrier layer precursor on the upper and side surfaces of the three-dimensional structure. Furthermore, the reactant gas can be continuously supplied to the reaction space during the above steps. One cycle is formed by supplying the barrier layer forming gas and the reactant gas, the purging step, and the RF power application step, and this cycle is performed once or multiple times, thereby forming a barrier layer 11A on the upper, side, and bottom surfaces of the three-dimensional structure of the substrate layer 10.

[0067] The barrier layer forming gas is a gas obtained by vaporizing the film-forming raw material, such as a Si-containing gas, a Ti-containing gas, or a Ge-containing gas. The reactant gas is a reactive gas used to generate reactive substances and produce oxygen plasma in the reaction space by applying RF power; for example, it contains one or more of O2, N2O, H2O, and N2. The barrier layer precursor is a single molecular layer formed by the reaction of adsorbed molecules chemically adsorbed onto the surface of a three-dimensional structure with reactive substances such as free radicals; for example, it is composed of silicon oxide (SiO), titanium oxide (TiO), germanium oxide (GeO), silicon nitride (SiN), or silicon oxynitride (SiON). The barrier layer 11A is a layer formed by stacking one or more of the above-mentioned barrier layer precursors, and is the same as the barrier layer precursor, for example, composed of SiO, TiO, or GeO.

[0068] In step (B), the barrier layer forming gas and the reactant-containing gas are supplied to the reaction space in pulses for a specified time. The pulses for supplying the barrier layer forming gas and the reactant-containing gas can be the same or different. Then, purging or venting is performed for a specified time to remove the gas containing unreacted substances and products from the reaction space. The RF power and the application time of the RF power can be combined in various ways depending on specifications. The RF power range is, for example, 50W to 800W, and the application time of the RF power in one cycle is, for example, 0.1sec to 2sec.

[0069] When the barrier layer precursor is composed of SiO, one or more organoamino silanes, including bis(diethylamino)silane (BDEAS), tetra(dimethylamino)silane (4DMAS), tri(dimethylamino)silane (3DMAS), bis(dimethylamino)silane (2DMAS), tetra(ethylmethylamino)silane (4EMAS), tri(ethylmethylamino)silane (3EMAS), bis(tert-butylamino)silane (BTBAS), and bis(ethylmethylamino)silane (BEMAS), can be used as film-forming materials.

[0070] The thickness of the barrier layer 11A formed in step (B) is not particularly limited, but for example, the thickness of the barrier layer 11A formed on the upper surface of the three-dimensional structure is less than 5 nm, and the thickness of the barrier layer 11A formed on the side surface of the three-dimensional structure is 0.1 nm to 5 nm.

[0071] Figures 4A to 4C Figures 4 and 5 show electron micrographs of the barrier layers formed in the upper, central, and lower regions of the substrate when the RF power is applied for 1.0 sec in one cycle. It should be noted that the trench aspect ratio (height / width) in the 3D structures of Figures 4 and 5 is 40, the barrier layer is SiO, and the applied RF power is 50 W. Figures 4A to 4C As shown, when the RF power is applied for 1.0 sec, it can be confirmed that a barrier layer is formed on the upper surface, side surface, and bottom surface of the three-dimensional structure. Furthermore, it can be confirmed that the barrier layer formed on the side surface of the three-dimensional structure thins along the direction from the upper surface of the three-dimensional structure toward the bottom surface.

[0072] Next, in Figures 5A to 5C The value shown represents the case where the RF power application time in one cycle is 0.05 seconds. In this case, it can be confirmed that a barrier layer is formed on the upper and side surfaces of the three-dimensional structure. Figures 5A to 5C ), where a barrier layer of uneven thickness is formed on the bottom surface of the three-dimensional structure, or where a barrier layer is not formed in certain areas. Figure 5C Furthermore, it can be confirmed that the barrier layer formed on the side of the three-dimensional structure thins along the direction from the upper surface of the three-dimensional structure toward the bottom surface, and is formed thinner overall compared to the case where the RF power is applied for 0.05 seconds.

[0073] As can be seen from the above results, the thickness of the barrier layer 11A formed on the side of the three-dimensional structure can be controlled by the duration of RF power application. Furthermore, by making the RF power application time appropriate, the thickness of the barrier layer 11A formed on the side of the three-dimensional structure can be gradually reduced along the direction from the upper surface of the three-dimensional structure toward the bottom surface.

[0074] <Step (C)>

[0075] Next, using the ALD process, a doped layer 12A is formed on the barrier layer 11A. Figure 2C The ALD process in step (C) is the same as in step (B), and is preferably the PEALD process.

[0076] For example, such as Figure 3 As shown, a dopant-containing layer formation gas and a reactant-containing gas for generating reactive substances are pulsed into the reaction space. After purging or venting, RF power is pulsed into the reaction space for a predetermined time, thereby generating a dopant-containing layer precursor on the upper and side surfaces of the three-dimensional structure. Furthermore, the reactant-containing gas can be continuously supplied into the reaction space during the above steps. One cycle is formed by these steps of supplying the dopant-containing layer formation gas and reactant, the purging step, and the application of RF power. This cycle is performed once or multiple times to form a dopant-containing layer 12A on the barrier layer 11A.

[0077] The gas used to form the dopant layer is a gas obtained by vaporizing the film-forming material, such as a P-containing gas or a B-containing gas. The reactant gas is the same as in step (B), and is the reactive gas used to generate reactive substances and produce oxygen plasma in the reaction space by applying RF power; for example, it includes one or more of O2, N2O, and H2O. The dopant layer precursor is a monolayer formed by the reaction of adsorbed molecules chemically adsorbed onto the surface of a three-dimensional structure with active substances such as free radicals; for example, it is composed of phosphosilicate glass or borosilicate glass. The dopant layer 12A is a layer formed by stacking one or more of the above-mentioned dopant layer precursors, and is the same as the dopant layer precursor, for example, composed of phosphosilicate glass or borosilicate glass.

[0078] When the barrier layer precursor is made of phosphosilicate glass, one or more organophosphorus compounds containing P(OCH3)3 or PO(C2H5O)3 can be used as film-forming materials. Furthermore, when the barrier layer precursor is made of borosilicate glass, one or more organoboron compounds containing B(C2H5O)3 or B(CH3O)3 can be used as film-forming materials.

[0079] The thickness of the doped layer 12A formed in step (C) decreases along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure. However, it is not limited to this; the thickness of the doped layer 12A may also be uniform along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure. The thickness of the doped layer 12A is not particularly limited, but for example, the thickness of the doped layer 12A formed on the upper surface of the three-dimensional structure is 1 nm to 10 nm, and the thickness of the doped layer 12A formed on the side surface of the three-dimensional structure is 1 nm to 10 nm.

[0080] <Step (D)>

[0081] Subsequently, heat treatment is performed to allow the dopant contained in the dopant layer 12A to diffuse into the base layer 10 via the barrier layer 11A. Figure 2D In this embodiment, the concentration of dopant in the dopant-containing layer 12A is substantially uniform along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure. At this time, the dopant in the dopant-containing layer 12A diffuses into the substrate layer 10 through the barrier layer 11A, whose thickness is controlled in the height direction of the three-dimensional structure. Therefore, the distribution or concentration of dopant in the dopant diffusion layer 30 can be made uniform in the height direction of the three-dimensional structure of the substrate layer 10. Thus, a conformal dopant diffusion layer 30 is formed integrally on the surface portion of the three-dimensional structure of the substrate layer 10.

[0082] The heat treatment in step (D) is, for example, annealing, with conditions such as a treatment temperature of 800°C to 1200°C and a treatment time of 0.5 sec to 5 sec. This significantly increases the diffusion rate of the dopant from the dopant-containing layer 12A to the substrate layer 10. The dopant is a solid-diffusion (SSD) material to the substrate layer 10, and can be, for example, either element B or element P.

[0083] Then, the dopant-containing layer 12A and the barrier layer 11A after dopant diffusion are removed by etching such as wet etching, thus ending the process. Furthermore, from the viewpoint of simplifying the steps, the etching of the dopant-containing layer 12A and the barrier layer 11A may be omitted.

[0084] Figure 6 This is a graph showing the relationship between the thickness of the barrier layer and the dopant concentration in the dopant diffusion layer of the substrate. Figure 6 In this context, the element P is used as an example of a dopant. According to... Figure 6As can be seen from the curve, the thickness of the barrier layer is related to the dopant concentration; if the thickness of the barrier layer increases, the dopant concentration decreases. Therefore, by forming the barrier layer such that its thickness decreases along the direction from the upper region to the lower region of the three-dimensional structure, the dopant in the dopant diffusion layer diffuses to the substrate layer through the barrier layer, thereby making the distribution or concentration of the dopant in the dopant diffusion layer uniform in the height direction of the three-dimensional structure of the substrate layer 10.

[0085] In the above embodiment, the film thickness of the barrier layer 11A is controlled in step (B), but the film quality of the barrier layer can be controlled instead of controlling the film thickness of the barrier layer 11A.

[0086] For example, such as Figure 7A As shown, a barrier layer 11B can be formed with varying film composition along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure. The dots in the barrier layer 11B in the figure represent film inhomogeneities. Then, as... Figure 7B As shown, a doped layer 12A can be formed on the barrier layer 11B by using the same method as in step (C) above.

[0087] The film quality of the barrier layer 11B can be controlled, for example, by adjusting the RF power and the application time of the RF power. Specifically, by setting the RF power and the application time of the RF power to appropriate ranges, the density of the barrier layer 11B can be varied. As a result, in step (C), the diffusion of dopant from the dopant layer 12A through the barrier layer 11B can be controlled. In particular, it is believed that by reducing the density of the barrier layer 11B formed on the side of the three-dimensional structure along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure, the distribution of dopant in the dopant diffusion layer 30 can be made uniform in the height direction of the three-dimensional structure of the substrate layer 10.

[0088] In addition to controlling the film thickness of the barrier layer 11A as described above, the film quality of the barrier layer 11A can also be further controlled. This allows for high-precision control of the barrier layer 11A, enabling a more uniform distribution of dopant in the dopant diffusion layer 30 along the height direction of the three-dimensional structure of the substrate layer 10.

[0089] The film type of the barrier layer 11A can be controlled instead of controlling the film thickness of the barrier layer 11A in step (B) of the above embodiment. For example, the film type of the barrier layer is (a) composed of SiN with regional selectivity or (b) composed of SiON, thereby controlling the film type by adjusting the concentration of N element.

[0090] Specifically, when the barrier layer is composed of SiN, it can be formed essentially by using the same method as step (B) above, employing an ALD process, preferably a PEALD process. That is, a barrier layer forming gas and a reactant gas for generating reactive substances are pulsedly supplied to the reaction space where the substrate 10 is placed. After purging or degassing, RF power is pulsedly applied to the reaction space for a predetermined time, thereby forming a barrier layer precursor on the upper and side surfaces of the three-dimensional structure. Furthermore, the reactant gas can be continuously supplied to the reaction space during the above steps. Each step—controlling the barrier layer forming gas and reactants, purging, and applying RF power—consists of one cycle, and this cycle is performed once or multiple times to form a barrier layer 11A on the upper and side surfaces of the three-dimensional structure of the substrate 10.

[0091] The aforementioned PEALD process is preferably a high-pressure PEALD process. In the high-pressure PEALD process, when the substrate layer 10 is brought into contact with nitrogen plasma within the reaction space, the pressure of the reaction space is, for example, 20 Torr or higher. Furthermore, the reaction temperature is, for example, 100°C to 650°C. The RF power used to generate the aforementioned nitrogen plasma is, for example, 500W to 1000W.

[0092] When the barrier layer precursor is made of SiN, the gas used to form the barrier layer is, for example, a Si-containing gas. The reactant gas is a reactive gas used to generate nitrogen plasma in the reaction space, and may contain, for example, one or more selected from NH3, N2H4, N2 / H2 mixtures, and N2. The barrier layer precursor is made of SiN.

[0093] In this case, as a film-forming material, for example, one or more halosilanes selected from HSiI3, H2SiI2, H3SiI, H2Si2I4, H4Si2I2, and H5Si2I can be used. Other specific examples of film-forming materials include silicon precursors or Si precursors as described in Japanese Patent Application Publication No. 2017-79327, which are incorporated herein by reference in their entirety.

[0094] During the SiN film formation process using the PEALD process, a SiN film serving as a barrier layer can be selectively formed on the surface of the three-dimensional structure of the substrate layer 10. For example, by using the difference in wet etching rates between the side surface and the top and bottom surfaces, film-forming portions and non-film-forming portions can be formed on the side surface of the three-dimensional structure. If the RF power is reduced, the etching rate of the side surface increases, while the etching rates of the top and bottom surfaces decrease. On the other hand, if the RF power is increased, the etching rate of the side surface decreases, while the etching rates of the top and bottom surfaces increase. Thus, by controlling the RF power, the difference between the etching rates of the side surface and the top and bottom surfaces can be adjusted. Furthermore, the N element in the SiN film suppresses the diffusion of dopants in the SiN film. Therefore, it is believed that by selectively forming the barrier layer on the side surface of the three-dimensional structure along the direction from the upper region 10a to the lower region 10b, the distribution of dopants in the dopant diffusion layer 30 can be made uniform in the height direction of the three-dimensional structure of the substrate layer 10.

[0095] Furthermore, in the case where the barrier layer is made of SiON, the above steps in the case where the barrier layer is made of SiN allow the barrier layer precursor to be formed from SiON by supplying a smaller amount of the reactant gas, i.e., the nitrogen-containing gas, than usual. In this case, the barrier layer forming gas and the reactant gas are the same as in the case where the barrier layer is made of SiN.

[0096] SiON films contain more oxygen (O) than nitrogen (N). The nitrogen content in SiON films is typically 3 to 20% to suppress dopant diffusion.

[0097] During the formation of the SiON film using the PEALD process, the concentration of nitrogen (N) in the SiON film, which serves as a barrier layer, can be varied along the surface of the three-dimensional structure of the substrate 10. For example, by controlling the RF power and / or irradiation time used in the nitriding plasma, the N content can be varied along the in-plane direction of the SiON film. Furthermore, the N content in the SiON film is similar to that in the formation of the SiN film, suppressing the diffusion of dopants in the SiON film. Therefore, it is believed that by reducing the concentration of N in the SiON film along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure, the distribution of dopants in the dopant diffusion layer 30 can be made uniform along the height direction of the three-dimensional structure of the substrate 10.

[0098] In addition to controlling the film thickness of the barrier layer 11A as described above, the film type of the barrier layer 11A can be further controlled. Furthermore, the film thickness, film quality, and film type of the barrier layer 11A can be controlled. Therefore, the barrier layer 11A can be controlled with higher precision, and the distribution of dopants in the dopant diffusion layer 30 can be made more uniform in the height direction of the three-dimensional structure of the substrate layer 10.

[0099] Figures 8A to 8D This is a schematic diagram illustrating another example of the manufacturing method of the semiconductor device shown in Figure 2. Figures 8A to 8D The manufacturing method shown is basically the same as Figures 2A to 2D The manufacturing methods shown are the same, and the same reference numerals are used for the same structures, while their descriptions are omitted.

[0100] like Figure 8B As shown, in step (B), with Figure 2B In the same case, the ALD process is used to form the barrier layer 11A on the side of the three-dimensional structure in such a way that the film thickness of the barrier layer 11A decreases in the direction from the upper region 10a of the three-dimensional structure toward the lower region 10b.

[0101] Next, in step (C), an ALD process is used to form a doped layer 12B on the barrier layer 11A. Figure 8C At this point, the concentration of dopant in the dopant-containing layer 12B can be controlled along the height direction of the three-dimensional structure. The dots in the dopant-containing layer 12B in the figure represent non-uniform dopant concentration. Specifically, the concentration of dopant contained in the dopant-containing layer 12B is reduced along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure. When the concentration of dopant contained in the dopant-containing layer 12B is controlled, the film thickness of the dopant-containing layer 12B is not particularly limited; it can increase along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure, remain approximately constant, or decrease along this direction.

[0102] By adjusting the concentration of the dopant in the dopant-containing layer 12B, the amount of dopant diffusion in the substrate layer 10 can be controlled. Therefore, by forming the barrier layer 11A such that its thickness decreases from the upper region 10a to the lower region 10b of the three-dimensional structure, and by reducing the dopant concentration in the dopant-containing layer 12B from the upper region 10a to the lower region 10b of the three-dimensional structure, the dopant diffusion layer 30 (see reference) can be effectively diffused. Figure 8D The distribution or concentration of dopants in the substrate is more uniform in the height direction of the three-dimensional structure.

[0103] Figure 9A and Figure 9B Yes Figure 8B and Figure 8C A schematic diagram illustrating a variation of the steps shown. Figure 8B In this process, the thickness of the barrier layer 11A is controlled in the height direction of the three-dimensional structure, but it is not limited to this, such as... Figure 9A As shown, the barrier layer 11A can be formed on the side of the three-dimensional structure in such a manner that the film thickness of the barrier layer 11B is substantially uniform along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure. At this time, with... Figure 7A Similar to the case of barrier layer 11B, it is possible to control any one or both of the membrane material and membrane type.

[0104] In this case, in step (C), with Figure 8C Similarly, the dopant-containing layer 12B can be formed such that the concentration of the dopant contained in the dopant-containing layer decreases along the direction from the upper region 10a of the three-dimensional structure toward the lower region 10b. Figure 9B The thickness of the dopant layer 12B is the same as described above, and can be approximately constant along the direction from the upper region 10a to the lower region 10b of the three-dimensional structure, or it can be increased or decreased along this direction.

[0105] According to this modified example, the dopant diffusion layer 30 (refer to) can be made... Figure 8D The distribution or concentration of dopants in the substrate 10 is more uniform in the height direction of the three-dimensional structure.

[0106] As described above, according to this embodiment, using the ALD process, at least one of the film thickness, film quality, and film type of the barrier layer 11A (11B) is controlled in the height direction of the three-dimensional structure of the substrate layer 10. Therefore, by allowing the dopant in the dopant-containing layer 12A (12B) to diffuse into the substrate layer 10 via the barrier layer, the distribution or concentration of the dopant in the dopant diffusion layer 30 can be made uniform in the height direction of the three-dimensional structure of the substrate layer 10. Therefore, even when the substrate layer 10 has a three-dimensional structure with a high aspect ratio, the dopant can be uniformly distributed within the substrate layer.

[0107] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the specific configuration is not limited to these embodiments, and various modifications and substitutions can be made without departing from the spirit of the present invention. The structures described in the above embodiments can also be combined.

[0108] For example, in the above embodiments, the barrier layer and the doped layer were formed using the PEALD process (steps (B) and (C)), but it is not limited to this, and the thermal atomic layer deposition (ALD) process can also be used to form the barrier layer and the doped layer.

[0109] In this case, for example in step (B), a barrier layer forming gas is supplied to the reaction space containing the substrate layer. After purging or venting, a reactant-containing gas for generating reactive substances is supplied, and a thermal reaction is carried out in an oxygen atmosphere, thereby generating a barrier layer precursor on the upper and side surfaces of the three-dimensional structure. Furthermore, by performing the above cycle once or multiple times, a barrier layer can be formed on the upper and side surfaces of the three-dimensional structure of the substrate layer.

[0110] Furthermore, in step (C), a dopant-containing layer formation gas is supplied to the aforementioned reaction space. After purging or venting, a reactant-containing gas for generating reactive substances is supplied, and a thermal reaction is carried out in an oxygen atmosphere, thereby generating a dopant-containing layer precursor on the upper and side surfaces of the three-dimensional structure. Moreover, by performing the above cycle once or multiple times, a dopant-containing layer can be formed on the barrier layer and the side surfaces of the three-dimensional structure of the substrate layer.

[0111] It should be noted that the program for implementing the functions of the apparatus (e.g., ALD apparatus, semiconductor manufacturing apparatus) applicable to the above-described embodiments can be recorded on a computer-readable recording medium (storage medium), so that the computer system can read and execute the program recorded on the recording medium to perform processing.

[0112] It should be noted that the term "computer system" as used here may include hardware such as operating system (OS) or peripheral devices.

[0113] Furthermore, "computer-readable recording media" refers to writable non-volatile storage devices such as floppy disks, optical disks, ROM (Read Only Memory), and flash memory; removable media such as DVDs (Digital Versatile Discs); and storage devices such as hard drives built into computer systems. Additionally, as a recording medium, it can also be a medium that temporarily records data.

[0114] In addition, "computer-readable recording media" includes media that retain programs for a certain period of time, such as volatile memory (e.g., DRAM) inside a computer system that acts as a server or client when a program is sent via a network such as the Internet or a communication line such as a telephone line.

[0115] Furthermore, the aforementioned program can be transmitted from a computer system storing the program in a storage device or the like to other computer systems via a transmission medium or transmission waves within the transmission medium. Here, the "transmission medium" for transmitting the program refers to a medium with the function of transmitting information, such as a network (communication network) like the Internet or a communication line (communication line) like a telephone line.

[0116] Furthermore, the aforementioned program can be a part of a program used to implement the aforementioned functions. Alternatively, the aforementioned program can also be a so-called differential file (differential program) capable of implementing the aforementioned functions through combination with programs already recorded in the computer system.

[0117] In a computer, a processor such as the CPU (Central Processing Unit) reads and executes a program stored in memory.

Claims

1. A method for manufacturing a semiconductor device, comprising: Step (A) to form a base layer with a three-dimensional structure; Step (B) of forming a barrier layer on the substrate layer; Step (C) involves forming a doped layer on the barrier layer using atomic layer deposition (ALD) technology. The heat treatment step (D); In step (B), an atomic layer deposition process is used to control at least one of the film thickness, film quality, and film type of the barrier layer in the height direction of the three-dimensional structure. In step (D), the dopant contained in the dopant layer diffuses through the barrier layer to the substrate layer. In step (C), the concentration of dopant in the dopant-containing layer is controlled along the height direction of the three-dimensional structure; and in, The concentration of dopant in the dopant-containing layer decreases along the direction from the upper region to the lower region of the three-dimensional structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, In step (B), the atomic layer deposition process is plasma-enhanced atomic layer deposition, i.e., PEALD process.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, In step (B), the thickness of the barrier layer formed on the side of the three-dimensional structure is controlled by adjusting the application time of the RF power.

4. The method for manufacturing a semiconductor device according to claim 1, wherein, In step (B), the thickness of the barrier layer formed on the upper surface of the three-dimensional structure is controlled by adjusting the RF power and the application time of the RF power.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, In step (B), the film quality of the barrier layer is controlled by adjusting the RF power and the application time of the RF power.

6. The method for manufacturing a semiconductor device according to claim 1, wherein, In step (B), the barrier layer is composed of regionally selective SiN or SiON, and the film species of the barrier layer is controlled by adjusting the concentration of N element.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, In step (C), the atomic layer deposition process is plasma-enhanced atomic layer deposition, i.e., PEALD process.

8. The method for manufacturing a semiconductor device according to claim 1, wherein, The dopant is either element B or element P.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, The three-dimensional structure includes grooves. The depth-to-width ratio of the trench, i.e., the height-to-width ratio, is 10 to 100.

10. The method for manufacturing a semiconductor device according to claim 1, wherein, Step (A) of forming the substrate layer includes etching the substrate.

11. The method for manufacturing a semiconductor device according to claim 1, wherein, The substrate layer forms the channel region of the semiconductor device.

12. The method for manufacturing a semiconductor device according to claim 1, in, The three-dimensional structure includes trenches, and The depth-to-width ratio of the trench, i.e., the height-to-width ratio, is 50 to 100.

13. The method for manufacturing a semiconductor device according to claim 1, wherein, The substrate layer contains silicon.

14. The method for manufacturing a semiconductor device according to claim 1, wherein, Step (B) of forming the barrier layer includes providing a Si-containing gas, a Ti-containing gas, or a Ge-containing gas.

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