Reconstituted substrates for radio frequency applications

Abstract

The present disclosure relates to methods and apparatuses for forming thin form factor reconfigured substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein can be utilized in high density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnects. In addition, one or more cavities are structured to be filled or occupied with a flowable dielectric material. The integration of one or more radio frequency components adjacent to the filled dielectric cavities enables improved performance of the radio frequency elements while reducing signal loss caused by the silicon substrate.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to the field of semiconductor device manufacturing, and more specifically, to structures and methods for packaging semiconductor devices. Background Technology

[0002] In wireless networks such as mobile communication networks, connectivity and communication between devices are achieved using miniaturized antenna systems that combine antennas with other electronic components such as receivers or transmitters. Recently, the demand for increased data transmission rates in wireless networks has led to the development of 5G and 6G technologies utilizing new radio frequency (RF) bands, which has imposed stringent specifications on the design of RF antennas and other corresponding supporting components. Consequently, there is a growing demand for miniaturized RF antenna systems with high gain, large bandwidth, and reduced footprint for integration into compact and complex wireless electronic devices.

[0003] To integrate into wireless electronic devices, miniaturized antenna systems are typically assembled on package-level or printed circuit board (PCB)-level structures to interconnect semiconductor devices and their corresponding antennas. With advancements in wireless technology, these structures have evolved into increasingly complex 2D and 3D structures with millions of transistors, capacitors, and resistors integrated close together, along with the assembled antenna systems. Traditionally, package and PCB-level structures for antenna integration have utilized conventional semiconductor materials, such as silicon substrates. However, these conventional semiconductor materials are characterized by increased electromagnetic energy dissipation, resulting in reduced radiation efficiency and limited bandwidth for antennas assembled nearby. The loss properties of conventional semiconductor materials are particularly pronounced when using high-frequency (HF) antenna systems for high-frequency applications.

[0004] Therefore, there is a need in the art for improved structures and methods for substrate-level and / or package-level structures for high-frequency applications. Summary of the Invention

[0005] In some embodiments, a packaging assembly is provided. The packaging assembly includes: a frame having a first surface opposite a second surface; a frame material comprising silicon; at least one first cavity in which a semiconductor die is disposed; one or more second cavities; and a via having a via surface defining an opening extending through the frame from the first surface to the second surface. The packaging assembly further includes: an insulating layer disposed over the first and second surfaces and contacting at least a portion of each side of the semiconductor die; and a radio frequency (RF) element disposed over a portion of the insulating layer adjacent to one of the one or more second cavities. Electrical interconnects are disposed within the vias, wherein the insulating layer is disposed between the via surface and the electrical interconnects.

[0006] In some embodiments, a packaging assembly is provided. The packaging assembly includes: a silicon frame in which one or more cavities are formed; an oxide layer formed on a surface of the frame; and an insulating layer formed on the oxide layer and filling at least one of the one or more cavities. The insulating layer includes an epoxy resin material in which ceramic particles are disposed. One or more radio frequency (RF) elements are formed on at least one of the one or more cavities, and one or more metal interconnects are disposed within a portion of the packaging assembly.

[0007] In some embodiments, a packaging assembly is provided. The packaging assembly includes: a silicon frame having a first surface opposite a second surface; one or more first cavities in which a semiconductor die is disposed; one or more second cavities; and one or more vias having via surfaces defining openings extending through the frame from the first surface to the second surface. A first insulating layer is formed on the frame within each of the one or more second cavities and comprises an epoxy resin material having ceramic particles. One or more radio frequency (RF) elements are formed on the first insulating layer, wherein each of the one or more RF elements is aligned with one of the one or more second cavities. One or more electrical interconnects are disposed through the frame or the first insulating layer. The packaging assembly further includes a redistribution layer formed thereon, wherein the redistribution layer includes a second insulating layer formed on the first insulating layer and one or more electrical redistribution connections disposed through the second insulating layer. The second insulation embeds the one or more RF elements within the packaging assembly. Attached Figure Description

[0008] Therefore, in order to understand in detail the manner in which the features of this disclosure are described above, a more detailed description of this disclosure, which has been briefly summarized above, can be obtained by referring to the various embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and are not intended to limit the scope thereof, and other equivalent embodiments may be permitted.

[0009] Figure 1 A flowchart of a process for forming a reconstructed substrate according to an embodiment described herein is shown.

[0010] Figure 2 A flowchart is shown of a process for forming a reconstructed substrate according to an embodiment described herein.

[0011] Figures 3A to 3D Schematic illustration Figure 2 The image depicts cross-sectional views of the substrate at different stages of the substrate structuring process.

[0012] Figure 4 A flowchart is shown of a process for forming an intermediate die assembly having through-holes and contact holes, according to an embodiment described herein.

[0013] Figures 5A to 5K Schematic illustration Figure 4 The diagram depicts cross-sectional views of intermediate core assemblies at different stages of the process.

[0014] Figure 6 A flowchart is shown of a process for forming an intermediate die assembly having through-holes and contact holes, according to an embodiment described herein.

[0015] Figures 7A to 7G Schematic illustration Figure 6 The diagram depicts cross-sectional views of intermediate core assemblies at different stages of the process.

[0016] Figure 8 A flowchart of a process for forming interconnects and high-frequency components on an intermediate die assembly according to an embodiment described herein is shown.

[0017] Figures 9A to 9H Schematic illustration Figure 8 The image depicts a cross-sectional view of an intermediate die assembly at different stages of the high-frequency components and interconnect formation process.

[0018] Figure 10 A flowchart is shown of a process for slicing after forming a redistribution layer on a reconstructed substrate, according to an embodiment described herein.

[0019] Figures 11A to 11L Schematic illustration as follows Figure 10The image depicts cross-sectional views of the reconstructed substrate at different stages after the formation of the redistribution layer and subsequent single-cutting.

[0020] Figure 12 A cross-sectional view of a reconstructed substrate in a 3D stacked assembly is shown schematically according to an embodiment described herein.

[0021] For ease of understanding, the same element symbols have been used where possible to denote common elements in the figures. It is contemplated that elements and features of one embodiment can be advantageously incorporated into other embodiments without further detail. Detailed Implementation

[0022] This disclosure relates to methods and apparatus for forming thin form factor reconfiguration substrates and semiconductor device packages for high-frequency applications. The substrates and package structures described herein can be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placing semiconductor dies and vias for depositing conductive interconnects. Furthermore, one or more cavities are structured to be filled or occupied by a flowable dielectric material. Integration of one or more high-frequency components adjacent to the dielectric-filled cavities enables improved performance of radio frequency (“RF”) components while reducing signal loss caused by the silicon substrate.

[0023] Figure 1 A flowchart of a representative method 100 for forming a reconstructed substrate is shown. The reconstructed substrate can be homogeneous or heterogeneous for the devices or dies integrated therein. Method 100 includes multiple operations 110, 120, 130, and 140a-140c. (See reference...) Figures 2 to 12 Describe each operation in more detail. Methods may include one or more additional operations that are executed before any defined operation, between two defined operations, or after all defined operations (except for the possibility of context exclusion).

[0024] Typically, method 100 includes structuring the substrate to be used as a frame at operation 110, referencing... Figure 2 and Figure 3A to Figure 3D Further detailed description. At operation 120, an intermediate die assembly with one or more embedded devices and insulating material is formed, which will refer to... Figure 4 and Figures 5A to 5K ,and Figure 6 and Figures 7A to 7G More detailed description. At operation 130, one or more interconnects and / or one or more radio frequency (“RF”) elements are formed on the intermediate die assembly to form a functionally reconfigurable substrate, which refers to Figure 8and Figures 9A to 9H More detailed description. The reconstructed substrate may then have one or more redistribution layers (140a) formed thereon, which are monolithically cut into individual packages or systems within packages (140b), and / or used to form stacked 3D structures (140c). Reference Figure 10 and Figure 11 to Figure 11L Describe the formation of the redistribution layer.

[0025] Figure 2 A flowchart of a representative method 200 for structuring a substrate that will be used as a reconstructed substrate frame is shown. Figures 3A to 3D Schematic illustration Figure 2 The diagram shows cross-sectional views of substrate 302 at different stages of the substrate structuring process 200. Therefore, for clarity, this document describes them together. Figure 2 and Figures 3A to 3D .

[0026] Method 200 begins with operation 210 and the corresponding... Figure 3A In this process, substrate 302 is exposed to a first defect removal process. Substrate 302 is formed of any suitable substrate material, including but not limited to III-V compound semiconductor materials, silicon, and crystalline silicon (e.g., Si). <100> or Si <111> Materials include silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polycrystalline silicon, silicon nitride, quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In one embodiment, substrate 302 is a monocrystalline p-type or n-type silicon substrate. In another embodiment, substrate 302 is a p-type or n-type silicon solar substrate. Substrate 302 may further have a polygonal or circular shape. For example, substrate 302 may comprise a substantially square silicon substrate with a lateral dimension between about 120 mm and about 180 mm, said silicon substrate having or not having beveled edges. In another example, substrate 302 may comprise a circular silicon-containing wafer with a diameter between about 20 mm and about 700 mm (such as between about 100 mm and about 500 mm, for example, about 300 mm).

[0027] Unless otherwise stated, the embodiments and examples described herein are carried out on a substrate with a thickness between about 50 μm and about 1000 μm (such as between about 90 μm and about 780 μm). For example, substrate 302 has a thickness between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm. In another example, substrate 302 has a thickness between about 60 μm and about 160 μm, such as between about 80 μm and about 120 μm.

[0028] Prior to operation 210, the substrate 302 can be sliced ​​and separated from the bulk material by wire sawing, scribing and breaking, mechanical grinding sawing, or laser cutting. Slicing typically causes mechanical defects or deformations in the resulting substrate surface, such as scratches, microcracks, chipping, and other mechanical defects. Therefore, at operation 210, the substrate 302 is exposed to a first defect removal process to smooth and planarize the surface of the substrate 302 and remove any mechanical defects prepared for subsequent structuring and packaging operations. In some embodiments, the substrate 302 can be further thinned by adjusting the process parameters of the first defect removal process. For example, the thickness of the substrate 302 can decrease with increasing exposure to the first defect removal process.

[0029] In some embodiments, the first defect removal process at operation 210 includes exposing the substrate 302 to a substrate polishing process and / or an etching process, followed by a rinsing and drying process. For example, at operation 210, the substrate 302 may be exposed to a chemical mechanical polishing (CMP) process. In some embodiments, the etching process is a wet etching process that includes a buffered etching process selectively removing desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process utilizing an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used in the wet etching process. In one embodiment, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching. During the etching process, the etching solution may be heated to a temperature between about 30°C and about 100°C, such as between about 40°C and about 90°C, to accelerate the etching process. For example, the etching solution may be heated to about 70°C during the etching process.

[0030] In yet another embodiment, the etching process at operation 210 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes.

[0031] The thickness of substrate 302 can be adjusted by controlling the time substrate 302 is exposed to the polishing process and / or the etchant (e.g., etching solution) used during the etching process. For example, the final thickness of substrate 302 can decrease with increased exposure to the polishing process and / or etchant. Alternatively, substrate 302 can have a greater final thickness with decreased exposure to the polishing process and / or etchant.

[0032] At operations 220 and 230, the now planarized and substantially defect-free substrate 302 has one or more features, such as through-holes 303, main cavities 305, and secondary cavities 306 patterned and smoothed therein (for clarity, in Figure 3B A primary cavity 305, two secondary cavities 306, and four vias 303 are depicted in a lower cross-section of substrate 302. The vias 303 are used to form direct-contact electrical interconnects through substrate 302. The primary cavity 305 is used to receive and enclose (i.e., embed) one or more semiconductor dies therein, and the secondary cavities 306 are used to house dielectric material therein and support one or more RF elements thereon. As discussed herein, RF elements can include various RF communication elements (e.g., UHF, VHF, HF, or MF communication elements), such as antennas or other passive RF elements that facilitate various wireless communication, wireless signal reception, wireless signal transmission, and / or wireless sensing technologies. By integrating RF elements adjacent to the dielectric-filled secondary cavities 306 and away from substrate 302, radiation loss caused by the lossy substrate 302 can be limited. Although only three cavities and four vias are depicted, references to Operations 210-250 and... Figures 3A to 3D The substrate structuring process described herein can be used to form patterned features in substrate 302 with any desired depth, lateral dimensions, shape, and arrangement.

[0033] In one embodiment, a desired pattern is formed in a substrate 302, such as a solar panel substrate or even a semiconductor wafer, by laser ablation. The laser ablation system for laser drilling features in the substrate 302 can include any suitable type of laser source. In some examples, the laser source is an infrared (IR) laser. In some examples, the laser source is a picosecond UV laser. In other examples, the laser source is a femtosecond UV laser. In still other examples, the laser source is a femtosecond green laser. The laser source generates a continuous or pulsed laser beam for patterning the substrate. For example, the laser source can generate a pulsed laser beam with a frequency between 5 kHz and 500 kHz (e.g., between 10 kHz and about 200 kHz). In one example, laser source 407 is configured to deliver a pulsed laser beam at an output power between about 10 watts and about 100 watts, a wavelength between about 200 nm and about 1200 nm, and a pulse duration between about 10 ns and about 5000 ns. The laser source is configured to form any desired pattern and feature in the substrate 302, including those described above and... Figure 3B The main cavity 305, secondary cavity 306, and through hole 303 are depicted in the figure.

[0034] Similar to the process of separating substrate 302 from bulk material, laser patterning of substrate 302 may cause undesirable mechanical defects, such as chipping and cracking, on the surface of substrate 302. Therefore, after forming the desired features in substrate 302 by direct laser patterning, substrate 302 is exposed to a second defect removal and cleaning process that is substantially similar to the first defect removal process described above. Figure 3B and Figure 3C The structured substrate 302 before and after the second damage removal and cleaning process is shown, resulting in a smooth substrate 302 in which a main cavity 305, a secondary cavity 306, and a through hole 303 are formed.

[0035] During the second damage removal process at operation 230, substrate 302 is etched, rinsed, and dried. The etching process is carried out for a predetermined duration to smooth the surface of substrate 302, particularly the surface exposed to laser patterning. Alternatively, the etching process is used to remove any unwanted debris remaining from the laser ablation process. The etching process can be isotropic or anisotropic. In some embodiments, the etching process is a wet etching process using any suitable wet etchant or combination of wet etchants in an aqueous solution. For example, substrate 302 can be immersed in an aqueous HF etching solution or an aqueous KOH etching solution. In some embodiments, the etching solution is heated to further accelerate the etching process. For example, during etching of substrate 302, the etching solution can be heated to a temperature between about 40°C and about 80°C, such as between about 50°C and about 70°C, such as about 60°C. In yet other embodiments, the etching process at operation 230 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes.

[0036] Figure 3C A longitudinal cross-section of the substrate 302 is shown after operation 230 is completed. As described above, Figure 3C The substrate 302 is depicted having a single main cavity 305, two secondary cavities 306, and four through-holes 303 formed therethrough. The main cavity 305 and the secondary cavities 306 are depicted with different lateral dimensions, thus allowing the cavities to serve different functions within the subsequently formed reconfigured substrate. For example, the main cavity 305 is used to receive and house (e.g., enclose) semiconductor devices and / or dies, while the secondary cavities 306 can later be filled with a flowable dielectric material to serve as a support structure for the integration of one or more RF elements formed thereon. It is believed that the dielectric material provides better electrical isolation than silicon, and therefore, the RF elements formed on the dielectric-filled secondary cavities 306 achieve reduced radiative dissipation compared to the silicon substrate 302.

[0037] In one example, the main cavity 305 has an RF chip placed and embedded therein, and the secondary cavity 306 is filled with a flowable dielectric material on which an antenna or other passive RF component is formed. Thus, the main cavity 305 can be shaped and sized to accommodate any desired device and / or die therein, and the secondary cavity 306 can be shaped and sized to at least have the dimensions of the RF component formed thereon. Although in Figure 3B to Figure 3D Only three cavities and four through holes are depicted in the figure, but any number and arrangement of cavities and through holes can be formed in the substrate when performing method 200.

[0038] In one embodiment, the main cavity 305, the secondary cavity 306, and the through-hole 303 have a depth equal to the thickness of the substrate 302, thus forming a hole (e.g., through the thickness of the substrate 302) on opposite surfaces of the substrate 302. For example, the main cavity 305, the secondary cavity 306, and the through-hole 303 formed in the substrate 302 may have a depth between about 50 μm and about 1 mm (e.g., between about 100 μm and about 200 μm, such as between about 110 μm and about 190 μm), depending on the thickness of the substrate 302. In other embodiments, the main cavity 305, the secondary cavity 306, and / or the through-hole 303 may have a depth equal to or less than the thickness of the substrate 302, thus forming a hole only on one surface (e.g., a side surface) of the substrate 302.

[0039] In one embodiment, each primary cavity 305 and secondary cavity 306 has a lateral dimension ranging from about 0.1 mm to about 50 mm (e.g., between about 1 mm and about 15 mm, or between about 5 mm and about 10 mm), depending on the size of one or more semiconductor devices or dies to be embedded therein or the size of one or more RF elements to be integrated thereon. In some embodiments, the primary cavity 305 has a larger lateral dimension than the secondary cavity 306. For example, the primary cavity 305 has a lateral dimension between about 1 mm and about 50 mm, and the secondary cavity has a lateral dimension between about 0.2 mm and about 3 mm. In one embodiment, the primary cavity 305 and secondary cavity 306 are sized to have lateral dimensions substantially similar to those of the semiconductor device or die or RF element. For example, the lateral dimensions of each formed main cavity 305 and sub-cavity 306 exceed the lateral dimensions of the corresponding semiconductor device, die, or RF element by less than about 150 μm, such as less than about 120 μm, such as less than 100 μm. This reduced variation in the dimensions of the main cavity 305 and sub-cavity 306, and the semiconductor device, die, or RF element to be embedded therein or on, decreases the amount of gap filler material subsequently required.

[0040] The via 303 is typically cylindrical in shape. However, other forms of the via 303 are also anticipated. For example, the via 303 may have a tapered or conical shape, wherein the diameter at its first end is larger than the diameter at its second end. The formation of the tapered or conical shape can be achieved by moving a laser beam from the utilized laser source during structuring in a helical (e.g., circular, spiral) motion relative to the central axis of each via 303. The laser beam can also be angled using a motion system to form the tapered via 303. The same method can also be used to form cylindrical vias 303 having a uniform diameter.

[0041] In one embodiment, each via 303 has a diameter ranging from about 20 μm to about 200 μm, such as between about 50 μm and about 150 μm, such as between about 60 μm and about 130 μm, such as between about 80 μm and 110 μm. The minimum spacing between the centers of adjacent vias 303 is between about 70 μm and about 200 μm, such as between about 85 μm and about 160 μm, such as between about 100 μm and 140 μm.

[0042] At operation 240, substrate 302 is exposed to an optional oxidation process to grow or deposit an insulating oxide film (i.e., layer) 314 on its desired surface after removal of mechanical defects. For example, oxide film 314 may be formed on all surfaces of substrate 302 such that it surrounds substrate 302. Insulating oxide film 314 acts as a passivation layer on substrate 302 and provides a protective external barrier layer against corrosion and other forms of damage. In one embodiment, the oxidation process is a thermal oxidation process. Thermal oxidation processes are performed at temperatures between about 800°C and about 1200°C (e.g., between about 850°C and about 1150°C). For example, thermal oxidation processes are performed at temperatures between about 900°C and about 1100°C (e.g., between about 950°C and about 950°C). In one embodiment, the thermal oxidation process is a wet oxidation process using water vapor as an oxidant. In one embodiment, the thermal oxidation process is a dry process using molecular oxygen as an oxidant. It is anticipated that at operation 240, substrate 302 can be exposed to any suitable oxidation process to form oxide film 314 thereon. In some embodiments, oxide film 314 is a silicon dioxide film. Oxide film 314 typically has a thickness between about 100 nm and about 3 μm (e.g., between about 200 nm and about 2.5 μm). For example, oxide film 314 has a thickness between about 300 nm and about 2 μm, such as about 1.5 μm.

[0043] After structuring, substrate 302 can be used as a framework to form a reconfigurable substrate in subsequent packaging operations. Figure 4and Figure 6 Flowcharts of representative methods 400 and 600 for fabricating intermediate die assembly 502 around substrate 302 prior to completion (e.g., final) reconstruction of substrate or package formation are shown respectively. Figures 5A to 5K Schematic illustration Figure 4 Cross-sectional views of substrate 302 at different stages of method 400 depicted in the diagram, and Figures 7A to 7G The diagram schematically illustrates cross-sectional views of the substrate 302 at different stages of method 600 depicted in Figure 5. For clarity, this document will... Figure 4 and Figures 5A to 5K Described together, and this article will include Figure 5 and Figures 7A to 7G Describe them together.

[0044] Typically, method 400 begins with operation 402 and Figure 5A In this embodiment, a first side 575 (e.g., a first main surface 506) with desired features is placed on a first insulating film 516a, wherein a substrate 302 is now formed. In some embodiments, the first insulating film 516a comprises one or more flowable layers 518a formed of a polymer-based dielectric material. Examples of suitable polymer-based dielectric materials include polyimides, silazane-based polymers, acrylics, epoxy molding compounds, and other low-dielectric-constant dielectric materials. Typically, the flowable layers 518 are formed of a dielectric material having a dielectric constant (k) value between about 3.1 and about 3.2, and a loss tangent (tanδ) between about 0.004 and about 0.02. Figure 5A In the embodiment depicted, the first insulating film 516a includes a flowable layer 518a formed of epoxy resin.

[0045] In some examples, the flowable layer 518a may be formed of ceramic filler or particulate epoxy resin, such as epoxy resin filled with (e.g., containing) substantially spherical silica (SiO2) particles. As used herein, the term "spherical" refers to any circular, elliptical, or spherical shape. For example, in some embodiments, the ceramic filler may have an elliptical shape, an elongated elliptical shape, or other similar circular shape. However, other morphologies are also contemplated. Other examples of ceramic fillers that may be used to form the other layers of the flowable layer 518a and the insulating film 516a include aluminum nitride (AlN), alumina (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), and Sr2Ce2Ti5O. 16 Zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium oxide (CeO2), boron nitride (BN), and copper-titanium calcium oxide (CaCu3Ti4O) 12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc.

[0046] In some examples, the ceramic filler used to form the flowable layer 518a has particles ranging from about 40 nm to about 1.5 μm (e.g., between about 80 nm and about 1 μm). For example, the ceramic filler used to form the flowable layer 518a has particles ranging from about 200 nm to about 800 nm (e.g., between about 300 nm and about 600 nm). In some embodiments, the ceramic filler comprises particles having a size smaller than about 25% of the width or diameter of a feature formed in the substrate (e.g., a via, cavity, or through-assembly via) (e.g., smaller than about 15% of the width or diameter of the desired feature).

[0047] The flowable layer 518a typically has a thickness of less than about 60 μm (e.g., between about 5 μm and about 50 μm). For example, the flowable layer 518a has a thickness between about 10 μm and about 25 μm. In one embodiment, the insulating film 516a may further include one or more protective layers. For example, the insulating film 516a includes a polyethylene terephthalate (PET) protective layer 522a. However, for the insulating film 516a, any suitable combination of layers and insulating materials is contemplated. In some embodiments, the entire insulating film 516a has a thickness of less than about 120 μm, such as less than about 90 μm.

[0048] The substrate 302, coupled to the insulating film 516a and, particularly, to the flowable layer 518a of the insulating film 516a on its first side 575, may optionally be further placed on the carrier 524 for mechanical support during subsequent processing operations. The carrier is formed of any suitable mechanically and thermally stable material. For example, the carrier 524 is formed of polytetrafluoroethylene (PTFE). In another example, the carrier 524 is formed of PET.

[0049] At operation 404 and in Figure 5B As depicted, one or more semiconductor dies 526 are placed within a main cavity 305 formed in a substrate 302, such that the semiconductor die 526 is constrained by an insulating film 516a on one side and the substrate 302 on four or more sides (in... Figure 5B The image depicts a semiconductor die 526. The semiconductor die 526 is placed only within a main cavity 305, which is intended to enclose and house the semiconductor die 526, while a secondary cavity 306 remains without any semiconductor die 526 for subsequent filling with a flowable dielectric material. The secondary cavity 306, containing only the flowable dielectric material, is later used to support one or more RF components, including antennas or other passive RF components. Figure 5B In this configuration, the central main cavity 305 has a single semiconductor die 526 placed therein, while the peripheral secondary cavities 306 do not have any semiconductor dies 526. Thus, the secondary cavities 306 will subsequently be filled with a flowable dielectric material and used to support RF components thereon.

[0050] A semiconductor die 526, placed within the main cavity 305, is positioned above the surface of an insulating film 516a exposed through the main cavity 305. In one embodiment, the semiconductor die 526 is placed on an optional adhesion layer (not shown) disposed or formed on the insulating film 516a. Typically, one or more semiconductor dies 526 are multi-purpose dies on which integrated circuits are formed on their active surfaces 528. For example, one or more semiconductor dies 526 include RF chips. In some embodiments, the semiconductor dies 526 are all of the same type of semiconductor device or die. In other embodiments, the semiconductor dies 526 include different types of semiconductor devices or dies.

[0051] After placing die 526 into the main cavity 305, in operation 406 and Figure 5C A first protective film 560 is placed on a second side surface 577 (e.g., surface 508) of the substrate 302. The protective film 560 is coupled to the second side surface 577 of the substrate 302 and faces the first insulating film 516a, such that the protective film 560 contacts and covers the active surface 528 of the die 526 disposed within the main cavity 305. In one embodiment, the protective film 560 is formed of a material similar to that of the protective layer 522a. For example, the protective film 560 is formed of PET, such as biaxial PET. However, the protective film 560 can be formed of any suitable protective material. In some embodiments, the protective film 560 has a thickness between about 50 μm and about 150 μm.

[0052] The substrate 302, now with an insulating film 516a attached to the first side 575 and a protective film 560 attached to the second side 577, and further having a die 526 disposed in the main cavity 305 therein, is exposed to the first lamination process at operation 408. During the lamination process, the substrate 302 is exposed to elevated temperatures, causing the flowable layer 518a of the insulating film 516a to soften and flow into the open volume between the insulating film 516a and the protective film 560, such as into the vias 303 and the gaps 550 within the secondary cavity 306, and into the gap 551 between the inner wall of the main cavity 305 and the die 526. Thus, as Figure 5D As depicted, the semiconductor die 526 becomes at least partially embedded in the material of the insulating film 516a within the main cavity 305 and the secondary cavity 306, and the via 303 becomes partially filled with the material of the insulating film 516a.

[0053] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In one embodiment, the lamination process is performed using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C for a duration between about 5 seconds and about 1.5 minutes, such as between about 30 seconds and about 1 minute. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 50 psig while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 516a for a duration between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100°C and about 120°C for a duration between about 10 seconds and about 1 minute. For example, the lamination process is performed at a temperature of about 110°C for a duration of about 20 seconds.

[0054] At operation 410, the protective film 560 is removed, and the substrate 302, now having a flowable layer 518a, of laminated insulating material is coupled to the second protective film 562. The flowable layer 518a at least partially surrounds one or more dies 526 within the main cavity 305 and partially fills the through-hole 303 and the secondary cavity 306. Figure 5E The second protective film 562 is depicted coupled to a first side 575 of the substrate 302, such that the second protective film 562 is disposed opposite (e.g., adjacent to) the protective layer 522a of the insulating film 516a. In some embodiments, the substrate 302, now coupled to the protective film 562, may optionally be placed on a carrier 524 for additional mechanical support on the first side 575. In some embodiments, the protective film 562 is placed on the carrier 524, which is now laminated with the insulating film 516a, before being coupled to the substrate 302. Typically, the protective film 562 is substantially similar in composition to the protective film 560. For example, the protective film 562 may be formed of PET, such as biaxial PET. However, the protective film 562 may be formed of any suitable protective material. In some embodiments, the protective film 562 has a thickness between about 50 μm and about 150 μm.

[0055] After coupling the substrate 302 to the second protective film 562, in operation 412 and Figure 5FAt the location, a second insulating film 516b, substantially similar to the first insulating film 516a, is placed on the second side surface 577 of the substrate 302, thereby replacing the protective film 560. In one embodiment, the second insulating film 516b is positioned on the second side surface 577 of the substrate 302 such that the flowable layer 518b of the second insulating film 516b contacts and covers the active surface 528 of the die 526 within the main cavity 305. In one embodiment, the second insulating film 516b is placed on the substrate 302 to close the gaps 550 and 551 between the insulating film 516b and the laminated insulating material that partially surrounds the flowable layer 518a of one or more dies 526. The second insulating film 516b may comprise one or more layers formed of a polymer-based dielectric material. Figure 5F As depicted, the second insulating film 516b includes a flowable layer 518b similar to the flowable layer 518a described above. The second insulating film 516b may further include a protective layer 522b formed of a material similar to the protective layer 522a, such as PET.

[0056] At operation 414, such as Figure 5G The diagram depicts a third protective film 564 placed on top of the second insulating film 516b. Typically, the protective film 564 is substantially similar in composition to the protective films 560 and 562. For example, the protective film 564 is formed of PET, such as biaxial PET. However, the protective film 564 can be formed of any suitable protective material. In some embodiments, the protective film 564 has a thickness between about 50 μm and about 150 μm.

[0057] In operation 416 and Figure 5H At this point, the substrate 302, which now has the insulating film 516b and protective layer 564 attached to the second side 577, and the protective film 562 and optional carrier 524 on the first side 575, is exposed to a second lamination process. Similar to the lamination process at operation 408, the substrate 302 is exposed to an elevated temperature, causing the flowable layer 518b of the insulating film 516b to soften and flow into the gap between the insulating film 516b and the already laminated insulating material of the flowable layer 518a, thus integrating itself with the insulating material of the flowable layer 518a. As a result, the gaps 550 and 551 become filled with insulating material (e.g., encapsulation, sealing), and the semiconductor die 526 placed within the main cavity 305 becomes completely embedded within the insulating material of the flowable layers 518a, 518b.

[0058] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In one embodiment, the lamination process is performed using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C for a duration between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 150 psig while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 516b for a duration between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 20 psig and about 100 psig and a temperature between about 100°C and about 120°C for a duration between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a duration of about 5 minutes.

[0059] After lamination, at operation 418, the substrate 302 is detached from the carrier 524 and the protective films 562 and 564 are removed, thereby producing the laminated intermediate die assembly 502. Figure 5I The diagram depicts an intermediate die assembly 502 comprising a substrate 302, in addition to the die 526 embedded within the main cavity 305. The substrate 302 has one or more main cavities 305 and secondary cavities 306 and / or vias 303 formed therein and is filled with an insulating dielectric material containing flowable layers 518a, 518b. The insulating dielectric material of the flowable layers 518a, 518b surrounds the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302 (such as main surfaces 506, 508) and contacts all sides of the embedded semiconductor die 526. In some examples, protective layers 522a, 522b are also removed from the intermediate die assembly 502 at operation 418. Typically, protective layers 522a and 522b, carrier 524, and protective films 562 and 564 are removed from the intermediate die assembly 502 by any suitable mechanical process (such as peeling).

[0060] After removing protective layers 522a, 522b and protective films 562, 564, the intermediate die assembly 502 is exposed to a curing process to fully cure (i.e., harden by chemical reaction and crosslinking) the insulating dielectric material of the flowable layers 518a, 518b, thus forming a cured insulating layer 519. The insulating layer 519 substantially surrounds the substrate 302 and the semiconductor die 526 embedded therein. For example, the insulating layer 519 contacts or encapsulates at least sidewalls 575, 577 (including surfaces 606, 608) of the substrate 302 and at least six sidewalls or surfaces of each semiconductor die 526, said sidewalls or surfaces having a rectangular prism shape as shown in FIG. 5I.

[0061] In one embodiment, the curing process is performed at a high temperature to fully cure the insulation layer 519. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a period of time between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a period of time between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a period of time of about 30 minutes. In a further embodiment, the curing process at operation 418 is performed under ambient (e.g., atmospheric) pressure conditions or near ambient (e.g., atmospheric) pressure conditions.

[0062] After curing, at operation 420, one or more through-holes 503 are drilled through the intermediate die assembly 502, thereby forming a channel through the entire thickness of the intermediate die assembly 502 for subsequent interconnect formation. In some embodiments, the intermediate die assembly 502 may be placed on a carrier (such as carrier 524) for mechanical support during the formation of the through-holes 503 and subsequent contact holes 532. Through-holes 503 formed in the substrate 302 are drilled and subsequently filled with an insulating layer 519. Thus, the through-holes 503 can be circumferentially surrounded by the insulating layer 519 filled within the through-holes 303. By lining the walls of the through-holes 303 with a polymer-based dielectric material (e.g., an epoxy material containing ceramic fillers) of the insulating layer 519, capacitive coupling (see reference) is achieved between the conductive silicon-based substrate 302 and the interconnect 944. Figure 8 and Figures 9E to 9H (Description), and therefore, in the completed 2D reconstruction substrate 900, adjacently positioned vias 303 and / or redistributed connections 1144 (refer to) Figure 10 and Figures 11H to 11L The capacitive coupling between the components (described) is significantly reduced compared to other conventional interconnect structures utilizing conventional through-hole insulating pads or films. Furthermore, the fluidity of the insulating material enables more consistent and reliable packaging and insulation, thus enhancing electrical performance by minimizing leakage current in the completed reconfigured substrate 900.

[0063] In one embodiment, the through-hole 503 has a diameter of less than about 100 μm (e.g., less than about 75 μm). For example, the through-hole 503 has a diameter of less than about 60 μm (e.g., less than about 50 μm). In one embodiment, the through-hole 503 has a diameter between about 25 μm and about 50 μm, such as between about 35 μm and about 40 μm. In one embodiment, the through-hole 503 is formed using any suitable mechanical process. For example, the through-hole 503 is formed using a mechanical drilling process. In one embodiment, the through-hole 503 is formed through the intermediate die assembly 502 by laser ablation. For example, the through-hole 503 is formed using an ultraviolet laser. In one embodiment, the laser source for laser ablation has a frequency between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse duration between about 10 ns and about 100 ns and a pulse energy between about 50 microjoules (μJ) and about 500 μJ. Using an epoxy resin material with small ceramic filler particles in the insulating layer 519 facilitates more precise and accurate laser patterning of small-diameter vias (such as via 503) because the small ceramic filler particles exhibit reduced laser reflection, scattering, diffraction, and transmission away from the region where the via will be formed during the laser ablation process.

[0064] In operation 422 and Figure 5K One or more contact holes 532 are drilled through the insulating layer 519 to expose one or more contacts 530 formed on the active surface 528 of each embedded semiconductor die 526. The contact holes 532 are drilled through the insulating layer 519 by laser ablation, thereby exposing all outer surfaces of the semiconductor die 526 covered and surrounded by the insulating layer 519, as well as the contacts 530. Thus, the contacts 530 are exposed by forming contact holes 532. In one embodiment, the laser source can generate a pulsed laser beam with a frequency between about 100 kHz and about 1000 kHz. In one embodiment, the laser source is configured to deliver the pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ. In one embodiment, CO2, green light, or UV lasers are used to drill the contact holes 532. In one embodiment, the contact hole 532 has a diameter between about 5 μm and about 60 μm, such as a diameter between about 20 μm and about 50 μm.

[0065] After the contact hole 532 is formed, at operation 422, the intermediate die assembly 502 is exposed to a decontamination process to remove any unwanted residues and / or debris caused by laser ablation during the formation of the through-hole 503 and the contact hole 532. The decontamination process thus cleans the through-hole 503 and the contact hole 532 and fully exposes the contacts 530 on the active surface 528 of the embedded semiconductor die 526 for subsequent metallization. In one embodiment, the decontamination process is a wet decontamination process. Any suitable aqueous etchant, solvent, and / or combination thereof can be used for the wet decontamination process. In one example, potassium permanganate (KMnO4) solution can be used as the etchant. The exposure of the intermediate die assembly 502 to the wet decontamination process at operation 422 can be varied depending on the residue thickness. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process could be a plasma decontamination process using an O2:CF4 gas mixture. Plasma decontamination processes may include generating plasma by applying a power of about 700 W and causing O2:CF4 to flow at a ratio of about 10:1 (e.g., 100:10 sccm) for a time period between about 60 seconds and about 120 seconds. In a further embodiment, the decontamination process is a combination of wet and dry processes.

[0066] See below for reference Figure 8 and Figures 9A to 9H As described, after the decontamination process at operation 422, the intermediate die assembly 502 is prepared to form interconnect paths therein and to form RF elements thereon.

[0067] As discussed above, Figure 4 and Figures 5A to 5K A representative method 400 for forming an intermediate die assembly 502 is shown. Figure 6 and Figures 7A to 7G An alternative method 600, substantially similar to method 400 but with fewer operations, is shown. Method 600 typically includes seven operations 610-670. However, operations 610, 620, 660, and 670 of method 600 are substantially similar to operations 402, 404, 420, and 422 of method 400, respectively. Therefore, for clarity, this document only describes operations 610-670. Figure 7C , Figure 7D ,and Figure 7E Operations 630, 640, and 650 are described in the text.

[0068] Thus, after one or more semiconductor dies 526 are placed onto the surface of the insulating film 516a exposed through the cavity 305, before lamination, in operation 630 and Figure 7CThe second insulating film 516b is positioned on the second side surface 577 (e.g., the main surface 508) of the substrate 302. In some embodiments, the second insulating film 516b is positioned on the second side surface 577 of the substrate 302 such that the flowable layer 518b of the second insulating film 516b contacts and covers the active surface 528 of the semiconductor die 526 within the main cavity 305. In some embodiments, a second carrier 725 is attached to the protective layer 522b of the second insulating film 516b for additional mechanical support during subsequent processing operations. Figure 7C As depicted, one or more gaps 550 are formed between the insulating films 516a, 516b and the secondary cavity 306 within the via 303, and one or more gaps 551 are formed between the semiconductor die 526 and the inner wall of the main cavity 305.

[0069] In operation 640 and Figure 7D At this point, the substrate 302, now attached to insulating films 516a and 516b and in which the die 526 is disposed, is exposed to a single lamination process. During the single lamination process, the substrate 302 is exposed to elevated temperatures, causing the flowable layers 518a and 518b of the two insulating films 516a and 516b to soften and flow into the open voids 550 or gaps 551 between the insulating films 516a and 516b. As a result, the semiconductor die 526 becomes embedded within the material of the insulating films 516a and 516b, and the vias 303 and the secondary cavities 306 are completely filled by the semiconductor die 526.

[0070] Similar to a reference Figure 4 and Figures 5A to 5K The lamination process described, at operation 640, can be a vacuum lamination process, which can be performed in an autoclave or other suitable apparatus. In another embodiment, the lamination process is performed using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C for a period of time between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 150 psig while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film layers 516a, 516b for a period of time between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psig and about 100 psig and a temperature between about 100°C and about 120°C for a period of time between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of time between about 5 minutes.

[0071] At operation 650, one or more protective layers of insulating films 516a and 516b are removed from substrate 302 to obtain laminated intermediate die assembly 502. Figure 7E The intermediate die assembly 502 is depicted as including a substrate 302 and a die 526 embedded within a cavity 305. The substrate 302 has one or more main cavities 305, secondary cavities 306, and / or through-holes 303 formed therein and is filled with a flowable layer of insulating dielectric material 518a, 518b. The insulating material surrounds the substrate 302 such that it covers at least two surfaces or sides of the substrate 302, such as main surfaces 506, 508. In one example, protective layers 522a, 522b are removed from the intermediate die assembly 502, and thus the intermediate die assembly 502 is detached from carriers 524, 725. Typically, the protective layers 522a, 522b and the carriers 524, 725 are removed by any suitable mechanical process, such as peeling.

[0072] After removing protective layers 522a and 522b, the intermediate die assembly 502 is exposed to a curing process to fully cure the insulating dielectric material of the flowable layers 518a and 518b. The curing of the insulating material results in the formation of a cured insulating layer 519. Figure 7E Depicted in and similar to Figure 5I In the corresponding operation 518, the insulating layer 519 substantially surrounds the substrate 302 and the semiconductor die 526 embedded in the main cavity 305. Furthermore, the insulating layer 519 completely fills the through-hole 303 and the secondary cavity 306.

[0073] In one embodiment, the curing process is performed at a high temperature to fully cure the intermediate die assembly 502. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a period of time between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a period of time between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a period of time of about 30 minutes. In a further embodiment, the curing process at operation 650 is performed under ambient (e.g., atmospheric) pressure conditions or near ambient (e.g., atmospheric) pressure conditions.

[0074] Following curing at operation 650, method 600 is substantially similar to operations 420 and 422 of method 400. For example, intermediate die assembly 502 has one or more through-assembly vias 503 drilled through insulation layer 519 and one or more contact vias 532. Subsequently, intermediate die assembly 502 is exposed to a cleaning process, after which intermediate die assembly 502 is prepared to form interconnect paths therein, as described below.

[0075] Figure 8 A flowchart of a representative method 800 for forming electrical interconnects between electrical components within a portion of an intermediate die assembly 502 and / or RF elements positioned thereon is shown. Figures 9A to 9H Schematic illustration Figure 8 The cross-sectional view of the intermediate die assembly 502 at different stages of the process described in Method 800 is shown in the image. Therefore, for clarity, this article will... Figure 8 and Figures 9A to 9H Describe them together.

[0076] In one embodiment, the electrical interconnects and RF elements formed on the intermediate die assembly 502 are typically formed of copper. Therefore, method 800 may optionally begin with operation 810 and Figure 9A The intermediate die assembly 502, having a through-hole 503 and a contact hole 532 formed therein, has an adhesion layer 940 and / or a seed layer 942 formed thereon. A magnified partial view of the adhesion layer 940 and the seed layer 942 formed on the intermediate die assembly 502 is depicted in... Figure 9H For reference only. Adhesion layer 940 can be formed on the desired surface of insulating layer 519 where interconnects 944 and RF elements 946 are subsequently deposited. For example, adhesion layer 940 is formed on the main surfaces 905, 907 of intermediate die assembly 502, the active surface 528 within contact holes 532 on each semiconductor die 526, and the inner wall of through-hole 503. Adhesion layer 940 helps promote adhesion and prevents diffusion of subsequently formed seed layer 942, interconnects 944, and RF elements 946. Thus, in one embodiment, adhesion layer 940 serves as an adhesion layer; in another embodiment, adhesion layer 940 serves as a barrier layer. However, in both embodiments, adhesion layer 940 will be described hereinafter as an "adhesion layer".

[0077] In one embodiment, the optional adhesion layer 940 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, the adhesion layer 940 has a thickness between about 10 nm and about 300 nm (e.g., between about 50 nm and about 150 nm). For example, the adhesion layer 940 has a thickness between about 75 nm and about 125 nm (e.g., about 100 nm). The adhesion layer 940 is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), and the like.

[0078] Optional seed layer 942 may be formed on adhesive layer 940 or directly on insulating layer 519 (e.g., without forming adhesive layer 940). Seed layer 942 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, seed layer 942 has a thickness between about 50 nm and about 500 nm (e.g., between about 100 nm and about 300 nm). For example, seed layer 942 has a thickness between about 150 nm and about 250 nm (e.g., about 200 nm). In one embodiment, seed layer 942 has a thickness between about 0.1 μm and about 1.5 μm. Similar to adhesive layer 940, seed layer 942 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In one embodiment, molybdenum adhesive layer 940 and copper seed layer 942 are formed in combination on intermediate die assembly. The combination of Mo-Cu adhesion and seed layer enables improved adhesion to the surface of insulating layer 519 and reduces undercut of conductive interconnects during subsequent seed layer etching processes at operation 870.

[0079] In corresponding to respectively Figure 9B and Figure 9C At operations 820 and 830, a spin-coated / spray-coated or dry resist film 950 (such as photoresist) is applied to the two main surfaces 905, 907 of the intermediate die assembly 502 and subsequently patterned. In one embodiment, the resist film 950 is patterned via selective exposure to UV radiation. In one embodiment, an adhesion promoter (not shown) is applied to the intermediate die assembly 502 prior to the formation of the resist film 950. The adhesion promoter improves the adhesion of the resist film 950 to the intermediate die assembly 502 by creating an interfacial adhesive layer for the resist film 950 and by removing any moisture from the surface of the intermediate die assembly 502. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0080] In operating 840 and Figure 9D At this point, the intermediate die assembly 502 is exposed to the resist film development process. For example... Figure 9DThe description indicates that the development of the resist film 950 results in the exposure of the through-hole 503, contact hole 532, and the area adjacent to the main surfaces 905, 907 where the sub-cavity 306 of the RF element will be formed. In one embodiment, the film development process is a wet process, such as a wet process that involves exposing the resist to a solvent. In one embodiment, the film development process is a wet etching process utilizing an aqueous etching process. In other embodiments, the film development process is a wet etching process utilizing a buffered etching process that is selective to the desired material. Any suitable combination of wet solvents or wet etchants can be used in the resist film development process.

[0081] At operation 850 and corresponding to Figure 9E Interconnect 944 is formed through exposed through-assembly vias 503 and contact vias 532, and RF element 946 is formed over exposed areas of main surfaces 905, 907. Interconnect 944 and RF element 946 will include a conductive layer formed by any suitable method including electroplating and electroless deposition or electroless plating. In one example, interconnect 944 and / or RF element 946 are formed of copper. In other examples, interconnect 944 and / or RF element are formed of another suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.

[0082] Interconnect 944 may completely fill the through-hole 503 and contact hole 532 or only cover their inner peripheral walls. For example, interconnect 944 may be lined within the inner peripheral wall of the through-hole 503 and have a hollow core. In some embodiments, such as Figure 9E As depicted, interconnect 944 protrudes from one or both of the main surfaces 905 and 907.

[0083] RF element 946 may include any suitable components for wireless network devices and systems, including 4G, 5G, and 6G systems. For example, RF element 946 may include antenna patches, capacitors, inductors, resistors, etc. In some embodiments, RF element 946 remains exposed after the reconstruction substrate 900 is completed. In other embodiments, RF element 946 is embedded within the reconstruction substrate 900 after one or more additional redistribution layers (e.g., redistribution layers 1158, 1160 discussed below) are formed thereon. In some embodiments, RF element 946 will include a metallized layer having a desired shape (e.g., a shape in the XY plane parallel to the main surface 907) to facilitate the formation of an RF communication element. In one example, one or more of RF elements 946 have a shape configured to form at least a portion of a monopole, bipole, loop, aperture (e.g., slotted, inverted-F), or array-type RF antenna. The shape of the formed RF element 946 can be produced during the patterning process of the resist film 950 performed during operations 820-840 and during the subsequent metallization processes(s) performed during operation 850. As depicted, the RF element 946 is formed on a sub-cavity 306, which is now filled with the dielectric material of the insulating layer 519. Thus, by forming the RF element 946 on the insulating layer 519 rather than on the substrate 302, any radiation loss caused by the conductivity of the substrate 302 is limited, thereby resulting in improved radiation efficiency of the RF element 946.

[0084] After forming interconnects 944 and RF elements 946, the resist film 950 is removed at operation 860, and the intermediate die assembly 502 is exposed to adhesion and / or seed layer etching processes at operation 970, respectively corresponding to Figure 9F and Figure 9G The etching process at operation 970 results in the removal of exposed areas of the adhesion layer 940 and the seed layer 942, thus leading to the formation of the reconstructed substrate 900. In one embodiment, the seed layer etching is a wet etching process that includes rinsing and drying the intermediate die assembly 502. In one embodiment, the seed layer etching process is a buffered etching process selective for the desired material, such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etching process is an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the seed layer etching process.

[0085] In some embodiments, after operations 820-860 are completed, one or more contacts 530 coupled to semiconductor die 526 are further coupled to one or more RF elements 946 via lateral trace regions (not shown) of the one or more contacts 530. The lateral trace regions may include a portion of a conductive layer formed in operation 850 and are used to electrically connect the RF element 946 to at least one of the one or more contacts 530. The lateral trace regions will typically extend across a portion of the main surface 907 between the RF element 946 and at least one of the one or more contacts 530.

[0086] Following the adhesion and / or seed layer etching process at 870, the reconstructed substrate 900 can be diced into one or more electrically functional packages or SiPs, and subsequently integrated with other semiconductor devices and packages in various 2D and 3D arrangements and architectures. For example, packages or SiPs can be vertically stacked with additional packages or SiPs and / or other semiconductor devices and systems to form homogeneous or heterogeneous 3D stacked systems. Alternatively, the reconstructed substrate 900 can be integrated with additional semiconductor devices and systems prior to dicing.

[0087] In yet another embodiment, after etching the adhesion and / or seed layer, if desired, the reconstructed substrate 900 may have one or more redistribution layers 1158, 1160 formed thereon (in... Figures 11K to 11L (As shown in the diagram), the contacts of interconnect 944 are designed to allow for rewiring and / or extension to desired locations on the surface of the reconfiguration substrate 900. The formation of redistribution layers 1158 and 1160 also embeds the RF element 946 within the dielectric material, thus improving the integration density of subsequent single-cut packages by replacing larger passive RF components with smaller embedded RF elements. Furthermore, embedding the RF element 946 improves system performance because the passive RF element is placed closer to the front-end device compared to off-chip passive RF components typically integrated from it. This reduces the overall interconnect length, thereby minimizing losses due to lengthy interconnects.

[0088] Figure 10 A flowchart of a representative method 1000 for forming a redistribution layer 1158 on a reconstruction substrate 900 is shown. Figures 11A to 11L Schematic illustration Figure 10 The cross-sectional view of the reconstruction substrate 900 at different stages of the method 1000 depicted herein. Therefore, for clarity, this paper will... Figure 10 and Figures 11A to 11L Describe them together.

[0089] Method 1000 is essentially similar to methods 400, 600, and 800 described above. Typically, method 1000 begins with operation 1002 and... Figure 11A In this process, an insulating film 1116 is placed on a reconstruction substrate 900 on which an insulating layer 519 has been formed, and then laminated. The insulating film 1116 may be substantially similar to the insulating film 516 and may include one or more flowable layers 1118 formed of a flowable and polymer-based dielectric material and one or more protective layers 1122 formed of PET.

[0090] In one embodiment, the flowable layer 1118 comprises an epoxy resin material. In another embodiment, the flowable layer 1118 comprises an epoxy resin material containing ceramic fillers. In yet another embodiment, the flowable layer 1118 comprises a photodefinable polyimide material. The material properties of photodefinable polyimide enable the formation of smaller (e.g., narrower) vias through the resulting interconnect redistribution layer formed by the insulating film 1116. However, any suitable combination of the flowable layer 1118 and the insulating material is contemplated for use with the insulating film 1116. For example, the insulating film 1116 may comprise one or more flowable layers 1118 comprising a non-photosensitive polyimide material, a polybenzoxazole (PBO) material, a silica material, and / or a silicon nitride material.

[0091] In some examples, the material of the flowable layer 1118 differs from that of the flowable layer 518 of the insulating film 516. For example, the flowable layer 518 may comprise an epoxy resin material containing ceramic fillers, and the flowable layer 1118 may comprise a light-definable polyimide material. In another example, the flowable layer 1118 comprises an inorganic dielectric material different from that of the flowable layer 518. For example, the flowable layer 518 may comprise an epoxy resin material containing ceramic fillers, and the flowable layer 1118 may comprise a silica material.

[0092] The insulating film 1116 has a total thickness of less than about 120 μm (e.g., between about 40 μm and about 100 μm). For example, the insulating film 1116, including the flowable layer 1118 and the protective layer 1122, has a total thickness between about 50 μm and about 90 μm. In one embodiment, the flowable layer 1118 has a thickness of less than about 60 μm, such as between about 5 μm and about 50 μm, or such as about 20 μm. The insulating film 1116 is placed on the surface of the reconstructed substrate 900 having exposed interconnects 944 coupled to contacts 530 on the active surface 528 of the semiconductor die 526 and / or coupled to metallized through-assembly vias 503, such as the main surface 907.

[0093] After the insulating film 1116 is placed, the reconstructed substrate 900 is exposed to a lamination process substantially similar to that described with reference to operations 408, 416, and 640. The reconstructed substrate 900 is exposed to elevated temperatures to soften the flowable layer 1118, which is then bonded to the insulating layer 519 already formed on the reconstructed substrate 900. Thus, in one embodiment, the flowable layer 1118 becomes integrated with the insulating layer 519 and forms an extension thereto. The integration of the flowable layer 1118 and the insulating layer 519 results in an extended insulating layer 519 that covers the previously exposed interconnects 944. Therefore, the bonded flowable layer 1118 and the insulating layer 519 are described herein together as the insulating layer 519. However, in other embodiments, the lamination and subsequent curing of the flowable layer 1118 forms a second insulating layer (not shown) on the insulating layer 519. In some examples, the second insulating layer is formed of a layer of material different from the insulating layer 519.

[0094] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In one embodiment, the lamination process is performed using a hot pressing process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C for a duration between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between 10 psig and about 100 psig while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1116 for a duration between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30 psig and about 80 psig and a temperature between about 100°C and about 120°C for a duration between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a duration of about 5 minutes. In a further example, the lamination process is performed at a pressure between about 30 psig and about 70 psig (such as about 50 psig).

[0095] In operation 1004 and Figure 11BAt this point, the protective layer 1122 is removed from the reconstructed substrate 900 by a mechanical process. After removing the protective layer 1122, the reconstructed substrate 900 is exposed to a curing process to fully cure the newly extended insulating layer 519. In one embodiment, the curing process is substantially similar to the curing process described with reference to operations 418 and 650. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a period of time between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a period of time between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a period of time of about 30 minutes. In a further embodiment, the curing process at operation 1004 is performed under ambient pressure conditions or near ambient pressure conditions.

[0096] Reconstructing substrate 900 then proceeds in operation 1006 and Figure 11C The area is selectively patterned by laser ablation. Laser ablation at operation 1006 forms a redistribution via 1103 through the newly extended insulating layer 519 and exposes the desired interconnects 944 for redistribution of their contact points. In one embodiment, the redistribution via 1103 has a diameter between about 1 μm and about 70 μm, such as between about 2 μm and about 60 μm, such as between about 10 μm and about 50 μm, such as between about 20 μm and about 45 μm. In one embodiment, the laser ablation process at operation 1006 is performed using a CO2 laser. In one embodiment, the laser ablation process is performed using a UV laser. In one embodiment, the laser ablation process is performed using a green laser. At operation 1006, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm and a pulse energy between about 10 μJ and about 300 μJ for a pulse duration between about 10E-4 and about 10E-2 ns. At operation 1006, laser ablation can also be used to form an optional RF element via (not shown) extending between the top surface of the reconstructed substrate 900 and a region of the RF element 946, allowing the RF element 946 to be connected to a semiconductor die 526 or an external electronic device (not shown).

[0097] In an alternative embodiment, at operation 1006, the patterning of the reconstructed substrate 900 is performed using a plasma surface modification process (such as a plasma dry etching process utilizing reactive gases of fluorocarbons, O2, NH3, N2, He, Cl2 and / or Ar).

[0098] After patterning, the reconstructed substrate 900 is exposed to a decontamination process substantially similar to that at operations 422 and 670. During the decontamination process at operation 1006, any unwanted residues and debris formed by laser ablation during the formation of the redistribution via 1103 are removed from the redistribution via 1103 to clean (e.g., sanitize) its surface for subsequent metallization. In one embodiment, the decontamination process is a wet process. Any suitable aqueous etchant, solvent, and / or combination thereof can be used in a wet decontamination process. In one example, a KMnO4 solution can be used as an etchant. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process can be a plasma decontamination process using an O2 / CF4 gas mixture. In a further embodiment, the decontamination process is a combination of wet and dry processes.

[0099] In operation 1008 and Figure 11D At this location, an optional adhesion layer 1140 and / or seed layer 1142 are formed on the insulating layer 519. In one embodiment, the adhesion layer 1140 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, the adhesion layer 1140 has a thickness between about 10 nm and about 300 nm (e.g., between about 50 nm and about 150 nm). For example, the adhesion layer 1140 has a thickness between about 75 nm and about 125 nm (e.g., about 100 nm). The adhesion layer 1140 can be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, etc.

[0100] The optional seed layer 1142 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, the seed layer 1142 has a thickness between about 50 nm and about 500 nm (e.g., between about 100 nm and about 300 nm). For example, the seed layer 1142 has a thickness between about 150 nm and about 250 nm (e.g., about 200 nm). In one embodiment, the seed layer 1142 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1140, the seed layer 1142 can be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In one embodiment, the molybdenum adhesion layer 1140 and the copper seed layer 1142 are formed on the reconstructed substrate 900 to reduce the undercut of conductive interconnects during a subsequent seed layer etching process at operation 1020.

[0101] In corresponding to respectively Figure 11E , Figure 11F,and Figure 11G At operations 1010, 1012, and 1014, a spin-coated / spray-coated or dry resist film 1150 (such as photoresist) is applied to the adhesion and / or seed surface of the reconstruction substrate 900, followed by patterning and development. In one embodiment, an adhesion promoter (not shown) is applied to the reconstruction substrate 900 prior to the placement of the resist film 1150. Exposure and development of the resist film 1150 results in the opening of the redistribution via 1103. Therefore, patterning of the resist film 1150 can be performed by selectively exposing portions of the resist film 1150 to UV radiation and subsequently developing the resist film 1150 by a wet process (such as a wet etching process). In one embodiment, the resist film development process is a wet etching process utilizing a buffered etching process that is selective for the desired material. In other embodiments, the resist film development process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in resist film development processes.

[0102] In corresponding to respectively Figure 11H and Figure 11I At operations 1016 and 1018, redistribution connections 1144 are formed through exposed redistribution vias 1103, and then the resist film 1150 is removed. The redistribution connections 1144, including the conductive layer, are formed by any suitable method, including electroplating and electroless deposition. In one embodiment, the resist film 1150 is removed via a wet process. Figure 11H and 11I As depicted, after the resist film 1150 is removed, the redistribution connection 1144 fills the redistribution via 1103 and protrudes from the surface of the reconstruction substrate 900. In one embodiment, the redistribution connection 1144 and the optional RF element via are formed of copper. In other embodiments, the redistribution connection 1144 can be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.

[0103] In operation 1020 and Figure 11J The reconstructed substrate 900, on which the redistribution connections 1144 are formed, is exposed to a seed layer etching process substantially similar to operation 870. In one embodiment, the seed layer etching is a wet etching process, including rinsing and drying the reconstructed substrate 900. In one embodiment, the seed layer etching process is a wet etching process utilizing a buffered etching process that is selective to the desired material of the seed layer 1142. In other embodiments, the etching process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the seed layer etching process.

[0104] At operation 1022 and in Figure 11K As depicted, one or more functional 2D packages 1100 with embedded RF elements 946 can be cut from a 2D reconstruction substrate 900. (Although described as a package, package 1100 can also refer to SIP and other functional packaged devices.) However, in some embodiments, an additional redistribution layer can be formed on the reconstruction substrate 900 before the package 1100 is individually cut using the sequence and processes described above. Figure 11L As depicted, for example, one or more additional redistribution layers 1160 may be formed on a side or surface (such as main surface 1007) of the reconstructed substrate 900 opposite to the first redistribution layer 1258. Alternatively, one or more additional redistribution layers 1160 may be formed on the same side or surface (such as main surface 907) as the first redistribution layer 1158. Subsequently, after all desired redistribution layers have been formed, the package 1100 may be diced from the reconstructed substrate 900. Thereafter, each package 1100 may be integrated with other semiconductor devices and packages in desired 2D and 3D arrangements and architectures, which may be heterogeneous or homogeneous. For example, the package 1100 may be vertically stacked with other semiconductor devices and systems to form a heterogeneous 3D stacked system. However, in other embodiments, the reconstructed substrate 900 on which one or more redistribution layers 1158, 1160 are formed can be integrated with additional semiconductor devices and systems, which can be heterogeneous or homogeneous, before being diced into individual 3D packages or SIPs.

[0105] As described above, the apparatus and methods described herein can be used in any suitable 2D or 3D integration application, including stacked PCBs and / or stacked package assemblies. Figure 12 In one exemplary embodiment depicted, a reconstructed substrate 900, incorporating multiple RF components 946 and semiconductor dies 526, is stacked with another reconstructed substrate 1200 and a PCB 1250 to form a stacked 3D structure 1202. The integration of the reconstructed substrate 900 into the stacked structure 1202 provides several advantages to RF devices compared to conventional stacked structures. These benefits include a thin form factor and a high die-to-package volume ratio, enabling greater I / O scaling to meet the increasing bandwidth and power efficiency requirements of high-performance computing (HPC) and wireless devices. Using a structured silicon framework for the reconstructed substrate 900 also provides optimal material stiffness and thermal conductivity for improved electrical performance and thermal management, as well as flexibility for 3D integrated circuit (3D IC) architectures.

[0106] In some embodiments, PCB 1250 is formed of a suitable dielectric material, such as glass fiber reinforced epoxy resin (e.g., FR-1, FR-2, FR-4, halogen-free FR-4, high-T...).g (FR-4, and FR-5). Other examples of suitable dielectric materials include resin-coated copper (RCC), polyimide, polytetrafluoroethylene (PTFE), CEM-3, etc. PCB 1250 can be a single-sided or double-sided circuit board. In some embodiments, PCB 1250 includes an electrical distribution layer 1270 formed thereon and electrically connected to interconnects 944 of reconfiguration substrate 1200 and / or reconfiguration substrate 900. The electrical distribution layer 1270 is formed of any suitable conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof, and has a thickness between about 40 μm and about 100 μm, such as between about 60 μm and about 80 μm. For example, the electrical distribution layer 1270 has a thickness of about 70 μm. Furthermore, although a single electrical distribution layer 1270 is depicted, PCB 1250 and / or reconfiguration substrates 900, 1200 may have more or fewer electrical distribution layers formed on their surfaces. In other embodiments, PCB 1250 includes conductive pads or other suitable electrical contacts for interconnection with reconfiguration substrates 900, 1200.

[0107] The reconfigurable substrate 1200 is substantially similar to the reconfigurable substrate 900 and includes a substrate 302, an insulating layer 519, an embedded die 526, interconnects 944, and redistribution connections 1144. In some embodiments, the reconfigurable substrate 1200 may further include one or more embedded RF elements 946.

[0108] PCB 1250 and reconfigurable substrates 900, 1200 are electrically conductive directly or indirectly through one or more solder bumps 1240 disposed between electrical contacts (e.g., electrical distribution layer 1270) on PCB 1250 and interconnects 944 and redistribution connections 1144 on reconfigurable substrates 900, 1200. In one embodiment, the solder bumps 1240 are formed of a material substantially similar to interconnects 944, redistribution connections 1144, and / or electrical distribution layer 1270. For example, the solder bumps 1240 are formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In other examples, the solder bumps 1240 are formed of a solder alloy such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable material or combination thereof. In one embodiment, the solder bumps 1240 include C4 (Controlled Collapse Chip Connection) bumps. In one embodiment, solder bump 1240 includes C2 (chip interconnect, such as a Cu pillar with a solder cap) bump. The C2 solder bump enables smaller spacing between interconnects and improved thermal and / or electrical properties of the stack structure 1202. In some embodiments, solder bump 1240 has a diameter between about 10 μm and about 150 μm, such as a diameter between about 50 μm and about 100 μm. Solder bump 1240 can be further formed by any suitable wafer bumping process, including but not limited to electrochemical deposition (ECD) and electroplating.

[0109] Solder bumps 1240 are used to bridge interconnects 944, redistribution connections 1144, and / or electrical distribution layers 1270, creating spaces (e.g., distances) between reconstructed substrates 900, 1200, and / or PCB 1250. In some embodiments, these spaces are filled with encapsulation material (not shown) to enhance the reliability of the solder bumps 1240 disposed therein. The encapsulation material is any suitable type of encapsulant or underfill material and substantially surrounds the solder bumps 1240. In one example, the encapsulation material includes pre-assembled underfill materials such as non-flowing underfill (NUF) materials, non-conductive paste (NCP) materials, and non-conductive film (NCF) materials. In one example, the encapsulation material includes post-assembled underfill materials such as capillary underfill (CUF) materials and molded underfill (MUF) materials. In one embodiment, the encapsulation material includes a resin containing low-expansion fillers, such as those filled with (e.g., containing) SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O. 16 , ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O 12 Epoxy resins containing MgO, TiO2, ZnO, etc.

[0110] Although illustrated with an exemplary arrangement, the reconfigurable substrate 900 can be integrated into any desired 2D or 3D arrangement having one or more of the illustrated systems and / or devices.

[0111] In summary, the embodiments described herein advantageously provide an improved method for forming reconfigurable substrates for advanced integrated semiconductor devices used in high-frequency applications. By utilizing the methods described above, high aspect ratio RF features can be formed on glass and / or silicon substrates while maintaining high radiation efficiency and optimal bandwidth, thus enabling the economical formation of thinner and narrower reconfigurable substrates for 2D and 3D integration. The thin and small form factor reconfigurable substrates and reconfigurable substrate stacks depicted herein not only provide the benefits of increased RF radiation efficiency, high I / O density, and improved bandwidth and power, but also offer the benefits of more economical manufacturing and higher productivity through the elimination of single-chip flip-chip attachment, wire bonding, and overmolding steps, which are prone to feature damage in the high-volume manufacturing of integrated semiconductor devices.

[0112] Although the foregoing relates to embodiments of this disclosure, other embodiments and additional embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is defined by the appended claims.

Claims

1. An encapsulation component, comprising: A frame having a first surface opposite to the second surface, the frame further comprising: The framework material includes silicon; At least one first cavity, in which a semiconductor die is disposed; One or more second cavities; and A through-hole, the through-hole including a through-hole surface defining an opening that extends through the frame from the first surface to the second surface; An insulating layer is disposed over the first surface and the second surface, the insulating layer contacting at least a portion of each side of the semiconductor die; Radio frequency (RF) element, the RF element being disposed on a portion of the insulating layer adjacent to one of the one or more second cavities; and An electrical interconnect is disposed within the via, wherein an insulating layer is disposed between the surface of the via and the electrical interconnect.

2. The packaging assembly of claim 1, wherein the frame has a thickness between 60 μm and 160 μm.

3. The packaging assembly of claim 1, wherein the at least one first cavity has a lateral dimension between 3 mm and 50 mm.

4. The packaging assembly of claim 3, wherein the lateral dimension of the at least one first cavity is greater than the lateral dimension of the semiconductor die by less than 150 μm.

5. The packaging assembly of claim 1, wherein the via has a diameter between 20 μm and 200 μm.

6. The encapsulation assembly of claim 1, wherein the insulating layer comprises epoxy resin.

7. The encapsulation assembly of claim 6, wherein the epoxy resin comprises ceramic particles.

8. The encapsulation assembly of claim 7, wherein the ceramic particles comprise silicon dioxide particles.

9. The packaging assembly of claim 6, wherein the insulating layer has a thickness between 5 μm and 50 μm between the electrical interconnect and the semiconductor die.

10. The packaging assembly of claim 1, further comprising an adhesion layer or seed layer disposed between the electrical interconnect and the insulating layer.

11. The encapsulation assembly of claim 10, wherein the adhesion layer comprises molybdenum and the seed layer comprises copper.

12. The package assembly of claim 1, wherein the radio frequency element includes an antenna or an inductor.

13. The packaging assembly of claim 1, wherein the radio frequency element includes a conductor.

14. The packaging assembly of claim 12 or 13, wherein the semiconductor die is a radio frequency chip.

15. An encapsulation component, comprising: A frame comprising silicon and having one or more cavities formed therein; An oxide layer is disposed on the surface of the frame; An insulating layer formed on the oxide layer and filling at least one of the one or more cavities, the insulating layer comprising an epoxy resin material having ceramic particles disposed within the epoxy resin material; One or more radio frequency (RF) elements, the one or more RF elements being formed on at least one filled cavity in the one or more cavities; as well as One or more metal interconnects are disposed within a portion of the package assembly.

16. The encapsulation assembly of claim 15, wherein the frame comprises a monocrystalline solar substrate.

17. The packaging assembly of claim 16, wherein the frame has a thickness between 60 μm and 160 μm.

18. The encapsulation component of claim 15, wherein the frame further comprises: One or more semiconductor dies, wherein the one or more semiconductor dies are disposed within at least one cavity of the one or more cavities; as well as One or more through holes are formed therein, wherein the one or more metal interconnects are disposed through the one or more through holes.

19. The package assembly of claim 15, wherein the one or more radio frequency elements include an antenna or an inductor.

20. The package assembly of claim 15, wherein the one or more radio frequency elements include conductors.

21. An encapsulation component, comprising: A framework comprising silicon and having a first surface opposite to a second surface, the framework further comprising: One or more first cavities, the one or more first cavities having a semiconductor die disposed in the one or more first cavities; One or more second cavities; and One or more through holes, the one or more through holes including a through hole surface defining an opening that extends through the frame from the first surface to the second surface; A first insulating layer is formed on the frame, the first insulating layer comprising an epoxy resin material containing ceramic particles, the first insulating layer being disposed within each of the one or more second cavities; One or more radio frequency (RF) elements are formed on the first insulating layer, and each of the one or more RF elements is aligned with one of the one or more second cavities; One or more electrical interconnects are disposed through the frame or the first insulating layer; and A redistribution layer is formed on the semiconductor die, the redistribution layer comprising: A second insulating layer is formed on the first insulating layer, and the second insulating layer embeds the one or more radio frequency components within the package assembly; and One or more electrical redistribution connections are disposed through the second insulating layer.

22. The packaging assembly of claim 21, wherein the second insulating layer is formed of the same material as the first insulating layer.

Images